WO2012073477A1

WO2012073477A1 - Plasma display device and method for driving plasma display device

Info

Publication number: WO2012073477A1
Application number: PCT/JP2011/006625
Authority: WO
Inventors: 岩見　隆
Original assignee: パナソニック株式会社
Priority date: 2010-11-30
Filing date: 2011-11-29
Publication date: 2012-06-07

Abstract

In order to reduce the power consumption of a data-electrode drive circuit in a plasma display device, the data-electrode drive circuit includes, for each data electrode, an output buffer having a high-voltage-side switch that outputs a high-side voltage and a low-voltage-side switch that outputs a low-side voltage. When the voltage of a write pulse is to be transitioned from the low-side voltage to the high-side voltage, the output buffer turns the low-voltage-side switch off and the high-voltage-side switch on and thereby changes the output voltage to the high-side voltage in a first transition period provided in each write cycle. When the voltage of the write pulse is to be transitioned from the high-side voltage to the low-side voltage, the output buffer turns the high-voltage-side switch off and the low-voltage-side switch on and thereby changes the output voltage to the low-side voltage in a second transition period provided in the write cycle. The second transition period and the first transition period immediately after the second transition period are separated temporally.

Description

Plasma display apparatus and driving method of plasma display apparatus

The present invention relates to a plasma display device which is an image display device using an AC surface discharge type plasma display panel and a driving method of the plasma display device.

2. Description of the Related Art A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate that are arranged to face each other. In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs.

The back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.

Then, the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.

The subfield method is generally used as a method for driving the panel. In the subfield method, one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization operation is performed to generate an initialization discharge in each discharge cell. Thereby, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.

In the address period, the scan pulse is sequentially applied to the scan electrodes, and the address pulse is selectively applied to the data electrodes based on the image signal to be displayed. As a result, an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”). ).

In the sustain period, the number of sustain pulses based on the luminance weight determined for each subfield is alternately applied to the display electrode pairs composed of the scan electrodes and the sustain electrodes. As a result, a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”). Also written as “lit”.) Thereby, each discharge cell is made to emit light with the luminance according to the luminance weight. In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.

The plasma display device has a scan electrode drive circuit, a sustain electrode drive circuit, and a data electrode drive circuit in order to generate a drive voltage waveform necessary for image display. The drive voltage waveform generated in the scan electrode drive circuit is applied to the scan electrode, the drive voltage waveform generated in the sustain electrode drive circuit is applied to the sustain electrode, and the drive voltage waveform generated in the data electrode drive circuit is applied to the data electrode. Apply.

In recent years, with the increase in screen size and resolution, the power consumed in write operations has increased. And the power consumption in the data electrode driving circuit increases the power consumption of the plasma display device.

Therefore, various methods for reducing the power consumption of the data electrode driving circuit have been proposed.

When viewed from the data electrode drive circuit, the data electrode is a capacitive load (load capacity). In view of this, a plasma display device is disclosed in which a power recovery unit is added to a power source that supplies power to a data electrode driving circuit (see, for example, Patent Document 1). In the technique described in Patent Document 1, this power supply reduces power consumption by resonating the load capacitance and the recovery coil and supplying power to the data electrode driving circuit.

However, the load capacity of the data electrode varies greatly depending on the image data. Therefore, in the technique described in Patent Document 1, the power consumption may increase depending on the design of the image. The image data is data generated based on an image signal in order to display an image on the panel.

A plasma display device that improves this point is also disclosed (see, for example, Patent Document 2). In the technique described in Patent Document 2, the output amplitude of the power recovery unit added to the power supply is controlled according to the image data.

Thus, the power consumption in the plasma display device can be reduced by adding the power recovery unit to the power source that supplies power to the data electrode driving circuit. However, if a power recovery unit is added to the power supply, the voltage supplied to the data electrode drive circuit tends to be unstable, and the address discharge may become unstable. When the address discharge becomes unstable, the image display quality in the plasma display device is degraded.

For these reasons, there is a demand for a plasma display device capable of stably supplying power to the data electrode driving circuit to perform a stable addressing operation and reducing power consumption of the data electrode driving circuit.

JP 2002-278509 A JP 2004-212699 A

The present invention includes a panel having a plurality of display electrode pairs and a plurality of data electrodes, and a data electrode driving circuit for applying a writing pulse to the data electrodes, the data electrode driving circuit having a writing pulse for each writing cycle in a writing period. The high voltage side voltage or the low voltage side voltage of the write pulse is applied to each data electrode. The data electrode driving circuit includes an output buffer having a high-voltage side switch that outputs a high-voltage side voltage and a low-voltage side switch that outputs a low-voltage side voltage for each of the data electrodes. The output buffer turns off the low-voltage side switch and turns on the high-voltage side switch during the first transition period provided in the write cycle when the voltage of the write pulse changes from the low-voltage side voltage to the high-voltage side voltage. To high voltage. When transitioning the voltage of the write pulse from the high-voltage side voltage to the low-voltage side voltage, the high-voltage side switch is turned off and the low-voltage side switch is turned on during the second transition period provided in the write cycle. To. Then, the second transition period and the first transition period immediately after the second transition period are separated in time.

Thus, it is possible to stably supply power to the data electrode driving circuit to perform a stable addressing operation and reduce the power consumption of the data electrode driving circuit.

In the plasma display apparatus of the present invention, the data electrode driving circuit calculates a substantial load capacity between adjacent data electrodes, and the data electrode having a relatively large substantial load capacity is substantially The high voltage side switch and the low voltage side switch may be controlled for each output buffer so that the start time of the first transition period or the second transition period is earlier than the data electrode having a relatively small load capacity.

In the plasma display device of the present invention, the data electrode driving circuit is constituted by using a plurality of integrated circuits in which a plurality of output buffers are integrated. In the integrated circuit, the substantial load capacitance generated for each data electrode is determined. In an integrated circuit with a large maximum value, the high-voltage side switch and the low-voltage side switch are integrated so that the start time of the first transition period or the second transition period is earlier than that of the integrated circuit with a small maximum value. You may control for every circuit.

The present invention also includes a panel having a plurality of display electrode pairs and a plurality of data electrodes, and a data electrode driving circuit for applying an address pulse to the data electrodes, and the data electrode driving circuit is provided for each address period in the address period. In the plasma display device, a high voltage side voltage of an address pulse or a low voltage side voltage of an address pulse is applied to each data electrode. The data electrode driving circuit includes an output buffer having a high-voltage side switch that outputs a high-voltage side voltage and a low-voltage side switch that outputs a low-voltage side voltage for each of the data electrodes. The output buffer turns off the low-voltage side switch and turns on the high-voltage side switch during the first transition period provided in the write cycle when the voltage of the write pulse changes from the low-voltage side voltage to the high-voltage side voltage. To high voltage. When transitioning the voltage of the write pulse from the high-voltage side voltage to the low-voltage side voltage, the high-voltage side switch is turned off and the low-voltage side switch is turned on during the second transition period provided in the write cycle. To. Then, in the two data electrodes adjacent to each other, the second transition period and the first transition period immediately after the second transition period are temporally separated.

According to the present invention, one field includes a plurality of subfields each having an address period and a sustain period, and in the address period, a write cycle is applied to a data electrode of a panel having a plurality of display electrode pairs and a plurality of data electrodes. This is a driving method of a plasma display device in which an address pulse is applied every time. In this driving method, the voltage of the write pulse is changed from the low voltage side voltage to the high voltage side voltage in the first transition period provided in the write cycle, and the voltage of the write pulse is changed in the second transition period provided in the write cycle. Transition from high voltage to low voltage. Then, the second transition period and the first transition period immediately after the second transition period are separated in time.

FIG. 1 is an exploded perspective view showing a structure of a panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 2 is an electrode array diagram of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 3 is a diagram schematically showing the interelectrode capacitance of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 4 is a diagram schematically showing drive voltage waveforms applied to each electrode of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 5 is a diagram schematically showing an example of a circuit block constituting the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 6 is a circuit diagram schematically showing a configuration of an output buffer included in the data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 7 is a timing chart schematically showing an example of the operation of the data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 8A is a circuit diagram schematically showing a configuration of an output buffer provided in the data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 8B is a diagram schematically showing an example of the operating state of the output buffer provided in the data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 8C is a diagram schematically showing another example of the operating state of the output buffer provided in the data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 8D is a diagram schematically showing another example of the operating state of the output buffer provided in the data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 8E is a diagram schematically showing another example of the operating state of the output buffer provided in the data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 9 is a circuit diagram schematically showing a configuration of a data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 10 is a diagram schematically showing an example of a circuit block constituting the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 11 is a circuit diagram schematically showing a configuration of a data electrode driving circuit of the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 12 is a timing chart schematically showing an example of the operation of the data electrode driving circuit of the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 13 is a circuit diagram schematically showing a configuration of a data electrode driving circuit of the plasma display device in accordance with the third exemplary embodiment of the present invention. FIG. 14 is a timing chart schematically showing an example of the operation of the data electrode driving circuit of the plasma display device in accordance with the third exemplary embodiment of the present invention. FIG. 15 is a circuit diagram schematically showing a configuration of a data electrode driving circuit of the plasma display device in accordance with the fourth exemplary embodiment of the present invention. FIG. 16 is a timing chart schematically showing an example of the operation of the data electrode driving circuit of the plasma display device in accordance with the fourth exemplary embodiment of the present invention.

Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

A plurality of display electrode pairs 14 each including a scanning electrode 12 and a sustaining electrode 13 are formed on a glass front substrate 11. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15.

This protective layer 16 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is made of a material mainly composed of magnesium oxide (MgO).

A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is further formed thereon. On the side surfaces of the barrier ribs 24 and on the dielectric layer 23, a phosphor layer 25R that emits red (R), a phosphor layer 25G that emits green (G), and a phosphor layer 25B that emits blue (B). Is provided. Hereinafter, the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.

The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21. . And the outer peripheral part is sealed with sealing materials, such as glass frit. Then, for example, a mixed gas of neon and xenon is sealed in the discharge space inside as a discharge gas.

The discharge space is divided into a plurality of sections by the partition walls 24, and discharge cells are formed at the intersections between the display electrode pairs 14 and the data electrodes 22.

Then, a discharge is generated in these discharge cells, and the phosphor layer 25 of the discharge cells emits light (lights the discharge cells), thereby displaying a color image on the panel 10.

In the panel 10, one pixel is composed of three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends. The three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) (red discharge cell), and a discharge cell having a phosphor layer 25G and emitting green (G) (green). And a discharge cell having a phosphor layer 25B and emitting blue (B) light (blue discharge cell).

Note that the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.

FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

The panel 10 includes n scan electrodes SC (1) to scan electrodes SC (n) (scan electrodes 12 in FIG. 1) and n sustain electrodes SU (1) to (horizontal direction (row direction)). Sustain electrodes SU (n) (sustain electrodes 13 in FIG. 1) are arranged and m data electrodes D (1) to D (m) (data electrodes in FIG. 1) extended in the vertical direction (column direction). 22) are arranged.

One discharge is generated in a region where a pair of scan electrodes SC (i) (i = 1 to n) and sustain electrodes SU (i) intersect with one data electrode D (j) (j = 1 to m). A cell is formed. In other words, m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 and n = 1080.

The interelectrode capacitance exists between the electrodes of the electrodes arranged in this way.

FIG. 3 is a diagram schematically showing the interelectrode capacitance of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

In FIG. 3, as an example, five scan electrodes SC (i−2) to scan electrode SC (i + 2), five sustain electrodes SU (i−2) to sustain electrode SU (i + 2), Data electrodes D (j−2) to data electrode D (j + 3) are shown, and the interelectrode capacitance related to the data electrode 22 is shown. In FIG. 3, a display electrode pair composed of scan electrode SC (i) and sustain electrode SU (i) is indicated by one thick horizontal line.

As shown in FIG. 3, in the panel 10, “capacitance Cs” exists in each of the regions where the display electrode pair 14 and the data electrode 22 intersect. Further, “capacitance Cc” exists between the data electrodes 22 adjacent to each other.

One data electrode D (j) intersects n scan electrodes SC (1) to scan electrode SC (n) and n sustain electrodes SU (1) to sustain electrode SU (n). That is, one data electrode D (j) intersects n display electrode pairs 14. Therefore, in the panel 10, a capacitance (n × Cs) exists between one data electrode D (j) and the display electrode pair 14. Hereinafter, the capacity (n × Cs) is expressed as “capacity Cg”.

Further, one data electrode D (j) has a capacitance Cc between the data electrode D (j + 1) adjacent to the right side and a capacitance between the data electrode D (j−1) adjacent to the left side. Cc exists.

Thus, since the capacitance Cg, the capacitance Cc, and the capacitance Cc exist in one data electrode D (j), the total load capacitance in one data electrode D (j) is the capacitance (Cg + 2Cc). . Therefore, in the panel 10, a capacitance (Cg + 2Cc) exists in each of the data electrodes 22.

Next, a driving voltage waveform for driving the panel 10 and an outline of its operation will be described.

The plasma display device in the present embodiment drives the panel 10 by the subfield method. In the subfield method, one field of an image signal is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield. Therefore, each field has a plurality of subfields having different luminance weights.

Each subfield has an initialization period, an address period, and a sustain period. Based on the image signal, light emission / non-light emission of each discharge cell is controlled for each subfield. That is, a plurality of gradations based on the image signal are displayed on the panel 10 by combining the light-emitting subfield and the non-light-emitting subfield based on the image signal.

In the initializing period, an initializing operation is performed in which initializing discharge is generated in the discharge cells and wall charges necessary for the address discharge in the subsequent address period are formed on each electrode.

In the address period, a scan pulse is applied to the scan electrode 12 and an address pulse is selectively applied to the data electrode 22 to selectively generate an address discharge in the discharge cells to emit light. Then, an address operation is performed to form wall charges in the discharge cells for generating a sustain discharge in the subsequent sustain period.

In the sustain period, the sustain pulses of the number obtained by multiplying the luminance weight set in each subfield by a predetermined proportional constant are alternately applied to the scan electrode 12 and the sustain electrode 13 to generate the address discharge in the immediately preceding address period. A sustain discharge is generated in the discharge cell, and a sustain operation for emitting light from the discharge cell is performed. This proportionality constant is a luminance multiple. For example, when the luminance multiple is twice, the sustain pulse is applied four times to each of the scan electrode 12 and the sustain electrode 13 in the sustain period of the subfield having the luminance weight “2”. Therefore, the number of sustain pulses generated in the sustain period is 8.

The luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”.

Thus, for example, one field is composed of eight subfields (subfield SF1, subfield SF2, subfield SF3, subfield SF4, subfield SF5, subfield SF6, subfield SF7, subfield SF8). If luminance weights of (1, 2, 4, 8, 16, 32, 64, 128) are set in each subfield of SF1 to subfield SF8, each discharge cell has a gradation value of “0”. The 256 gradation values up to the value “255” can be displayed.

In this way, by controlling the light emission / non-light emission of each discharge cell for each subfield in a combination according to the image signal, each subfield is selectively emitted to emit each discharge cell with various gradation values, An image can be displayed on the panel 10.

In the present invention, the number of subfields constituting one field, the luminance weight of each subfield, and the like are not limited to the above-described numerical values.

The initializing operation includes all-cell initializing operation that generates initializing discharge in the discharge cells regardless of the operation of the immediately preceding subfield, and the address discharge is generated in the immediately preceding subfield addressing period and is maintained in the sustaining period. There is a selective initializing operation in which initializing discharge is selectively generated only in the discharge cells that have generated discharge. In the all-cell initialization operation, an ascending rising waveform voltage and a descending falling waveform voltage are applied to the scan electrode 12 to generate an initializing discharge in all the discharge cells in the image display region. Then, among all the subfields, the all-cell initialization operation is performed in the initialization period of one subfield, and the selective initialization operation is performed in the initialization period of the other subfield. Hereinafter, the initialization period for performing the all-cell initialization operation is referred to as “all-cell initialization period”, and the subfield having the all-cell initialization period is referred to as “all-cell initialization subfield”. An initialization period for performing the selective initialization operation is referred to as “selective initialization period”, and a subfield having the selective initialization period is referred to as “selective initialization subfield”.

In this embodiment, the first subfield (subfield SF1) of each field is an all-cell initializing subfield, and the other subfields are selective initializing subfields.

Thereby, since the initializing discharge is generated in all the discharge cells at least once in one field, the addressing operation after the initializing operation for all the cells can be stabilized. Further, light emission not related to image display is only light emission due to discharge in the all-cell initializing operation in the subfield SF1. Therefore, the black luminance that is the luminance of the black display region where no sustain discharge occurs is only weak light emission in the all-cell initialization operation, and an image with high contrast can be displayed on the panel 10.

However, in the present embodiment, the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above-described numerical values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

FIG. 4 is a diagram schematically showing drive voltage waveforms applied to the respective electrodes of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

FIG. 4 shows scan electrode SC (1) that performs the address operation first in the address period, scan electrode SC (n) that performs the address operation last in the address period (for example, scan electrode SC (1080)), and sustain electrode SU. (1) Drive voltage waveforms applied to sustain electrode SU (n) and data electrode D (1) to data electrode D (m) are shown. In addition, scan electrode SC (i), sustain electrode SU (i), and data electrode D (k) in the following are selected from each electrode based on image data (data indicating light emission / non-light emission for each subfield). Represents an electrode.

FIG. 4 shows driving voltage waveforms of two subfields, subfield SF1 and subfield SF2. The subfield SF1 is a subfield for performing an all-cell initialization operation, and the subfield SF2 is a subfield for performing a selective initialization operation. Therefore, the waveform shape of the drive voltage applied to the scan electrode 12 in the initialization period differs between the subfield SF1 and the subfield SF2. The drive voltage waveform in the other subfield is substantially the same as the drive voltage waveform in subfield SF2 except that the number of sustain pulses generated in the sustain period is different.

In the present embodiment, the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above values.

First, the subfield SF1, which is an all-cell initialization subfield, will be described.

In the first half of the initialization period of the subfield SF1 that performs the all-cell initialization operation, the data electrode D (1) to the data electrode D (m) and the sustain electrode SU (1) to the sustain electrode SU (n) A voltage of 0 (V) is applied. A voltage Vi1 is applied to scan electrode SC (1) to scan electrode SC (n) after voltage 0 (V) is applied, and an upward ramp waveform voltage (ramp voltage) gradually rising from voltage Vi1 to voltage Vi2. ) Is applied. Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU (1) to sustain electrode SU (n), and voltage Vi2 is set to a voltage exceeding the discharge start voltage.

While this ramp voltage rises, scan electrode SC (1) to scan electrode SC (n) and sustain electrode SU (1) to sustain electrode SU (n) of each discharge cell, and scan electrode SC (1 ) To the scan electrode SC (n) and the data electrode D (1) to the data electrode D (m), weak initializing discharges are continuously generated. Then, negative wall voltage is accumulated on scan electrode SC (1) to scan electrode SC (n), and data electrode D (1) to data electrode D (m) and sustain electrode SU (1) to sustain electrode SU. (N) A positive wall voltage is accumulated on the top. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

In the second half of the initializing period of subfield SF1, positive voltage Ve is applied to sustain electrode SU (1) to sustain electrode SU (n), and data electrode D (1) to data electrode D (m) are applied to data electrode D (1) to data electrode D (m). A voltage of 0 (V) is applied. Scan electrode SC (1) to scan electrode SC (n) are applied with a downward ramp waveform voltage (ramp voltage) that gently falls from voltage Vi3 toward negative voltage Vi4. Voltage Vi3 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU (1) to sustain electrode SU (n), and voltage Vi4 is set to a voltage exceeding the discharge start voltage.

While this ramp voltage is applied to scan electrode SC (1) -scan electrode SC (n), scan electrode SC (1) -scan electrode SC (n) and sustain electrode SU (1) -sustain electrode of each discharge cell. A weak initializing discharge occurs between SU (n) and between scan electrode SC (1) -scan electrode SC (n) and data electrode D (1) -data electrode D (m). . Thus, negative wall voltage on scan electrode SC (1) to scan electrode SC (n), positive wall voltage on sustain electrode SU (1) to sustain electrode SU (n), and data electrode D (1) The positive wall voltage on the data electrode D (m) is adjusted to a value suitable for the write operation.

Thus, the all-cell initializing operation in the initializing period of the subfield SF1 is completed, and wall charges necessary for the subsequent addressing operation are formed on each electrode in all the discharge cells.

In this embodiment, a device for reducing power consumption is applied to the waveform shape of the address pulse applied to the data electrode D (1) to the data electrode D (m) in the subsequent address period. Details of this will be described later. Hereinafter, an outline of the write operation in the write period will be described.

In the address period of subfield SF1, first, voltage Ve is applied to sustain electrode SU (1) to sustain electrode SU (n), and voltage 0 (V) is applied to data electrode D (1) to data electrode D (m). ) And a voltage Vc is applied to scan electrode SC (1) to scan electrode SC (n).

Then, in the first address period, a negative scan pulse with a negative voltage Va is applied to the scan electrode SC (1) of the first line (first row). Then, a positive address pulse having a positive voltage Vd is applied to the data electrode D (k) of the discharge cell that should emit light in the first line among the data electrodes D (1) to D (m).

In the discharge cell at the intersection of the data electrode D (k) to which the address pulse voltage Vd is applied and the scan electrode SC (1) to which the scan pulse voltage Va is applied, the data electrode D (k) and the scan electrode SC ( Discharge occurs between 1) and 1).

In addition, since voltage Ve is applied to sustain electrode SU (1) to sustain electrode SU (n), it is induced by a discharge generated between data electrode D (k) and scan electrode SC (1). Discharge is also generated between sustain electrode SU (1) and scan electrode SC (1) in the region intersecting data electrode D (k). Thus, an address discharge occurs in the discharge cell (discharge cell to emit light) to which the voltage Va of the scan pulse and the voltage Vd of the address pulse are simultaneously applied, and a positive wall voltage is accumulated on the scan electrode SC (1). A negative wall voltage is accumulated on the sustain electrode SU (1), and a negative wall voltage is also accumulated on the data electrode D (k).

In this way, the address operation in the discharge cell on the first line is completed. In the discharge cells to which no address pulse is applied, the address discharge does not occur, and the wall voltage after the end of the initialization period is maintained.

Next, in the second address period, a scan pulse of voltage Va is applied to the scan electrode SC (2) of the second line (second row), and the data electrode corresponding to the discharge cell that should emit light on the second line. An address pulse of voltage Vd is applied to D (k). As a result, address discharge occurs in the discharge cells of the second line to which the scan pulse and address pulse are simultaneously applied. Thus, an address operation is performed in the discharge cell of the second line.

Similarly, a scan pulse of voltage Va is applied to the scan electrode SC (i) of the i-th line in the i-th write cycle, and the data electrode D (k) corresponding to the discharge cell to emit light on the i-th line is applied. An address pulse of voltage Vd is applied. As a result, an address discharge occurs in the i-th line discharge cell to which the scan pulse and the address pulse are simultaneously applied, and an address operation is performed in the i-th line discharge cell.

The same address operation is sequentially performed until the discharge cell on the n-th line, and the address period of the subfield SF1 ends.

Note that voltage Ve applied to sustain electrode SU (1) to sustain electrode SU (n) in the latter half of the initialization period and voltage Ve applied to sustain electrode SU (1) to sustain electrode SU (n) in the address period Different voltage values may be used.

In the subsequent sustain period of subfield SF1, voltage 0 (V) is first applied to sustain electrode SU (1) to sustain electrode SU (n). Then, sustain pulse of positive voltage Vs is applied to scan electrode SC (1) to scan electrode SC (n).

In the discharge cell in which the address discharge is generated by the application of the sustain pulse, the voltage difference between the scan electrode SC (i) and the sustain electrode SU (i) exceeds the discharge start voltage, and the sustain discharge is generated. And the fluorescent substance layer 25 light-emits with the ultraviolet-ray which generate | occur | produced by this discharge. Further, due to this discharge, a negative wall voltage is accumulated on scan electrode SC (i), and a positive wall voltage is accumulated on sustain electrode SU (i). Furthermore, a positive wall voltage is also accumulated on the data electrode D (k). However, no sustain discharge occurs in the discharge cells in which no address discharge has occurred during the address period.

Subsequently, voltage 0 (V) is applied to scan electrode SC (1) to scan electrode SC (n), and a sustain pulse of voltage Vs is applied to sustain electrode SU (1) to sustain electrode SU (n). . In the discharge cell that has generated a sustain discharge immediately before, a sustain discharge occurs again, a negative wall voltage is accumulated on sustain electrode SU (i), and a positive wall voltage is accumulated on scan electrode SC (i).

Thereafter, in the same manner, scan electrodes SC (1) to scan electrode SC (n) and sustain electrodes SU (1) to sustain electrode SU (n) are alternately supplied with the number of sustain pulses obtained by multiplying the brightness weight by a predetermined brightness multiple. Apply to. Thus, the discharge cells that have generated the address discharge in the address period emit light with a luminance corresponding to the luminance weight.

Then, after the sustain pulse is generated in the sustain period, scanning is performed with voltage 0 (V) applied to sustain electrode SU (1) to sustain electrode SU (n) and data electrode D (1) to data electrode D (m). A ramp waveform voltage (ramp voltage) that gently rises from voltage 0 (V) to voltage Vr is applied to electrode SC (1) to scan electrode SC (n).

During the application of this ramp voltage to scan electrode SC (1) to scan electrode SC (n), a weak discharge is generated in the discharge cell that has generated the sustain discharge. The charged particles generated by the weak discharge are on the sustain electrode SU (i) and the scan electrode SC (i) so as to alleviate the voltage difference between the sustain electrode SU (i) and the scan electrode SC (i). Accumulated as wall charges on top. Thereby, the wall voltage on scan electrode SC (i) and sustain electrode SU (i) is weakened while the positive wall voltage on data electrode D (k) remains. That is, unnecessary wall charges in the discharge cell are erased.

When the voltage applied to scan electrode SC (1) to scan electrode SC (n) reaches voltage Vr, the voltage applied to scan electrode SC (1) to scan electrode SC (n) is lowered to voltage 0 (V). . Thus, the sustain operation in the sustain period of subfield SF1 is completed.

Thus, subfield SF1 is completed.

Next, subfield SF2, which is a selective initialization subfield, will be described.

In the initializing period of subfield SF2, voltage Ve is applied to sustain electrode SU (1) to sustain electrode SU (n), and voltage 0 (V) is applied to data electrode D (1) to data electrode D (m). Is applied. Scan electrode SC (1) to scan electrode SC (n) have a ramp waveform voltage (ramp voltage) that gently falls from a voltage (for example, voltage 0 (V)) that is less than the discharge start voltage toward negative voltage Vi4. Is applied. Voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU (1) to sustain electrode SU (n).

In a discharge cell in which a sustain discharge is generated in the sustain period of the immediately preceding subfield (subfield SF1 in FIG. 4) while this ramp voltage is applied to scan electrode SC (1) to scan electrode SC (n), it is weak. Initializing discharge occurs. The initialization discharge weakens the wall voltage on scan electrode SC (i) and sustain electrode SU (i). In addition, an excessive portion of the wall voltage accumulated on the data electrode D (k) is discharged. Thus, the wall voltage in the discharge cell is adjusted to a wall voltage suitable for the address operation.

On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period of the immediately preceding subfield (subfield SF1), the initialization discharge does not occur and the previous wall voltage is maintained.

As described above, the initializing operation in the subfield SF2 is a selective initializing operation in which the initializing discharge is selectively generated in the discharge cells that have performed the addressing operation in the address period of the immediately preceding subfield.

Thus, the selective initialization operation in the initialization period of subfield SF2 is completed.

In the address period of the subfield SF2, a drive voltage waveform similar to that in the address period of the subfield SF1 is applied to each electrode, and an address operation for accumulating wall voltage on each electrode of the discharge cell to emit light is performed.

In the subsequent sustain period, similarly to the sustain period of subfield SF1, the number of sustain pulses corresponding to the luminance weight is applied to scan electrode SC (1) to scan electrode SC (n) and sustain electrode SU (1) to sustain electrode SU ( n) alternately, and sustain discharge is generated in the discharge cells that have generated address discharge in the address period.

In the initialization period and address period of each subfield after subfield SF3, the same drive voltage waveform as that in the initialization period and address period of subfield SF2 is applied to each electrode. In the sustain period of each subfield after subfield SF3, the drive voltage waveform similar to that of subfield SF2 is applied to each electrode except for the number of sustain pulses generated in the sustain period.

The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

FIG. 5 is a diagram schematically showing an example of a circuit block constituting the plasma display device 30 according to the first embodiment of the present invention.

The plasma display device 30 shown in the present embodiment includes a panel 10 and a drive circuit that drives the panel 10. The drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.

The image signals input to the image signal processing circuit 31 are a red image signal, a green image signal, and a blue image signal. The image signal processing circuit 31 sets each gradation value of red, green, and blue in each discharge cell based on the red image signal, the green image signal, and the blue image signal. In the image signal processing circuit 31, the input image signal includes a luminance signal (Y signal) and a saturation signal (C signal, or RY signal and BY signal, or u signal and v signal, etc.). In some cases, a red image signal, a green image signal, and a blue image signal are calculated based on the luminance signal and the saturation signal, and then each of the red, green, and blue tone values (represented by one field) is stored in each discharge cell. Tone value). Then, the red, green, and blue gradation values set in each discharge cell are associated with image data indicating lighting / non-lighting for each subfield (light emission / non-light emission corresponds to digital signals “1” and “0”). Data). That is, the image signal processing circuit 31 converts the red image signal, the green image signal, and the blue image signal into red image data, green image data, and blue image data and outputs the converted image data.

The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. The generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).

Scan electrode drive circuit 33 includes an initialization waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 5), and generates a drive voltage waveform based on a timing signal supplied from timing generation circuit 35. It is prepared and applied to each of scan electrode SC (1) to scan electrode SC (n). The initialization waveform generation circuit generates an initialization waveform to be applied to scan electrode SC (1) to scan electrode SC (n) during the initialization period based on the timing signal. The sustain pulse generation circuit generates a sustain pulse to be applied to scan electrode SC (1) to scan electrode SC (n) during the sustain period based on the timing signal. The scan pulse generation circuit includes a plurality of scan electrode drive ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC (1) to scan electrode SC (n) during an address period based on a timing signal.

Sustain electrode drive circuit 34 includes a sustain pulse generation circuit and a circuit (not shown in FIG. 5) for generating voltage Ve, creates a drive voltage waveform based on the timing signal supplied from timing generation circuit 35, The voltage is applied to each of sustain electrode SU (1) to sustain electrode SU (n). In the sustain period, a sustain pulse is generated based on the timing signal and applied to sustain electrode SU (1) to sustain electrode SU (n).

The data electrode drive circuit 32 corresponds to each data electrode D (1) to data electrode D (m) based on the image data of each color output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. A write pulse is generated. Then, the data electrode drive circuit 32 applies the address pulse to the data electrodes D (1) to D (m) during the address period.

The data electrode driving circuit 32 has an output buffer provided for each of the data electrode D (1) to the data electrode D (m). This output buffer will be described with reference to FIG.

FIG. 6 is a circuit diagram schematically showing a configuration of an output buffer included in data electrode drive circuit 32 of plasma display device 30 according to the first exemplary embodiment of the present invention. FIG. 6 shows only circuit blocks that constitute the output buffer, and other circuit blocks are omitted.

The data electrode drive circuit 32 has m output buffers provided for each of the data electrodes D (1) to D (m). One output buffer has one high-voltage side switch QH that outputs the high-voltage side voltage Vd of the write pulse, and one low-voltage side switch QL that outputs the low-voltage side voltage 0 (V) of the write pulse. Therefore, the data electrode drive circuit 32 has m high-voltage side switches QH (1) to high-voltage side switches QH (m) and m low-voltage side switches QL (1) to low-voltage side switches QL (m). .

For example, in the case of the data electrode driving circuit 32 that drives the panel 10 having 1920 × 3 = 5760 discharge cells in one line, 5760 high-voltages that have 5760 output buffers and constitute 5760 output buffers. Side switch QH (1) to high voltage side switch QH (5760) and 5760 low voltage side switches QL (1) to low voltage side switch QL (5760).

Then, the data electrode driving circuit 32 turns on the low voltage side switch QL (j) corresponding to the data electrode D (j), thereby applying the low voltage side voltage 0 (V) of the write pulse to the data electrode D (j). Apply. In addition, the data electrode driving circuit 32 applies the high-voltage side voltage Vd of the write pulse to the data electrode D (j) by turning on the high-voltage side switch QH (j) corresponding to the data electrode D (j).

The data electrode driving circuit 32 applies the high voltage side voltage Vd of the write pulse or the low voltage side voltage 0 (V) of the write pulse to the data electrode D (1) to the data electrode D (m) for each write cycle of the write period to be described later. ).

Next, details of the address pulse applied to the data electrode D (1) to the data electrode D (m) will be described together with the operation of the data electrode drive circuit 32. FIG.

In the present embodiment, a first transition period Ta is provided at the beginning of each write cycle, and a second transition period Tb is provided at the end of each write cycle. This write cycle is a period from the start to the end of one write operation, for example, a cycle from the start of generation of one scan pulse to the end of generation.

When the address pulse is applied to the data electrode 22, the voltage applied to the data electrode 22 is changed from the low voltage side voltage 0 (V) to the high voltage side voltage Vd during the first transition period Ta. It is during the second transition period Tb that the voltage applied to is shifted from the high voltage Vd to the low voltage 0 (V).

FIG. 7 is a timing chart schematically showing an example of the operation of the data electrode driving circuit 32 of the plasma display device 30 in the first exemplary embodiment of the present invention.

FIG. 7 shows three address periods (address period T (i−1), address period T (i), address period T (i + 1)) in the address period as an example, and scan electrode SC (i−1) ) To scanning electrode SC (i + 1) and data electrode D (j−2) to driving electrode waveform applied to data electrode D (j + 3) by way of example.

FIG. 7 also shows that data electrode D (j-2), data electrode D (j-1), data electrode D (j) and data electrode D (j + 2) are written in address cycle T (i-1). A pulse is applied, no address pulse is applied to the data electrode D (j + 1) and the data electrode D (j + 3), and an address is written to the data electrode D (j + 1) and the data electrode D (j + 3) in the address period T (i). A pulse is applied, an address pulse is not applied to the data electrode D (j-2), the data electrode D (j-1), the data electrode D (j), and the data electrode D (j + 2), and the address period T (i + 1 ), An address pulse is applied to data electrode D (j−1), data electrode D (j) and data electrode D (j + 3), and data electrode D (j−2), data electrode D (j + 1) and data electrode are applied. Write to D (j + 2) An example applying no pulse.

Although not shown in FIG. 7, in the example described below, in the write cycle T (i-2) immediately before the write cycle T (i-1), the data electrode D (j-2) to the data electrode It is assumed that no write pulse is applied to D (j + 3).

In the write cycle T (i-1), a negative polarity scan pulse of voltage Va is applied to the scan electrode SC (i-1) of the (i-1) th line.

Then, an address pulse is applied to the data electrode D (j-2), the data electrode D (j-1), the data electrode D (j), and the data electrode D (j + 2).

That is, at the start time t1 of the first transition period Ta in the write cycle T (i−1), the high-voltage side switch QH (j−2) and the high-voltage side switch QH (j−1) of the output buffer included in the data electrode driving circuit 32. ), The high-voltage side switch QH (j) and the high-voltage side switch QH (j + 2) are turned on, and the data electrode D (j-2), the data electrode D (j-1), the data electrode D (j), and the data electrode D The high voltage Vd is applied to (j + 2), and the voltage of the data electrodes 22 is changed from the low voltage 0 (V) to the high voltage Vd.

Thus, an address pulse of voltage Vd is applied to data electrode D (j-2), data electrode D (j-1), data electrode D (j), and data electrode D (j + 2). The address discharge is generated in the discharge cell on the (i-1) th line to which the scan pulse and the address pulse are simultaneously applied.

Then, after the occurrence of the address discharge until the time t21, the high voltage side switch QH (j-2), the high voltage side switch QH (j-1), the high voltage side switch QH (j) and the high voltage side switch QH (j + 2) Turn off.

Next, in the second transition period Tb, the voltage of the data electrode D (j−2), the data electrode D (j−1), the data electrode D (j), and the data electrode D (j + 2) is decreased from the high-voltage side voltage Vd. The side voltage is changed to 0 (V). At this time, in the present embodiment, as shown in FIG. 7, the start time of the second transition period Tb is set to a different time for each of the data electrodes 22.

Specifically, the start time of the second transition period Tb is set to one of the earliest start time t21, the next start time t22, and the latest start time t23 for each of the data electrodes 22.

In the example shown in FIG. 7, the start time t21 is the start time of the second transition period Tb in the data electrode D (j + 2), and the second transition period Tb in the data electrode D (j-2) and the data electrode D (j) The start time is the start time t22, and the start time of the second transition period Tb in the data electrode D (j−1) is the start time t23.

Hereinafter, in the write cycle T (i−1), the second transition period Tb starting from the start time t21 is referred to as “second transition period Tb1”, and the second transition period Tb starting from the start time t22 is referred to as “second transition period”. Period Tb2 ”, and the second transition period Tb starting from the start time t23 is referred to as“ second transition period Tb3 ”.

That is, at the start time t21 of the second transition period Tb1, the low voltage side switch QL (j + 2) of the output buffer is turned on, and the voltage of the data electrode D (j + 2) is changed from the high voltage side voltage Vd to the low voltage side voltage 0 (V). Let Further, at the start time t22 of the second transition period Tb2, the low voltage side switch QL (j-2) and the low voltage side switch QL (j) of the output buffer are turned on, and the data electrode D (j-2) and the data electrode D ( The voltage j) is transitioned from the high voltage Vd to the low voltage 0 (V). Further, at the start time t23 of the second transition period Tb3, the low voltage side switch QL (j-1) of the output buffer is turned on, and the voltage of the data electrode D (j-1) is changed from the high voltage side voltage Vd to the low voltage side voltage 0 ( Transition to V).

Thus, the second transition period Tb in the write cycle T (i-1) ends.

During this time, the operation of returning the voltage of the scan electrode SC (i-1) of the (i-1) -th line from the voltage Va to the voltage Vc is started, and the voltage of the scan electrode SC (i-1) becomes the voltage Vc. Thus, the write cycle T (i−1) ends.

As described above, write pulses are applied to the data electrodes D (1) to D (m) from the output buffers corresponding to the data electrodes 22 at different timings.

Next, in the write cycle T (i), a negative scan pulse of voltage Va is applied to the scan electrode SC (i) on the (i) line.

Then, an address pulse is applied to the data electrode D (j + 1) and the data electrode D (j + 3).

That is, at the start time t3 of the first transition period Ta in the write cycle T (i), the high-voltage side switch QH (j + 1) and the high-voltage side switch QH (j + 3) of the output buffer included in the data electrode driving circuit 32 are turned on. The high voltage side voltage Vd is applied to the data electrode D (j + 1) and the data electrode D (j + 3), and the voltage of the data electrode 22 is changed from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

Thus, an address pulse of voltage Vd is applied to the data electrode D (j + 1) and the data electrode D (j + 3). The address discharge is generated in the discharge cell on the (i) line to which the scan pulse and the address pulse are simultaneously applied.

Then, the high-voltage side switch QH (j + 1) is turned off between the occurrence of the address discharge and the time t41. Note that, in the subsequent address period T (i + 1), the address pulse is applied to the data electrode D (j + 3), so that the high voltage side switch QH (j + 3) is kept on.

Next, in the second transition period Tb (referred to as “second transition period Tb1” in FIG. 7) in the write cycle T (i), the voltage of the data electrode D (j + 1) is changed from the high-voltage side voltage Vd to the low-voltage side voltage. Transition to 0 (V).

That is, at the start time t41 of the second transition period Tb1 in the write cycle T (i), the low-voltage side switch QL (j + 1) of the output buffer is turned on, and the voltage of the data electrode D (j + 1) is changed from the high-voltage side voltage Vd to the low-voltage side. Transition to voltage 0 (V).

Thus, the second transition period Tb in the write cycle T (i) ends.

During this time, the operation of returning the voltage of the scan electrode SC (i) on the (i) line from the voltage Va to the voltage Vc is started, and the voltage of the scan electrode SC (i) becomes the voltage Vc and the write cycle T (I) ends.

Next, in the write cycle T (i + 1), a negative scan pulse of voltage Va is applied to the scan electrode SC (i + 1) of the (i + 1) -th line.

Then, an address pulse is applied to the data electrode D (j−1), the data electrode D (j), and the data electrode D (j + 3).

That is, at the start time t5 of the first transition period Ta in the write cycle T (i + 1), the high voltage side switch QH (j−1) and the high voltage side switch QH (j) of the output buffer included in the data electrode driving circuit 32 are turned on. Thus, the high voltage side voltage Vd is applied to the data electrode D (j−1) and the data electrode D (j), and the voltage of the data electrode 22 is changed from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

Note that, since the high-voltage side switch QH (j + 3) is kept on from the second transition period Tb1 of the write cycle T (i), the data electrode D is output during the first transition period Ta of the write cycle T (i + 1). The voltage (j + 3) remains the high voltage Vd.

In this manner, when the address pulse of the voltage Vd is applied to the data electrode D (j−1), the data electrode D (j), and the data electrode D (j + 3), the scan pulse and the address pulse are simultaneously applied (i + 1). ) Address discharge occurs in the discharge cells on the line.

The high-voltage side switch QH (j−1) and the high-voltage side switch QH (j + 3) are turned off after the address discharge occurs until time t61. Note that, in the subsequent address period T (i + 2), the address pulse is applied to the data electrode D (j), so that the high-voltage side switch QH (j) remains on.

Next, in the second transition period Tb, the voltage of the data electrode D (j−1) and the data electrode D (j + 3) is transitioned from the high voltage side voltage Vd to the low voltage side voltage 0 (V).

At this time, in the example shown in FIG. 7, the start time of the second transition period Tb is set to a relatively early start time t61 with respect to the data electrode D (j−1), and the data electrode D (j + 3) Is set to a relatively late start time t62.

Hereinafter, in the write cycle T (i + 1), the second transition period Tb starting from the start time t61 is referred to as “second transition period Tb1”, and the second transition period Tb starting from the start time t62 is referred to as “second transition period Tb2”. "

That is, at the start time t61 of the second transition period Tb1, the low-voltage side switch QL (j-1) of the output buffer is turned on, and the voltage of the data electrode D (j-1) is changed from the high-voltage side voltage Vd to the low-voltage side voltage 0 ( Transition to V). Further, at the start time t62 of the second transition period Tb2, the low-voltage side switch QL (j + 3) of the output buffer is turned on, and the voltage of the data electrode D (j + 3) is changed from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V). Let

Thus, the second transition period Tb in the write cycle T (i + 1) ends.

During this time, the operation of returning the voltage of the scan electrode SC (i + 1) of the (i + 1) -th line from the voltage Va to the voltage Vc is started, and the voltage of the scan electrode SC (i + 1) becomes the voltage Vc and the write cycle T (I + 1) ends.

In the present embodiment, the first transition period Ta and the second transition period Tb do not overlap in time, and the first transition period Ta and the second transition period Tb are separated in time. .

That is, the second transition period Tb in the write cycle T (i-2) and the first transition period Ta in the write cycle T (i-1) do not overlap in time, and in the write cycle T (i-1). The second transition period Tb and the first transition period Ta in the write period T (i) do not overlap in time, and the second transition period Tb in the write period T (i) and the first in the write period T (i + 1). The transition period Ta does not overlap in time, and the second transition period Tb in the write cycle T (i + 1) and the first transition period Ta in the write cycle T (i + 2) do not overlap in time.

As described above, the output buffer of the data electrode driving circuit 32 in the present embodiment turns on the high-voltage side switch QH in the first transition period Ta provided in each of the write cycles, and the output voltage is reduced to the low-voltage side voltage. Transition from 0 (V) to the high voltage Vd. The output buffer is provided in each of the write cycles and turns on the low-voltage side switch QL in the second transition period Tb that does not overlap with the first transition period Ta in time, and the output voltage is lowered from the high-voltage side voltage Vd. The side voltage is changed to 0 (V).

Thus, power can be supplied from the power supply having a constant voltage Vd to the data electrode driving circuit 32 to perform a stable addressing operation, and the power consumption of the data electrode driving circuit 32 can be reduced. The reason will be described below with reference to FIGS. 8A to 8E.

FIG. 8A is a circuit diagram schematically showing a configuration of an output buffer provided in data electrode drive circuit 32 of plasma display device 30 in accordance with the first exemplary embodiment of the present invention.

FIG. 8B is a diagram schematically showing an example of the operation state of the output buffer provided in the data electrode drive circuit 32 of the plasma display device 30 in accordance with the first exemplary embodiment of the present invention.

FIG. 8C is a diagram schematically showing another example of the operation state of the output buffer provided in the data electrode driving circuit 32 of the plasma display device 30 in accordance with the first exemplary embodiment of the present invention.

FIG. 8D is a diagram schematically showing another example of the operation state of the output buffer provided in the data electrode driving circuit 32 of the plasma display device 30 according to the first exemplary embodiment of the present invention.

FIG. 8E is a diagram schematically showing another example of the operating state of the output buffer provided in the data electrode driving circuit 32 of the plasma display device 30 in accordance with the first exemplary embodiment of the present invention.

For ease of explanation, FIG. 8A shows an output buffer that drives the data electrode D (j) and an output buffer that drives the data electrode D (j + 1), and FIGS. 8A schematically shows a current flowing through each output buffer shown in FIG. 8A. 8A to 8E, the interelectrode capacitance generated between the data electrode D (j) and the data electrode D (j + 1) is represented by a capacitor Cc.

Hereinafter, the data electrode D (j) transitions from a state where no address pulse is applied to a state where an address pulse is applied, and the data electrode D (j + 1) transitions from a state where the address pulse is applied to the address pulse. Consider the case of transition to a state where no voltage is applied.

In this case, as shown in FIG. 8B, in the initial state, the terminal voltage on the data electrode D (j) side of the capacitor Cc is the low voltage 0 (V) of the write pulse, and the data electrode D (j + 1) side Is a high-voltage side voltage Vd of the write pulse.

For comparison with the operation in the present embodiment, when the first transition period Ta and the second transition period Tb are not temporally separated and the voltages at both ends of the capacitor Cc are simultaneously shifted, that is, data The operation of transitioning the voltage of the electrode D (j) from the low-voltage side voltage 0 (V) to the high-voltage side voltage Vd and the voltage of the data electrode D (j + 1) are transitioned from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V). Consider a case in which operations are performed simultaneously.

In this case, as shown in FIG. 8C, the high-voltage side switch QH (j) connected to the data electrode D (j) and the low-voltage side switch QL (j + 1) connected to the data electrode D (j + 1) are simultaneously Turn on. Therefore, the current Ic flows from the power source of the voltage Vd to the high voltage side switch QH (j), the capacitor Cc, the low voltage side switch QL (j + 1), and the ground potential. As a result, the capacitor Cc is charged, the one terminal voltage of the capacitor Cc (that is, the voltage on the data electrode D (j) side) becomes the high voltage Vd, and the other terminal voltage of the capacitor Cc (that is, the data electrode D). (Voltage on the side of (j + 1)) is the low voltage 0 (V).

At this time, the voltage between the terminals of the capacitor Cc (the voltage of the data electrode D (j) with the data electrode D (j + 1) as a reference) changes from the voltage (−Vd) to the voltage Vd. Therefore, the charge supplied from the power source to charge the capacitor Cc is
Q = Cc × 2Vd
The power at that time is QV = 2Cc × Vd × Vd
It becomes.

On the other hand, in the present embodiment, the first transition period Ta and the second transition period Tb are temporally separated. Therefore, first, from the initial state shown in FIG. 8B, the low-voltage side switch QL (j + 1) is turned on in the second transition period Tb. As a result, as shown in FIG. 8D, a current Id flows from the ground potential to the parasitic diode of the low-voltage side switch QL (j), the capacitor Cc, the low-voltage side switch QL (j + 1), and the ground potential. As a result, the capacitor Cc is discharged, and the two terminal voltages of the capacitor Cc (that is, the voltages of the data electrode D (j) and the data electrode D (j + 1)) are both set to the low voltage 0 (V).

Thereafter, the high-voltage side switch QH (j) is turned on in the first transition period Ta. As a result, as shown in FIG. 8E, a current Ie flows from the power source of the voltage Vd to the high-voltage side switch QH (j), the capacitor Cc, the low-voltage side switch QL (j + 1), and the ground potential. Thereby, the capacitor Cc is charged. As a result, the capacitor Cc is charged, the one terminal voltage of the capacitor Cc (that is, the voltage on the data electrode D (j) side) becomes the high voltage Vd, and the other terminal voltage of the capacitor Cc (that is, the data electrode D). (Voltage on the side of (j + 1)) is the low voltage 0 (V).

At this time, the voltage between the terminals of the capacitor Cc (the voltage of the data electrode D (j) when the data electrode D (j + 1) is used as a reference) changes from the voltage 0 (V) to the voltage Vd. Therefore, the charge supplied from the power source to charge the capacitor Cc is
Q = Cc × Vd
The power at that time is QV = Cc × Vd × Vd
It becomes. This power is not temporally separated from the first transition period Ta and the second transition period Tb, and is half the power (QV = 2Cc × Vd × Vd) when the voltages at both ends of the capacitor Cc are transitioned simultaneously. It is.

As described above, when the voltages of the two adjacent data electrodes 22 transition to voltages having opposite phases to each other (that is, the voltage of one data electrode 22 changes from the low voltage 0 (V) to the high voltage Vd. When the voltage of the other data electrode 22 transits from the high voltage Vd to the low voltage 0 (V)), the first transition period Ta and the second transition period Tb are separated in time. Thus, compared with the case where the first transition period Ta and the second transition period Tb overlap in time, the power required for charging / discharging the interelectrode capacitance Cc can be reduced to approximately half.

The above is the reason why the power of the data electrode driving circuit 32 can be reduced in the plasma display device 30 according to the first exemplary embodiment of the present invention.

Next, the reason why the start time of the second transition period Tb is set to a different time for each of the data electrodes 22 will be described.

As described above, the load capacitance of the data electrode 22 (for example, the data electrode D (j)) includes the capacitance Cg generated between the display electrode pair 14 and the data electrode 22 (for example, the data electrode D ( j + 1)) and the capacitance Cc generated between the data electrode 22 adjacent to the left side (for example, the data electrode D (j−1)) (Cg + 2Cc).

However, when the voltage applied to the data electrode D (j) is transitioned, the substantial additional capacitance viewed from the output buffer is applied to the adjacent data electrode D (j + 1) and data electrode D (j−1). Varies depending on the voltage.

For example, consider the load capacitance of the data electrode D (j−1) in the second transition period Tb of the write cycle T (i−1) shown in FIG. The voltage applied to the data electrode D (j−1) transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V). The voltage applied to each of the data electrode D (j-2) and the data electrode D (j) adjacent to the data electrode D (j-1) is similarly changed from the high voltage side voltage Vd to the low voltage side voltage 0 (V). Transition to.

Therefore, with respect to the data electrode D (j−1) in the second transition period Tb of the write cycle T (i−1), the capacitance Cc between the data electrode D (j−2) whose voltage transitions in the same direction and The capacitance Cc between the data electrode D (j) can be ignored. Therefore, the substantial load capacitance of the data electrode D (j−1) in the second transition period Tb of the write cycle T (i−1) is the capacitance Cg.

In the second transition period Tb of the write cycle T (i-1) shown in FIG. 7, the voltage applied to the data electrode D (j) transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V). Similarly, the voltage applied to the data electrode D (j−1) adjacent to the data electrode D (j) also changes from the high voltage side voltage Vd to the low voltage side voltage 0 (V). However, the voltage applied to the data electrode D (j + 1) adjacent to the data electrode D (j) remains unchanged at the low voltage 0 (V).

Therefore, regarding the data electrode D (j) in the second transition period Tb of the write cycle T (i−1), the capacitance Cc between the data electrode D (j−1) whose voltage transitions in the same direction is ignored. be able to. However, the capacitance Cc between the data electrode D (j + 1) cannot be ignored. Therefore, the substantial load capacitance of the data electrode D (j) in the second transition period Tb of the write cycle T (i−1) is the capacitance (Cg + Cc).

Therefore, in the second transition period Tb of the write cycle T (i−1), the time required to transition the voltage of the data electrode D (j) from the high voltage side voltage Vd to the low voltage side voltage 0 (V) is It becomes longer than the time required for the voltage of D (j−1) to transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V).

In the second transition period Tb of the write cycle T (i−1) shown in FIG. 7, the voltage applied to the data electrode D (j + 2) transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V). However, the voltage applied to the data electrode D (j + 1) and the data electrode D (j + 3) adjacent to the data electrode D (j + 2) remains the low voltage 0 (V).

Therefore, for the data electrode D (j + 2) in the second transition period Tb of the write cycle T (i−1), the capacitance Cc between the data electrode D (j + 1) and the capacitance between the data electrode D (j + 3) Both Cc cannot be ignored. Therefore, the substantial load capacitance of the data electrode D (j + 2) in the second transition period Tb of the write cycle T (i−1) is the capacitance (Cg + 2Cc).

Therefore, in the second transition period Tb of the write cycle T (i−1), the time required for the voltage of the data electrode D (j + 2) to transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) is It becomes longer than the time required for the voltage of D (j) to transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V).

As described above, the substantial load capacity that affects the transition of the voltage applied to the data electrode 22 varies according to the image data. That is, when the voltage applied to the data electrode 22 of interest and the voltage applied to the two data electrodes 22 adjacent to the data electrode 22 of interest transition in the same way, the substantial load capacitance at the data electrode 22 of interest is The capacity is Cg. In addition, when only the voltage applied to the data electrode 22 of interest and the voltage applied to one data electrode 22 adjacent to the data electrode 22 of interest change in the same manner, the substantial load capacitance at the data electrode 22 of interest is Capacity (Cg + Cc). In addition, when the voltage applied to the data electrode 22 of interest transitions and the voltages applied to the two data electrodes 22 adjacent to the data electrode 22 of interest do not change, the substantial load capacitance at the data electrode 22 of interest is Capacity (Cg + 2Cc).

And, the time required to transition the voltage applied to the data electrode 22 becomes longer as the substantial load capacity generated in the data electrode 22 becomes larger.

For these reasons, in the present embodiment, the start time of the second transition period is set for each of the output buffers according to the substantial load capacity generated in the data electrode 22.

That is, in the second transition period, one of the two adjacent data electrodes 22 (for example, the data electrode D (j−1) and the data electrode D (j + 1)) (for example, the data electrode D ( In the output buffer corresponding to the data electrode 22 (for example, the data electrode D (j)) in which only the voltage applied to j-1)) transits from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V), The data electrode 22 (for example, the data electrode 22 (for example, the data electrode D (j-2) and the data electrode D (j)) of which the voltage applied to the data electrode 22 (for example, the data electrode D (j-2) and the data electrode D (j)) transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V). The start time of the second transition period is set earlier than the output buffer corresponding to the data electrode D (j−1)).

Further, in the second transition period, the data electrode 22 (for example, the data electrode D) in which the voltage applied to the two adjacent data electrodes 22 (for example, the data electrode D (j + 1) and the data electrode D (j + 3)) does not transition together. In the output buffer corresponding to (j + 2)), one of the two adjacent data electrodes 22 (for example, the data electrode D (j−1) and the data electrode D (j + 1)) (for example, the data electrode 22 Than the output buffer corresponding to the data electrode 22 (for example, the data electrode D (j)) in which only the voltage applied to the electrode D (j-1)) transitions from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V). The start time of the second transition period is set to an early time.

As described above, in the present embodiment, it is known in advance that the time required for the voltage applied to the data electrode 22 to transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) is relatively long. For the data electrode 22, the start time of the second transition period is set relatively early. As a result, the end time of the second transition period in each data electrode 22 can be made substantially the same time (for example, time t3) regardless of the substantial load capacitance. Therefore, it is possible to effectively use the time required for the write operation in the write period. For example, in the data electrode 22 having a relatively small substantial load capacity, the time for applying the high-voltage side voltage Vd of the write pulse can be made relatively long.

Next, details of the data electrode drive circuit 32 will be described with reference to FIG.

FIG. 9 is a circuit diagram schematically showing the configuration of the data electrode driving circuit 32 of the plasma display device 30 according to the first embodiment of the present invention. In FIG. 9, only a part of the circuit blocks constituting the data electrode drive circuit 32 is shown, and other circuit blocks having the same configuration are omitted.

The data electrode drive circuit 32 includes a shift register unit 41, a self load calculation unit 42, an adjacent load calculation unit 44, and an output buffer unit 48.

The shift register unit 41 is a shift register. The shift register unit 41 includes the same number of latches 141 as the number of N (for example, N = 1920 × 3) data electrodes 22 driven by the data electrode driving circuit 32 or more. Each latch 141 is connected in series, and the input signal is forwarded (shifted) to the subsequent latch 141 in synchronization with the clock signal (clock Dck). Then, serial data transmitted from a data converter (not shown) is converted into parallel data.

Serial data is data expressed in the form of a plurality of bit signals that are temporally continuous so that a plurality of bit signals constituting one data can be transmitted by one signal line. For example, if the data is composed of 8 bits, it becomes 8 bit signals continuous in time.

Parallel data refers to data expressed in a format that can be transmitted through the same number of signal lines as bit signals so that a plurality of bit signals constituting one data can be transmitted at the same timing in synchronization with one clock signal. It is. For example, if the data is composed of 8 bits, it becomes 8 parallel bit signals that change at the same timing according to the change of the data, and can be transmitted in parallel by 8 signal lines.

Although not shown, the data conversion unit is provided between the image signal processing circuit 31 and the data electrode driving circuit 32, and receives image data (images assigned to each discharge) transmitted from the image signal processing circuit 31. Data) is converted into data for each subfield. This conversion will be described.

For example, if one field is composed of eight subfields (subfield SF1 to subfield SF8), the image data is 8-bit data. Each bit data of the image data represents light emission / non-light emission in each subfield of subfield SF1 to subfield SF8. Since the panel 10 is driven by the subfield method, each discharge cell of the panel 10 needs to be controlled to emit or not emit light for each subfield. Therefore, if the image data is used as it is, the light emission / non-light emission of each discharge cell cannot be controlled for each subfield.

In order to drive the panel 10 by the subfield method, for example, in the subfield SF1, only the bit data corresponding to the subfield SF1 of the image data assigned to each discharge cell is extracted as one data, In SF2, it is necessary to extract only the bit data corresponding to the subfield SF2 of the image data assigned to each discharge cell to be one data. The data conversion unit performs this conversion.

That is, for each subfield, the data conversion unit extracts only the bit data corresponding to the subfield from the image data assigned to each discharge cell and performs conversion into one data.

The data is transmitted as serial data to the shift register unit 41. The shift register unit 41 converts a plurality of bits of serial data corresponding to the subfield transmitted from the data conversion unit into parallel data.

Hereinafter, of the image data, the bit image data corresponding to the subfield SFQ is referred to as “image data Q”. That is, the shift register unit 41 receives N-bit serial image data Q corresponding to each of the N data electrodes 22 transmitted from the data conversion unit, and N-bit parallel image data corresponding to each of the N data electrodes 22. Is converted into image data Q and output.

The self-load calculating unit 42 includes N 1-line delays 142 and logic gates 43 corresponding to the N (for example, N = 1920 × 3) data electrodes 22 driven by the data electrode driving circuit 32.

Hereinafter, the configuration and operation of the data electrode driving circuit 32 will be described by taking as an example the case of calculating the substantial load capacity in the data electrode D (j). Therefore, the configuration and operation of data electrode driving circuit 32 described below are the configuration and operation for data electrode D (j), but the configuration and operation for other data electrode 22 are also the configuration and operation for data electrode D (j). It is the same.

It is assumed that the data electrode 22 adjacent to the data electrode D (j) is the data electrode D (j−1) and the data electrode D (j + 1).

The 1-line delay 142 (j) delays the image data Q (j) corresponding to the data electrode D (j) by 1 line (1 horizontal synchronization period) and outputs the image data DQ (j).

The logic gate 43 (j) is an AND gate with two inputs and one output (a logic circuit that performs an AND operation). In FIG. 9, the small circles at the input terminals of the logic gates are inverters (logic circuits that perform logic inversion). Therefore, a signal obtained by inverting the image data Q (j) is input to the logic gate 43 (j).

The logic gate 43 (j) detects a change in the voltage applied to the data electrode D (j) based on the image data DQ (j) and the image data Q (j).

When the image data DQ (j) is “H” and the image data Q (j) is “L”, the output of the logic gate 43 (j) is “H”. Therefore, if the output of the logic gate 43 (j) is “H”, the image data Q (j) changes from “H” to “L”, and the voltage applied to the data electrode D (j) is the high voltage side voltage. It can be determined that the voltage changes from Vd to the low voltage 0 (V) (from “H” to “L”).

In other cases, the output of the logic gate 43 (j) is “L”. At this time, the image data Q (j) maintains the “L” state or the “H” state, and the voltage applied to the data electrode D (j) is also the low-voltage side voltage 0 (V) (“L”). Or the high voltage side voltage Vd (“H”).

The adjacent load calculation unit 44 has a logic circuit provided corresponding to each of the data electrodes 22. This logic circuit includes a logic gate 144, a logic gate 45, a logic gate 46, and a logic gate 47. Therefore, the adjacent load calculation unit 44 has N logic circuits corresponding to N (for example, N = 1920 × 3) data electrodes 22 driven by the data electrode driving circuit 32, and N logic circuits Each circuit includes a logic gate 144, a logic gate 45, a logic gate 46, and a logic gate 47.

The logic gate 144, the logic gate 45, and the logic gate 46 are AND gates having two inputs and one output, and the logic gate 47 is an OR gate having two inputs and one output (a logic circuit that performs an OR operation).

A logic circuit including the logic gate 144 (j), the logic gate 45 (j), the logic gate 46 (j), and the logic gate 47 (j) illustrated in FIG. 9 includes a data electrode D (j) and a data electrode D. This is a circuit for detecting a change in image data corresponding to the data electrode D (j−1) and the data electrode D (j + 1) adjacent to (j). In the present embodiment, the substantial load capacitance of the data electrode D (j) is calculated based on the detection result.

Both the image data Q (j−1) of the data electrode D (j−1) and the image data Q (j + 1) of the data electrode D (j + 1) do not change (maintain “L” state or “H” state) Is maintained), the output of the logic gate 46 (j) becomes “H”. At this time, the substantial load capacity of the data electrode D (j) when the image data Q (j) of the data electrode D (j) changes from “H” to “L” in the second transition period Tb is described above. As shown, the capacity is (Cg + 2Cc). Therefore, if the output of the logic gate 46 (j) is “H”, it can be determined that the substantial load capacitance of the data electrode D (j) in the second transition period Tb is the capacitance (Cg + 2Cc).

Only one of the image data Q (j−1) of the data electrode D (j−1) and the image data Q (j + 1) of the data electrode D (j + 1) changes from “H” to “L”. Sometimes, the output of the logic gate 47 (j) becomes “H”. At this time, the substantial load capacity of the data electrode D (j) when the image data Q (j) of the data electrode D (j) changes from “H” to “L” in the second transition period Tb is described above. As shown, the capacitance is (Cg + Cc). Therefore, if the output of the logic gate 47 (j) is “H”, it can be determined that the substantial load capacitance of the data electrode D (j) in the second transition period Tb is the capacitance (Cg + Cc).

When both the image data Q (j−1) of the data electrode D (j−1) and the image data Q (j + 1) of the data electrode D (j + 1) change from “H” to “L”, the logic gate 46 (j ) And the output of the logic gate 47 (j) are both “L”. At this time, the substantial load capacity of the data electrode D (j) when the image data Q (j) of the data electrode D (j) changes from “H” to “L” in the second transition period Tb is described above. As shown, the capacity is Cg. Therefore, if both the output of the logic gate 46 (j) and the output of the logic gate 47 (j) are “L”, the substantial load capacitance of the data electrode D (j) in the second transition period Tb is the capacitance Cg. It can be judged that there is.

The above is the operation of the adjacent load calculation unit 44 that calculates the substantial load capacity at the data electrode D (j).

The output buffer unit 48 includes N output buffers 148 corresponding to each of N (for example, N = 1920 × 3) data electrodes 22 driven by the data electrode driving circuit 32. Each output buffer 148 generates an address pulse to be applied to the data electrode 22.

The output buffer unit 48 includes N high-voltage switches QH, N low-voltage switches QL, and N HL timing controllers 49. For example, if N = 1920 × 3, the output buffer unit 48 includes the high voltage side switch QH (1) to the high voltage side switch QH (5760), and the low voltage side switch QL (1) to the low voltage side switch QL (5760). HL timing control unit 49 (1) to HL timing control unit 49 (5760).

As shown in FIG. 9, in this embodiment, each output buffer 148 includes a circuit combining one high-voltage side switch QH and one low-voltage side switch QL, and one HL timing control unit 49. Have.

The high voltage side switch QH outputs the voltage Vd on the high voltage side of the write pulse, and the low voltage side switch QL outputs the voltage 0 (V) on the low voltage side of the write pulse.

The HL timing control unit 49 controls the high-voltage side switch QH and the low-voltage side switch QL based on the signals output from the adjacent load calculation unit 44 (the output signal of the logic gate 46 and the output signal of the logic gate 47). That is, the HL timing control unit 49 controls the timing at which the voltage applied to the data electrode 22 transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V) based on the signal output from the adjacent load calculation unit 44.

For example, if the output of the logic gate 46 (j) is “H”, the HL timing control unit 49 (j) reduces the voltage applied to the data electrode D (j) from the high-voltage side voltage Vd to the low voltage side. When transitioning to the side voltage 0 (V), the second transition period starts at the earliest timing (for example, time t21) so that the time length of the second transition period becomes the longest.

In addition, when the output of the logic gate 47 (j) is “H”, the HL timing control unit 49 (j) reduces the voltage applied to the data electrode D (j) from the high-voltage side voltage Vd to the low voltage side. At the time of transition to the side voltage 0 (V), the second transition period is started at the second earliest timing (for example, time t22) so that the time length of the second transition period becomes the second longest.

The HL timing control unit 49 (j) applies the data electrode D (j) to the data electrode D (j) in the second transition period if both the output of the logic gate 46 (j) and the output of the logic gate 47 (j) are “L”. When the applied voltage transitions from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V), the second transition period is at the latest timing (for example, time t23) so that the time length of the second transition period becomes the shortest. To start.

As described above, the plasma display device 30 in the present embodiment calculates the substantial load capacity between the adjacent data electrodes 22 in the second transition period. Then, the start time when the voltage applied to the data electrode 22 is changed from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) according to the substantial load capacitance between the adjacent data electrodes 22. That is, the start time of the second transition period is controlled.

Then, the data electrode drive circuit 32 finishes transition of all voltages applied to the data electrodes 22 of the data electrode D (1) to the data electrode D (m) from the high voltage side voltage Vd to the low voltage side voltage 0 (V). After the second transition period ends, the subsequent first transition period starts and the voltage applied to the data electrode 22 transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

Thereby, it becomes possible to drive the panel 10 while effectively using the time required for the writing operation in the writing period.

(Embodiment 2)
In the first embodiment, the example in which the start time of the second transition period is set for each of the output buffers 148 has been described. However, the present invention is not limited to this configuration.

For example, when a data electrode driving circuit is configured by using a plurality of integrated circuits having a plurality of output buffers, the start time of the second transition period can be set for each of the integrated circuits. In the second embodiment, this configuration will be described.

FIG. 10 is a diagram schematically showing an example of a circuit block constituting the plasma display device 60 according to the second embodiment of the present invention.

The plasma display device 60 shown in the present embodiment includes a panel 10 and a drive circuit that drives the panel 10. The drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 62, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.

The plasma display device 60 shown in the present embodiment is different from the plasma display device 30 shown in FIG. 5 in the first embodiment in the configuration of the data electrode driving circuit 62, but the other circuit blocks are the same as the plasma display device 30. It has the same configuration and performs the same operation. Therefore, the same reference numerals as those shown in FIG. 5 are given to the circuit blocks having the same configuration and operation as those of the circuit block shown in FIG.

Similarly to the data electrode drive circuit 32, the data electrode drive circuit 62 is based on the image data of each color output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. -An address pulse corresponding to the data electrode D (m) is generated. Then, the data electrode drive circuit 32 applies the address pulse to the data electrodes D (1) to D (m) during the address period.

However, the data electrode driving circuit 62 has a plurality of integrated circuits. Each integrated circuit generates an address pulse that is applied to a predetermined number of data electrodes 22. This integrated circuit is hereinafter referred to as a “data driver”. In the present embodiment, the data driver 80 is configured as a monolithic IC, for example. Each data driver 80 generates an address pulse to be applied to, for example, 384 data electrodes 22. Panel 10 in the present embodiment has 1920 pixels in the horizontal direction. That is, the panel 10 has 1920 × 3 = 5760 discharge cells in one line. Therefore, the data electrode drive circuit 62 includes, for example, 15 data drivers 80 (data driver 80 (1) to data driver 80 (15)), and drives 5760 data electrodes 22.

FIG. 11 is a circuit diagram schematically showing a configuration of data electrode drive circuit 62 of plasma display device 60 in accordance with the second exemplary embodiment of the present invention. In FIG. 11, only a part of the circuit blocks constituting the data electrode driving circuit 62 is shown, and other circuit blocks having the same configuration are omitted.

The data electrode drive circuit 62 includes fifteen data drivers 80 (data driver 80 (1) to data driver 80 (15)), a maximum load calculation unit 72 provided corresponding to each of the data drivers 80, data And a timing pulse selector 74 provided corresponding to each of the drivers 80.

Hereinafter, the data drivers 80 (1) to 80 (15) are collectively referred to as “data driver 80 (p)”, and the maximum load calculation unit 72 corresponding to the data driver 80 (p) is referred to as the maximum load calculation unit 72. (P), and the timing pulse selector 74 corresponding to the data driver 80 (p) is referred to as a timing pulse selector 74 (p). In the present embodiment, p is a numerical value from 1 to 15.

The maximum load calculation unit 72 (p) calculates a substantial load capacity in each of the plurality of data electrodes 22 (for example, 384 data electrodes 22) driven by the data driver 80 (p), and calculates the calculated load capacity. The maximum value of is calculated.

The timing pulse selection unit 74 (p) has three timing signals LLP (a timing signal LLP1, a timing signal LLP2, and a timing signal LLP3) based on the substantial maximum value of the load capacity calculated by the maximum load calculation unit 72 (p). One of the timing signals LLP is selected. Then, the selected timing signal LLP is output as the write timing signal LP (p).

Here, the timing signal LLP1, the timing signal LLP2, and the timing signal LLP3 will be described.

FIG. 12 is a timing chart schematically showing an example of the operation of the data electrode drive circuit 62 of the plasma display device 60 in the second exemplary embodiment of the present invention.

In FIG. 12, the timing signal LLP1, the timing signal LLP2, the timing signal LLP3, the write timing signal LP (p) output from the timing pulse selector 74 (p), and the write output from the timing pulse selector 74 (p + 1) are shown. A timing signal LP (p + 1), an address pulse applied to the data electrode D (p), and an address pulse applied to the data electrode D (p + 1) are shown.

As shown in FIG. 12, the timing of rising of each timing signal LLP of the timing signal LLP1, the timing signal LLP2, and the timing signal LLP3 is the same. However, the timing of the fall of each timing signal LLP is the earliest timing signal LLP1, the next timing signal LLP2, and the latest timing signal LLP3.

In the present embodiment, the time when each timing signal LLP falls represents the start time of the second transition period, and the time when each timing signal LLP rises represents the start time of the first transition period.

Therefore, when the timing pulse selection unit 74 selects the timing signal LLP1 as the write timing signal LP, the time length of the second transition period becomes the longest. When the timing pulse selector 74 selects the timing signal LLP2 as the write timing signal LP, the time length of the second transition period becomes the second longest. When the timing pulse selector 74 selects the timing signal LLP3 as the write timing signal LP, the time length of the second transition period becomes the shortest.

The timing pulse selection unit 74 (p) generates a write timing signal LP based on the maximum value of the substantial load capacity of the plurality of data electrodes 22 (for example, 384 data electrodes 22) driven by the data driver 80 (p). Select.

Specifically, the timing pulse selection unit 74 (p) selects the timing signal LLP1 as the write timing signal LP (p) if the substantial maximum value of the load capacity in the second transition period is the capacity (Cg + 2Cc). To do. If the maximum value of the substantial load capacity in the second transition period is the capacity (Cg + Cc), the timing pulse selection unit 74 (p) selects the timing signal LLP2 as the write timing signal LP (p). Then, the timing pulse selection unit 74 (p) selects the timing signal LLP3 as the write timing signal LP (p) if the substantial maximum value of the load capacity in the second transition period is the capacity Cg.

Each of the data driver 80 (1) to the data driver 80 (15) includes a shift register unit 81, a data latch unit 83, and an output buffer unit 85.

The shift register unit 81 is a shift register. The shift register unit 81 has the same number of latches 82 as the number of N (for example, N = 384) data electrodes 22 driven by the data driver 80 or more. Each latch 82 is connected in series, and the input signal is forwarded (shifted) to the subsequent latch 82 in synchronization with the clock signal (clock Dck). And the serial data transmitted from the data converter (not shown) mentioned above are converted into parallel data.

That is, like the shift register unit 41, the shift register unit 81 outputs N pieces of N-bit serial image data Q corresponding to each of the N data electrodes 22 transmitted from the data conversion unit for each subfield. Are converted into N-bit parallel image data Q corresponding to each of the data electrodes 22 and output.

The data latch unit 83 includes N latches 84 corresponding to the N (for example, N = 384) data electrodes 22 driven by the data driver 80. Each latch 84 latches the image data Q corresponding to each data electrode 22 with the write timing signal LP and outputs the latched data to the output buffer unit 85.

The output buffer unit 85 includes N output buffers 86 corresponding to N (for example, N = 384) data electrodes 22 driven by the data driver 80. Each output buffer 86 generates an address pulse to be applied to the data electrode 22.

The output buffer unit 85 includes N high-voltage switches QH, N low-voltage switches QL, and N HL timing controllers 89. For example, if N = 384, the output buffer unit 85 includes the high voltage side switch QH (1) to the high voltage side switch QH (384), the low voltage side switch QL (1) to the low voltage side switch QL (384), and HL. Timing control unit 89 (1) to HL timing control unit 89 (384).

As shown in FIG. 11, in this embodiment, each output buffer 86 includes a circuit combining one high-voltage side switch QH and one low-voltage side switch QL, and one HL timing control unit 89. Have.

The high voltage side switch QH outputs the high voltage side voltage Vd of the write pulse, and the low voltage side switch QL outputs the low voltage side voltage 0 (V) of the write pulse.

The HL timing control unit 89 controls the high voltage side switch QH and the low voltage side switch QL based on the signal output from the latch 84 and the write timing signal LP. That is, the HL timing control unit 89 controls the timing at which the voltage applied to the data electrode 22 transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V) based on the write timing signal LP. As a result, each output buffer 86 generates a write pulse at a timing based on the write timing signal LP.

For example, the timing pulse selector 74 (p) corresponding to the data driver 80 (p) selects the timing signal LLP3 in the write cycle T (i-1), and selects the timing signal LLP1 in the write cycle T (i). In the write cycle T (i + 1), if the timing signal LLP2 is selected and output as the write timing signal LP (p), as shown in FIG. 12, the buffer unit 85 (p) of the data driver 80 (p) is selected. ) Generates a write pulse so that the second transition period starts at time t23 in the write cycle T (i-1), and starts the second transition period at time t41 in the write cycle T (i). And a write pulse is generated so that the second transition period starts at time t62 in the write cycle T (i + 1).

In addition, the timing pulse selector 74 (p + 1) corresponding to the data driver 80 (p + 1) selects the timing signal LLP1 in the write cycle T (i−1) and selects the timing signal LLP2 in the write cycle T (i). In the write cycle T (i + 1), if the timing signal LLP3 is selected and output as the write timing signal LP (p + 1), as shown in FIG. 12, the buffer unit 85 (p + 1) of the data driver 80 (p + 1) Generates a write pulse so that the second transition period starts at time t21 in the write period T (i-1), and starts the second transition period at time t42 in the write period T (i). Is written so that the second transition period starts at time t63 in the write cycle T (i + 1). It generates a write pulse to pulse to generation.

As described above, the plasma display device 60 according to the present exemplary embodiment has the second transition period start time based on the substantial maximum value of the load capacity generated in each of the plurality of data electrodes 22 driven by the data driver 80. Is set for each of the data drivers 80.

That is, the timing pulse selection unit 74 (p) selects the timing signal LLP1 as the write timing signal LP (p) if the substantial maximum value of the load capacity in the second transition period is the capacity (Cg + 2Cc). If the maximum value of the substantial load capacity in the second transition period is the capacity (Cg + Cc), the timing pulse selection unit 74 (p) selects the timing signal LLP2 as the write timing signal LP (p). Then, the timing pulse selection unit 74 (p) selects the timing signal LLP3 as the write timing signal LP (p) if the substantial maximum value of the load capacity in the second transition period is the capacity Cg.

In other words, in the plasma display device 60 according to the present exemplary embodiment, the voltage applied to at least one data electrode 22 of the two data electrodes 22 adjacent to each of both sides is low voltage 0 (V) in the second transition period. ) Without transition, or the data driver 80 (for example, the data driver 80 (p) in the write cycle T (i + 1)) having the data electrode 22 that does not transition as the high-voltage side voltage Vd is the start time ( For example, at time t62), the data driver 80 (for example, writing) in which the voltage applied to all the data electrodes 22 driven by the data driver 80 transitions from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) in the second transition period. Start of second transition period in data driver 80 (p + 1)) in period T (i + 1) Time (for example, time t63) is set at an earlier time than.

In the plasma display device 60, the voltage applied to all the data electrodes 22 driven by the data driver 80 does not change at the low voltage 0 (V) in the second transition period, or does not change at the high voltage Vd. The start time (for example, time t41) of the second transition period in the data driver 80 that does not perform (for example, the data driver 80 (p) in the write cycle T (i)) is the two data electrodes 22 adjacent to both sides. The data driver 80 (for example, writing) in which the data electrode 22 in which the applied voltage to at least one of the data electrodes 22 does not change as the low voltage side voltage 0 (V) or does not change as the high voltage side voltage Vd exists in the second transition period. Start time of second transition period in data driver 80 (p + 1) in period T (i) (example) If, time t42) is set at an earlier time than.

Thereby, in the second transition period, the data having the data electrode 22 having a relatively large substantial load capacity and a relatively long time length for transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V). In the driver 80, the substantial load capacity of the data electrode 22 is relatively small, and the time length required for the transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) is relatively short compared to the data driver 80. The start time of the two transition periods can be advanced. Therefore, the end times of the second transition periods can be made uniform among the data drivers 80.

Then, the data electrode drive circuit 62 finishes the transition of all voltages applied to the data electrodes 22 of the data electrodes D (1) to D (m) from the high voltage side voltage Vd to the low voltage side voltage 0 (V). After the second transition period ends, the subsequent first transition period starts and the voltage applied to the data electrode 22 transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

For example, in the plasma display device in which the start times of the second transition periods are set to the same time in the respective data drivers 80 regardless of the substantial difference in load capacity, the data drivers are displayed at the end times of the second transition periods. Differences between 80 are likely to occur.

Therefore, as compared with such a plasma display device, in the plasma display device 60 shown in the present embodiment, the second transition period and the first transition period that occurs immediately after the second transition period are temporally mutually different. It becomes easy to set the first transition period and the second transition period so as not to overlap. Therefore, it is possible to drive the panel 10 while effectively using the time required for the writing operation in the writing period.

In the first embodiment, the example in which the start time of the second transition period is set for each data electrode 22 based on the substantial load capacity has been described. In the second embodiment, the example in which the start time of the second transition period is set for each data driver 80 based on the substantial maximum value of the load capacity has been described. However, the present invention is not limited to this configuration.

For example, the start time of the first transition period may be set for each data electrode 22 or for each data driver 80. Alternatively, the start time of the first transition period and the start time of the second transition period may be set for each data electrode 22 or for each data driver 80.

Hereinafter, in the third and fourth embodiments, an example in which the start time of the first transition period is set for each data electrode 22 will be described.

(Embodiment 3)
In the third embodiment, when an address pulse is applied to the data electrode 22 in the address period, the voltage applied to the two data electrodes 22 adjacent to both sides in the immediately preceding second transition period is the high voltage side voltage. A configuration in which the start time of the first transition period in the data electrode 22 that does not transition from Vd to the low-voltage side voltage 0 (V) is relatively advanced will be described. Thereby, in the present embodiment, stable write operation and reduction of power consumption in the data electrode driving circuit are realized.

FIG. 13 is a circuit diagram schematically showing a configuration of data electrode driving circuit 132 of the plasma display device in accordance with the third exemplary embodiment of the present invention. FIG. 13 shows only a part of the circuit blocks constituting the data electrode driving circuit 132, and other circuit blocks having the same configuration are omitted.

The plasma display device in the present embodiment is different from the plasma display device 30 shown in FIG. 5 in the first embodiment in the configuration of the data electrode driving circuit 132. However, the other circuit blocks have the same configuration as the plasma display device 30 and perform the same operation. Therefore, only the data electrode driving circuit 132 will be described below.

The data electrode driving circuit 132 includes a shift register unit 41, a self load calculation unit 42, an adjacent load calculation unit 44, a self load calculation unit 50, an adjacent load calculation unit 54, and an output buffer unit 57.

Hereinafter, the self-load calculation unit 42 is referred to as a “first self-load calculation unit 42”, the self-load calculation unit 50 is referred to as a “second self-load calculation unit 50”, and the adjacent load calculation unit 44 is referred to as a “first self-load calculation unit 42”. The adjacent load calculator 54 is referred to as a “first adjacent load calculator 44”, and the adjacent load calculator 54 is referred to as a “second adjacent load calculator 54”.

Note that the shift register unit 41 in the present embodiment has the same configuration and operation as the shift register unit 41 described in the first embodiment. The first self-load calculation unit 42 has the same configuration and operation as the self-load calculation unit 42 described in the first embodiment. The first adjacent load calculation unit 44 has the same configuration and operation as the adjacent load calculation unit 44 described in the first embodiment. Therefore, description of these circuit blocks is omitted in this embodiment.

The second self-load calculating unit 50 includes N one-line delays 51, logic gates 52, and logic corresponding to each of N (for example, N = 1920 × 3) data electrodes 22 driven by the data electrode driving circuit 32. And a gate 53.

Hereinafter, the configuration and operation of the data electrode driving circuit 132 will be described by taking as an example the case where an address pulse is applied to the data electrode D (j). Therefore, the configuration and operation of data electrode drive circuit 132 described below are the configuration and operation for data electrode D (j), but the configuration and operation for other data electrode 22 are also the configuration and operation for data electrode D (j). It is the same.

The one-line delay 51 (j) in the second self-load calculating unit 50 is the image data Q (j) corresponding to the data electrode D (j), similarly to the one-line delay 142 (j) shown in the first embodiment. Is delayed by one line (one horizontal synchronization period) to output image data DQ (j).

The logic gate 52 (j) and the logic gate 53 (j) are 2-input 1-output AND gates (logic circuits that perform a logical product operation). In FIG. 13, small circles at the input terminals of the logic gates are inverters (logic circuits that perform logic inversion). Therefore, a signal obtained by inverting the image data Q (j) is input to the logic gate 52 (j), and a signal obtained by inverting the image data DQ (j) is input to the logic gate 53 (j).

The logic gate 52 (j) and the logic gate 53 (j) detect a change in the voltage applied to the data electrode D (j) based on the image data DQ (j) and the image data Q (j).

When the image data DQ (j) is “H” and the image data Q (j) is “L”, the output of the logic gate 52 (j) is “H”. Therefore, if the output of the logic gate 52 (j) is “H”, the image data Q (j) changes from “H” to “L”, and the voltage applied to the data electrode D (j) is the high voltage side voltage. It can be determined that the voltage changes from Vd to the low voltage 0 (V) (from “H” to “L”).

When the image data DQ (j) is “L” and the image data Q (j) is “H”, the output of the logic gate 53 (j) is “H”. Therefore, if the output of the logic gate 53 (j) is “H”, the image data Q (j) changes from “L” to “H”, and the voltage applied to the data electrode D (j) is the low voltage side voltage. It can be determined that the voltage changes from 0 (V) to the high-voltage side voltage Vd (from “L” to “H”).

In other cases, the output of the logic gate 52 (j) and the output of the logic gate 53 (j) are both “L”. At this time, the image data Q (j) maintains the “L” state or the “H” state, and the voltage applied to the data electrode D (j) is also the low-voltage side voltage 0 (V) (“L”). Or the high voltage side voltage Vd (“H”).

The second adjacent load calculation unit 54 has a logic circuit provided corresponding to each of the data electrodes 22. This logic circuit includes a logic gate 154, a logic gate 55, and a logic gate 56. Therefore, the second adjacent load calculation unit 54 has N logic circuits corresponding to each of N (for example, N = 1920 × 3) data electrodes 22 driven by the data electrode driving circuit 132, and N Each of the logic circuits includes a logic gate 154, a logic gate 55, and a logic gate 56.

The logic gate 154 and the logic gate 55 are AND gates having two inputs and one output, and the logic gate 56 is an OR gate having two inputs and one output (a logic circuit that performs an OR operation).

The logic circuit including the logic gate 154 (j), the logic gate 55 (j), and the logic gate 56 (j) shown in FIG. 13 has image data Q (j−1) corresponding to the data electrode D (j−1). ), A circuit for detecting changes in the image data Q (j) corresponding to the data electrode D (j) and the image data Q (j + 1) corresponding to the data electrode D (j + 1).

At least one of the image data Q (j−1) of the data electrode D (j−1) and the image data Q (j + 1) of the data electrode D (j + 1) changes from “H” to “L”, and When the image data Q (j) of the data electrode D (j) changes from “L” to “H”, the output of the logic gate 56 (j) becomes “H”.

This is because, in the first transition period, the voltage applied to the data electrode D (j) transits from the low voltage side voltage 0 (V) to the high voltage side voltage Vd, and the voltage and data applied to the data electrode D (j−1). This represents that at least one of the voltages applied to the electrode D (j + 1) transits from the high voltage side voltage Vd to the low voltage side voltage 0 (V).

In other cases, the output of the logic gate 56 (j) is “L”.

The output buffer unit 57 includes N high-voltage switches QH, N low-voltage switches QL, N LH timing controllers 58, and N HL timing controllers 59. For example, if N = 1920 × 3, the output buffer unit 57 includes the high voltage side switch QH (1) to the high voltage side switch QH (5760), the low voltage side switch QL (1) to the low voltage side switch QL (5760). , An LH timing control unit 58 (1) to an LH timing control unit 58 (5760) and an HL timing control unit 59 (1) to an HL timing control unit 59 (5760).

As shown in FIG. 13, in this embodiment, each output buffer 157 includes a circuit combining one high-voltage side switch QH and one low-voltage side switch QL, and one LH

timing control unit

58 and 1. Two HL timing control units 59.

Similarly to the HL timing control unit 49 shown in the first embodiment, the HL timing control unit 59 outputs signals from the first adjacent load calculation unit 44 (the output signal of the logic gate 46 and the output signal of the logic gate 47). Based on this, the high voltage side switch QH and the low voltage side switch QL are controlled, and the timing at which the voltage applied to the data electrode 22 transitions from the high voltage side voltage Vd to the low voltage side voltage 0 (V) is controlled.

For example, when the output of the logic gate 46 (j) is “H”, the HL timing control unit 59 (j) reduces the voltage applied to the data electrode D (j) from the high-voltage side voltage Vd to the low voltage side. When transitioning to the side voltage 0 (V), the second transition period starts at the earliest timing so that the time length of the second transition period becomes the longest.

In addition, when the output of the logic gate 47 (j) is “H”, the HL timing control unit 59 (j) reduces the voltage applied to the data electrode D (j) from the high-voltage side voltage Vd to the low voltage side. When transitioning to the side voltage 0 (V), the second transition period is started at the second earliest timing so that the time length of the second transition period is the second longest.

The HL timing control unit 59 (j) applies the data electrode D (j) to the data electrode D (j) in the second transition period if both the output of the logic gate 46 (j) and the output of the logic gate 47 (j) are “L”. When the voltage to be applied is changed from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V), the second transition period is started at the latest timing so that the time length of the second transition period becomes the shortest.

The LH timing control unit 58 controls the high-voltage side switch QH and the low-voltage side switch QL based on the signal output from the second adjacent load calculation unit 54 (the output signal of the logic gate 56), and determines the voltage to be applied to the data electrode 22. The timing of transition from the low-voltage side voltage 0 (V) to the high-voltage side voltage Vd is controlled.

For example, when the output of the logic gate 56 (j) is “H”, the LH timing control unit 58 (j), as in the first embodiment, the data electrodes D (1) to D (m). After all the voltages applied to each data electrode 22 have transitioned from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) and the second transition period has ended, the subsequent first transition period is started and the data electrode 22 The applied voltage transits from the low-voltage side voltage 0 (V) to the high-voltage side voltage Vd.

Further, when the output of the logic gate 56 (j) is “L”, the LH timing control unit 58 (j) performs the first transition at an earlier timing than when the output of the logic gate 56 (j) is “H”. Start the period. That is, if the output of the logic gate 56 (j) is “L”, the LH timing control unit 58 (j) starts the first transition period that follows before the end of the second transition period and applies the data electrode 22 to the data electrode 22. The applied voltage transits from the low-voltage side voltage 0 (V) to the high-voltage side voltage Vd.

FIG. 14 is a timing chart schematically showing an example of the operation of the data electrode drive circuit 132 of the plasma display device in accordance with the third exemplary embodiment of the present invention.

FIG. 14 shows four write cycles (write cycle T (i−1), write cycle T (i), write cycle T (i + 1), and write cycle T (i + 2)) in the write period as examples. The drive voltage waveforms applied to scan electrode SC (i−1) to scan electrode SC (i + 1) and data electrode D (j−2) to data electrode D (j + 3) will be described as an example.

In FIG. 14, in the write cycle T (i−1), a write pulse is applied to the data electrode D (j−2) and the data electrode D (j + 3), and the data electrode D (j−1), the data electrode No write pulse is applied to D (j), data electrode D (j + 1) and data electrode D (j + 2), and data electrode D (j−1), data electrode D (j), An address pulse is applied to the data electrode D (j + 1) and the data electrode D (j + 2), no address pulse is applied to the data electrode D (j-2) and the data electrode D (j + 3), and an address period T (i + 1) ), An address pulse is applied to the data electrode D (j-2) and the data electrode D (j + 3), and the data electrode D (j-1), the data electrode D (j), the data electrode D (j + 1), and the data electrode D (j + 2) In the write cycle T (i + 2), no write pulse is applied to the data electrode D (j-2), the data electrode D (j-1), the data electrode D (j + 1), and the data electrode D (j + 2). An example is shown in which the write pulse is not applied to the data electrode D (j) and the data electrode D (j + 3).

In the second transition period of the write cycle T (i−1), the voltage applied to the data electrode D (j−2) and the data electrode D (j + 3) is changed from the high voltage side voltage Vd to the low voltage side voltage 0 (V). Transition. In the first transition period of the write cycle T (i), the voltage applied to the data electrode D (j−1), the data electrode D (j), the data electrode D (j + 1), and the data electrode D (j + 2) is the low-voltage side voltage. Transition from 0 (V) to the high voltage Vd.

Accordingly, at this time, the outputs of the logic gate 52 (j−2) and the logic gate 52 (j + 3) of the second self-load calculating unit 50 are “H”, and the logic gate 53 (j−1) and the logic gate 53 (j ), The outputs of the logic gate 53 (j + 1) and the logic gate 53 (j + 2) are “H”.

Thereby, the outputs of the logic gate 56 (j−1) and the logic gate 56 (j + 2) of the second adjacent load calculating unit 54 become “H”, and the outputs of the logic gate 56 (j) and the logic gate 56 (j + 1) are “L”.

Since the outputs of the logic gate 56 (j−1) and the logic gate 56 (j + 2) are “H”, the LH timing control unit 58 (j−1) and the LH timing control unit 58 (j + 2) In the transition period (here, the second transition period of the write cycle T (i-1)), all the voltages applied to the data electrode 22 to which the voltage should be transitioned from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) At timing t33 after the transition from the side voltage Vd to the low voltage side voltage 0 (V), the voltage applied to the data electrode D (j-1) and the data electrode D (j + 2) is changed from the low voltage side voltage 0 (V). Transition to the high voltage Vd.

On the other hand, since the outputs of the logic gate 56 (j) and the logic gate 56 (j + 1) are “L” in the LH timing control unit 58 (j) and the LH timing control unit 58 (j + 1), the data electrode D (j) The voltage applied to the data electrode D (j + 1) starts to transition from the low-voltage side voltage 0 (V) to the high-voltage side voltage Vd at a timing t31 earlier than the timing t33.

In other words, the LH timing control unit 58 (j) and the LH timing control unit 58 (j + 1) have a voltage applied to the data electrode D (j-2) and the data electrode D (j + 3) from the high voltage side voltage Vd to the low voltage side voltage 0. Before the transition to (V) is completed, the operation of transitioning the voltage applied to the data electrode D (j) and the data electrode D (j + 1) from the low voltage side voltage 0 (V) to the high voltage side voltage Vd is started.

In the second transition period of the write cycle T (i), the voltage applied to the data electrode D (j−1), the data electrode D (j), the data electrode D (j + 1), and the data electrode D (j + 2) Transition from the voltage Vd to the low high voltage 0 (V). In the first transition period of the write cycle T (i + 1), the voltage applied to the data electrode D (j−2) and the data electrode D (j + 3) transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

Therefore, at this time, the outputs of the logic gate 52 (j−1), the logic gate 52 (j), the logic gate 52 (j + 1), and the logic gate 52 (j + 2) of the second self-load calculation unit 50 are “H”. The outputs of logic gate 53 (j−2) and logic gate 53 (j + 3) are “H”.

Thereby, the outputs of the logic gate 56 (j−2) and the logic gate 56 (j + 3) of the second adjacent load calculation unit 54 become “H”.

Since the outputs of the logic gate 56 (j-2) and the logic gate 56 (j + 3) are “H”, the LH timing control unit 58 (j−2) and the LH timing control unit 58 (j + 3) In the transition period (here, the second transition period of the write cycle T (i)), all the voltages applied to the data electrode 22 to which the voltage should be transitioned from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) At the timing t53 after the transition from Vd to the low-voltage side voltage 0 (V), the voltage applied to the data electrode D (j-2) and the data electrode D (j + 3) is changed from the low-voltage side voltage 0 (V) to the high-voltage side. Transition to voltage Vd.

In the second transition period of the write cycle T (i + 1), the voltage applied to the data electrode D (j + 3) transits from the high voltage side voltage Vd to the low voltage side voltage 0 (V). In the first transition period of the write cycle T (i + 2), the voltage applied to the data electrode D (j−1), the data electrode D (j + 1), and the data electrode D (j + 2) is from the low voltage side voltage 0 (V) to the high voltage side. Transition to voltage Vd.

Therefore, at this time, the output of the logic gate 52 (j + 3) of the second self-load calculation unit 50 is “H”, and the logic gate 53 (j−1), the logic gate 53 (j + 1), and the logic gate 53 (j + 2) The output is “H”.

Thereby, the output of the logic gate 56 (j + 2) of the second adjacent load calculation unit 54 becomes “H”, and the outputs of the logic gate 56 (j−1) and the logic gate 56 (j + 1) become “L”.

Since the output of the logic gate 56 (j + 2) is “H”, the LH timing control unit 58 (j + 2) has a high voltage in the immediately preceding second transition period (here, the second transition period of the write cycle T (i + 1)). At the timing t73 after all the voltages applied to the data electrode 22 to which the voltage is to be changed from the side voltage Vd to the low voltage 0 (V) have been changed from the high voltage Vd to the low voltage 0 (V), The voltage applied to the data electrode D (j + 2) transits from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

On the other hand, since the outputs of the logic gate 56 (j−1) and the logic gate 56 (j + 1) are “L”, the LH timing controller 58 (j−1) and the LH timing controller 58 (j + 1) The voltage applied to D (j−1) and the data electrode D (j + 1) starts to transition from the low voltage side voltage 0 (V) to the high voltage side voltage Vd at a timing t71 earlier than the timing t73.

That is, the LH timing control unit 58 (j−1) and the LH timing control unit 58 (j + 1) finish the transition of the voltage applied to the data electrode D (j + 3) from the high voltage side voltage Vd to the low voltage side voltage 0 (V). Before the operation, the voltage applied to the data electrode D (j−1) and the data electrode D (j + 1) is changed from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

As described above, in the plasma display device according to the present embodiment, when the address pulse is applied to the data electrode 22 in the address period, two data adjacent to both sides in the immediately preceding second transition period. Data electrode 22 in which the voltage applied to at least one data electrode 22 of electrode 22 changes from high-voltage side voltage Vd to low-voltage side voltage 0 (V) (for example, data electrode D (j−1) in write cycle T (i)) And the data electrode D (j + 2)) at which the first transition period start time (for example, time t33) is to be transferred from the high voltage Vd to the low voltage 0 (V) in the immediately preceding second transition period. The time is set after all the voltages to be applied to the electrodes 22 have finished transitioning from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V).

Thereby, in the plasma display device according to the present embodiment, the voltage applied to the data electrode 22 is changed to the low voltage side while the voltage applied to the adjacent data electrode 22 transits from the high voltage side voltage Vd to the low voltage side voltage 0 (V). Transition from the voltage 0 (V) to the high voltage Vd can be prevented. That is, the voltage applied to the data electrode 22 can be prevented from transitioning from the low voltage side voltage 0 (V) to the high voltage side voltage Vd in a state where the substantial load capacity is relatively large. Thereby, the power consumption in the data electrode drive circuit 132 can be reduced.

Further, in the plasma display device according to the present embodiment, when an address pulse is applied to the data electrode 22 in the address period, application to the two data electrodes 22 adjacent to both sides in the immediately preceding second transition period is performed. A first transition period in the data electrode 22 (for example, the data electrode D (j) and the data electrode D (j + 1) in the write cycle T (i)) in which both voltages do not transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V). Can be set to a time before the end of the immediately preceding second transition period.

As a result, the plasma display device according to the present exemplary embodiment sets the start time of the first transition period and the time before the end of the immediately preceding second transition period for the data electrode 22 having a relatively small substantial load capacity. The time length of the first transition period can be increased accordingly. Therefore, for the data electrode 22 having a relatively small substantial load capacity, the write cycle can be made relatively long, and the write operation can be performed more stably.

(Embodiment 4)
In the fourth embodiment, when an address pulse is applied to one data electrode 22 of two adjacent data electrodes 22 and then an address pulse is applied to the other data electrode 22 in the address period, one data electrode 22 is applied. The voltage applied to one data electrode 22 changes from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) so that the second transition period in the second data electrode 22 and the first transition period in the other data electrode 22 do not overlap in time. After that (second transition period), the configuration in which the voltage applied to the other data electrode 22 transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd (first transition period) will be described. In this embodiment, at this time, the start time of the first transition period in the other data electrode 22 is controlled according to the time length of the second transition period in one data electrode 22. This realizes a stable write operation and a reduction in power consumption in the data electrode drive circuit.

FIG. 15 is a circuit diagram schematically showing a configuration of data electrode drive circuit 232 of the plasma display device in accordance with the fourth exemplary embodiment of the present invention. FIG. 15 shows only a part of the circuit blocks constituting the data electrode drive circuit 232, and other circuit blocks having the same configuration are omitted.

The plasma display device in the present embodiment is different from the plasma display device 30 shown in FIG. 5 in the first embodiment in the configuration of the data electrode driving circuit 232. However, the other circuit blocks have the same configuration as the plasma display device 30 and perform the same operation. Therefore, only the data electrode driving circuit 232 will be described below.

The data electrode drive circuit 232 includes a shift register unit 41, a second self-load calculation unit 50, an adjacent load calculation unit 160, and an output buffer unit 67.

Hereinafter, the adjacent load calculation unit 160 is referred to as a “third adjacent load calculation unit 160”.

Note that the shift register unit 41 in the present embodiment has the same configuration and operation as the shift register unit 41 described in the first embodiment. The second self-load calculation unit 50 has the same configuration and operation as the second self-load calculation unit 50 described in the third embodiment. Therefore, description of these circuit blocks is omitted in this embodiment.

Hereinafter, the configuration and operation of the data electrode driving circuit 232 will be described by taking as an example the case where an address pulse is applied to the data electrode D (j). Therefore, the configuration and operation of data electrode drive circuit 232 described below are the configuration and operation for data electrode D (j), but the configuration and operation for other data electrode 22 are also the configuration and operation for data electrode D (j). It is the same.

The third adjacent load calculation unit 160 has a logic circuit provided corresponding to each of the data electrodes 22. This logic circuit includes a logic gate 61, a logic gate 162, a logic gate 63, a logic gate 64, a logic gate 65, and a logic gate 66. Therefore, the third adjacent load calculation unit 160 includes N logic circuits corresponding to each of N (for example, N = 1920 × 3) data electrodes 22 driven by the data electrode driving circuit 232, and N Each logic circuit includes a logic gate 61, a logic gate 162, a logic gate 63, a logic gate 64, a logic gate 65, and a logic gate 66.

The logic gate 61, the logic gate 162, the logic gate 63, and the logic gate 65 are AND gates with two inputs and one output, and the logic gate 64 and the logic gate 66 are OR gates with two inputs and one output (a logic circuit that performs an OR operation). is there. In FIG. 15, small circles at the input terminals of the logic gates are inverters (logic circuits that perform logic inversion). Therefore, for example, a signal obtained by inverting the output signal of the logic gate 52 (j−1) is input to the logic gate 63 (j + 1), and the logic gate 52 (j + 1) has the signal of the logic gate 52 (j + 1). A signal obtained by inverting the output signal is input.

The logic circuit composed of the logic gate 61 (j), the logic gate 162 (j), the logic gate 63 (j), the logic gate 64 (j), the logic gate 65 (j), and the logic gate 66 (j) This is a logic circuit provided corresponding to the electrode D (j). The logic circuit includes image data Q (j-2) and image data DQ (j-2) corresponding to the data electrode D (j-2), and image data Q corresponding to the data electrode D (j-1). (J-1) and image data DQ (j-1), image data Q (j) corresponding to the data electrode D (j), image data DQ (j), image data Q corresponding to the data electrode D (j + 1) Based on (j + 1) and image data DQ (j + 1), image data Q (j + 2) and image data DQ (j + 2) corresponding to data electrode D (j + 2), a logical operation is performed. The result of the logical operation indicates, for example, whether or not the voltage applied to the data electrode D (j) changes from the low voltage 0 (V) to the high voltage Vd. The result of the logical operation indicates whether or not the voltage applied to the data electrode D (j−1) and the data electrode D (j + 1) changes from the high voltage side voltage Vd to the low voltage side voltage 0 (V). When a change occurs, it represents the time length required for the change (the length of the second transition period).

As described above, for example, when the image data DQ (j) is “L” and the image data Q (j) is “H”, the image data Q (j) changes from “L” to “H”. When the image data DQ (j) is “H” and the image data Q (j) is “L”, the image data Q (j) changes from “H” to “L”.

When the image data Q (j−1) changes from “H” to “L” and the image data Q (j) changes from “L” to “H”, the logic gate 61 (j) H "is output. In other cases, the logic gate 61 (j) outputs “L”.

The logic gate 162 (j) outputs “H” when the image data Q (j + 1) changes from “H” to “L” and the image data Q (j) changes from “L” to “H”. Is output. In other cases, the logic gate 162 (j) outputs “L”.

Then, the logic gate 64 (j) outputs “H” when at least one of the outputs of the logic gate 61 (j) and the logic gate 162 (j) is “H”, and the logic gate 64 (j) When both the gate 162 (j) outputs “L”, “L” is output.

That is, at least one of the image data Q (j−1) and the image data Q (j + 1) changes from “H” to “L”, and the logic gate 64 (j) has the image data Q (j) set to “L”. "H" is output when changing from "" to "H". At other times (for example, both the image data Q (j−1) and the image data Q (j + 1) do not change from “H” to “L”), the logic gate 64 (j) is “L”. Is output.

In other words, the output of the logic gate 64 (j) is output from the high-voltage side voltage Vd to the low-voltage side voltage 0 to at least one of the voltage applied to the data electrode D (j-1) and the voltage applied to the data electrode D (j + 1). When the transition to (V) occurs (second transition period) and the voltage applied to the data electrode D (j) transitions from the low voltage 0 (V) to the high voltage Vd in the subsequent first transition period. “H”. If the voltage applied to the data electrode D (j−1) and the voltage applied to the data electrode D (j + 1) are both maintained at the high voltage Vd or the low voltage 0 (V), “L”. It becomes.

The logic gate 63 (j) does not change the image data Q (j-2) from “H” to “L” (that is, changes from “L” to “H” or maintains “L”). Or “H” is maintained), and “H” is output when the output of the logic gate 61 (j) is “H”. In other cases (the image data Q (j-2) changes from “H” to “L”, or the image data Q (j−1) is maintained at “H” or “L”). The logic gate 63 (j) outputs “L”.

The logic gate 65 (j) does not change the image data Q (j + 2) from “H” to “L” (that is, changes from “L” to “H”, or maintains “L”, or “ "H" is maintained), and "H" is output when the output of the logic gate 162 (j) is "H". At other times (the image data Q (j + 2) changes from “H” to “L”, or the image data Q (j + 1) is maintained at “H” or “L”), the logic gate 65 (J) outputs “L”.

The logic gate 66 (j) outputs “H” when at least one of the outputs of the logic gate 63 (j) and the logic gate 65 (j) is “H”, and the logic gate 63 (j) When both the gate 65 (j) outputs “L”, “L” is output.

That is, the output of the logic gate 66 (j) becomes “H” at the following time. The image data Q (j-2) does not change from “H” to “L”, the image data Q (j−1) changes from “H” to “L”, and the image data Q (j) It changes from “L” to “H”. Alternatively, the image data Q (j + 2) does not change from “H” to “L”, the image data Q (j + 1) changes from “H” to “L”, and the image data Q (j) becomes “L”. "" To "H".

In other cases, the output of the logic gate 66 (j) is “L”. That is, the image data Q (j-2) changes from “H” to “L”, or the image data Q (j−1) is maintained at “H” or “L”, and the image data Q (J + 2) changes from “H” to “L”, or the image data Q (j + 1) is maintained at “H” or “L”.

In other words, the output of the logic gate 66 (j) is such that the voltage applied to the data electrode D (j-2) is maintained at the high voltage Vd or the low voltage 0 (V), and the data electrode D (j−1) ) Changes from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) (second transition period), and the voltage applied to the data electrode D (j) in the subsequent first transition period becomes the low-voltage side voltage 0. It becomes “H” when transitioning from (V) to the high voltage Vd.

The output of the logic gate 66 (j) is a voltage applied to the data electrode D (j + 2) while the voltage applied to the data electrode D (j + 2) is maintained at the high-voltage side voltage Vd or the low-voltage side voltage 0 (V). Transitions from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) (second transition period), and the voltage applied to the data electrode D (j) in the subsequent first transition period increases from the low-voltage side voltage 0 (V). It also becomes “H” when transitioning to the side voltage Vd.

The output of the logic gate 66 (j) is applied to the data electrode D (j-2) while the voltage applied to the data electrode D (j + 1) is maintained at the high voltage Vd or the low voltage 0 (V). And the voltage applied to the data electrode D (j−1) both transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) (second transition period), and in the subsequent first transition period, the data electrode D ( It becomes “L” when the voltage applied to j) transitions from the low voltage 0 (V) to the high voltage Vd.

The output of the logic gate 66 (j) is applied to the data electrode D (j + 2) while the voltage applied to the data electrode D (j-1) is maintained at the high voltage Vd or the low voltage 0 (V). And the voltage applied to the data electrode D (j + 1) both transition from the high voltage Vd to the low voltage 0 (V) (second transition period), and the data electrode D (j) in the subsequent first transition period. Becomes “L” when the voltage applied to is transitioned from the low-voltage side voltage 0 (V) to the high-voltage side voltage Vd.

The output of the logic gate 66 (j) includes a voltage applied to the data electrode D (j-2), a voltage applied to the data electrode D (j-1), a voltage applied to the data electrode D (j + 1), and data. The voltage applied to the electrode D (j + 2) both changes from the high voltage side voltage Vd to the low voltage side voltage 0 (V) (second transition period), and the voltage applied to the data electrode D (j) in the subsequent first transition period. Becomes “L” when transitioning from the low voltage 0 (V) to the high voltage Vd.

The output buffer section 67 has N output buffers 69 corresponding to each of N (for example, N = 1920 × 3) data electrodes 22 driven by the data electrode driving circuit 232. Each output buffer 69 generates an address pulse to be applied to the data electrode 22.

The output buffer unit 67 includes N high-voltage switches QH, N low-voltage switches QL, and N LH timing controllers 68. For example, if N = 1920 × 3, the output buffer unit 67 includes a high voltage side switch QH (1) to a high voltage side switch QH (5760), and a low voltage side switch QL (1) to a low voltage side switch QL (5760). , LH timing control unit 68 (1) to LH timing control unit 68 (5760).

As shown in FIG. 15, in this embodiment, each output buffer 69 includes a circuit combining one high-voltage side switch QH and one low-voltage side switch QL, and one LH timing control unit 68. Have.

The LH timing control unit 68 controls the high voltage side switch QH and the low voltage side switch QL based on the signals (the output signal of the logic gate 64 and the output signal of the logic gate 66) output from the third adjacent load calculation unit 160. That is, the LH timing control unit 68 controls the timing at which the voltage applied to the data electrode 22 transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd based on the signal output from the third adjacent load calculation unit 160. To do.

For example, if the output of the logic gate 64 (j) is “H” and the output of the logic gate 66 (j) is “H”, the LH timing control unit 68 (j) has the data electrode D (1). The first transition period that continues after the end of the second transition period after all the voltages applied to the data electrodes 22 of the data electrode D (m) have transitioned from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V). And the voltage applied to the data electrode D (j) is changed from the low voltage 0 (V) to the high voltage Vd.

When the output of the logic gate 64 (j) is “H” and the output of the logic gate 66 (j) is “L”, the LH timing control unit 68 (j) The voltage applied to the data electrode D (j) by starting the first transition period at a time earlier than when the output of the logic gate 66 (j) is “H” and the output of the logic gate 66 (j) is “H”. A transition is made from the side voltage 0 (V) to the high voltage side voltage Vd.

If the output of the logic gate 64 (j) is “H” and the output of the logic gate 66 (j) is “L”, the voltage applied to the data electrode D (j−2), the data electrode D (j The voltage applied to -1), the voltage applied to the data electrode D (j + 1), and the voltage applied to the data electrode D (j + 2) all transit from the high voltage side voltage Vd to the low voltage side voltage 0 (V).

Therefore, the substantial load capacitance generated at the data electrode D (j−1) at that time is such that the voltage applied to the data electrode D (j−2) is maintained at the high voltage Vd or the low voltage 0 (V). In addition, the voltage applied to the data electrode D (j−1) is smaller than when the high voltage side voltage Vd transits to the low voltage side voltage 0 (V). Therefore, the time required for the voltage applied to the data electrode D (j−1) to transition from the high voltage Vd to the low voltage 0 (V) is relatively small.

Similarly, the substantial load capacitance generated at the data electrode D (j + 1) at that time is such that the voltage applied to the data electrode D (j + 2) is maintained at the high voltage Vd or the low voltage 0 (V), and the data The voltage applied to the electrode D (j + 1) is smaller than when transitioning from the high voltage side voltage Vd to the low voltage side voltage 0 (V). Therefore, the time required for the voltage applied to the data electrode D (j + 1) to transition from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) is relatively small.

Therefore, in such a case, the time at which the voltage applied to the data electrode D (j) transitions from the low-voltage side voltage 0 (V) to the high-voltage side voltage Vd can be relatively advanced, and the data electrode D (j) It is possible to perform the writing operation more stably by relatively increasing the time length during which the high-voltage side voltage Vd is applied.

If the output of the logic gate 64 (j) is “L”, the LH timing control unit 68 (j) indicates that the output of the logic gate 64 (j) is “H” and the logic gate 66 (j). The first transition period starts at a time earlier than when the output of “L” is “L”, and the voltage applied to the data electrode D (j) transitions from the low voltage 0 (V) to the high voltage Vd.

If the output of the logic gate 64 (j) is “L”, the voltage applied to the data electrode D (j−1) and the data electrode D (j + 1) is set to the high voltage side voltage Vd or the low voltage side voltage 0 (V). Maintained.

Therefore, in such a case, the time at which the voltage applied to the data electrode D (j) transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd can be relatively advanced, and the data electrode D (j) It is possible to perform the writing operation more stably by relatively increasing the length of time during which the high-voltage side voltage Vd is applied.

FIG. 16 is a timing chart schematically showing an example of the operation of the data electrode drive circuit 232 of the plasma display device in accordance with the fourth exemplary embodiment of the present invention.

In FIG. 16, four write cycles (write cycle T (i−1), write cycle T (i), write cycle T (i + 1), and write cycle T (i + 2)) in the write period are shown as examples. The drive voltage waveforms applied to scan electrode SC (i−1) to scan electrode SC (i + 1) and data electrode D (j−2) to data electrode D (j + 3) will be described as an example.

In FIG. 16, in the write cycle T (i−1), a write pulse is applied to the data electrode D (j−1), the data electrode D (j + 2), and the data electrode D (j + 3), and the data electrode D ( j-2), an address pulse is not applied to the data electrode D (j) and the data electrode D (j + 1), and the address is written to the data electrode D (j) and the data electrode D (j + 1) in the address period T (i). A pulse is applied, an address pulse is not applied to the data electrode D (j-2), the data electrode D (j-1), the data electrode D (j + 2), and the data electrode D (j + 3), and the address period T (i + 1 ), An address pulse is applied to data electrode D (j-1), data electrode D (j + 1) and data electrode D (j + 2), and data electrode D (j-2), data electrode D (j) and data electrode D (j + 3) In the write cycle T (i + 2), the data electrode D (j-2), the data electrode D (j-1), the data electrode D (j), the data electrode D (j + 1), and the data electrode D ( An example in which an address pulse is applied to j + 3) and an address pulse is not applied to the data electrode D (j + 2) is shown.

In the second transition period of the write cycle T (i−1), the voltage applied to the data electrode D (j−1), the data electrode D (j + 2) and the data electrode D (j + 3) is changed from the high voltage side voltage Vd to the low voltage side. Transition to voltage 0 (V). In the first transition period of the write cycle T (i), the voltage applied to the data electrode D (j) and the data electrode D (j + 1) transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

Accordingly, at this time, the outputs of the logic gate 52 (j−1), the logic gate 52 (j + 2), and the logic gate 52 (j + 3) of the second self-load calculating unit 50 become “H”, and the logic gate 53 (j) and The output of the logic gate 53 (j + 1) is “H”.

As a result, the output of the logic gate 64 (j) and the output of the logic gate 66 (j) of the third adjacent load calculation unit 160 become “H”, the output of the logic gate 64 (j + 1) becomes “H”, and the logic gate The output of 66 (j + 1) is “L”.

Since both the output of the logic gate 64 (j) and the output of the logic gate 66 (j) are “H”, the LH timing control unit 68 (j) has the data electrode D (1) to the data electrode D (m). At time t33 after all the voltages applied to each data electrode 22 have finished transitioning from the high voltage side voltage Vd to the low voltage side voltage 0 (V), the voltage applied to the data electrode D (j) is changed to the low voltage side voltage 0 ( The operation of transition from V) to the high voltage Vd is started.

In addition, since the output of the logic gate 64 (j + 1) is “H” and the output of the logic gate 66 (j + 1) is “L”, the LH timing control unit 68 (j + 1) is more timely than the time t33. At an early time t32, the operation of transitioning the voltage applied to the data electrode D (j + 1) from the low voltage side voltage 0 (V) to the high voltage side voltage Vd is started.

In the second transition period of the write cycle T (i), the voltage applied to the data electrode D (j) transits from the high voltage side voltage Vd to the low voltage side voltage 0 (V). In the first transition period of the write cycle T (i + 1), the voltage applied to the data electrode D (j−1) and the data electrode D (j + 2) transitions from the low voltage side voltage 0 (V) to the high voltage side voltage Vd.

Therefore, as a result, the output of the logic gate 64 (j−1) and the output of the logic gate 66 (j−1) of the third adjacent load calculation unit 160 are both “H”, and the output of the logic gate 64 (j + 2) is “L”.

Since the LH timing control unit 68 (j-1) has both the output of the logic gate 64 (j-1) and the output of the logic gate 66 (j-1) being "H", the data electrode D (1) to the data electrode D Applied to data electrode D (j-1) at time t53 after all the voltages applied to each data electrode 22 of electrode D (m) have transitioned from high-voltage side voltage Vd to low-voltage side voltage 0 (V). The operation of changing the voltage to be changed from the low voltage 0 (V) to the high voltage Vd is started.

Since the output of the logic gate 64 (j + 2) is “L”, the LH timing control unit 68 (j + 2) reduces the voltage applied to the data electrode D (j + 2) at time t51 earlier than time t53. The operation of transitioning from the side voltage 0 (V) to the high voltage side voltage Vd is started. The time length between time t51 and time t53 is longer than the time length between time t32 and time t33.

As described above, in the plasma display device in the present embodiment, in the address period, the address pulse is applied to one data electrode 22 of the two adjacent data electrodes 22 and then the other data electrode 22 is addressed. Is applied, the voltage applied to one data electrode 22 is set to the high voltage Vd so that the second transition period of one data electrode 22 and the first transition period of the other data electrode 22 do not overlap in time. After the transition to the low voltage 0 (V) from the second voltage (second transition period), the voltage applied to the other data electrode 22 transitions from the low voltage 0 (V) to the high voltage Vd (first transition period). . Then, the start time of the first transition period in the other data electrode 22 is controlled according to the time length of the second transition period in one data electrode 22.

As a result, the voltage applied to the data electrode 22 changes from the low voltage 0 (V) to the high voltage while the voltage applied to the adjacent data electrode 22 changes from the high voltage Vd to the low voltage 0 (V). Transition to Vd can be prevented. That is, the voltage applied to the data electrode 22 can be prevented from transitioning from the low voltage side voltage 0 (V) to the high voltage side voltage Vd in a state where the substantial load capacity is relatively large. Thereby, power consumption in the data electrode drive circuit 232 can be reduced.

Then, by controlling the start time of the first transition period in the other data electrode 22 according to the time length of the second transition period in one data electrode 22, the data electrode having a relatively small substantial load capacity As for No. 22, since the time length of the write cycle can be made relatively long, the write operation can be performed more stably.

In the first embodiment and the second embodiment, when the voltage applied to the data electrode 22 is changed, the low voltage side voltage 0 (V) is first changed from the high voltage side voltage Vd to the low voltage side voltage 0 (V). The configuration of transition from the high voltage Vd to the high voltage Vd has been described. Therefore, the start time of the second transition period is set for each output buffer or each data driver. However, for example, first, after the transition from the low voltage side voltage 0 (V) to the high voltage side voltage Vd, the transition may be made from the high voltage side voltage Vd to the low voltage side voltage 0 (V). In this case, the start time of the first transition period may be set for each output buffer or each data driver.

The drive voltage waveforms shown in FIGS. 4, 7, 12, 14, and 16 are merely examples in the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms. Is not to be done.

Further, the circuit configurations shown in FIGS. 5, 6, 9, 10, 11, 13, and 15 are merely examples in the embodiment of the present invention, and the present invention is not limited to these. The circuit configuration is not limited.

Note that each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.

In the embodiment of the present invention, an example in which one field is composed of eight subfields has been described. However, in the present invention, the number of subfields constituting one field is not limited to the above number. For example, by increasing the number of subfields, the number of gradations that can be displayed on the panel 10 can be further increased.

In the embodiment of the present invention, an example in which one pixel is constituted by discharge cells of three colors of red, green, and blue has been described. However, a panel in which one pixel is constituted by discharge cells of four colors or more. However, it is possible to apply the configuration shown in the embodiment of the present invention, and the same effect can be obtained.

The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Also, the number of subfields constituting one field, the luminance weight of each subfield, etc. are not limited to the values shown in the embodiment of the present invention, and the subfield configuration is based on the image signal or the like. It may be configured to switch.

The present invention can stably supply power to a data electrode driving circuit to perform a stable address operation and reduce power consumption of the data electrode driving circuit. Therefore, the present invention provides a plasma display device and a plasma display device driving method. Useful.

DESCRIPTION OF SYMBOLS 10 Panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 14

Display electrode pair

15, 23 Dielectric layer 16 Protection layer 21 Back substrate 22 Data electrode 24 Partition 25, 25R, 25G, 25B Phosphor layer 30, 60 Plasma display device 31 Image

Signal processing circuit

32, 62, 132, 232 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35

Timing generation circuit

41, 81

Shift register unit

42, 50 Self

load calculation unit

43, 45, 46, 47, 52 , 53, 55, 56, 61, 63, 64, 65, 66, 144, 154, 162

Logic gate

44, 54, 160 Adjacent

load calculation unit

48, 57, 67, 85

Output buffer unit

49, 59, 89 HL timing

Control unit

51, 142 1 line delay 58, 6 LH

timing control unit

69, 86, 157, 148 Output buffer 72 Maximum load calculation unit 74 Timing pulse selection unit 80

Data driver

82, 84, 141 Latch 83 Data latch unit LP Write timing signal LLP, LLP1, LLP2, LLP3 Timing signal QH High pressure side switch QL Low pressure side switch

Claims

A plasma display panel having a plurality of display electrode pairs and a plurality of data electrodes, and a data electrode driving circuit for applying an address pulse to the data electrodes, wherein the data electrode driving circuit performs the writing for each writing cycle in a writing period. A plasma display device that applies a high-voltage side voltage of a pulse or a low-voltage side voltage of the write pulse to each of the data electrodes,
The data electrode drive circuit includes an output buffer having a high voltage side switch for outputting the high voltage side voltage and a low voltage side switch for outputting the low voltage side voltage for each of the data electrodes,
The output buffer turns off the low-voltage side switch during the first transition period provided in the write cycle when the voltage of the write pulse changes from the low-voltage side voltage to the high-voltage side voltage. Turn on the switch to set the output voltage to the high-voltage side voltage,
When transitioning the voltage of the write pulse from the high voltage side voltage to the low voltage side voltage, the high voltage side switch is turned off and the low voltage side switch is turned on during the second transition period provided in the write cycle. The output voltage is the low voltage side voltage,
The plasma display apparatus characterized by temporally separating the second transition period and the first transition period immediately after the second transition period.
The data electrode driving circuit includes:
The size of the substantial load capacity between the adjacent data electrodes is calculated, and the data electrode having a relatively large substantial load capacity is compared with the data electrode having a relatively small substantial load capacity. 2. The plasma display device according to claim 1, wherein the high-voltage side switch and the low-voltage side switch are controlled for each of the output buffers so that a start time of the first transition period or the second transition period is advanced. .
The data electrode driving circuit includes:
A plurality of integrated circuits in which a plurality of the output buffers are integrated,
In the integrated circuit, the maximum value of the substantial load capacitance generated for each data electrode is calculated,
In the integrated circuit having a large maximum value, the high-voltage side switch and the low-voltage side switch are integrated so that the start time of the first transition period or the second transition period is earlier than that of the integrated circuit having the small maximum value. The plasma display device according to claim 1, wherein the control is performed for each circuit.
A plasma display panel having a plurality of display electrode pairs and a plurality of data electrodes, and a data electrode driving circuit for applying an address pulse to the data electrodes, wherein the data electrode driving circuit performs the writing for each writing cycle in a writing period. A plasma display device that applies a high-voltage side voltage of a pulse or a low-voltage side voltage of the write pulse to each of the data electrodes,
The data electrode drive circuit includes an output buffer having a high voltage side switch for outputting the high voltage side voltage and a low voltage side switch for outputting the low voltage side voltage for each of the data electrodes,
The output buffer turns off the low-voltage side switch during the first transition period provided in the write cycle when the voltage of the write pulse changes from the low-voltage side voltage to the high-voltage side voltage. Turn on the switch to set the output voltage to the high-voltage side voltage,
When transitioning the voltage of the write pulse from the high voltage side voltage to the low voltage side voltage, the high voltage side switch is turned off and the low voltage side switch is turned on during the second transition period provided in the write cycle. The output voltage is the low voltage side voltage,
A plasma display apparatus characterized in that, in two data electrodes adjacent to each other, the second transition period and the first transition period immediately after the second transition period are separated in time.
One field is composed of a plurality of subfields having an address period and a sustain period,
A driving method of a plasma display device, wherein an address pulse is applied to each data electrode of a plasma display panel having a plurality of display electrode pairs and a plurality of data electrodes in the address period,
In the first transition period provided in the write cycle, the voltage of the write pulse is changed from the low voltage to the high voltage.
In a second transition period provided in the write cycle, the voltage of the write pulse is changed from the high voltage side voltage to the low voltage side voltage,
A method for driving a plasma display device, characterized in that the second transition period and the first transition period immediately after the second transition period are separated in time.