WO2012102033A1

WO2012102033A1 - Plasma display panel drive method and plasma display device

Info

Publication number: WO2012102033A1
Application number: PCT/JP2012/000446
Authority: WO
Inventors: 裕也塩崎; 貴彦折口; 鮎彦齋藤; 富岡　直之; 佑紀今井
Original assignee: パナソニック株式会社
Priority date: 2011-01-28
Filing date: 2012-01-25
Publication date: 2012-08-02

Abstract

The purpose of the present invention is to perform stable write operations even when driving a high-definition large-screen plasma display panel. To that end, the plasma display panel is driven by dividing said panel into multiple scan electrode groups which include a first scan electrode group and a second scan electrode group. Further, a field is provided into subfields which comprise, after an adjustment period in which the scan electrodes, sustain electrodes and data electrodes are sustained at a base potential, an initialization period in which a first downward-sloping waveform voltage is applied to the first scan electrode group and a second downward-sloping waveform voltage is applied to the second scan electrode group, and a write period in which a third downward-sloping waveform voltage is applied to the scan electrodes between a write operation to the first scan electrode group and a write operation to the second scan electrode group. Also, the length of the adjustment period changes depending on the number of sustain pulses generated in the sustain period of the immediately preceding subfield.

Description

Plasma display panel driving method and plasma display device

The present invention relates to a plasma display device using an AC surface discharge type plasma display panel and a driving method of the plasma display panel.

2. Description of the Related Art A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate that are arranged to face each other.

In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs.

The back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.

Then, the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.

A subfield method is generally used as a method for displaying an image in an image display area of a panel by combining binary control of light emission and non-light emission in a discharge cell.

In the subfield method, one field is divided into a plurality of subfields having different emission luminances. In each discharge cell, light emission / non-light emission of each subfield is controlled by a combination according to a desired gradation value. Thus, each discharge cell emits light with the emission luminance of one field set to a desired gradation value, and an image composed of various combinations of gradation values is displayed in the image display area of the panel.

In the subfield method, each subfield has an initialization period, an address period, and a sustain period.

In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization operation is performed to generate an initialization discharge in each discharge cell. Thereby, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.

In the address period, the scan pulse is sequentially applied to the scan electrodes, and the address pulse is selectively applied to the data electrodes based on the image signal to be displayed. As a result, an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”). ).

In the sustain period, the number of sustain pulses based on the luminance weight determined for each subfield is alternately applied to the display electrode pairs composed of the scan electrodes and the sustain electrodes. As a result, a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”). Also written as “lit”.) Thereby, in each subfield, each discharge cell is made to emit light with the luminance according to the luminance weight. In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.

In the sustain period, a technique is disclosed in which, after the sustain pulse is applied to the display electrode pair, a rising ramp voltage is applied to the sustain electrode to generate a weak discharge (erase discharge) (for example, Patent Document 1). reference). By generating the erasing discharge, the wall charge in the discharge cell caused by the sustain discharge is erased, the potential difference between the pair of display electrodes is relaxed, and the address discharge in the subsequent subfield address period can be stably generated. It becomes possible.

In addition, after the application of the sustain pulse to the display electrode pair is completed in the sustain period, a ramp voltage that maintains the voltage for a certain period is applied to the scan electrode after rising to a predetermined voltage, and then the ramp voltage that rises is maintained. A technique for erasing wall charges in a discharge cell by applying to an electrode is disclosed (for example, see Patent Document 2).

In addition, after the sustain pulse is applied to the display electrode pair in the sustain period, a rising ramp voltage is applied to the scan electrode, and the tilt is changed in accordance with the average luminance of the display image, so that the wall in the discharge cell is changed. A technique for erasing electric charges is disclosed (for example, see Patent Document 3).

In a large-screen panel with high definition, the number of electrodes that must be driven increases, and the impedance during driving also increases, so the writing operation tends to become unstable. Therefore, a plasma display device provided with such a panel is also required to stably generate an address discharge and stably display an image on the panel.

Also, wall charges formed in the discharge cell by the initializing discharge gradually decrease under the influence of the address pulse applied to the data electrode in order to generate the address discharge in other discharge cells. For this reason, in a discharge cell in which the scan pulse is applied in a late order, wall charges may decrease before the scan pulse and the address pulse are applied to the discharge cell, and a discharge failure of address discharge may occur.

In particular, in a high-definition panel, the time spent for the address operation becomes longer due to the increase in the number of scan electrodes, and therefore, the wall charge in the discharge cell in which the address is written toward the end of the address period is reduced. Further, the address discharge tends to become unstable.

JP 2004-348140 A JP 2005-141224 A JP 2003-5700 A

The present invention provides a panel including a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode, and a plurality of scan electrodes each including a first scan electrode group and a second scan electrode group. This is a method for driving a panel that is divided into scan electrode groups. In this driving method, after the adjustment period for maintaining the display electrode pair and the data electrode at the base potential, the first downward ramp waveform voltage is applied to the first scan electrode group and the second scan electrode group is supplied with the second scan electrode group. Initialization period in which a downward ramp waveform voltage is applied, an address operation in which an address pulse is applied to a discharge cell to emit light in the first scan electrode group, and an address pulse is applied to a discharge cell to emit light in the second scan electrode group One field is a subfield having an address period in which the third downward ramp waveform voltage is applied to the scan electrodes and an sustain period in which the number of sustain pulses corresponding to the luminance weight is applied to the display electrode pair during the address operation. Included. Then, the length of the adjustment period is changed according to the number of sustain pulses generated in the sustain period of the immediately preceding subfield.

This makes it possible to perform a stable writing operation even when driving a high-definition large-screen panel and display a high-quality image on the panel.

Further, in the driving method of the panel of the present invention, the difference between the lowest voltage of the first falling ramp waveform voltage and the lowest voltage of the third falling ramp waveform voltage is calculated by subtracting the length of the adjustment period from the subfield having a longer adjustment period. It is desirable to change with a short subfield.

In the panel driving method of the present invention, it is desirable to lower the minimum voltage of the third downward ramp waveform voltage in the subfield having a short adjustment period than in the subfield having a long adjustment period.

In addition, the present invention applies a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and applies a number of sustain pulses corresponding to the address period and luminance weight to the display electrode pair. And driving the panel by dividing the scan electrodes into a plurality of scan electrode groups including a first scan electrode group and a second scan electrode group, wherein one field is composed of a plurality of subfields having a sustain period. It is. In this driving method, the first type subfield and the second type subfield are provided in one field. The first type subfield includes a scan electrode that applies an upward ramp waveform voltage that rises to a voltage at which discharge occurs in the discharge cell and a downward ramp waveform voltage that decreases toward a negative voltage, and no discharge occurs in the discharge cell. This is a subfield having an initialization period in which a scan electrode to which a voltage and a falling ramp waveform voltage are applied exists. The second type subfield is a subfield having an initializing period in which a first downward ramp waveform voltage that drops to a voltage at which discharge occurs only in the discharge cells that have generated address discharge in the immediately preceding subfield is applied to the scan electrodes. is there. In the initialization period of the first type subfield, the first voltage is applied to the data electrode during the period in which the downward ramp waveform voltage is applied to the scan electrode. In the initialization period of the second type subfield, a second voltage higher than the first voltage is applied to the data electrode during the period in which the first downward ramp waveform voltage is applied to the scan electrode. In the subfields other than the last subfield of one field, the rising ramp waveform voltage that rises from the base potential to a predetermined voltage set lower than the sustain pulse voltage after the generation of the last sustain pulse in the sustain period is applied to the scan electrodes. Apply. In the second type subfield, an adjustment period for maintaining the display electrode pair and the data electrode at the base potential is provided immediately before the initialization period. In the initialization period of the second type subfield, the first downward ramp waveform voltage is applied to the first scan electrode group and the second downward ramp waveform voltage is applied to the second scan electrode group. In the address period of the second type subfield, an address operation that applies an address pulse to the discharge cells that should emit light in the first scan electrode group and an address that applies an address pulse to the discharge cells that should emit light in the second scan electrode group A third downward ramp waveform voltage is applied to the scan electrode during the operation. Then, the length of the adjustment period is changed according to the number of sustain pulses generated in the sustain period of the immediately preceding subfield.

This makes it possible to perform a stable writing operation even when driving a high-definition large-screen panel and display a high-quality image on the panel. In addition, it is possible to reduce the luminance of black and display an image with high contrast on the panel.

Further, in the panel driving method of the present invention, the difference between the lowest voltage of the first falling ramp waveform voltage and the lowest voltage of the third falling ramp waveform voltage is calculated by subtracting the length of the adjustment period from the subfield and the adjustment period. It is desirable to change the subfield with a short length.

Further, in the panel driving method of the present invention, in the subfield having a short adjustment period, the lowest voltage of the third downward ramp waveform voltage can be set lower than in the subfield having a long adjustment period. Good.

In the panel driving method of the present invention, the lowest voltage of the first descending ramp waveform voltage is set to a voltage higher than the lowest voltage of the descending ramp waveform voltage of the first type subfield, and the first descending ramp waveform is set. A voltage may be generated.

In the panel driving method of the present invention, a positive voltage is applied to the sustain electrode during the period in which the down-gradient waveform voltage of the first type subfield is applied to the scan electrode, and the first down-gradient waveform voltage is applied to the scan electrode. A voltage higher than the positive voltage may be applied to the sustain electrode during the period applied to the sustain electrode.

The present invention also provides a panel including a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode, and a plurality of scan electrodes including a first scan electrode group and a second scan electrode group. And a driving circuit for driving the panel divided into the scanning electrode groups. In this plasma display device, the drive circuit applies the first downward ramp waveform voltage to the first scan electrode group and the second scan electrode after the adjustment period for maintaining the display electrode pair and the data electrode at the base potential. An initializing period in which a second downward ramp waveform voltage is applied to the group, an address operation in which an address pulse is applied to the discharge cells to emit light in the first scan electrode group, and a discharge cell to emit light in the second scan electrode group A write period in which a third downward ramp waveform voltage is applied to the scan electrodes between the write operation for applying the write pulses to the scan electrodes, and a sustain period in which the number of sustain pulses corresponding to the luminance weight is applied to the display electrode pairs The panel is driven by including subfields in one field. Then, the driving circuit changes the length of the adjustment period according to the number of sustain pulses generated in the sustain period of the immediately preceding subfield.

In the plasma display device of the present invention, the driving circuit may calculate the difference between the lowest voltage of the first falling ramp waveform voltage and the lowest voltage of the third falling ramp waveform voltage as a subfield having a long adjustment period. It is desirable to change the subfield with a short adjustment period.

In the plasma display device of the present invention, the drive circuit lowers the minimum voltage of the third downward ramp waveform voltage in the subfield having a short adjustment period compared to the subfield having a long adjustment period. May be.

In addition, the present invention applies a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and a number of sustain pulses corresponding to the address period and luminance weight to the display electrode pair. Drive circuit for driving a panel by forming one field with a plurality of subfields having a sustain period and dividing the scan electrodes into a plurality of scan electrode groups including a first scan electrode group and a second scan electrode group Is a plasma display device. In this plasma display device, the drive circuit drives the panel by providing the first type subfield and the second type subfield in one field. The first type subfield includes a scan electrode that applies an upward ramp waveform voltage that rises to a voltage at which discharge occurs in the discharge cell, and a downward ramp waveform voltage that decreases toward a negative voltage, and discharge occurs in the discharge cell. And an initializing period in which there are scan electrodes to which the voltage to be applied and the downward ramp waveform voltage are applied. The second type subfield has an initializing period in which a first falling ramp waveform voltage that drops to a voltage at which only the discharge cells that have generated address discharge in the immediately preceding subfield are discharged is applied to the scan electrodes. In the initialization period of the first type subfield, the first voltage is applied to the data electrode during the period in which the downward ramp waveform voltage is applied to the scan electrode. In the initialization period of the second type subfield, a second voltage higher than the first voltage is applied to the data electrode during a period in which the first downward ramp waveform voltage is applied to the scan electrode. In the second type subfield, an adjustment period for maintaining the display electrode pair and the data electrode at the base potential is provided immediately before the initialization period. In the initialization period of the second type subfield, the first downward ramp waveform voltage is applied to the first scan electrode group and the second downward ramp waveform voltage is applied to the second scan electrode group. In the address period of the second type subfield, an initialization period, an address operation in which an address pulse is applied to the discharge cells to emit light in the first scan electrode group, and an address to the discharge cells to emit light in the second scan electrode group A third downward ramp waveform voltage is applied to the scan electrode during the write operation in which a pulse is applied.

Then, the drive circuit changes the length of the adjustment period according to the number of sustain pulses generated in the last subfield sustain period.

FIG. 1 is an exploded perspective view showing a structure of a panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 2 is an electrode array diagram of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 3 is a schematic diagram showing an example of the division of the scan electrode group of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 4 is a diagram showing a driving voltage waveform in a one-phase driving operation applied to each electrode of the panel used in the plasma display device in the first exemplary embodiment of the present invention. FIG. 5 is a diagram showing a driving voltage waveform in a two-phase driving operation applied to each electrode of the panel used in the plasma display device in the first exemplary embodiment of the present invention. FIG. 6 is a diagram showing a driving voltage waveform in a two-phase driving operation applied to each electrode of the panel used in the plasma display device in the first exemplary embodiment of the present invention. FIG. 7 is a diagram illustrating an example of parameters of the drive voltage waveform in the first embodiment of the present invention. FIG. 8 is a diagram showing a relationship between the adjustment period TSF and the voltage Vset in the first embodiment of the present invention. FIG. 9 is a diagram showing an example of the relationship between the adjustment period TSF and the voltage Vset in the first embodiment of the present invention. FIG. 10 is a diagram showing another example of the relationship between the adjustment period TSF and the voltage Vset in the first embodiment of the present invention. FIG. 11 is a diagram showing the relationship between the voltage difference between the voltage Vr and the voltage Vs and the voltage Vset2 in the first embodiment of the present invention. FIG. 12 is a circuit block diagram of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 13 is a circuit diagram schematically showing a configuration of a scan electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 14 is a circuit diagram schematically showing a configuration of a sustain electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 15 is a circuit diagram schematically showing a configuration of a data electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 16 is a circuit diagram of the scan pulse generating circuit according to the first embodiment of the present invention. FIG. 17 is a schematic diagram illustrating a connection state between the scan IC and the scan electrode of the scan electrode driving circuit according to the first embodiment of the present invention. FIG. 18 is a diagram for explaining a correspondence relationship between the control signals OC1 and OC2 and the operation state of the scan IC in the first embodiment of the present invention. FIG. 19 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in one embodiment of the present invention. FIG. 20 schematically shows the relationship between the scan pulse voltage (amplitude) necessary to generate a stable address discharge and the order of address operations when performing the two-phase drive operation in the first embodiment of the present invention. FIG. FIG. 21 is a diagram showing a driving voltage waveform during a one-phase driving operation applied to each electrode of the panel used in the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 22 is a diagram showing a drive voltage waveform during a two-phase drive operation applied to each electrode of panel 10 used in the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 23 is a diagram schematically showing a relationship between a scan electrode to which a forced initialization waveform is applied and a field in the second embodiment of the present invention. FIG. 24 is a timing chart for explaining the operation of the driving circuit of the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 25 is a waveform diagram showing another example of the waveform shape of the downward ramp waveform voltage applied to the scan electrode in the embodiment of the present invention.

Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

The protective layer 26 is formed of a material mainly composed of magnesium oxide (MgO), which is a material having high electron emission performance, in order to easily generate discharge in the discharge cell.

The protective layer 26 may be composed of a single layer or may be composed of a plurality of layers. Moreover, the structure which particle | grains exist on a layer may be sufficient.

A plurality of data electrodes 32 are formed on the rear substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and a discharge space is formed in the gap between the front substrate 21 and the rear substrate 31. Provide. And the outer peripheral part is sealed with sealing materials, such as glass frit. Then, for example, a mixed gas of neon (Ne) and xenon (Xe) is sealed in the discharge space inside as a discharge gas.

The discharge space is divided into a plurality of sections by partition walls 34, and discharge cells constituting pixels are formed at the intersections of the display electrode pairs 24 and the data electrodes 32. A color image is displayed on the panel 10 by discharging and emitting (lighting) these discharge cells.

In the panel 10, three continuous discharge cells arranged in the extending direction of the display electrode pair 24, that is, discharge cells that emit red (R), and discharge cells that emit green (G), One pixel is composed of three discharge cells, ie, discharge cells emitting blue (B).

Note that the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall. The mixing ratio of the discharge gas may be, for example, a xenon partial pressure of 10%, but the xenon partial pressure may be further increased in order to improve the light emission efficiency in the discharge cell. Good.

FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

The panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) extended in the horizontal direction (row direction and line direction) and n sustain electrodes SU1 to SUn (FIG. 1). Are arranged, and m data electrodes D1 to Dm (data electrode 32 in FIG. 1) extending in the vertical direction (column direction) are arranged.

Then, one discharge cell is formed in a region where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). That is, m discharge cells are formed on one display electrode pair 24, and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 and n = 1080. In the present embodiment, n = 1080, but the present invention is not limited to this value.

Next, a method for driving the panel 10 of the plasma display apparatus according to the present embodiment will be described. Note that the plasma display device in this embodiment performs gradation display by a subfield method. In the subfield method, one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield. Each subfield has an initialization period, an address period, and a sustain period. An image is displayed on the panel 10 by controlling light emission / non-light emission of each discharge cell for each subfield.

The luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”. Therefore, various gradations can be displayed and images can be displayed by selectively causing each subfield to emit light in a combination according to the image signal.

In the present embodiment, one field is divided into 8 subfields (subfield SF1, subfield SF2,..., Subfield SF8), and the luminance weight increases in the subfield later in time. An example will be described in which each subfield has a luminance weight of (1, 2, 4, 8, 16, 32, 64, 128).

In this embodiment, with this configuration, a red image signal (R signal), a green image signal (G signal), and a blue image signal (B signal) are displayed in 256 gradations from 0 to 255, respectively. Can do.

In the initialization period, an initialization discharge is generated, and an initialization operation is performed to form wall charges necessary for the subsequent address discharge on each electrode. The initializing operation at this time includes all-cell initializing operation in which initializing discharge is generated in all discharge cells, and selective initializing with respect to the discharge cells that have generated sustain discharge in the sustain period of the immediately preceding subfield. There is a selective initialization operation that generates a discharge.

In the address period, an address operation is performed in which an address discharge is selectively generated in the discharge cells to emit light to form wall charges necessary for the sustain discharge.

In the sustain period, a sustain pulse is alternately applied to the display electrode pair 24, and a sustain operation is performed in the discharge cell in which the address discharge is generated to emit light from the discharge cell.

In the present embodiment, among the plurality of subfields, the all-cell initialization operation is performed in the initialization period of one subfield, and the selective initialization operation is performed in the initialization period of the other subfield. Hereinafter, the subfield that performs the all-cell initializing operation is referred to as “all-cell initializing subfield”, and the subfield that performs the selective initializing operation is referred to as “selective initializing subfield”.

In the present embodiment, an example will be described in which the all-cell initializing operation is performed in the initializing period of the subfield SF1, and the selective initializing operation is performed in the initializing periods of the subfield SF2 to the subfield SF8. Thereby, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initializing operation in the subfield SF1. Therefore, the black luminance, which is the luminance of the black display region where no sustain discharge occurs, is only weak light emission in the all-cell initialization operation, and an image with high contrast can be displayed on the panel 10.

In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined proportional constant is applied to each display electrode pair 24. This proportionality constant is the luminance magnification.

Therefore, for example, when the luminance magnification is double, the sustain pulse is applied to the scan electrode 22 and the sustain electrode 23 four times in the sustain period of the subfield having the luminance weight “2”. Therefore, the number of sustain pulses generated in the sustain period is 8.

However, in the present embodiment, the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

Next, the scan electrode group in the present embodiment will be described.

FIG. 3 is a schematic diagram showing an example of the division of the scan electrode group of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

The plasma display device in the present embodiment includes a plurality of scan electrode driving ICs (hereinafter referred to as “scan IC 95”), and drives the scan electrodes SC1 to SCn using the plurality of scan ICs 95. Details of the scan IC 95 will be described later.

One scan IC 95 is connected to the plurality of scan electrodes 22, and one scan IC 95 drives the plurality of scan electrodes 22. Hereinafter, in the present embodiment, an example will be described in which panel 10 includes 1080 scan electrodes 22 (scan electrode SC1 to scan electrode SC1080), and one scan IC 95 drives 90 scan electrodes 22. Therefore, the plasma display device described in this embodiment includes 12 scan ICs 95 (scan IC 95 (1) to scan IC 95 (12)).

In this embodiment, the scan IC 95 is driven in two groups, and the first scan IC group (in this embodiment, from the scan IC 95 (1) to the scan IC 95 (6)), the second IC Different control signals are input to the scan IC groups (in this embodiment, from scan IC 95 (7) to scan IC 95 (12)).

Note that FIG. 3 simply shows the connection between the panel 10 and the scan IC 95. In FIG. 3, the display electrode pairs 24 are arranged extending in the left-right direction in the drawing (direction parallel to the long side of the panel 10), as in FIG. A region separated by a dotted line in the panel 10 represents a region where a plurality of (in this embodiment, 90) scanning electrodes 22 driven by one scanning IC 95 are arranged. The output terminal of the scan IC 95 is connected to each of the scan electrodes SC1 to SCn by a generally used flexible wiring board 77.

The plasma display device according to the present embodiment divides the display area of panel 10 into two areas as indicated by broken lines in FIG. A plurality of scan electrodes included in one region is defined as one scan electrode group. That is, scan electrode SC1 to scan electrode SCn are divided into two scan electrode groups, a first scan electrode group and a second scan electrode group, and panel 10 is driven. Hereinafter, this driving method is referred to as “two-phase driving”.

In the present embodiment, for example, when the number of scan electrodes n = 1080, scan electrode SC1 to scan electrode SC540 are set as the first scan electrode group, and scan electrode SC541 to scan electrode SC1080 are set as the second scan electrode group. Perform phase drive.

Hereinafter, a discharge cell constituted by the first scan electrode group is referred to as a “first discharge cell group”. A discharge cell constituted by the second scan electrode group is referred to as a “second discharge cell group”. In FIG. 3, two regions surrounded by a broken line are a first discharge cell group and a second discharge cell group.

For example, if the number of scan electrodes connected to one scan IC 95 is 90, first, the scan electrode SC1 to the scan electrode SC90 are connected to the first scan IC 95 (1). Next, scan electrode SC91 to scan electrode SC180 are connected to second scan IC 95 (2). In this way, 90 scanning electrodes are connected to the scanning IC 95 at a time.

Scan ICs 95 (1) to 95 (6) connected to scan electrodes SC 1 to SC 540 are set as a first scan IC group, and scan ICs 95 (7) to 95 (7) to 7 are connected to scan electrode SC 541 to scan electrode SC 1080. The scan IC 95 (12) is a second scan IC group.

In the present embodiment, panel 10 is driven by dividing a plurality of subfields constituting one field into subfields that perform two-phase driving and subfields that do not perform two-phase driving. In the sub-field that performs the two-phase driving, different initialization waveforms are generated in the first scan IC group and the second scan IC group. Hereinafter, driving that is not two-phase driving is referred to as “one-phase driving”.

The plasma display device in the present embodiment performs one-phase driving in subfield SF1 and subfield SF2, and performs two-phase driving in other subfields (for example, subfield SF3 to subfield SF8).

Hereinafter, first, the driving voltage waveform of the one-phase driving will be described, and next, the driving voltage waveform of the two-phase driving will be described.

FIG. 4 is a diagram showing a driving voltage waveform during a one-phase driving operation applied to each electrode of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

FIG. 4 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform to be applied is shown.

FIG. 4 shows driving voltage waveforms of two subfields having different driving voltage waveform shapes applied to scan electrode SC1 through scan electrode SCn during the initialization period. These two subfields are a subfield SF1 which is an all-cell initializing subfield and a subfield SF2 which is a selective initializing subfield.

Note that the drive voltage waveforms in the other subfields are substantially the same as the drive voltage waveforms in the subfield SF2 except that the number of sustain pulses generated in the sustain period is different. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the electrodes based on image data (data indicating lighting / non-lighting for each subfield).

First, the subfield SF1, which is an all-cell initialization subfield, will be described.

In the first half of the initialization period of subfield SF1, voltage 0 (V) is applied to data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. Voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn. Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.

Further, a ramp waveform voltage that gently rises from voltage Vi1 to voltage Vi2 is applied to scan electrode SC1 through scan electrode SCn. Hereinafter, this ramp waveform voltage is referred to as “up-ramp voltage L1”. Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. An example of the gradient of the up-ramp voltage L1 is a numerical value of about 1.3 V / μsec.

While the rising ramp voltage L1 rises, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. In each case, a weak initializing discharge is continuously generated. Negative wall voltage is accumulated on scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated on data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. In addition, priming particles that help generate subsequent discharge are also generated.

The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

In the latter half of the initialization period, positive voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied as the first voltage to data electrode D1 through data electrode Dm. Scan electrode SC1 through scan electrode SCn are applied with a first downward ramp waveform voltage that gently decreases from voltage Vi3 toward negative voltage Vi4.

Hereinafter, this first downward ramp waveform voltage is referred to as “down-ramp voltage L2”. Voltage Vi3 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn, and voltage Vi4 is set to a voltage exceeding the discharge start voltage. An example of the gradient of the down-ramp voltage L2 is a numerical value of about −2.5 V / μsec. Further, the voltage Vi4 is equal to a voltage obtained by superimposing the voltage Vset2 on the negative voltage Va when a scanning pulse described later is generated.

While applying the down-ramp voltage L2 to scan electrode SC1 through scan electrode SCn, scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and scan electrode SC1 through scan electrode SCn and data electrode D1 through A weak initializing discharge is generated between each data electrode Dm.

Then, the negative wall voltage on scan electrode SC1 through scan electrode SCn and the positive wall voltage on sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage on data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. In addition, priming particles that help generate subsequent discharge are also generated. The priming particles have a function of shortening the discharge delay time of the address discharge in the subsequent address period. The discharge delay time is the time from when the voltage applied to the discharge cell exceeds the discharge start voltage until the actual discharge occurs.

Thus, the all-cell initializing operation for generating the initializing discharge in all the discharge cells is completed.

Hereinafter, the period for performing the all-cell initialization operation is referred to as “all-cell initialization period”. The drive voltage waveform generated for performing the all-cell initialization operation is referred to as “all-cell initialization waveform”.

In the subsequent address period, a scan pulse of voltage Va is sequentially applied to scan electrode SC1 through scan electrode SCn. An address pulse of a positive voltage Vd is applied to data electrode D1 to data electrode Dm to data electrode Dk corresponding to the discharge cell to emit light. Thus, an address discharge is selectively generated in each discharge cell.

Specifically, following the latter half of the initialization period, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage Ve is applied to sustain electrode SU1 to sustain electrode SUn, and scan electrode SC1 to scan electrode are applied. A voltage Vc is applied to SCn.

Next, a scan pulse of the negative voltage Va is applied to the scan electrode SC1 in the first row where the address operation is performed first. At the same time, an address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row of the data electrodes D1 to Dm. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference between the externally applied voltages (voltage Vd−voltage Va). It will be added. As a result, the voltage difference between data electrode Dk and scan electrode SC1 exceeds the discharge start voltage, and a discharge is generated between data electrode Dk and scan electrode SC1.

Since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (voltage Ve−voltage Va), and sustain electrode SU1. The difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do.

Thus, a discharge is generated between the sustain electrode SU1 and the scan electrode SC1 in a region intersecting the data electrode Dk, induced by a discharge generated between the data electrode Dk and the scan electrode SC1. Thus, an address discharge is generated in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Is accumulated.

In this way, in the first row, an address operation is performed in which an address discharge is generated in the discharge cells to emit light and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode 32 and the scan electrode SC1 to which the address pulse is not applied does not exceed the discharge start voltage, so the address discharge does not occur.

Next, a scan pulse is applied to the scan electrode SC2 that performs the second address operation, and an address pulse is applied to the data electrode Dk that corresponds to the discharge cell that should emit light in the second row that performs the address operation. In the discharge cells to which the scan pulse and the address pulse are simultaneously applied, an address discharge is generated and an address operation is performed.

The above address operation is sequentially performed until the discharge cell in the n-th row, and the address period ends. In this manner, in the address period, address discharge is selectively generated in the discharge cells to emit light, and wall charges necessary for generating sustain discharge in the subsequent sustain period are formed in the discharge cells.

In the subsequent sustain period, voltage 0 (V) is applied to data electrode D1 to data electrode Dm. Then, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of positive voltage Vs is applied to scan electrode SC1 through scan electrode SCn. In the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi added to sustain pulse voltage Vs. It will be a thing.

Thereby, the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. And the fluorescent substance layer 35 light-emits with the ultraviolet-ray which generate | occur | produced by this discharge. Further, due to this discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. In a discharge cell that has generated a sustain discharge immediately before, the voltage difference between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage. As a result, a sustain discharge is generated again between sustain electrode SUi and scan electrode SCi, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi.

Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. By doing so, sustain discharge is continuously generated in the discharge cells that have generated address discharge in the address period.

After all sustain pulses are generated in the sustain period, that is, after the last sustain pulse is generated in the sustain period, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm. While being applied, an upward ramp waveform voltage that gradually rises from voltage 0 (V), which is the base potential and less than the discharge start voltage, to voltage Vr, which is a predetermined voltage, is applied to scan electrode SC1 through scan electrode SCn. Hereinafter, this upward ramp waveform voltage is referred to as “upward erasing ramp voltage L3”.

As a result, a weak discharge is continuously generated in the discharge cell in which the sustain discharge is generated, and a part of the wall voltage on the scan electrode SCi and the sustain electrode SUi is left while the positive wall voltage on the data electrode Dk remains. Or erase everything.

Specifically, ascending erase ramp voltage L3 rising from voltage 0 (V) toward voltage Vr while voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm. Is generated with a steeper slope than the up-ramp voltage L1, and is applied to scan electrode SC1 through scan electrode SCn. This gradient is, for example, about 5 V / μsec. By setting the voltage Vr to a voltage exceeding the discharge start voltage, a weak discharge is generated between the sustain electrode SUi and the scan electrode SCi of the discharge cell that has generated the sustain discharge.

The weak discharge is continuously generated during a period in which the voltage applied to scan electrode SC1 through scan electrode SCn rises above the discharge start voltage. When the increasing voltage reaches predetermined voltage Vr, the voltage applied to scan electrode SC1 through scan electrode SCn is decreased to voltage 0 (V).

In this embodiment, the voltage Vr is set to a voltage lower than the sustain pulse voltage Vs. The reason will be described later.

The charged particles generated by this weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi. Thereby, the wall voltage between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn is the difference between the voltage applied to scan electrode SCi and the discharge start voltage, for example, (voltage Vr−discharge start voltage). It is weakened to the extent. That is, the discharge generated by the ascending erasing ramp voltage L3 works as an erasing discharge.

Thereafter, scan electrode SC1 to scan electrode SCn are returned to voltage 0 (V), and the sustain operation in the sustain period ends.

In the initializing period of the subfield SF2, the voltage 0 (V) that is the first voltage is applied to the data electrodes D1 to Dm. In addition, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn. Scan electrode SC1 through scan electrode SCn gradually decrease from voltage Vi3 ′ (eg, voltage 0 (V), which is the base potential), which is less than the discharge start voltage, to negative voltage Vi4 that exceeds the discharge start voltage. A first downward ramp waveform voltage is applied.

Hereinafter, the first downward ramp waveform voltage is referred to as “down-ramp voltage L4”. The slope of the down-ramp voltage L4 may be the same as the slope of the down-ramp voltage L2, and an example thereof is a numerical value of about −2.5 V / μsec.

As a result, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the sustain period of the immediately preceding subfield (subfield SF1 in FIG. 4). Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened, and the wall voltage on data electrode Dk is also adjusted to a value suitable for the write operation.

On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period of the immediately preceding subfield, the initialization discharge does not occur, and the wall charge at the end of the immediately preceding subfield initialization period is maintained. In this way, the initialization operation in the subfield SF2 is completed.

As described above, the initializing operation in subfield SF2 is a selective initializing operation in which initializing discharge is generated only in the discharge cells in which the address discharge is generated in the address period of the immediately preceding subfield and the sustain discharge is generated in the sustain period. .

Hereinafter, the period for performing the selective initialization operation is referred to as the selective initialization period. A drive voltage waveform generated for performing the selective initialization operation is referred to as a “selective initialization waveform”.

In the address period and sustain period of the subfield SF2, the same drive voltage waveform as that in the address period and sustain period of the subfield SF1 is applied to each electrode, except for the number of sustain pulses.

The above is the outline of the driving voltage waveform during the one-phase driving operation applied to each electrode of the panel 10 when displaying an image in the present embodiment.

In the present embodiment, a one-phase driving operation is performed in the subfield SF1 and the subfield SF2. In subfield SF3 to subfield SF8, a two-phase driving operation is performed.

Next, driving voltage waveforms during the two-phase driving operation in the present embodiment will be described.

FIG. 5 is a diagram showing a driving voltage waveform during a two-phase driving operation applied to each electrode of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

In FIG. 5, the scan electrode 22 that performs the address operation at the beginning of the address period, the scan electrode SC1 that belongs to the first scan electrode group, and the scan electrode 22 that performs the address operation at the end of the first scan electrode group. Scan electrode SCn / 2 (for example, scan electrode SC540), scan electrode SCn / 2 + 1 (for example, scan electrode SC541) that is the scan electrode 22 that performs the address operation first in the second scan electrode group, and the address period Finally, scan electrode 22 that performs an address operation is applied to each of scan electrode SCn (for example, scan electrode SC1080) belonging to the second scan electrode group, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. The drive voltage waveform to be shown is shown.

In the present embodiment, subfield SF3 to subfield SF8 are selective initialization subfields.

In the initialization period of the subfield SF3, an adjustment period TSF is first generated.

In this adjustment period TSF, a voltage at which no discharge occurs in the discharge cell is applied to each electrode. That is, during the adjustment period TSF, the display electrode pair 24 and the data electrode 32 are maintained at the base potential. Therefore, during the adjustment period TSF, voltage 0 (V), which is the base potential, is applied to data electrode D1 to data electrode Dm, sustain electrode SU1 to sustain electrode SUn, and scan electrode SC1 to scan electrode SCn.

After adjustment period TSF, positive voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm.

In this embodiment, scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group and scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group are different from each other. Apply an initialization waveform of waveform shape. Specifically, the first and second scan electrode groups generate different down-slope waveform voltages having the lowest potential of the down-slope waveform voltage, and apply them to the scan electrodes.

The drive voltage waveform having the same waveform as the down-ramp voltage L4 described as the selective initialization waveform is applied to scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group. Therefore, hereinafter, this drive voltage waveform is also referred to as “first downward ramp waveform voltage”. That is, the first downward ramp waveform voltage (down-ramp voltage L4) is a negative voltage Vi4 that exceeds the discharge start voltage from voltage Vi3 ′ that is less than the discharge start voltage with respect to sustain electrode SU1 to sustain electrode SUn / 2. That is, it is a ramp waveform voltage that drops to voltage Va + voltage Vset2.

As a result, for the first discharge cell group formed on the first scan electrode group, the sustain period of the immediately preceding subfield (subfield SF2 in FIG. 5) is similar to the initialization period of subfield SF2. A weak initializing discharge is generated only in the discharge cells that have generated the sustain discharge.

For scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group, a second down-slope waveform voltage (hereinafter referred to as “down-ramp”) that gently falls from voltage Vi3 ′ toward negative voltage (Va + Vset5). (Referred to as voltage L8 "). At this time, the voltage Vset5 is set to a voltage higher than the voltage Vset2. In the present embodiment, for example, the voltage Vset2 is set to 25 (V), and the voltage Vset5 is set to 70 (V).

Thus, in this embodiment, the lowest voltage of the down-ramp voltage L8 applied to the second scan electrode group is higher than the lowest low voltage Vi4 of the down-ramp voltage L4 applied to the first scan electrode group. To do. Accordingly, the down-ramp voltage L4 applied to the first scan electrode group drops to the voltage (Va + Vset2), whereas the down-ramp voltage L8 applied to the second scan electrode group is higher than the voltage (Va + Vset2). It descends only to (Va + Vset5).

Thereby, almost no discharge is generated in the second discharge cell group formed on the second scan electrode group. Therefore, after the initialization operation with the down-ramp voltage L8, more wall charges remain in each discharge cell of the second discharge cell group than in each discharge cell of the first discharge cell group.

In the subsequent address period, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc (Vc = Va + Vscn) is applied to scan electrode SC1 through scan electrode SCn, as in the address period in subfield SF1 and subfield SF2.

Then, scan pulses are sequentially applied to scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group, similarly to the address period of subfield SF1 and subfield SF2. That is, an address operation for generating an address discharge by applying an address pulse to the discharge cells to emit light is sequentially performed from the discharge cells in the first row to the discharge cells in the n / 2th row.

Thus, the address operation in the first discharge cell group is completed.

After the address operation to the first scan electrode group is completed, before starting the address operation to the second scan electrode group, a negative voltage from the voltage 0 (V), which is a base potential lower than the discharge start voltage, is set. A third downward ramp waveform voltage (hereinafter referred to as “down-ramp voltage L9”) that gently falls toward the voltage (Va + Vset3) is applied to the second scan electrode group.

In the present embodiment, the voltage Vset3 is set to a voltage lower than the voltage Vset2. For example, the voltage Vset2 is 25 (V) and the voltage Vset3 is 22 (V). As a result, the down-ramp voltage L9 becomes a down-slope waveform voltage that drops to a voltage lower than the down-ramp voltage L4 (for example, to a voltage 3 (V) lower than the down-ramp voltage L4).

Thus, in the present embodiment, after the address operation to the first scan electrode group is completed, the down-ramp voltage L9 drops to a voltage (Va + Vset3) lower than the voltage Vi4 that is the lowest voltage of the down-ramp voltage L4. Is applied to the second scan electrode group.

As described above, the down-ramp voltage L8 applied to the second scan electrode group during the initialization period only drops to a negative voltage (Va + Vset5). Therefore, more wall charges remain in each discharge cell of the second discharge cell group than in each discharge cell of the first discharge cell group.

Then, by setting the voltage Vset3 to a voltage sufficiently lower than the voltage Vset5, the downramp voltage L9 can be lowered to a voltage sufficiently lower than the downramp voltage L8. Thereby, in each discharge cell of the second discharge cell group, an initializing discharge can be generated in a discharge cell that has generated a sustain discharge in the sustain period of the immediately preceding subfield (subfield SF2 in FIG. 5). In the present embodiment, for example, the voltage Vset3 is set to 22V, the voltage Vset5 is set to 70 (V), and the down-ramp voltage L9 is lowered to a voltage sufficiently lower than the down-ramp voltage L8.

Therefore, in each discharge cell of the second discharge cell group, an initialization operation can be performed immediately before starting an address operation to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. .

The wall charge formed by the initialization discharge decreases with time. Therefore, in the drive method (one-phase drive) in which the initialization operation is performed only in the initialization period immediately before the address period in all the scan electrodes 22, the order of the address operation in the discharge cells in which the order of the address operation in the address period is slow. There is a risk that the wall charge is reduced more than in the early discharge cell, and the address operation becomes unstable.

However, in the present embodiment, the initialization operation is performed on the second discharge cell group immediately before the address operation is started in the second scan electrode group in the address period. Therefore, in the second discharge cell group, the wall charges can be brought into an appropriate state immediately before the address operation is started. Accordingly, even in the discharge cells belonging to the second discharge cell group whose address operation is late in the address period, it is possible to perform a stable address operation without increasing the applied voltage necessary for the address discharge.

FIG. 5 shows a waveform diagram in which the down-ramp voltage L9 is applied to the first scan electrode group at the same timing as the down-ramp voltage L9 is applied to the second scan electrode group. This is due to the following reason.

In each discharge cell on the first scan electrode group that has already finished the address operation, it is desirable not to generate unnecessary discharge until the subsequent sustain operation. Accordingly, it is desirable to apply a voltage at which no discharge occurs, for example, voltage 0 (V), to the first scan electrode group during the period in which the down-ramp voltage L9 is applied to the second scan electrode group.

However, due to the configuration of the drive circuit that drives the scan electrode 22, the voltage 0 (V) is applied to the first scan electrode group during the period in which the down-ramp voltage L9 is applied to the second scan electrode group. It may be difficult to generate a drive voltage waveform.

On the other hand, in each discharge cell of the first discharge cell group, a down-ramp voltage L4 that drops to the voltage (Va + Vset2) in the initialization period is applied to the first scan electrode group (scan electrode SC1 to scan electrode SCn / 2). Then perform the initialization operation. Therefore, even if the down-ramp voltage L9 that falls to a voltage (Va + Vset3) slightly lower than the voltage (Va + Vset2) is applied to the first scan electrode group in the middle of the address period, each discharge cell of the first discharge cell group It is very unlikely that initializing discharge will occur again. Therefore, even if the down-ramp voltage L6 is applied to the first scan electrode group during the address period, there is no problem.

The above is the reason why the waveform diagram for applying the down-ramp voltage L9 to the first scan electrode group is shown in FIG.

After applying the down-ramp voltage L9 to the second scan electrode group, scan pulses are sequentially applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group in the same procedure as described above. To do.

The above address operation is performed up to the discharge cell in the nth row, and the address operation in the second discharge cell group is completed. Thus, the writing period in subfield SF3 is completed.

Note that, during the period in which the down-ramp voltage L9 is applied to the second scan electrode group, the voltage 0 (V) is applied to the data electrodes D1 to Dm.

In the sustain period of subfield SF3, the same drive voltage waveform as in the sustain period of subfield SF2 is applied to each electrode, except for the number of sustain pulses generated. In each subfield after subfield SF4, the drive voltage waveform substantially similar to that of subfield SF3 is applied to each electrode, except for the number of sustain pulses.

However, in subfield SF3 and subfield SF4, and in subfield SF5 to subfield SF8, each scan electrode 22 (scan electrode SCn) of the second scan electrode group immediately after the write operation to the first scan electrode group is completed. The minimum voltage of the third downward ramp waveform voltage applied to / 2 + 1 to scan electrode SCn) is slightly changed.

FIG. 6 is a diagram showing drive voltage waveforms during a two-phase drive operation applied to each electrode of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

In the subfield SF3 and the subfield SF4, as shown in FIG. 5, immediately after the write operation to the first scan electrode group is completed, the voltage drops to the voltage Va + voltage Vset3 as the third downward ramp waveform voltage. The ramp voltage L9 is applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. However, in the subfield SF5 to the subfield SF8, as shown in FIG. 6, immediately after the address operation to the first scan electrode group is completed, the base that becomes less than the discharge start voltage as the third downward ramp waveform voltage is obtained. A down-ramp voltage L10 that drops from voltage 0 (V) as a potential to voltage Va + voltage Vset4 is applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to each scan electrode 22 of the second scan electrode group.

In the present embodiment, the voltage Vset4 is set to a voltage lower than the voltage Vset2 and higher than the voltage Vset3. For example, the voltage Vset2 is 25 (V), the voltage Vset3 is 22 (V), and the voltage Vset4 is 23 (V). As a result, the down-ramp voltage L9 becomes a third down-slope waveform voltage that drops to a voltage that is, for example, 3 (V) lower than the down-ramp voltage L4. The down-ramp voltage L10 is a third down-slope waveform voltage that drops to a voltage that is 2 (V) lower than the down-ramp voltage L4, for example.

The above is the outline of the driving voltage waveform during the two-phase driving operation applied to each electrode of the panel 10 when displaying an image in the present embodiment.

In this embodiment, for example, voltages Vi1 = 150 (V), voltage Vi2 = 350 (V), voltage Vi3 = 215 (V), and voltage Vi3 ′ = 0 ( V), voltage Vi4 = −175 (V), voltage Vc = −50 (V), voltage Va = −200 (V), voltage Vs = 215 (V), voltage Vr = 200 (V), voltage Ve = 170 (V), voltage Vd = 60 (V), Vset2 = 25 (V), Vset3 = 22 (V), Vset4 = 23 (V), Vset5 = 70 (V). However, these voltage values are only examples in the embodiment. Each voltage value is not limited to the value described above, and it is desirable to set the voltage value to an optimal value as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device.

Next, the adjustment period TSF in the present embodiment will be described.

FIG. 7 is a diagram showing an example of parameters of the driving voltage waveform in the first embodiment of the present invention.

FIG. 7 shows the length of the adjustment period TSF in each subfield, the presence / absence of two-phase driving, and the voltage value of voltage Vset2-voltage Vset3 or voltage Vset2-voltage Vset4. Further, “◯” shown in FIG. 7 indicates that two-phase driving is performed in the subfield.

In this embodiment, as shown in FIG. 7, in the subfield SF1 and the subfield SF2, the one-phase driving whose drive voltage waveform is shown in FIG. 4 is performed. Then, in the subfield SF3 to the subfield SF8, two-phase driving whose driving voltage waveform is shown in FIG. 5 or FIG. 6 is performed.

In this embodiment, the adjustment period TSF is set in accordance with the number of sustain pulses generated in the sustain period of the immediately preceding subfield in the subfield that performs two-phase driving.

For example, assume that the luminance weight of each subfield of subfield SF1 to subfield SF8 is (1, 2, 4, 8, 16, 32, 64, 128). At this time, as shown in an example in FIG. 7, the adjustment period TSF is set to 50 μsec in the subfield SF3 and the subfield SF4. In subfield SF5, adjustment period TSF is set to 100 μsec. In subfield SF6, adjustment period TSF is set to 200 μsec. In subfield SF7, adjustment period TSF is set to 300 μsec. In the subfield SF8, the adjustment period TSF is set to 400 μsec.

Thus, in the present embodiment, the adjustment period TSF is lengthened as the number of sustain pulses generated in the sustain period of the immediately preceding subfield increases. This is due to the following reason.

Priming particles and wall charges are generated by the sustain discharge in the discharge cell where the sustain discharge has occurred in the sustain period of the immediately preceding subfield. The amount of priming particles and wall charges generated increases as the number of sustain pulses generated in the sustain period increases.

In this embodiment, as described above, the priming particles and wall charges generated by the sustain discharge are erased by the erasing discharge with the ascending erasing ramp voltage L3. However, some priming particles and wall charges remain without being erased. If the number of sustain pulses generated in the sustain period increases and excessive priming particles and wall charges are generated, the erasing discharge with the ascending erasing ramp voltage L3 cannot sufficiently erase, and the amount of remaining priming particles and wall charges Will increase.

In such a discharge cell, a strong initializing discharge occurs during the selective initializing operation, and the wall charge in the discharge cell is excessively adjusted. As a result, in such a discharge cell, address discharge is less likely to occur, and the possibility of occurrence of “address failure” increases. “Writing failure” is a phenomenon in which address discharge does not occur in a discharge cell to which an address pulse is applied. Therefore, in such a discharge cell, the amplitude of the address pulse necessary for stably generating the address discharge increases.

However, the inventor of the present application confirmed by experiments that the occurrence of the write failure can be reduced in such a discharge cell by providing the adjustment period TSF.

FIG. 8 is a diagram showing the relationship between the adjustment period TSF and the voltage Vset in the first embodiment of the present invention.

In FIG. 8, the voltage difference between the lowest voltage of the downward ramp waveform voltage generated in the selective initialization operation and the voltage Va is denoted as “voltage Vset”. In FIG. 8, the horizontal axis represents the adjustment period TSF, and the vertical axis represents the voltage Vset.

8, the graph plotted with a circle represents the upper limit of the voltage Vset that can stably generate the address discharge in the subsequent address period. If the voltage Vset is set to a voltage exceeding this upper limit, there is a high possibility that erroneous discharge will occur in the subsequent address period. This erroneous discharge is a phenomenon in which an address discharge occurs even in a discharge cell to which an address pulse is not applied (a discharge cell to which only a scan pulse is applied).

Further, in FIG. 8, the graph plotted with triangles represents the lower limit of the voltage Vset that can stably generate the address discharge in the subsequent address period. If the voltage Vset is set to a voltage lower than this lower limit, there is a high possibility that a write failure will occur in the subsequent write period.

Therefore, the smaller the lower limit, the smaller the amplitude of the write pulse necessary for preventing the occurrence of write failure in the subsequent write period. That is, if this lower limit is made small, the amplitude of the write pulse necessary for performing a stable write operation can be reduced.

As shown in FIG. 8, as the adjustment period TSF is lengthened, the voltage Vset that can stably generate the address discharge in the subsequent address period decreases. This is because the priming particles and wall charges decrease with time, so that the longer the adjustment period TSF, the more priming particles and wall charges decrease during the adjustment period TSF, which occurs during the selective initialization operation. This is because the initializing discharge becomes weaker and the wall charges in the discharge cell are adjusted more appropriately.

Therefore, in the present embodiment, as shown in FIG. 7, the adjustment period TSF is lengthened as the number of sustain pulses generated in the sustain period of the immediately preceding subfield increases.

In the present embodiment, the minimum voltage of the downward ramp waveform voltage (first phase downward ramp waveform voltage) generated in the initialization period and the downlink generated in the middle of the writing period according to the length of the adjustment period TSF. The voltage difference with the ramp waveform voltage (second phase descending ramp waveform voltage) is changed.

5 and 6, the down-ramp voltage L4 is the first-phase down-slope waveform voltage, and the down-ramp voltage L9 and the down-ramp voltage L10 are the second-phase down-slope waveform voltage.

In the example shown in FIG. 7, in the subfield SF3 and subfield SF4 in which the adjustment period TSF is set to 50 μsec, the difference between the lowest voltage of the first-phase downward ramp waveform voltage and the lowest voltage of the second-phase downward ramp waveform voltage ( In the example shown in FIG. 5, the first-phase downward ramp waveform voltage and the second-phase downward ramp waveform voltage are generated such that the voltage Vset2-voltage Vset3) is 3 (V).

In the example shown in FIG. 5, for example, the voltage Vset2 is set to 25 (V) to generate the downward ramp voltage L4, and the voltage Vset3 is set to 22 (V) to generate the downward ramp voltage L9.

In the example shown in FIG. 7, in the subfield SF5 to the subfield SF8 in which the adjustment period TSF is set to 100 μsec or more, the lowest voltage of the first-phase downward ramp waveform voltage and the lowest voltage of the second-phase downward ramp waveform voltage are The first-phase down-slope waveform voltage and the second-phase down-slope waveform voltage are generated so that the difference between them (corresponding to the voltage Vset2-voltage Vset4 in the example shown in FIG. 6) is 2 (V). .

In the example shown in FIG. 6, for example, the voltage Vset2 is set to 25 (V) to generate the down-ramp voltage L4, and the voltage Vset4 is set to 23 (V) to generate the down-ramp voltage L10.

This is because, when the length of the adjustment period TSF is short, the inventor of the present application has the lowest voltage of the downward ramp waveform voltage (first phase downward ramp waveform voltage) generated during the initialization period and the downward shift generated during the writing period. This is because it has been confirmed by experiments that the writing operation can be performed more stably by increasing the voltage difference from the ramp waveform voltage (second phase descending ramp waveform voltage) than when the adjustment period TSF is long.

FIG. 9 is a diagram showing an example of the relationship between the adjustment period TSF and the voltage Vset in the first embodiment of the present invention.

FIG. 10 is a diagram showing another example of the relationship between the adjustment period TSF and the voltage Vset in the first embodiment of the present invention.

In FIG. 9 and FIG. 10, the voltage difference between the lowest voltage of the first-phase downward ramp waveform voltage generated in the selective initialization operation and the voltage Va is denoted as voltage Vset.

In the experiments whose results are shown in FIGS. 9 and 10, one field is composed of eight subfields from subfield SF1 to subfield SF8, and the luminance weight of each subfield from subfield SF1 to subfield SF8 is ( 1, 2, 4, 8, 16, 32, 64, 128).

Further, in the experiment whose result is shown in FIG. 10, each parameter of the drive voltage waveform is set to the numerical value shown in FIG. Further, in the experiment whose result is shown in FIG. 9, each parameter of the drive voltage waveform is set to Vset−Vset3 = 2 (V) in the subfield SF3 and the subfield SF4, and other parameters are set to the numerical values shown in FIG. Set.

9 and 10, the graphs plotted with circles and solid lines represent the upper limit of the voltage Vset in the first-phase falling ramp waveform voltage that can stably generate the address discharge in the subsequent address period. The graph plotted with a circle and a broken line represents the upper limit of the voltage Vset in the second-phase downward ramp waveform voltage that can generate the address discharge stably in the subsequent address period. Also, the graph plotted with a triangle mark and a solid line represents the lower limit of the voltage Vset in the first-phase downward ramp waveform voltage that can generate the address discharge stably in the subsequent address period. The graph plotted with a triangle mark and a broken line represents the lower limit of the voltage Vset in the second-phase downward ramp waveform voltage that can generate the address discharge stably in the subsequent address period.

When the voltage Vset is set to a voltage exceeding this upper limit, there is a high possibility that erroneous discharge will occur in the subsequent address period. This erroneous discharge is a phenomenon in which an address discharge occurs even in a discharge cell to which an address pulse is not applied (a discharge cell to which only a scan pulse is applied).

Also, if the voltage Vset is set to a voltage lower than this lower limit, the possibility of a write failure occurring in the subsequent write period increases.

Therefore, the larger the difference (margin) between the upper limit and the lower limit, the more stable the write operation can be performed in the subsequent write period.

In FIG. 9, the smallest value of the upper limit of Vset is the upper limit of the voltage Vset at the second-phase downward ramp waveform voltage in the subfield SF3, which is about 85.5 (V). The largest value of the lower limit of Vset is the lower limit of voltage Vset in the first-phase downward ramp waveform voltage in subfield SF4, which is about 76 (V). The difference between the upper limit and the lower limit is about 9.5 (V).

On the other hand, in FIG. 10, the smallest value of the upper limit of Vset is the upper limit of voltage Vset in the second-phase downward ramp waveform voltage in subfield SF3, which is about 86.5 (V). The largest value of the lower limit of Vset is the lower limit of voltage Vset in the first-phase downward ramp waveform voltage in subfield SF4, which is about 76 (V). The difference between the upper limit and the lower limit is about 10.5 (V), which is about 1 (V) larger than the result shown in FIG. This indicates that the margin of the voltage Vset is increased, and the write operation can be stably performed correspondingly.

Thus, when the length of the adjustment period TSF is short, the minimum voltage of the downward ramp waveform voltage (first-phase downward ramp waveform voltage) generated during the initialization period and the downward ramp waveform voltage generated during the write period ( Experiments have confirmed that the voltage difference from the second-phase downward ramp waveform voltage) is larger than when the adjustment period TSF is long, so that the margin of the voltage Vset is increased and the writing operation can be performed more stably. It was.

This is thought to be because the remaining amount of priming particles and wall charges increases as the length of the adjustment period TSF becomes shorter.

From these facts, in this embodiment, for example, as shown in FIGS. 5 and 6, in the initialization period of the subfield in which the two-phase drive is performed, the voltage 0 (V) is used as the first-phase downward ramp waveform voltage. The ramp-down voltage L4 that falls from the voltage Va to the voltage Vset2 is generated. Further, in the writing period of the subfield in which the length of the adjustment period TSF is relatively short, a down-ramp voltage L9 that falls from the voltage 0 (V) to the voltage Va + voltage Vset3 is generated as the second-phase down-slope waveform voltage. Further, in the address period of the subfield in which the length of the adjustment period TSF is relatively long, a down-ramp voltage L10 that falls from the voltage 0 (V) to the voltage Va + voltage Vset4 is generated as the second-phase downward ramp waveform voltage.

Then, as shown in FIG. 7, for example, the voltages Vset2, Vset3, and Vset4 are set so that the voltage Vset2-voltage Vset3 is larger than the voltage Vset2-voltage Vset4.

In the present embodiment, the example in which the adjustment period TSF is not provided in the subfield that performs one-phase driving has been described. However, as described above, the adjustment period TSF in the present embodiment is provided to adjust excessively generated priming particles and wall charges. Therefore, an adjustment period TSF may be provided in a subfield that performs one-phase driving.

Next, the reason why the voltage Vr, which is the arrival potential of the ascending erasing ramp voltage L3, is set to a voltage lower than the sustain pulse voltage Vs will be described.

FIG. 11 is a diagram showing the relationship between the voltage difference between the voltage Vr and the voltage Vs and the voltage Vset2 in the first embodiment of the present invention.

11, the horizontal axis represents the voltage difference between the voltage Vr and the voltage Vs, that is, the voltage Vr−the voltage Vs, and the vertical axis represents the voltage Vset2.

In FIG. 11, the graph plotted with a circle represents the upper limit of the voltage Vset2 that can stably generate the address discharge in the subsequent address period. If the voltage Vset2 is set to a voltage exceeding this upper limit, the possibility of erroneous discharge occurring in the subsequent address period increases. This erroneous discharge is a phenomenon in which an address discharge occurs even in a discharge cell to which an address pulse is not applied (a discharge cell to which only a scan pulse is applied).

In FIG. 11, the graph plotted with triangles represents the lower limit of the voltage Vset2 at which address discharge can be stably generated in the subsequent address period. If the voltage Vset2 is set to a voltage lower than this lower limit, the possibility of a write failure occurring in the subsequent write period increases.

Therefore, the larger the difference between the upper limit and the lower limit, the more stable the write operation can be performed in the subsequent write period.

In the graph shown in FIG. 11, the voltage Vs = 215 (V) and the voltage Va = −200 (V) are set, and the voltage Vr is 5 (V) from the voltage Vs + 5 (V) to the voltage Vs−30 (V). An experiment is performed in the procedure of confirming the occurrence of discharge by changing the voltage Vset2 while changing the voltage step by step, and the obtained result is shown.

As shown in FIG. 11, when the voltage Vr−the voltage Vs is 0 (V), that is, when the voltage Vr = the voltage Vs, the upper limit (approximately 83.5 (V)) and the lower limit (approximately The difference from 76.5 (V)) was about 7 (V).

When the voltage Vr−the voltage Vs is −5 (V), that is, when the voltage Vr = the voltage Vs−5 (V), the upper limit (about 84.1 (V)) and the lower limit (about 76 (V) of the voltage Vset2 are set. The difference from V)) was about 8.1 (V).

When the voltage Vr−the voltage Vs is −10 (V), that is, when the voltage Vr = the voltage Vs−10 (V), the upper limit (about 85.2 (V)) and the lower limit (about 75.V.) of the voltage Vset2. The difference from 5 (V)) was about 9.7 (V).

When the voltage Vr−the voltage Vs is −15 (V), that is, when the voltage Vr = the voltage Vs−15 (V), the upper limit (about 85.5 (V)) and the lower limit (about 74 (V) of the voltage Vset2 are set. The difference from V)) was about 11.5 (V).

When the voltage Vr−the voltage Vs is −20 (V), that is, when the voltage Vr = the voltage Vs−20 (V), the upper limit (approximately 85.2 (V)) and the lower limit (approximately 73.V.) of the voltage Vset2. 5 (V)) was about 11.7 (V).

When the voltage Vr−the voltage Vs is −25 (V), that is, when the voltage Vr = the voltage Vs−25 (V), the upper limit (about 85.5 (V)) and the lower limit (about 73 ( The difference from V)) was about 12.5 (V).

When the voltage Vr−the voltage Vs is −30 (V), that is, when the voltage Vr = the voltage Vs−30 (V), the upper limit (about 85.4 (V)) and the lower limit (about 73 ( The difference from V)) was about 12.4 (V).

Thus, from the result shown in FIG. 11, by setting the voltage Vr to a voltage lower than the voltage Vs, the address discharge can be stably performed in the subsequent address period, compared to when the voltage Vr is set to a voltage equal to the voltage Vs. It was confirmed that the write operation can be stabilized by increasing the difference between the upper limit and the lower limit of the voltage Vset2 that can be generated.

This is because, by setting the voltage Vr to a voltage lower than the voltage Vs, the duration of the erasing discharge is shortened and the wall charge generated by the sustain discharge is less than when the voltage Vr is set to a voltage equal to the voltage Vs. It is considered that a larger amount remains, and as a result, the discharge generated between the scan electrode 22 and the sustain electrode 23 becomes more stable.

Therefore, in this embodiment, the voltage Vr is set to a voltage lower than the voltage Vs.

However, when the voltage Vr−the voltage Vs is −35 (V) or less, that is, when the voltage Vr is set to the voltage Vs−35 (V) or less, the sustain discharge is performed even in the discharge cell to which the address pulse is not applied in the subsequent sustain period. Has been confirmed to be more likely to persist. This is presumably because the erase discharge is insufficient due to the voltage Vr being lowered too much, and the remaining amount of wall charges and priming particles becomes excessive.

Thus, it has been confirmed that if the voltage Vr is too low, there is a risk of erroneous discharge occurring in the subsequent sustain period. Therefore, in the present embodiment, the voltage Vr is set to a voltage that is lower than the voltage Vs and does not cause erroneous discharge in the subsequent sustain period.

Specifically, in this embodiment, the voltage Vr is set in the range of the voltage Vs-5 (V) to the voltage Vs-30 (V) based on the characteristics shown in FIG. For example, the voltage Vs = 215 (V) and the voltage Vr = 200 (V) are set.

However, these voltage values are only examples in the embodiment. Each voltage value is not limited to the value described above, and it is desirable to set the voltage value to an optimal value as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device.

Next, the configuration of the plasma display device in the present embodiment will be described. In the following description, the operation of conducting the switching element is represented as “on”, and the operation of shutting off is represented as “off”.

FIG. 12 is a circuit block diagram of plasma display device 40 in accordance with the first exemplary embodiment of the present invention.

The plasma display device 40 includes a panel 10 and a drive circuit that drives the panel 10. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.

The image signal processing circuit 41 assigns a gradation value to each discharge cell based on the input image signal. Then, the gradation value is converted into image data indicating light emission / non-light emission for each subfield.

For example, when the input image signal sig includes an R signal, a G signal, and a B signal, R, G, and B gradation values (in one field) are assigned to each discharge cell based on the R signal, the G signal, and the B signal. Assigned gradation value). Alternatively, when the input image signal sig includes a luminance signal (Y signal) and a saturation signal (C signal, RY signal and BY signal, or u signal and v signal), the luminance signal and R, G, and B signals are calculated based on the saturation signal, and thereafter, R, G, and B gradation values are assigned to the respective discharge cells. Then, the R, G, and B gradation values assigned to each discharge cell are converted into image data indicating light emission / non-light emission for each subfield.

The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. Then, the generated timing signal is supplied to each circuit block (image signal processing circuit 41, data electrode drive circuit 42, scan electrode drive circuit 43, sustain electrode drive circuit 44, etc.).

Scan electrode drive circuit 43 has an initialization waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown). The initialization waveform generating circuit generates an initialization waveform to be applied to scan electrode SC1 through scan electrode SCn during the initialization period. The sustain pulse generation circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn during the sustain period. The scan pulse generating circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period. Scan electrode driving circuit 43 drives scan electrode SC1 through scan electrode SCn based on the timing signal supplied from timing generation circuit 45, respectively.

The data electrode drive circuit 42 converts the data for each subfield constituting the image data into address pulses corresponding to the data electrodes D1 to Dm. Then, based on the timing signal supplied from the timing generation circuit 45, an address pulse is applied to each of the data electrodes D1 to Dm.

Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit for generating voltage Ve (not shown), and drives sustain electrode SU1 through sustain electrode SUn based on the timing signal supplied from timing generation circuit 45.

FIG. 13 is a circuit diagram schematically showing a configuration of scan electrode drive circuit 43 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention.

The scan electrode drive circuit 43 includes a sustain pulse generation circuit 50, a ramp waveform voltage generation circuit 60, and a scan pulse generation circuit 70. Each circuit block operates based on the timing signal supplied from the timing generation circuit 45, but details of the timing signal path are omitted in FIG. The voltage input to the scan pulse generation circuit 70 is referred to as “reference potential A”.

Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59. The power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode Di11, a diode Di12, a resonance inductor L11, and an inductor L12.

The power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L12, and stores it in the capacitor C10. The recovered power is LC-resonated between the interelectrode capacitance of the panel 10 and the inductor L11, supplied again from the capacitor C10 to the panel 10, and reused as power when driving the scan electrodes SC1 to SCn.

Switching element Q55 clamps scan electrode SC1 through scan electrode SCn to voltage Vs, and switching element Q56 clamps scan electrode SC1 through scan electrode SCn to voltage 0 (V). The switching element Q59 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

Thus, sustain pulse generating circuit 50 generates a sustain pulse of voltage Vs applied to scan electrode SC1 through scan electrode SCn.

Scan pulse generation circuit 70 includes switching element Q71H1 to switching element Q71Hn, switching element Q71L1 to switching element Q71Ln, switching element Q72, a power source that generates negative voltage Va, and a power source E71 that generates voltage Vp. Then, the voltage Vp (Vc = Va + Vp) is generated by superimposing the voltage Vp on the reference potential A of the scan pulse generation circuit 70, and is applied to scan electrode SC1 through scan electrode SCn while switching between voltage Va and voltage Vc. A scan pulse is generated. For example, if the voltage Va = −200 (V) and the voltage Vp = 150 (V), the voltage Vc = −50 (V).

Scan pulse generation circuit 70 sequentially applies scan pulses to scan electrode SC1 through scan electrode SCn at the timings shown in FIGS. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain period. That is, the reference potential A is output to scan electrode SC1 through scan electrode SCn.

The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61, a Miller integration circuit 62, and a Miller integration circuit 63, and generates the ramp waveform voltages shown in FIGS.

Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. Then, by applying a constant voltage to the input terminal IN61 (giving a constant voltage difference between two circles shown as the input terminal IN61), an upward ramp waveform voltage that gradually increases toward the voltage Vt is obtained. appear.

In the present embodiment, the voltage Vi2 is set to be equal to a voltage obtained by superimposing the voltage Vp on the voltage Vt. That is, when Miller integrating circuit 61 is operated, switching element Q72 and switching elements Q71L1 to Q71Ln are turned off, switching elements Q71H1 to switching element Q71Hn are turned on, and the upward slope generated in Miller integrating circuit 61 The up-ramp voltage L1 is generated by superimposing the voltage Vp of the power source E71 on the waveform voltage.

Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode Di62 for preventing backflow. Then, by applying a constant voltage to the input terminal IN62 (giving a constant voltage difference between two circles shown as the input terminal IN62), an up-slope waveform voltage that gradually rises toward the voltage Vr ( Ascending erasing ramp voltage L3) is generated.

Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63. Then, by applying a constant voltage to the input terminal IN63 (giving a constant voltage difference between two circles shown as the input terminal IN63), a downward ramp waveform voltage (gradiently decreasing toward the voltage Vi4 ( Down-ramp voltage L2 and down-ramp voltage L4) are generated.

Note that the switching element Q69 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

Note that these switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 45.

FIG. 14 is a circuit diagram schematically showing a configuration of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention.

The sustain electrode driving circuit 44 includes a sustain pulse generating circuit 80 and a constant voltage generating circuit 85. Each circuit block operates based on the timing signal supplied from the timing generation circuit 45, but details of the timing signal path are omitted in FIG.

Sustain pulse generation circuit 80 includes a power recovery circuit 81, a switching element Q83, and a switching element Q84. The power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode Di21, a diode Di22, a resonance inductor L21, and an inductor L22.

The power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L22, and stores it in the capacitor C20. Then, the recovered power is supplied to the panel 10 again from the capacitor C20 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L21, and reused as power when driving the sustain electrodes SU1 to SUn.

Switching element Q83 clamps sustain electrode SU1 through sustain electrode SUn to voltage Vs, and switching element Q84 clamps sustain electrode SU1 through sustain electrode SUn to voltage 0 (V).

Thus, sustain pulse generating circuit 80 generates a sustain pulse of voltage Vs applied to scan electrode SC1 through scan electrode SCn.

The constant voltage generation circuit 85 includes a switching element Q86 and a switching element Q87. Then, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn.

In addition, these switching elements can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements are controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

FIG. 15 is a circuit diagram schematically showing the configuration of the data electrode drive circuit 42 of the plasma display device 40 according to the first embodiment of the present invention.

The data electrode drive circuit 42 operates based on the image data supplied from the image signal processing circuit 41 and the timing signal supplied from the timing generation circuit 45. In FIG. 15, details of the paths of these signals are omitted. To do.

The data electrode driving circuit 42 has switching elements Q91H1 to Q91Hm and switching elements Q91L1 to Q91Lm. The voltage 0 (V) is applied to the data electrode Dj by turning on the switching element Q91Lj, and the voltage Vd is applied to the data electrode Dj by turning on the switching element Q91Hj.

Next, details of the scan pulse generation circuit 70 will be described.

FIG. 16 is a circuit diagram of scan pulse generation circuit 70 in the first exemplary embodiment of the present invention.

In the following description, the operation to turn on the switching element is expressed as “on”, the operation to turn off the switching element is expressed as “off”, the signal to turn on the switching element is expressed as “Hi”, and the signal to turn off is expressed as “Lo”. To do. Each circuit block operates based on the timing signal supplied from the timing generation circuit 45, but details of the timing signal path are omitted in FIG.

Scan pulse generating circuit 70 includes a plurality of scan ICs 95, switching element Q72, diode Di31 and capacitor C31, comparator CP1 and comparator CP2, switching element SW1, switching element SW2, switching element SW3, and OR gate. OR and AND gate AG are provided.

A plurality of scan ICs 95 (in this embodiment, scan IC 95 (1) to scan IC 95 (12)) output scan pulses to scan electrode SC1 to scan electrode SCn, respectively.

The switching element Q72 connects the reference potential A to the negative voltage Va in the writing period.

The diode Di31 and the capacitor C31 are circuit elements for applying a voltage obtained by superimposing the voltage Vp on the reference potential A to the high voltage side (input terminal INb) of the scan IC 95.

The comparator CP1 and the comparator CP2 compare the magnitudes of the input signals input to the two input terminals.

Switching element SW1 applies a voltage (Va + Vset2) to one input terminal of comparator CP1. The switching element SW2 applies a voltage (Va + Vset3) to one input terminal of the comparator CP1. The switching element SW3 applies a voltage (Va + Vset4) to one input terminal of the comparator CP1.

The OR gate OR includes a control signal SID (control signal SID (1) in the present embodiment) for controlling the scan IC 95 (scan IC 95 (7) in the present embodiment) and an output signal CPO of the comparator CP2. Perform the logical OR operation.

The AND gate AG is a logic between a control signal OC1 which is a first control signal for controlling the scan IC 95 (in this embodiment, scan IC 95 (1) to scan IC 95 (6)) and an output signal of the OR gate OR. Perform product operation.

The other input terminal of the comparator CP1 is connected to the reference potential A. One input terminal of the comparator CP2 is connected to the voltage (Va + Vset5), and the other input terminal of the comparator CP2 is connected to the reference potential A.

The scan IC 95 has two input terminals, ie, an input terminal INa that is an input terminal on the low voltage side and an input terminal INb that is an input terminal on the high voltage side, and a plurality of output terminals respectively connected to the scan electrodes. Then, the scan IC 95 outputs one of the voltages input to the two input terminals from each output terminal based on the control signal.

In this embodiment, the scan IC 95 is driven in two groups, and the first scan IC group (in this embodiment, scan IC 95 (1) to scan IC 95 (6)) and the second scan IC 95 are driven. Different control signals are input to the scan IC groups (scan IC 95 (7) to scan IC 95 (12) in this embodiment).

In the scan ICs 95 (1) to 95 (6) belonging to the first scan IC group, control signals OC1 output from the timing generation circuit 45 during the write period and control signals output from the comparator CP1 are used as control signals. OC2 is input. Further, the scan start signal SIU (1) output from the timing generation circuit 45 in the write period is input to the scan IC 95 (1) that starts the address operation first in the first scan IC group.

The control signals OC1 ′, which are the third control signals output from the AND gate AG, are output from the comparator CP1 to the scan ICs 95 (7) to 95 (12) belonging to the second scan IC group. The control signal OC2 is input. Further, in the scan IC 95 (7) which starts the address operation first in the second scan IC group, the scan start signal SID (1) which is the second control signal output from the timing generation circuit 45 in the address period. Is entered.

The control signal OC2 is a control signal input in common to all the scan ICs 95 (in this embodiment, the scan IC 95 (1) to the scan IC 95 (12)). In addition, a clock signal CLK that is a synchronization signal for synchronizing the signal processing operation is commonly input to all the scan ICs 95 (in this embodiment, the scan IC 95 (1) to the scan IC 95 (12)). The

FIG. 17 is a schematic diagram showing a connection state between scan IC 95 of scan electrode drive circuit 43 and scan electrode SC1 through scan electrode SCn in the first embodiment of the present invention.

In FIG. 17, circuits other than the scan IC 95 are omitted.

Scan pulse generation circuit 70 includes switching elements Q71H1 to Q71Hn and switching elements Q71L1 to Q71Ln for applying a scan pulse voltage to each of n scan electrodes SC1 to SCn. Switching element Q71H1 to switching element Q71Hn and switching element Q71L1 to switching element Q71Ln are integrated into a plurality of ICs for each of a plurality of outputs. This IC is a scanning IC 95.

In the present embodiment, switching elements for 90 outputs are integrated as one monolithic IC, and the panel 10 includes 1080 scanning electrodes. That is, the scan pulse generation circuit 70 is configured by using 12 scan ICs 95 (1) to 95 (12), and n = 1080 scan electrodes SC1 to SCn are driven. As described above, by making the large number of switching elements QH1 to QHn and switching elements QL1 to QLn into an IC, the number of parts in the plasma display device 40 can be reduced, and the mounting area can be reduced. However, the numerical values given in the present embodiment are merely examples, and the present invention is not limited to these numerical values.

In the address operation, first, the scan IC 95 (1) connected to scan electrode SC1 through scan electrode SC90 is operated. Next, scan IC 95 (2) connected to scan electrode SC91 to scan electrode SC180 is operated. Thereafter, the scan IC 95 (3) to the scan IC 95 (12) are sequentially operated.

As described above, in the present embodiment, scan IC 95 is divided into a first scan IC group and a second scan IC group, and scan electrodes SC1 to SCn are driven. In one field, a first scan electrode group (in this embodiment, scan electrode SC1 to scan electrode) connected to scan IC 95 (1) to scan IC 95 (6) belonging to the first scan IC group. SC540), a second scan electrode group (in this embodiment, scan electrode SC541 to scan electrode SC1080) connected to scan IC95 (7) to scan IC95 (12) belonging to the second scan IC group, Thus, subfields for applying initialization waveforms having different waveform shapes are included.

Next, the operation of the scanning IC 95 will be described.

FIG. 18 is a diagram for explaining a correspondence relationship between the control signals OC1 and OC2 and the operation state of the scan IC 95 according to the first embodiment of the present invention.

Note that the second scan IC group is assumed to be in the same operation state by replacing the control signal OC1 with the control signal OC1 '.

As shown in FIG. 18, when both the control signal OC1 and the control signal OC2 are at a high level (hereinafter referred to as “Hi”), the scan IC 95 is in an “All-Hi” state. In the case of “All-Hi”, the scanning IC 95 includes all the switching elements provided in the scanning IC 95 so that all the output terminals of the scanning IC 95 are electrically connected to the input terminal INb on the high voltage side. It will be in the switched state.

When the control signal OC1 is “Hi” and the control signal OC2 is low level (hereinafter referred to as “Lo”), the scan IC 95 is in the “All-Lo” state. In the case of “All-Lo”, the scan IC 95 includes all the switching elements provided in the scan IC 95 such that all the output terminals of the scan IC 95 are electrically connected to the input terminal INa on the low voltage side. It will be in the switched state.

For example, when the sustain pulse generating circuit 50 is operating, the control signal OC1 is set to “Hi”, and the control signal OC2 is set to “Lo”, thereby setting the scan IC 95 to the “All-Lo” state. As a result, switching elements Q71H1 to Q71Hn are turned off, switching elements Q71L1 to switching element Q71Ln are turned on, and reference potential A is output from scan IC 95. Therefore, a sustain pulse can be applied to each of scan electrode SC1 through scan electrode SCn via switching element Q71L1 through switching element Q71Ln.

When both the control signal OC1 and the control signal OC2 are “Lo”, the scanning IC 95 is in a high impedance state (hereinafter referred to as “HiZ”). In this “HiZ” state, the output voltage at the time when the scan IC 95 is in the “HiZ” state is held and output from each output terminal of the scan IC 95 as it is.

When the control signal OC1 is “Lo” and the control signal OC2 is “Hi”, the scan IC 95 is in the “DATA” state. In the “DATA” state, the scan IC 95 enters a state in which a predetermined series of operations are performed based on a scan start signal input to the scan IC 95.

Specifically, when a scan start signal is input to the scan IC 95 (in this embodiment, when the scan start signal changes from “Hi” to “Lo”), first, the first output terminal of the scan IC 95 Only the low voltage side input terminal INa is electrically connected, and all the remaining output terminals are electrically connected to the high voltage side input terminal INb.

After the state continues for a predetermined time (for example, 1 μsec), only the second output terminal of the scan IC 95 is electrically connected to the input terminal INa on the low voltage side, and all the remaining output terminals are high. It is electrically connected to the voltage side input terminal INb.

Then, after the state continues for a predetermined time, only the third output terminal of the scan IC 95 is electrically connected to the input terminal INa on the low voltage side.

In this way, each output terminal of the scan IC 95 is electrically connected to the input terminal INa on the low voltage side in order for a predetermined time. In the present embodiment, the scan IC 95 is set to this operation state in the address period to sequentially generate the scan pulse voltage Va, and the address operation of the scan electrodes SC1 to SCn is performed.

In the present embodiment, the scan start signal input to the scan IC 95 belonging to the first scan IC group is used as the scan start signal SIU, and the scan start signal input to the scan IC 95 belonging to the second scan IC group is used as the scan start. The signal SID is used.

In the present embodiment, the scan start signal SIU (1) used for the scan IC 95 (1) performing the address operation first in the first scan IC group and the address operation first in the second scan IC group. The timing generation circuit 45 generates a scan start signal SID (1) used for the scan IC 95 (7) that performs the above. The remaining scan start signals, that is, the scan start signals SIU (2) used for the scan IC 95 (2) to the scan start signals SIU (6) used for the scan IC 95 (6), and the scan IC 95 ( Each scan start signal from the scan start signal SID (2) used for 8) to the scan start signal SID (6) used for the scan IC 95 (12) is generated by the scan IC 95.

For example, after the write operation to all the scan electrodes connected to the scan IC 95 (1) is completed, the scan IC 95 (1) delays the scan start signal SIU (1) by a predetermined time using a shift register or the like. The created scan start signal SIU (2) is output and supplied to the next-stage scan IC 95 (2). Similarly, the scan IC 95 (2) supplies the scan start signal SIU (3) created by delaying the scan start signal SIU (2) by a predetermined time to the next stage scan IC 95 (3). Thereafter, similarly, each scan IC 95 creates a new scan start signal by delaying the input scan start signal for a predetermined time, and supplies it to the next-stage scan IC 95.

With this configuration, the timing generation circuit 45 does not generate the scan start signal SIU (2) to the scan start signal SIU (6) and the scan start signal SID (2) to the scan start signal SID (6). As a result, the number of wiring lines for the control signal connecting the timing generation circuit 45 and the scan electrode drive circuit 43 can be reduced.

In this embodiment, one field has subfields that generate initialization waveforms having different waveform shapes in the first scan IC group and the second scan IC group. Therefore, in the subfield, the control timing is changed between the control signal OC1 used for the first scan IC group and the control signal OC1 used for the second scan IC group.

The control signal OC1 used for the first scan IC group is generated by the timing generation circuit 45. The control signal OC1 used for the second scan IC group includes a third control signal generated by the AND gate AG (in order to distinguish it from the control signal OC1 used for the first scan IC group, “ Control signal OC1 ′ ”).

Further, a signal generated by the comparator CP1 is used as the control signal OC2.

Thus, in the present embodiment, the control signal OC1 'and the control signal OC2 are generated by a logical operation. Thereby, the number of control signals generated in the timing generation circuit 45 can be further reduced, and the number of wirings for the control signal connecting the timing generation circuit 45 and the scan electrode drive circuit 43 can be further reduced.

Note that the comparator CP1 that outputs the control signal OC2 compares the voltage (Va + Vset2) with the reference potential A when the switching element SW1 is on and the switching element SW2 and the switching element SW3 are off, as shown in FIG. When the switching element SW2 is on and the switching element SW1 and the switching element SW3 are off, the voltage (Va + Vset3) is compared with the reference potential A. When the switching element SW3 is on and the switching element SW1 and the switching element SW2 are off, the voltage (Va + Vset4) is compared with the reference potential A.

The comparator CP1 outputs “Lo” when the reference potential A is higher, and outputs “Hi” otherwise and supplies it to the scan IC 95 (1) to the scan IC 95 (12). The comparator CP2 that outputs the signal CPO used to generate the control signal OC1 ′ compares the voltage (Va + Vset5) with the reference potential A, and outputs “Hi” when the reference potential A is higher, otherwise Then, “Lo” is output.

The scan IC 95 adds the control signal OC1 ′ and the scan start signal SID (1) in accordance with the control signal OC2, and further adds the control signal OC1 ′ and the scan start signal SID (1) in the second scan IC group. It can be generated by switching at different voltages. Note that the timing generation circuit 45 controls ON / OFF of the switching elements SW1 to SW3.

Next, the operation of the scan electrode drive circuit 43 and the generation of the drive voltage waveform will be described.

FIG. 19 is a timing chart for explaining an example of the operation of scan electrode driving circuit 43 according to the embodiment of the present invention.

FIG. 19 mainly shows the operation in the subfield SF3. FIG. 19 also shows a drive voltage waveform applied to scan electrode SC1 that performs the address operation at the beginning of the address period, and scan electrode SCn / 2 + 1 that performs the address operation first in the second scan electrode group (for example, The drive voltage waveform applied to scan electrode SC541) is shown. In addition, the control signal OC1, the control signal OC2, the control signal OC1 ′, the output signal CPO of the comparator CP2, the scanning start signal SIU (1), and the scanning start signal SID (1) are shown, and are input to the input terminal IN1 and the input terminal IN2. The constant current supply state is shown.

In this embodiment, the scan IC 95 starts the writing operation when the scan start signal changes from “Hi” to “Lo” in the “DATA” state. The switching element Q69 is turned on during the first half of the initialization period and the sustain period, and the switching element Q69 is turned off during the second half of the initialization period and the writing period.

(Initialization period)
Although not shown in the initialization period, the sustaining pulse generation circuit 50 is used while the switching element Q72 is kept off after the time t2 after the time t1 when the operation in the sustain period of the immediately preceding subfield ends. Then, the reference potential A is clamped to the voltage 0 (V) (switching element Q56 is turned on).

At time t3, all the switching elements of sustain pulse generating circuit 50 are turned off, the output of sustain pulse generating circuit 50 is set to high impedance, switching element SW1 is turned on, and switching elements SW2 and SW3 are turned off. Thus, the reference potential A (voltage 0 (V) in the present embodiment) and the voltage (Va + Vset2) are compared in the comparator CP1.

At this time, since the reference potential A has a higher potential than the voltage (Va + Vset2), the control signal OC2 output from the comparator CP1 remains “Lo” following the sustain period of the immediately preceding subfield. Further, the control signal OC1 is also maintained at “Hi” after the sustain period of the immediately preceding subfield.

Therefore, since the control signal OC1 and the control signal OC1 'are “Hi” and the control signal OC2 is “Lo”, all the scan ICs 95 are in the “All-Lo” state. As a result, the reference potential A is output from the output terminals of all the scan ICs 95. That is, the drive voltage output from the ramp waveform voltage generation circuit 60 is output as it is from the output terminals of all the scan ICs 95.

Then, a predetermined voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 that generates the downward ramp waveform voltage, and the input terminal IN63 is set to “Hi”. As a result, the drain voltage of the transistor Q63 decreases in a ramp shape, the potential of the reference potential A decreases in a ramp shape, and the output voltage of the scan IC 95 also starts to decrease in a ramp shape.

In the comparator CP1, the down-ramp waveform at the reference potential A and the voltage (Va + Vset2) are compared. Therefore, the control signal OC2 output from the comparator CP1 switches from “Lo” to “Hi” at time t5 when the down-ramp waveform at the reference potential A becomes equal to or lower than the voltage (Va + Vset2).

Thereby, both the control signal OC1 and the control signal OC2 are set to “Hi”, and the first scan IC group is set to the “All-Hi” state. Therefore, the first scan IC group outputs a voltage input to the input terminal INb. That is, the first scan IC group outputs a voltage in which the voltage Vp is superimposed on the reference potential A.

As a result, the down-ramp waveform applied to scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group becomes down-ramp voltage L4 with an ultimate potential of voltage (Va + Vset2).

In this embodiment, the scanning start signal SID (1) is set to “Lo” immediately after the initialization period starts. In the comparator CP2, the reference potential A is compared with the voltage (Va + Vset5). Therefore, the signal CPO output from the comparator CP2 becomes “Lo” at time t4 when the reference potential A becomes equal to or lower than the voltage (Va + Vset5).

At this time, since the scanning start signal SID (1) is “Lo”, “Lo” is output from the OR gate OR. As a result, the control signal OC1 'output from the AND gate AG becomes "Lo".

Thereby, both the control signal OC1 'and the control signal OC2 become "Lo", and the scan ICs 95 (7) to 95 (12) belonging to the second scan IC group are in the "HiZ" state. That is, the output voltages of scan IC 95 (7) to scan IC 95 (12) are voltages in which the output voltage at time t4 is held as it is.

Therefore, the down-ramp waveform applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group is a down-ramp voltage L8 having an ultimate potential of voltage (Va + Vset5).

Then, before time t6 when the initialization period ends, for example, a voltage of 0 (V) is applied to the input terminal IN63, and the input terminal IN63 is set to “Lo”.

(Writing period)
In the address period, although not shown, the switching element Q72 is turned on to maintain the reference potential A at the negative voltage Va. Further, the switching element SW2 is turned on, and the switching element SW1 and the switching element SW3 are turned off. As a result, the comparator CP1 compares the reference potential A with the voltage (Va + Vset3).

At this time, since the reference potential A is equal to the negative voltage Va, and the reference potential A is lower in potential than the voltage (Va + Vset3), the control signal OC2 output from the comparator CP1 becomes “Hi”.

Also, the control signal OC1 is set to “Lo” at time t6. Therefore, the control signal OC1 'output from the AND gate AG is also "Lo". As a result, all the scan ICs 95 are in the “DATA” state. That is, the scan IC 95 enters a state in which an address operation is started by a scan start signal.

In the first half of the address period, first, scan pulses are sequentially applied to scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group. For this purpose, the scanning start signal SIU (1) is set to “Lo” for a predetermined period (for example, one period of the clock signal CLK) at time t7 immediately after the start of the writing period.

Thereby, the scanning IC 95 (1) starts the writing operation. Accordingly, scan pulses are sequentially applied from scan electrode SC1.

A scan start signal SIU (2) is output from the scan IC 95 (1) at the timing when the write operation of all the scan electrodes 22 connected to the scan IC 95 (1) is completed, and is supplied to the scan IC 95 (2). . As a result, the scan IC 95 (2) starts an address operation.

Thereafter, each scan IC 95 starts an address operation based on the input scan start signal, generates a new scan start signal, and supplies it to the next-stage scan IC 95. Thus, the write operation of the scan electrodes belonging to the first scan electrode group is sequentially performed.

Then, at time t8 after the application of the scan pulse to the scan electrode SCn / 2 is completed and the write operation to all the scan electrodes belonging to the first scan electrode group is completed, the control signal OC1 is set to “Hi”. . Since the scanning start signal SID (1) is maintained at “Hi”, the control signal OC1 ′ output from the AND gate AG also becomes “Hi”.

Although not shown, the switching element Q72 is turned off at time t8. Further, the switching element Q56 of the clamp circuit of the sustain pulse generating circuit 50 is turned on, and the reference potential A is set to voltage 0 (V).

Thereby, since the reference potential A is higher in potential than the voltage (Va + Vset3), the control signal OC2 output from the comparator CP1 becomes “Lo”. That is, the control signal OC1, the control signal OC1 'are "Hi", the control signal OC2 is "Lo", and all the scan ICs 95 are in the "All-Lo" state. Accordingly, the reference potential A (voltage 0 (V) at this time) is output from the output terminals of all the scan ICs 95.

At a subsequent time t9, a predetermined voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 that generates the downward ramp waveform voltage, and the input terminal IN63 is set to “Hi”. As a result, the drain voltage of the transistor Q63 decreases in a ramp shape, the potential of the reference potential A decreases in a ramp shape, and the output voltage of the scan IC 95 also starts to decrease in a ramp shape from the voltage 0 (V).

In the comparator CP1, the falling ramp waveform voltage at the reference potential A is compared with the voltage (Va + Vset3). Therefore, the control signal OC2 output from the comparator CP1 switches from “Lo” to “Hi” at time t10 when the downward ramp waveform voltage at the reference potential A becomes equal to or lower than the voltage (Va + Vset3).

As a result, the control signal OC1, the control signal OC1 ', and the control signal OC2 are all "Hi", and all the scan ICs 95 are in the "All-Hi" state. Accordingly, all the scan ICs 95 output a voltage input to the input terminal INb (a voltage obtained by superimposing the voltage Vp on the reference potential A).

As a result, the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn becomes the down-ramp voltage L9 having an ultimate potential of voltage (Va + Vset3).

Then, at time t11 after generating the down-ramp voltage L9, the input terminal IN63 is set to “Lo”.

As described above, the scan electrode driving circuit 43 generates the down-ramp voltage L9. Then, immediately before the address operation to the second scan electrode group is started, an initializing discharge is generated in the second discharge cell group.

At time t11, although not shown, the switching element Q72 is turned on to maintain the reference potential A at the negative voltage Va. Therefore, the reference potential A is lower than the voltage (Va + Vset3), and the control signal OC2 output from the comparator CP1 is “Hi”.

At time t11, the control signal OC1 is set to “Lo”. Therefore, the control signal OC1 'output from the AND gate AG is also "Lo". As a result, all the scan ICs 95 are in the “DATA” state. That is, all the scan ICs 95 are in a state of starting an address operation by a scan start signal.

In the second half of the address period, scan pulses are sequentially applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. For this purpose, the scanning start signal SID (1) is set to “Lo” for a predetermined period (for example, one cycle of the clock signal CLK) at time t12 immediately after the start of the second half of the writing period. As a result, the scan IC 95 (7) starts an address operation, and scan pulses are sequentially applied from the scan electrodes SCn / 2 + 1.

Thereafter, the write operation of the scan electrodes belonging to the second scan electrode group is sequentially performed by the same operation as described above.

(Maintenance period)
Then, at time t13 after the application of the scan pulse to the scan electrode SCn is finished and the write operation to all the scan electrodes belonging to the second scan electrode group is finished and the write period is finished, the control signal OC1 is changed to “ Hi ”. Since the scanning start signal SID (1) is maintained at “Hi”, the control signal OC1 ′ output from the AND gate AG also becomes “Hi”.

Although not shown, the switching element Q72 is turned off at time t13. Further, the switching element Q56 of the clamp circuit of the sustain pulse generating circuit 50 is turned on, and the reference potential A is set to voltage 0 (V).

As a result, the reference potential A becomes higher than the voltage (Va + Vset3), and the control signal OC2 output from the comparator CP1 becomes “Lo”.

Therefore, since the control signal OC1 and the control signal OC1 'are “Hi” and the control signal OC2 is “Lo”, all the scan ICs 95 are in the “All-Lo” state. Thereby, the reference potential A (voltage 0 (V) in the present embodiment) is output from the output terminals of all the scan ICs 95.

Subsequently, although not described in detail, the power recovery circuit and the clamp circuit of the sustain pulse generating circuit 50 are alternately operated to generate a predetermined number of sustain pulses. Then, at the end of the sustain period, an upstream erase ramp voltage L3 is generated. Thus, the maintenance period ends.

Although not shown in FIG. 19, when generating the ramp-down voltage L10, the switching element SW3 may be turned on instead of the switching element SW2 while the Miller integrating circuit 63 generates the downward ramp waveform voltage. Thus, the comparator CP1 may compare the downward ramp waveform voltage at the reference potential A with the voltage (Va + Vset4).

As described above, scan electrode drive circuit 43 causes scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group to go from voltage 0 (V) to voltage (Va + Vset2) during the initialization period. A downward ramp voltage L2 that falls is applied. Further, a down-ramp voltage L8 that decreases from voltage 0 (V) toward voltage (Va + Vset5) is applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. In the address period, the ramp-down voltage L9 that decreases from the voltage 0 (V) toward the voltage (Va + Vset3) is applied to the scan electrodes SC1 to SCn belonging to the first scan electrode group and the second scan electrode group. Alternatively, the down-ramp voltage L10 that decreases from the voltage 0 (V) toward the voltage (Va + Vset4) is applied.

FIG. 20 schematically shows the relationship between the scan pulse voltage (amplitude) necessary to generate a stable address discharge and the order of address operations when performing the two-phase drive operation in the first embodiment of the present invention. FIG.

The diagram shown in the upper part of FIG. 20 is a diagram schematically showing the relationship between the scan pulse voltage (amplitude) necessary for generating a stable address discharge and the order of address operations when performing a two-phase drive operation. is there. In this figure, the horizontal axis represents the order of the address operation of scan electrode SC1 to scan electrode SCn, and the vertical axis represents the scan pulse voltage (amplitude) necessary for generating a stable address discharge in each discharge cell.

The characteristic indicated by the broken line in the upper diagram of FIG. 20 is the scan pulse voltage (amplitude) necessary for generating a stable address discharge during the one-phase driving operation.

20 is a diagram showing drive waveforms applied to scan electrode SC1 through scan electrode SCn when performing a two-phase drive operation. In this figure, the scan electrode 22 that performs the address operation at the beginning of the address period and the scan electrode SC1 that belongs to the first scan electrode group, and the scan electrode 22 that performs the address operation at approximately the midpoint of the address period and the second electrode Drive voltage waveforms applied to each of the scan electrode SCn / 2 + 1 belonging to the scan electrode group and the scan electrode 22 performing the address operation at the end of the address period and belonging to the second scan electrode group are shown.

In the subfield in which two-phase driving is performed in the present embodiment, an initialization operation with a down-ramp voltage is performed for each discharge cell group immediately before the address operation is started in each scan electrode group.

That is, in each discharge cell of the first discharge cell group, an initialization operation with the down-ramp voltage L4 is performed immediately before starting the address operation in each scan electrode 22 of the first scan electrode group. In each discharge cell of the second discharge cell group, an initialization operation using the down-ramp voltage L9 (or the down-ramp voltage L10) is performed immediately before starting the address operation in each scan electrode 22 of the second scan electrode group. Do.

This initialization operation can bring the wall charge in the discharge cell to an appropriate state. Therefore, as indicated by a solid line in the upper diagram of FIG. 20, the scan pulse voltage (amplitude) necessary for generating a stable address discharge can be reduced in the second discharge cell group.

In the discharge cell that performs the address operation at the end of the address period, the scan pulse voltage (amplitude) necessary for generating a stable address discharge is approximately equal to that in the one-phase drive operation in the two-phase drive operation. It was confirmed by experiment that it could be reduced by 20 (V).

As described above, in this embodiment, the initialization operation using the down-ramp voltage is performed before the address operation to the second scan electrode group is started in the address period. By performing such a two-phase driving operation, it is possible to reduce the scan pulse voltage (amplitude) necessary for generating a stable address discharge. Therefore, even in a discharge cell in which the address operation is likely to become unstable, the voltage required for stable operation is prevented from increasing and a stable address operation can be performed.

As described above, in the present embodiment, the number of sustain pulses generated in the immediately preceding subfield is large, and in the subfield where priming particles generated by the sustain discharge and the wall charge are likely to remain excessively, 2 Perform phase drive. As a result, even in a discharge cell in which the address operation is likely to become unstable, the voltage necessary for stable operation is prevented from increasing, and a stable address operation can be performed.

In this embodiment, the adjustment period TSF is set according to the luminance weight of the immediately preceding subfield. That is, the adjustment period TSF is lengthened as the number of sustain pulses generated in the immediately preceding subfield increases. As a result, the number of sustain pulses generated in the immediately preceding subfield is large, and the occurrence of defective writing can be reduced in a subfield where priming particles and wall charges generated by the sustain discharge are likely to remain excessively. .

Further, in the present embodiment, the minimum voltage of the downward ramp waveform voltage (first phase downward ramp waveform voltage) generated in the initialization period and the downlink generated in the middle of the writing period according to the length of the adjustment period TSF. The voltage difference with the ramp waveform voltage (second phase descending ramp waveform voltage) is changed. When the length of the adjustment period TSF is short, the voltage difference between the lowest voltage of the first-phase downward ramp waveform voltage and the second-phase downward ramp waveform voltage is made larger than when the length of the adjustment period TSF is long. As a result, it is possible to prevent the amplitude of the address pulse required for stable address operation from increasing, and to generate address discharge stably.

Further, after generation of the last sustain pulse in the sustain period, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn An ascending ramp waveform voltage (ascending erasing ramp voltage L3) that gently rises from a voltage 0 (V), which is less than the discharge start voltage, toward a voltage Vr that is a predetermined voltage is applied. Then, the voltage Vr is set to a voltage that is lower than the voltage Vs and does not cause erroneous discharge in the subsequent address period. This makes it possible to perform a stable writing operation even when driving the high-definition large-screen panel 10 and display a high-quality image on the panel 10.

(Embodiment 2)
In the first embodiment, the example in which the panel 10 is driven by setting the number of times of performing the all-cell initialization operation once per field has been described. However, the present invention is not limited to this configuration. For example, the present invention can also be applied to a configuration in which the panel 10 is driven with the number of all-cell initializing operations performed once for a plurality of fields. In this case, the same effect as described above can be obtained.

In the driving method in which the number of times of performing the all-cell initialization operation is once in a plurality of fields, the light emission generated by the all-cell initialization operation is generated as compared with the configuration in which the all-cell initialization operation is performed once per field. It is possible to reduce the black luminance (the luminance of the gradation that does not generate the sustain discharge), and the contrast of the image displayed on the panel 10 can be improved.

Hereinafter, an example will be described in which the panel 10 is driven with the number of times of performing the all-cell initialization operation being once every three fields.

Also in the present embodiment, as in the first embodiment, one-phase driving is performed in subfield SF1 and subfield SF2, and two-phase driving is performed in the other subfields (subfield SF3 to subfield SF8). . Hereinafter, first, a driving voltage waveform for one-phase driving will be described, and then, a driving voltage waveform for two-phase driving will be described.

FIG. 21 is a diagram showing a drive voltage waveform during a one-phase drive operation applied to each electrode of panel 10 used in the plasma display device in accordance with the second exemplary embodiment of the present invention.

FIG. 21 shows each of scan electrode SC1 that performs an address operation first in the address period, scan electrode SC2 that performs an address operation second in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform applied to is shown.

In the present embodiment, the subfield SF1 is a first type subfield in which there are discharge cells that perform the forced initialization operation and discharge cells that do not perform the forced initialization operation. Further, subfield SF2 to subfield SF8 are second type subfields for performing selective initialization operation in all discharge cells.

The forced initializing operation is an initializing operation for forcibly generating an initializing discharge in a discharge cell regardless of the occurrence of address discharge (sustain discharge) in the immediately preceding subfield. This is the same initialization operation as the cell initialization operation. Therefore, the drive voltage waveform applied to each electrode in the forced initialization operation is equal to the all-cell initialization waveform applied to each electrode in the all-cell initialization period.

In FIG. 21, in the initializing period of subfield SF1, the discharge cell formed on scan electrode SC1 performs a forced initialization operation, and the discharge cell formed on scan electrode SC2 performs a forced initialization operation. The drive voltage waveform when performing the selective initialization operation without performing is shown.

In the first half of the initializing period of the first type subfield SF1, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage 0 (V) is also applied to the sustain electrodes SU1 to SUn. To do. Then, a drive voltage waveform having the same waveform shape as the all-cell initialization waveform shown in the first embodiment is applied to scan electrode SC1 that performs the forced initialization operation.

As a result, in the discharge cells formed on scan electrode SC1, the initialization operation similar to the all-cell initialization operation shown in the first embodiment is performed, and the address discharge (sustain discharge) in the immediately preceding subfield is performed. An initializing discharge is generated in the discharge cell regardless of whether or not it occurs.

On the other hand, an up-slope waveform voltage (up-ramp voltage L5) that gently rises from voltage 0 (V) to voltage Vi5 lower than voltage Vi2 is applied to scan electrode SC2 that does not perform the forced initialization operation. By setting the voltage Vi5 to a voltage lower than the discharge start voltage, the initialization discharge is not generated in the discharge cells formed on the scan electrode SC2.

As described above, in the first half of the initialization period of the subfield SF1, the scan electrode 22 (for example, the scan electrode SC1) that performs the forced initialization operation has an occurrence of the address discharge (sustain discharge) in the immediately preceding subfield. Regardless, an upward ramp waveform voltage (up-ramp voltage L1) that gently rises toward the voltage Vi2 at which discharge occurs is applied. In addition, an up-slope waveform voltage (up-ramp voltage L5) that gently rises toward voltage Vi5 lower than voltage Vi2 is applied to scan electrode 22 (for example, scan electrode SC2) that does not perform the forced initialization operation.

In the second half of the initialization period of the subfield SF1, a drive voltage waveform having the same waveform shape as that of the second half of the all-cell initialization period shown in the first embodiment is applied to each electrode. At this time, the drive voltage waveform applied to the scan electrode 22 that performs the forced initialization operation and the drive voltage waveform applied to the scan electrode 22 that does not perform the forced initialization operation have the same waveform shape.

As a result, a weak initialization discharge is generated in the discharge cell (for example, the discharge cell formed on the scan electrode SC1) that has been subjected to the forced initialization operation.

On the other hand, in a discharge cell that has not been subjected to the forced initialization operation (for example, a discharge cell formed on scan electrode SC2), in the immediately preceding subfield, that is, the last subfield of the immediately preceding field (for example, subfield SF8). A weak initialization discharge is generated only in the discharge cells that have generated the address discharge (sustain discharge). In the discharge cell that did not generate the address discharge (sustain discharge) in the immediately preceding subfield, the initialization discharge does not occur, and the previous wall voltage is maintained.

Therefore, the initialization operation performed in the discharge cell that does not perform the forced initialization operation is the selective initialization operation.

Thus, in the first type subfield (subfield SF1), the discharge cells that perform the forced initialization operation and the discharge cells that perform the selective initialization operation coexist in the initialization period.

Then, an initialization waveform having the same waveform shape as the all-cell initialization waveform is applied to the scan electrode 22 of the discharge cell that performs the forced initialization operation. That is, the up-ramp voltage L1 and the down-ramp voltage L2 are applied to the scan electrode 22 of the discharge cell that performs the forced initialization operation. The up-ramp voltage L1 is an up-slope waveform voltage that rises to a voltage Vi2 at which an initializing discharge is generated in the discharge cell regardless of whether an address discharge (sustain discharge) has occurred in the immediately preceding subfield. The down-ramp voltage L2 is a down-slope waveform voltage that drops to the voltage Vi4 at which discharge occurs.

Also, the up-ramp voltage L5 and the down-ramp voltage L2 are applied to the scan electrodes 22 of the discharge cells that do not perform the forced initialization operation. The up-ramp voltage L5 is an up-slope waveform voltage that is lower than the voltage Vi2 and rises to a voltage Vi5 that does not generate an initialization discharge in the discharge cell. The downward ramp voltage L2 is a downward ramp waveform voltage that decreases to the voltage Vi4.

Hereinafter, the period during which forced initialization is performed is referred to as “forced initialization period”. A drive voltage waveform generated for performing the forced initialization operation is referred to as a “forced initialization waveform”.

The operation in the subsequent writing period and sustaining period of subfield SF1 is the same as in the first embodiment.

That is, after generation of the last sustain pulse in the sustain period, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn An ascending ramp waveform voltage (ascending erasing ramp voltage L3) that gently rises from a voltage 0 (V), which is less than the discharge start voltage, toward a voltage Vr that is a predetermined voltage is applied. Then, the voltage Vr is set to a voltage that is lower than the voltage Vs and does not cause erroneous discharge in the subsequent address period.

Subfield SF2, which is a subsequent selective initialization subfield, is a second type subfield in which selective initialization operation is performed in all discharge cells in the initialization period.

In the initializing period (selective initializing period) of the subfield SF2, a driving voltage waveform having the same waveform shape as the driving voltage waveform shown in the selective initializing period of the first embodiment may be applied to each electrode. However, the minimum voltage of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn may be set higher than voltage Vi4, which is the minimum voltage of down-ramp voltage L2.

In the present embodiment, the minimum voltage of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn in the selective initialization period is set to voltage Vi6 having a voltage value higher than voltage Vi4, and voltage Vi3 ′ to voltage Vi6. A description will be given of an example in which a downward ramp waveform voltage (hereinafter referred to as “down-ramp voltage L6”) that falls to the above is applied to scan electrode SC1 through scan electrode SCn.

Since this down-slope waveform voltage has the same function as the first down-slope waveform voltage shown in the first embodiment, this down-slope waveform voltage (down-ramp voltage L6) is also the first down-slope waveform voltage. And

In the initialization period of subfield SF2, voltage Vh having a voltage value higher than voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn. Scan electrode SC1 to scan electrode SCn have a downward ramp waveform voltage (gradiently decreasing from voltage Vi3 ′ (eg, voltage 0 (V)), which is less than the discharge start voltage, to negative voltage Vi6, which exceeds the discharge start voltage. A down-ramp voltage L6) is applied.

The slope of the down-ramp voltage L6 may be the same as the slope of the down-ramp voltage L2, and an example thereof is a numerical value of about −2.5 V / μsec.

The voltage Vi6 can be generated by superimposing the voltage Vset6 on the voltage Va.

During the period in which down-ramp voltage L6 is applied to scan electrode SC1 through scan electrode SCn, a second voltage having a voltage value higher than the first voltage (voltage 0 (V)) is applied to data electrode D1 through data electrode Dm. (Positive voltage Vg) is applied.

As described above, the voltage Vi6 that is the lowest voltage of the down-ramp voltage L6 is higher than the voltage Vi4 that is the lowest voltage of the down-ramp voltage L2, and the discharge cell that has generated the address discharge (sustain discharge) in the immediately preceding subfield. Only the voltage at which discharge occurs is set. At this time, it is desirable to set the voltage Vi6 so that the voltage difference between the voltage Vg and the voltage Vi6 (the voltage applied to the discharge cell) is approximately the same as the voltage Vi4.

The operation in the subsequent writing period and sustaining period of the subfield SF2 is the same as the driving voltage waveform shown in the first embodiment.

FIG. 22 is a diagram showing a driving voltage waveform during a two-phase driving operation applied to each electrode of the panel 10 used in the plasma display device in accordance with the second exemplary embodiment of the present invention.

In FIG. 22, the scan electrode 22 that performs the address operation at the beginning of the address period, the scan electrode SC1 that belongs to the first scan electrode group, and the scan electrode 22 that performs the address operation at the end of the first scan electrode group. Scan electrode SCn / 2 (for example, scan electrode SC540), scan electrode SCn / 2 + 1 (for example, scan electrode SC541) that is the scan electrode 22 that performs the address operation first in the second scan electrode group, and the address period Finally, scan electrode 22 that performs an address operation is applied to each of scan electrode SCn (for example, scan electrode SC1080) belonging to the second scan electrode group, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. The drive voltage waveform to be shown is shown.

The drive voltage waveform during the two-phase drive operation shown in FIG. 22 is substantially equal to the drive voltage waveform during the two-phase drive operation shown in FIG. However, the lowest voltage of the downward initialization waveform voltage and the voltage applied to the data electrode 32 and the sustain electrode 23 during the initialization operation are different from the drive voltage waveform during the two-phase drive operation shown in FIG.

In the initializing period of subfield SF3 and subfield SF4, scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group has the same waveform shape as that of down-ramp voltage L6 described as the selective initializing waveform. Apply voltage waveform. Therefore, hereinafter, this drive voltage waveform is also referred to as “first downward ramp waveform voltage”.

That is, the first downward ramp waveform voltage (down-ramp voltage L6) is a negative voltage Vi6 that exceeds the discharge start voltage from voltage Vi3 ′ that is less than the discharge start voltage with respect to sustain electrode SU1 to sustain electrode SUn / 2. That is, it is a ramp waveform voltage that drops to voltage Va + voltage Vset6. The down-ramp voltage L6 is a first-phase down-slope waveform voltage.

For scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group, a second down-gradient waveform voltage (down-ramp voltage L8) that gently falls from voltage Vi3 ′ toward negative voltage (Va + Vset5). Apply.

During the period in which the downward ramp waveform voltage is applied to scan electrode 22, voltage Vh having a voltage value higher than voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, similar to the initialization period of subfield SF2. A second voltage (positive voltage Vg) having a voltage value higher than that of the first voltage (voltage 0 (V)) is applied to the data electrodes D1 to Dm.

After the write operation to the first scan electrode group is completed, the third downward ramp waveform voltage is applied to the second scan electrode group before the write operation to the second scan electrode group is started. The third downward ramp waveform voltage is a downward ramp waveform voltage that gradually falls from the voltage 0 (V), which is the base potential that is less than the discharge start voltage, toward the negative voltage (Va + Vset7).

In this embodiment, when the third downward ramp waveform voltage is applied to the second scan electrode group, the same third downward ramp waveform voltage is also applied to the first scan electrode group. The reason is as described in the first embodiment. The third downward ramp waveform voltage is the second-phase downward ramp waveform voltage.

Although not shown, the same drive voltage waveform as that of the subfield SF3 is generated in the initialization period of the subfield SF5 to the subfield SF8. In addition, in the address period from the subfield SF5 to the subfield SF8, after the address operation to the first scan electrode group is completed, before the address operation to the second scan electrode group is started, the third downlink A ramp waveform voltage is applied to the second scan electrode group. The third downward ramp waveform voltage is a downward ramp waveform voltage that gently falls from the voltage 0 (V), which is the base potential that is less than the discharge start voltage, toward the negative voltage (Va + Vset8).

In the present embodiment, when the third downward ramp waveform voltage is applied to the second scan electrode group, the same third downward ramp waveform voltage is also applied to the first scan electrode group. The third downward ramp waveform voltage is also the second phase downward ramp waveform voltage.

In the present embodiment, the voltage Vset8 is set to a voltage lower than the voltage Vset6 and higher than the voltage Vset7. For example, the voltage Vset6 is 80 (V), the voltage Vset7 is 77 (V), and the voltage Vset8 is 78 (V).

Thereby, the second-phase downward ramp waveform voltage generated in the writing period of the subfield SF3 and the subfield SF4 is the third downward ramp waveform voltage that drops to a voltage that is, for example, 3 (V) lower than the downward ramp voltage L6. Become.

Further, the second-phase downward ramp waveform voltage generated in the writing period of subfield SF5 to subfield SF8 is the third downward ramp waveform voltage that drops to a voltage that is, for example, 2 (V) lower than the downward ramp voltage L6. .

In each period other than those described here, a drive voltage waveform similar to that in the subfield SF2 is applied to each electrode except for the number of sustain pulses generated.

In this embodiment, for example, voltages Vi1 = 150 (V), voltage Vi2 = 350 (V), voltage Vi3 = 215 (V), and voltage Vi3 ′ = 0 ( V), voltage Vi4 = −175 (V), voltage Vi5 = 200 (V), voltage Vi6 = −120 (V), voltage Vc = −50 (V), voltage Va = −200 (V), voltage Vs = 215 (V), voltage Vr = 200 (V), voltage Ve = 170 (V), voltage Vd = 55 (V), voltage Vh = 215 (V), voltage Vg = 55 (V), Vset2 = 25 (V ), Vset5 = 70 (V), Vset6 = 80 (V), Vset7 = 77 (V), and Vset8 = 78 (V). However, these voltage values are only examples in the embodiment. Each voltage value is not limited to the value described above, and it is desirable to set the voltage value to an optimal value as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device.

Next, the relationship between the scan electrode 22 to which the forced initialization waveform is applied and the field will be described.

In the present embodiment, the scan electrode 22 that applies the forced initialization waveform to each field is set based on the following rules.

That is, N fields that are continuous in time (N is a natural number) are defined as one field group, and N scanning electrodes 22 that are continuously arranged are defined as one scan electrode group. For example, three fields that are temporally continuous are defined as one field group, and three consecutively arranged scan electrodes 22 are defined as one scan electrode group.

The forced initializing waveform is applied to each scan electrode 22 constituting one scan electrode group once for each field group.

In each field constituting one field group, a forced initializing waveform is applied only to one scan electrode 22 of each scan electrode group in one field group. Therefore, for example, if the number of scan electrodes 22 is 1080 and the number of scan electrode groups is 360, the number of scan electrodes 22 to which the forced initializing waveform is applied in one field is 360. Then, a forced initialization waveform is applied to the other 360 scan electrodes 22 in the next field, and a forced initialization waveform is applied to the remaining 360 scan electrodes 22 in the third field.

The scan electrode 22 to which the forced initialization waveform is applied is set so that the forced initialization waveform is not applied to the scan electrode 22 adjacent to the scan electrode 22 to which the forced initialization waveform is applied.

FIG. 23 is a diagram schematically showing the relationship between the scanning electrode 22 to which the forced initialization waveform is applied and the field in the second embodiment of the present invention.

23, a horizontal cell represents a field, and a vertical cell represents a scanning electrode 22. FIG. 23 shows an example where N = 3, that is, one field group is constituted by three temporally continuous fields, and one scanning electrode group is constituted by three consecutive scanning electrodes 22. An example of configuration will be shown.

In FIG. 23, field Fj to field Fj + 2, field Fj + 3 to field Fj + 5, field Fj + 6 to field Fj + 8, field Fj + 9 to field Fj + 11 constitute a field group, and each of scan electrode SCi to scan electrode SCi + 2 and scan electrode An example is shown in which each of SCi + 3 to scan electrode SCi + 5 and scan electrode SCi + 6 to scan electrode SCi + 8 constitutes a scan electrode group.

In FIG. 23, “◯” indicates that the forced initialization operation is performed in the initialization period of the subfield SF1. That is, “◯” represents that a forced initializing waveform having the up-ramp voltage L1 and the down-ramp voltage L2 is applied to the scan electrode 22 in the initialization period of the subfield SF1. “X” represents that the forced initialization operation is not performed in the initialization period of the subfield SF1. That is, “x” represents that an initialization waveform having an up-ramp voltage L5 and a down-ramp voltage L2 is applied to the scan electrode 22 in the initialization period of the subfield SF1.

As is clear from FIG. 23, the forced initializing waveform is applied to each scan electrode 22 constituting one scan electrode group once for each field group.

For example, forcible initialization waveforms are applied to the scan electrode SCi in each of the field Fj, the field Fj + 3, the field Fj + 6, the field Fj + 9,. The same applies to the other scanning electrodes 22.

This reduces the number of times that the forced initialization operation is performed to 1/3 compared to the case where the forced initialization operation is performed once for each field. Therefore, the number of times of light emission generated by the forced initialization operation is also reduced to one third, and the black luminance of the display image can be reduced accordingly.

Further, in each field constituting one field group, the forced initializing waveform is applied only to one scan electrode 22 of each scan electrode group in one field group.

For example, in field Fj, a forced initialization waveform is applied to scan electrode SCi, scan electrode SCi + 3, scan electrode SCi + 6,..., And in field Fj + 1, scan electrode SCi + 1, scan electrode SCi + 4, scan electrode SCi + 7,. A forced initializing waveform is applied to scan electrode SCi + 2, scan electrode SCi + 5, scan electrode SCi + 8,... In field Fj + 2. The same applies to the other fields.

Thereby, since the scanning electrodes 22 to which the forced initialization waveform is applied can be dispersed in each field, flicker (flickering appearing in the display image) can be reduced.

Further, no forced initialization waveform is applied to the scan electrode 22 adjacent to the scan electrode 22 to which the forced initialization waveform is applied.

For example, in the field Fj, the forced initialization waveform is applied to the scan electrode SCi + 3, and the forced initialization waveform is not applied to the scan electrode SCi + 2 and the scan electrode SCi + 4 adjacent to the scan electrode SCi + 3. The same applies to the other scanning electrodes 22.

Thereby, since temporal continuity and spatial continuity of the scan electrode 22 to which the forced initialization waveform is applied can be reduced, it is possible to make it difficult for the user to recognize light emission due to the forced initialization operation.

As described above, in the present embodiment, in each discharge cell, the forced initialization operation is performed in only one of a plurality of consecutive fields. As a result, the number of times that the forced initialization operation is performed is set to once in a plurality of fields, light emission that is not related to the gradation display generated by the forced initialization operation is reduced, the black luminance is reduced, and an image with high contrast is displayed. 10 can be displayed.

Note that the forced initialization operation has a function of accumulating wall charges necessary for generating an address discharge in the discharge cell in the subsequent address period. Furthermore, it has a function of generating priming particles necessary for shortening the discharge delay time and stably generating the address discharge.

Therefore, simply reducing the number of forced initialization operations increases the possibility that an address failure in which no address discharge occurs in the discharge cell to which the address pulse is applied will occur in the subsequent address period. Alternatively, there is a high possibility that the discharge delay time of the address discharge becomes too long and the address operation becomes unstable. As a result, it may not be possible to display an image normally.

However, in the present embodiment, in the initialization period of the second type subfield (for example, subfield SF2 to subfield SF8) in which the selective initializing operation is performed, the first voltage ( A second voltage (voltage Vg) higher than voltage 0 (V) is applied.

Further, the lowest voltage (voltage Vi6) of the downward ramp waveform voltage (down-ramp voltage L6) applied to scan electrode SC1 through scan electrode SCn is applied to scan electrode SC1 through scan electrode SC1 through sub-field SF1 as the first type subfield. It is set higher than the lowest voltage (voltage Vi4) of the downward ramp waveform voltage (down ramp voltage L2) applied to scan electrode SCn.

Thus, the address discharge can be stably generated even in the driving method according to the present embodiment in which the number of forced initialization operations is reduced. This is due to the following reason.

First, the reason why the positive voltage Vg is not applied to the data electrodes D1 to Dm in the initialization period of the first type subfield (subfield SF1) will be described.

There are discharge cells that perform a forced initializing operation in the initializing period of the first type subfield (subfield SF1). That is, in the first half of the initialization period, the rising ramp waveform voltage (up-ramp voltage L1) rising toward the voltage Vi2 at which discharge occurs regardless of the occurrence of address discharge (sustain discharge) in the immediately preceding subfield. There is a discharge cell that forcibly generates an initializing discharge when applied.

A wall voltage having a high positive polarity is accumulated on the data electrode 32 of such a discharge cell. When a positive voltage Vg is further applied to the data electrode D1 to the data electrode Dm to the discharge cell in which the wall voltage having a high positive polarity is accumulated on the data electrode 32, the voltage difference between the scan electrode 22 and the data electrode 32 is obtained. Becomes too large, and there is a high risk that strong discharge will occur in the latter half of the initialization period. When a strong discharge occurs in the latter half of the initialization period, wall charges and priming particles become excessive in the discharge cell, and the probability of generating an erroneous discharge in the subsequent address period increases.

In the present embodiment, in order to prevent such a phenomenon from occurring, a positive voltage is applied to the data electrode 32 during the initialization period of the first type subfield (subfield SF1) in which there are discharge cells that perform the forced initialization operation. Vg is not applied.

On the other hand, when the number of times of performing the forced initialization operation is reduced, there is a possibility that the variation of the wall voltage of each discharge cell becomes large.

In the discharge cell in which the wall voltage on the data electrode 32 is reduced, the discharge between the scan electrode 22 and the data electrode 32 is less likely to occur, and the initialization discharge is less likely to occur.

However, the inventor of the present application applies a positive voltage to the data electrode D1 to the data electrode Dm when performing the selective initialization operation, thereby stably generating the initialization discharge in the discharge cell performing the selective initialization operation. It was experimentally confirmed that the wall voltage on the data electrode Dk can be accurately adjusted. This is presumably because discharge between the scan electrode 22 and the data electrode 32 is likely to occur stably by applying a positive voltage to the data electrodes D1 to Dm.

Therefore, in the present embodiment, positive voltage Vg is applied to data electrode D1 to data electrode Dm in the initialization period of the second type subfield (subfield SF2 to subfield SF8) in which the selective initialization operation is performed. Shall.

In order to make the discharge intensity of the initialization discharge generated in the discharge cell to be approximately the same as the discharge generated by the down-ramp voltage L2, the voltage difference between the voltage Vi6 and the second voltage (voltage Vg) is the voltage Vi4. It is desirable to set each voltage so as to be substantially equal to the voltage difference between the first voltage (voltage 0 (V)). Thereby, the address discharge in the address period after the forced initializing operation and the address discharge in the address period after the selective initializing operation can be set to the same discharge intensity.

Note that the voltage Vh higher than the voltage Ve is applied to the sustain electrodes SU1 to SUn because the voltage Vi6 is set higher than the voltage Vi4, so that a discharge is generated between the scan electrode 22 and the sustain electrode 23. This is to prevent it from becoming difficult.

In this embodiment, the wall voltage on the data electrode Dk is adjusted with high accuracy in this way, so that the address discharge can be stably generated while reducing the number of forced initialization operations.

Next, the operation from the first type subfield (subfield SF1) to the second type subfield (subfield SF2) of the circuit for generating the drive voltage waveform in the present embodiment will be described.

Note that the scan electrode drive circuit, the sustain electrode drive circuit, and the data electrode drive circuit used in the present embodiment are the same as the scan electrode drive circuit 43, the sustain electrode drive circuit 44, and the data electrode drive circuit 42 described in the first embodiment. Since it is a structure, description is abbreviate | omitted about the structure of each circuit.

In the present embodiment, in the drive voltage waveform shown in FIG. 21, the voltage Vi1 is equal to the voltage Vp, the voltage Vi2 is equal to the voltage (Vt + Vp), the voltage Vi3 is equal to the voltage Vs, and the voltage Vc is equal to the voltage (Va + Vp). It shall be equal. The same applies to the drive voltage waveform shown in FIG.

In the drive voltage waveform shown in FIG. 21, the voltage Vi5 is equal to the voltage Vt, the voltage Vg is equal to the voltage Vd, and the voltage Vh is equal to the voltage Vs. However, these voltages are not limited to the above-described numerical values, and are desirably set as appropriate according to the characteristics of the panel 10 and the specifications of the plasma display device.

FIG. 24 is a timing chart for explaining the operation of the drive circuit of the plasma display device in accordance with the second exemplary embodiment of the present invention.

In FIG. 24, among scan electrodes SC1 to SCn, scan electrode 22 to which a forced initialization waveform is applied is indicated by scan electrode SCx, and scan electrode 22 to which no forced initialization waveform is applied is indicated by scan electrode SCy. .

In FIG. 24, among the switching elements Q71H1 to Q71Hn, the switching element corresponding to the scan electrode SCx is indicated by the switching element Q71Hx, and the switching element corresponding to the scan electrode SCy is indicated by the switching element Q71Hy. Similarly, among switching elements Q71L1 to Q71Ln, a switching element corresponding to scan electrode SCx is indicated by switching element Q71Lx, and a switching element corresponding to scan electrode SCy is indicated by switching element Q71Ly.

In the first half of the initialization period of subfield SF1, first, switching element Q56 of scan electrode drive circuit 43 is turned on to apply voltage 0 (V) to scan electrode SCx and scan electrode SCy.

Next, the switching element Q56 is turned off and the switching element Q71Lx is turned off, the switching element Q71Hx is turned on, and the voltage Vp is applied to the scan electrode SCx to which the forced initialization waveform is applied. On the other hand, voltage 0 (V) is kept applied to scan electrode SCy that does not perform the forced initialization operation.

Next, a constant voltage is applied to the input terminal IN61 of the Miller integrating circuit 61, and the voltage of the reference potential A is gradually raised to the voltage Vt. Since a voltage obtained by superimposing the voltage Vp on the reference potential A is applied to the scan electrode SCx to which the forced initializing waveform is applied, an upward ramp waveform that gradually rises from the voltage Vp to the voltage (Vt + Vp). A voltage (up-ramp voltage L1) can be applied.

On the other hand, since reference potential A is applied to scan electrode SCy to which no forced initialization waveform is applied, an upward ramp waveform voltage (up-ramp voltage) that gradually rises from voltage 0 (V) to voltage Vt is applied to scan electrode SCy. L5) can be applied.

In the second half of the initializing period of subfield SF1 that follows, switching element Q84 of sustain electrode drive circuit 44 is turned off, switching element Q86 and switching element Q87 are turned on, and voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn. To do.

Then, switching element Q71Hx of scan electrode drive circuit 43 is turned off, switching element Q71Lx is turned on, switching element Q55 and switching element Q59 are turned on, and voltage Vs is applied to scan electrode SCx and scan electrode SCy.

Thereafter, the switching element Q69 is turned off and a constant voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 to operate the Miller integrating circuit 63, so that the scanning electrode SCx and the scanning electrode SCy are gradually applied from the voltage Vi3 to the voltage Vi4. A descending ramp waveform voltage (down ramp voltage L2) is applied.

In the address period of the subfield SF1, the transistor Q63 of the Miller integrating circuit 63 of the scan electrode driving circuit 43 is turned off, the switching element Q72 is turned on, and the voltage of the reference potential A is set to the voltage Va. Then, switching element Q71Lx and switching element Q71Ly are turned off, switching element Q71Hx and switching element Q71Hy are turned on, and voltage (Va + Vp), that is, voltage Vc is applied to scan electrode SCx and scan electrode SCy.

Next, switching element Q71H1 is turned off, switching element Q71L1 is turned on, and a scan pulse that is displaced from voltage Vc to voltage Va is applied to scan electrode SC1.

Further, switching element Q91L1 to switching element Q91Lm of data electrode drive circuit 42 are turned on, switching element Q91H1 to switching element Q91Hm are turned off, and voltage 0 (V) is applied to data electrode D1 to data electrode Dm.

Then, at the timing of applying the scan pulse to the scan electrode SC1, the switching element Q91Lj is turned off and the switching element Q91Hj is turned on for the data electrode Dj to which the address pulse is applied based on the image data, and the voltage 0 (V ) Is applied to the data electrode Dj.

After a certain time (after completion of the write operation in the first row), the switching element Q71H1 is turned on, the switching element Q71L1 is turned off, and the voltage applied to the scan electrode SC1 is returned to the voltage Vc. At the same time, switching element Q91Lj is turned on, switching element Q91Hj is turned off, and the voltage applied to data electrode Dj is returned to voltage 0 (V). In this way, a scan pulse is applied to scan electrode SC1, and an address pulse is applied to data electrode Dj.

Subsequently, the same operation as described above is performed on the scan electrode SC2, a scan pulse is applied to the scan electrode SC2, and an address pulse is applied to the data electrode Dj.

FIG. 24 shows an example in which a scan pulse is applied to scan electrode SCx, and then a scan pulse is applied to scan electrode SCy.

Similarly, the scan pulse is sequentially applied to the scan electrode 22 and the address pulse is applied to the data electrode Dj until reaching the scan electrode SCn.

Thereafter, switching element Q72, switching element Q71Hx, and switching element Q71Hy are turned off, switching element Q56, switching element Q69, switching element Q71Lx, and switching element Q71Ly are turned on, respectively, and voltage 0 ( V) is applied. Thus, the writing period ends.

In sustain period of subfield SF1, scan electrode SC1 to scan electrode SCn and sustain electrode SU1 to sustain are maintained using sustain pulse generating circuit 50 of scan electrode driving circuit 43 and sustain pulse generating circuit 80 of sustain electrode driving circuit 44. The number of sustain pulses corresponding to the luminance weight is applied to each electrode SUn.

Then, after all the sustain pulses in the sustain period are generated, the switching element Q56 of the scan electrode drive circuit 43 is turned off. At the same time, a constant voltage is applied to input terminal IN62 of Miller integrating circuit 62 to operate Miller integrating circuit 62, and an upward ramp waveform voltage that gradually rises to voltage Vr is applied to scan electrode SC1 through scan electrode SCn. . The voltage Vr is a voltage lower than the voltage Vs (eg, voltage Vr = voltage Vs−15 (V)).

In the initialization period of subfield SF2, switching elements Q91L1 to Q91Lm of data electrode drive circuit 42 are turned off, switching elements Q91H1 to switching element Q91Hm are turned on, and positive voltage Vd is applied to data electrodes D1 to Dm. That is, the voltage Vg is applied.

Also, switching element Q84 of sustain electrode drive circuit 44 is turned off, switching element Q83 is turned on, and voltage Vs, that is, voltage Vh, is applied to sustain electrode SU1 through sustain electrode SUn.

Then, a constant voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 while the switching elements Q71L1 to Q71Ln of the scan electrode driving circuit 43 are turned on and the switching elements Q71H1 to Q71Hn are turned off. Miller integrating circuit 63 is thus operated, and a downward ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn.

When the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vi6, the voltage applied to input terminal IN63 is stopped. In this way, the downward ramp waveform voltage (down-ramp voltage L6) that gently decreases from voltage Vi3 '(voltage 0 (V)) to voltage Vi6 is applied to scan electrode SC1 through scan electrode SCn.

The subsequent operations in the writing period and the sustaining period of the subfield SF2 are the same as those in the writing period and the sustaining period of the subfield SF1.

Thus, in the present embodiment, the drive voltage waveforms shown in FIGS. 21 and 22 are generated using the data electrode drive circuit 42, the scan electrode drive circuit 43, and the sustain electrode drive circuit 44, and the data electrode D1 to data electrode Dm, scan electrode SC1 to scan electrode SCn, and sustain electrode SU1 to sustain electrode SUn can be applied to each.

In the initializing period of the first type subfield, a downward ramp waveform voltage is applied to the scan electrode 22 and a first voltage (voltage 0 (V)) is applied to the data electrode 32. In addition, a downward ramp waveform voltage is applied to the scan electrode and a second voltage (voltage Vg) higher than the first voltage is applied to the data electrode in the initialization period of the second type subfield. By doing so, the number of forced initialization operations can be reduced to suppress black luminance, and a stable write operation can be performed.

As described above, in the present embodiment, the forced initialization operation is performed once in a plurality of fields, so that the forced initialization operation is performed as compared with the configuration in which the forced initialization operation is performed once in one field. Accordingly, the emitted light can be reduced. As a result, the black luminance (the luminance of the gradation that does not generate the sustain discharge) can be lowered, and the contrast of the image displayed on the panel 10 can be improved.

Similarly to the first embodiment, after the last sustain pulse is generated in the sustain period, the scan electrode SU1 to sustain electrode SUn and the data electrode D1 to data electrode Dm are applied with the voltage 0 (V) while being applied with the scan electrode. An upward ramp waveform voltage (upward erasing ramp voltage L3) that gradually increases from voltage 0 (V), which is less than the discharge start voltage, toward voltage Vr, which is a predetermined voltage, is applied to SC1 through scan electrode SCn. Then, the voltage Vr is set to a voltage that is lower than the voltage Vs and does not cause erroneous discharge in the subsequent address period.

This makes it possible to perform a stable writing operation even when driving a large-screen panel 10 with high definition, and display a high-quality image on the panel 10.

In the present embodiment, the configuration in which the forced initializing operation is performed once every 3 fields in each discharge cell has been described, but the present invention is not limited to this configuration. It is desirable to set the number of times of performing the forced initialization operation appropriately according to the characteristics of the panel 10, the specifications of the plasma display device, the setting of the contrast ratio of the image displayed on the panel 10, and the like. .

In the present embodiment, the configuration in which the up-ramp voltage L5 is applied to the scan electrode 22 that does not perform the forced initialization operation in the first half of the initialization period of the first type subfield has been described. It is not limited to this configuration. In the first half of the initializing period of the first type subfield, the voltage applied to the scan electrode 22 that does not perform the forced initializing operation is a voltage that does not cause a discharge in the discharge cell formed on the scan electrode 22. Good. For example, it may be a fixed voltage of voltage 0 (V).

In the present embodiment, the configuration has been described in which all the downward ramp waveform voltages are generated with the same gradient.For example, the downward ramp waveform voltage is divided into a plurality of periods, and the gradient is changed in each period to generate the downward ramp waveform voltage. It may be configured to occur.

FIG. 25 is a waveform diagram showing another example of the waveform shape of the downward ramp waveform voltage applied to the scan electrode 22 in the embodiment of the present invention.

For example, as shown in FIG. 25, the voltage decreases at a relatively steep gradient (for example, −8 V / μsec) until the initialization discharge occurs, and then has a slightly gentle gradient (for example, −2.5 V / μsec). It is also possible to generate a downward ramp waveform voltage by descending at a lower slope and finally descending at a more gentle gradient (for example, -1 V / μsec). Even with such a configuration, it was confirmed that the same effect as described above was obtained. In addition, with this configuration, there is also an effect that the period for generating the downward ramp waveform voltage can be shortened.

Alternatively, although not shown, the downward ramp waveform voltage may be divided into two periods, and the slope may be changed in each period to generate the downward ramp waveform voltage.

In the present embodiment, the configuration in which either the all-cell initializing operation or the selective initializing operation is performed in all subfields has been described. However, for example, the panel may be driven while generating a field in which all cell initialization operations are not performed on all discharge cells on the panel. Even in such a case, the structure shown in this embodiment can be applied.

In this embodiment, an example in which one-phase driving is performed in subfield SF1 and subfield SF2 and two-phase driving is performed in subfield SF3 to subfield SF8 has been described, but the present invention is not limited to this configuration. It is not something. For example, two-phase driving may be performed in all subfields constituting one field, or two-phase driving is performed in subfield SF1 and subfield SF2, and one-phase driving is performed in other subfields. May be. Which subfield is to be driven in one phase and which subfield is to be driven in two phases may be optimally set according to the characteristics of the panel, the use of the plasma display device, and the like. Even in such a case, the structure shown in this embodiment can be applied.

In the present invention, the number of subfields constituting one field, subfields to be forced initialization subfields, luminance weights of each subfield, and the like are not limited to the above-described numerical values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

The drive voltage waveforms shown in FIGS. 4, 5, 6, 19, 21, and 22 are merely examples of the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms. It is not limited to.

The configuration of the drive circuit shown in FIGS. 12, 13, 14, 15, 16, and 17 is merely an example in the embodiment of the present invention, and the present invention is not limited to these circuits. The configuration is not limited.

Note that each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.

In the embodiment of the present invention, an example in which one field is composed of 8 subfields has been described. However, in the present invention, the number of subfields constituting one field is not limited to the above number. For example, by increasing the number of subfields, the number of gradations that can be displayed on the panel 10 can be further increased. Alternatively, the time required for driving panel 10 can be shortened by reducing the number of subfields.

In the embodiment of the present invention, an example in which one pixel is constituted by discharge cells of three colors of red, green, and blue has been described. However, a panel in which one pixel is constituted by discharge cells of four colors or more. However, it is possible to apply the configuration shown in the embodiment of the present invention, and the same effect can be obtained.

The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 24 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Also, the number of subfields constituting one field, the luminance weight of each subfield, etc. are not limited to the values shown in the embodiment of the present invention, and the subfield configuration is based on the image signal or the like. The structure to switch may be sufficient.

The present invention can perform a stable writing operation even when driving a high-definition large-screen panel, and can display a high-quality image on the panel. It is useful as a plasma display device.

DESCRIPTION OF SYMBOLS 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24

Display electrode pair

25,33 Dielectric layer 26 Protective layer 31 Back substrate 32 Data electrode 34 Partition 35 Phosphor layer 40 Plasma display device 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45

Timing generation circuit

50, 80 Sustain

pulse generation circuit

51, 81 Power recovery circuit 60 Ramp waveform

voltage generation circuit

61, 62, 63 Miller integration circuit 70 Scan pulse generation circuit 77 Flexible wiring board 85 Constant voltage generator 95 Scan IC
Di11, Di12, Di21, Di22, Di31, Di62 Diodes L11, L12, L21, L22 Inductors Q5, Q6, Q11, Q12, Q21, Q22, Q55, Q56, Q59, Q69, Q72, Q83, Q84, Q86, Q87, Q71H1 to Q71Hn, Q71L1 to Q71Ln, Q91H1 to Q91Hm, Q91L1 to Q91Lm, SW1, SW2, SW3 Switching element CP1, CP2 comparator OR OR gate AG AND gate C10, C20, C31, C61, C62, C63 capacitors R61, R62, R63 , R9, R12, R13 Resistors Q61, Q62, Q63 Transistors IN1, IN2, IN61, IN62, IN63, INa, INb Input terminals E71 Power supply L1, L5 Up-run Voltage L2, L4, L6, L8, L9, L10 down-ramp voltage L3, L7 erasing up-ramp voltage

Claims

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and a plurality of scans including the first scan electrode group and the second scan electrode group. A method of driving a plasma display panel that is driven by being divided into electrode groups,
After an adjustment period for maintaining the display electrode pair and the data electrode at a base potential, a first downward ramp waveform voltage is applied to the first scan electrode group, and a second downward is applied to the second scan electrode group. An initialization period in which a ramp waveform voltage is applied, an address operation for applying an address pulse to the discharge cells to emit light in the first scan electrode group, and an address pulse to the discharge cells to emit light in the second scan electrode group A subfield having an address period in which a third downward ramp waveform voltage is applied to the scan electrodes between the address operation to be applied, and a sustain period in which a number of sustain pulses corresponding to luminance weights are applied to the display electrode pairs In one field,
A method of driving a plasma display panel, wherein the length of the adjustment period is changed according to the number of sustain pulses generated in the sustain period of the immediately preceding subfield.
The difference between the lowest voltage of the first falling ramp waveform voltage and the lowest voltage of the third falling ramp waveform voltage is expressed as a subfield having a long adjustment period and a subfield having a short adjustment period. The method for driving a plasma display panel according to claim 1, wherein:
The minimum voltage of the third downward ramp waveform voltage is set lower in the subfield having a short adjustment period than in the subfield having a long adjustment period. Driving method of plasma display panel.
A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, an address period, and a sustain period in which a number of sustain pulses corresponding to the luminance weight are applied to the display electrode pair A method for driving a plasma display panel in which one field is composed of a plurality of subfields, and the scan electrodes are divided into a plurality of scan electrode groups including a first scan electrode group and a second scan electrode group Because
A first type subfield and a second type subfield are provided in one field,
The first type subfield includes a scan electrode that applies an upward ramp waveform voltage that rises to a voltage at which discharge occurs in the discharge cell, and a downward ramp waveform voltage that decreases toward a negative voltage, and discharges the discharge cell. Is a subfield having an initialization period in which there is a voltage that does not occur and a scan electrode that applies the downward ramp waveform voltage,
The second type subfield has an initialization period in which a first downward ramp waveform voltage that drops to a voltage at which a discharge is generated only in the discharge cell that has generated an address discharge in the immediately preceding subfield is applied to the scan electrode. Field,
A first voltage is applied to the data electrode during a period in which the downward ramp waveform voltage is applied to the scan electrode in the initialization period of the first type subfield, and the scan is performed in the initialization period of the second type subfield. Applying a second voltage higher than the first voltage to the data electrode during a period of applying the first downward ramp waveform voltage to the electrode;
In subfields other than the last subfield of one field, an up-gradient waveform voltage that rises from a base potential to a predetermined voltage set lower than the voltage of the sustain pulse after the last sustain pulse is generated is applied to the scan electrodes. ,
In the second type subfield, an adjustment period for maintaining the display electrode pair and the data electrode at the base potential is provided immediately before the initialization period, and in the initialization period of the second type subfield, The first downward ramp waveform voltage is applied to the second scan electrode group and the second downward ramp waveform voltage is applied to the second scan electrode group. In the address period of the second type subfield, A third downward ramp waveform between the address operation for applying the address pulse to the discharge cells to emit light in the scan electrode group and the address operation for applying the address pulse to the discharge cells to emit light in the second scan electrode group Applying a voltage to the scan electrode;
A method of driving a plasma display panel, wherein the length of the adjustment period is changed according to the number of sustain pulses generated in the sustain period of the immediately preceding subfield.
The difference between the lowest voltage of the first falling ramp waveform voltage and the lowest voltage of the third falling ramp waveform voltage is expressed as a subfield having a long adjustment period and a subfield having a short adjustment period. The method of driving a plasma display panel according to claim 4, wherein
The minimum voltage of the third downward ramp waveform voltage is set lower in a subfield having a shorter adjustment period than in a subfield having a longer adjustment period. Driving method of plasma display panel.
The lowest voltage of the first downward ramp waveform voltage is set to be higher than the lowest voltage of the downward ramp waveform voltage of the first type subfield to generate the first downward ramp waveform voltage. The method for driving a plasma display panel according to claim 4.
A positive voltage is applied to the sustain electrode during a period in which the downward ramp waveform voltage of the first type subfield is applied to the scan electrode, and a period during which the first downward ramp waveform voltage is applied to the scan electrode during the period The method of claim 4, wherein a voltage higher than a positive voltage is applied to the sustain electrode.
A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
A plasma display device comprising: a drive circuit for driving the plasma display panel by dividing the scan electrodes into a plurality of scan electrode groups including a first scan electrode group and a second scan electrode group;
The drive circuit is
After an adjustment period for maintaining the display electrode pair and the data electrode at a base potential, a first downward ramp waveform voltage is applied to the first scan electrode group, and a second downward is applied to the second scan electrode group. An initialization period in which a ramp waveform voltage is applied, an address operation for applying an address pulse to the discharge cells to emit light in the first scan electrode group, and an address pulse to the discharge cells to emit light in the second scan electrode group A subfield having an address period in which a third downward ramp waveform voltage is applied to the scan electrodes between the address operation to be applied, and a sustain period in which a number of sustain pulses corresponding to luminance weights are applied to the display electrode pairs In one field,
The length of the adjustment period is changed in accordance with the number of sustain pulses generated in the sustain period of the immediately preceding subfield.
The drive circuit is
The difference between the lowest voltage of the first falling ramp waveform voltage and the lowest voltage of the third falling ramp waveform voltage is expressed as a subfield having a long adjustment period and a subfield having a short adjustment period. The plasma display device according to claim 9, wherein the plasma display device is changed as follows.
The drive circuit is
11. The minimum voltage of the third downward ramp waveform voltage is set lower in a subfield having a shorter adjustment period than in a subfield having a longer adjustment period. Plasma display device.
A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
A plurality of subfields each having an address period and a sustain period in which a number of sustain pulses corresponding to luminance weights are applied to the display electrode pair constitute one field, and the scan electrodes are connected to the first scan electrode group and the second scan electrode group. And a driving circuit for driving the plasma display panel divided into a plurality of scanning electrode groups including the scanning electrode group,
The drive circuit is
A first type subfield and a second type subfield are provided in one field to drive the plasma display panel;
The first type subfield includes a scan electrode that applies an upward ramp waveform voltage that rises to a voltage at which discharge occurs in the discharge cell, and a downward ramp waveform voltage that decreases toward a negative voltage, and the discharge cell. There is an initialization period in which there is a voltage at which no discharge occurs and a scan electrode to which the downward ramp waveform voltage is applied, and the second type subfield is only in the discharge cells that have generated an address discharge in the immediately preceding subfield. An initialization period in which a first downward ramp waveform voltage that drops to a voltage at which discharge occurs is applied to the scan electrode;
A first voltage is applied to the data electrode during a period in which the downward ramp waveform voltage is applied to the scan electrode in the initialization period of the first type subfield, and the scan is performed in the initialization period of the second type subfield. Applying a second voltage higher than the first voltage to the data electrode during a period of applying the first downward ramp waveform voltage to the electrode;
In the second type subfield, an adjustment period for maintaining the display electrode pair and the data electrode at the base potential is provided immediately before the initialization period, and in the initialization period of the second type subfield, The first downward ramp waveform voltage is applied to the second scan electrode group and the second downward ramp waveform voltage is applied to the second scan electrode group. In the address period of the second type subfield, A third downward ramp waveform between the address operation for applying the address pulse to the discharge cells to emit light in the scan electrode group and the address operation for applying the address pulse to the discharge cells to emit light in the second scan electrode group Applying a voltage to the scan electrode;
The length of the adjustment period is changed in accordance with the number of sustain pulses generated in the sustain period of the immediately preceding subfield.