WO2012063910A1 - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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Publication number
WO2012063910A1
WO2012063910A1 PCT/JP2011/075956 JP2011075956W WO2012063910A1 WO 2012063910 A1 WO2012063910 A1 WO 2012063910A1 JP 2011075956 W JP2011075956 W JP 2011075956W WO 2012063910 A1 WO2012063910 A1 WO 2012063910A1
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WIPO (PCT)
Prior art keywords
liquid crystal
active matrix
photodiode
substrate
matrix substrate
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PCT/JP2011/075956
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French (fr)
Japanese (ja)
Inventor
広西 相地
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シャープ株式会社
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Publication of WO2012063910A1 publication Critical patent/WO2012063910A1/en

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306Circuit arrangements or driving methods for the control of single liquid crystal cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13312Circuits comprising photodetectors for purposes other than feedback
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509Filters, e.g. light shielding masks
    • G02F1/133512Light shielding layers, e.g. black matrix

Definitions

  • the present invention relates to a liquid crystal display device provided with a photodiode.
  • Patent Document 1 discloses a liquid crystal device in which a photodiode including a semiconductor film having an n-type semiconductor region, an intrinsic semiconductor region, and a p-type semiconductor region is formed on a substrate. Has been.
  • a light shielding film is disposed between a semiconductor film included in the photodiode and the substrate.
  • An object of the present invention is to provide a liquid crystal display device having a novel structure capable of preventing a decrease in output voltage of a photodiode while preventing light from a backlight from entering the photodiode.
  • the liquid crystal display device of the present invention includes an active matrix substrate, a counter substrate disposed to face the active matrix substrate, a liquid crystal layer sealed between the active matrix substrate and the counter substrate, and the counter substrate
  • a backlight disposed on the side opposite to the active matrix substrate side is provided, the active matrix substrate being formed on the liquid crystal layer side of the base substrate and the n-type semiconductor.
  • a photodiode including a semiconductor film having a region, an intrinsic semiconductor region, and a p-type semiconductor region; an insulating film covering the photodiode; and a light of the backlight incident on the photodiode. And a light-shielding film that prevents this.
  • liquid crystal display device of the present invention it is possible to prevent the output voltage of the photodiode from decreasing while avoiding the light from the backlight entering the photodiode.
  • FIG. 1 is a schematic diagram showing a schematic configuration of a liquid crystal display device as one embodiment of the present invention.
  • FIG. 2 is an enlarged plan view showing a main part of an active matrix substrate included in the liquid crystal display device shown in FIG. 1.
  • FIG. 2 is a schematic diagram illustrating a schematic configuration of a photodiode included in the liquid crystal panel illustrated in FIG. 1.
  • FIG. 2 is an equivalent circuit diagram of an optical sensor unit in the liquid crystal display device shown in FIG. 1.
  • a liquid crystal display device includes an active matrix substrate, a counter substrate disposed to face the active matrix substrate, and a liquid crystal layer sealed between the active matrix substrate and the counter substrate. And a backlight disposed opposite to the active matrix substrate side with respect to the counter substrate, and the active matrix substrate is formed on the liquid crystal layer side of the base substrate and the base substrate.
  • a photodiode including a semiconductor film having an n-type semiconductor region, an intrinsic semiconductor region, and a p-type semiconductor region, an insulating film covering the photodiode, and the light from the backlight is formed on the insulating film.
  • a light-shielding film that prevents the light from entering the photodiode (first configuration).
  • a light shielding film is formed. Therefore, it is possible to prevent light from the backlight from entering the photodiode.
  • the parasitic capacitance formed between the semiconductor film and the light shielding film can be reduced. Therefore, it is possible to prevent a decrease in the output voltage of the photodiode.
  • the active matrix substrate further includes wiring formed on the liquid crystal layer side of the photodiode and on the base substrate side of the light shielding film. And the light shielding film overlaps the wiring when the base substrate is viewed from the front. In such a configuration, it is possible to prevent light from the backlight from entering the photodiode by using the wiring. Therefore, the range in which the light from the backlight can be blocked is widened.
  • the third configuration is the first wiring in the second configuration in which the wiring extends in the row direction of the active matrix substrate.
  • the range in which the light from the backlight can be blocked extends in the column direction of the active matrix substrate.
  • a plurality of the first wirings are formed side by side in the column direction of the active matrix substrate, and the active matrix substrate when the active matrix substrate is viewed from the front.
  • the photodiode is located between two first wirings adjacent in the column direction.
  • the fifth configuration is the second wiring in any one of the second to fourth configurations, wherein the wiring extends in the column direction of the active matrix substrate.
  • the range in which the light from the backlight can be shielded extends in the row direction of the active matrix substrate.
  • the fifth configuration in combination with the third or fourth configuration.
  • the range in which light from the backlight can be shielded extends in the row direction and the column direction of the active matrix substrate.
  • a plurality of the second wirings are formed side by side in the row direction of the active matrix substrate, and the active matrix substrate when the active matrix substrate is viewed from the front.
  • the photodiode is positioned between two second wirings adjacent in the row direction.
  • the active matrix substrate is formed at a position different from the photodiode when the active matrix substrate is viewed from the front.
  • a pixel electrode is further provided.
  • the photodiode and the pixel electrode do not overlap when the active matrix substrate is viewed from the front. Therefore, it is possible to avoid the formation of a pre-made capacitor between the photodiode and the pixel electrode.
  • a plurality of the pixel electrodes are formed side by side in a specific direction, and the photodiode includes a plurality of the pixel electrodes when the active matrix substrate is viewed from the front.
  • the n-type semiconductor region, the intrinsic semiconductor region, and the p-type semiconductor region are arranged in a direction orthogonal to the specific direction.
  • the intrinsic semiconductor region can be enlarged while bringing the n-type semiconductor region and the p-type semiconductor region closer to each other. As a result, the photodetection accuracy of the photodiode can be improved.
  • the pixel electrode is a reflective electrode, and the light shielding film is formed in the same layer as the reflective electrode. In such a configuration, it is easy to form a light shielding film.
  • the semiconductor film is a low-temperature polysilicon film.
  • the low-temperature polysilicon film is formed, for example, by irradiating an excimer laser on an amorphous silicon film formed by plasma CVD, sputtering, or the like. In this case, it is difficult to sufficiently increase the thickness of the low-temperature polysilicon film. Therefore, the photocurrent generated according to the amount of light received by the photodiode is reduced.
  • the configuration according to an embodiment of the present invention is employed, the parasitic capacitance formed between the semiconductor film and the light shielding film can be reduced by increasing the film thickness dimension of the insulating film. Therefore, it is possible to prevent a decrease in the output voltage of the photodiode. Therefore, even if the generated photocurrent is small, it can be detected.
  • the eleventh configuration further includes a color filter in any one of the first to tenth configurations. In such a configuration, a color image can be displayed.
  • the color filter is located on the opposite side of the light shielding film with respect to the photodiode.
  • a liquid crystal display device can be used as a color scanner or an IR (infrared) touch panel.
  • the active matrix further includes the color filter, the color filter is closer to the liquid crystal layer than the base substrate, and more than the photodiode. It is formed on the base substrate side.
  • the color filter can be handled integrally with the active matrix substrate.
  • a fourteenth configuration further includes a color filter substrate having the color filter in the twelfth configuration, and the color filter substrate is attached to a surface of the active matrix substrate opposite to the liquid crystal layer side. ing.
  • the color filter and the active matrix substrate can be handled separately.
  • the liquid crystal display device according to the present invention can include arbitrary constituent members not shown in the drawings referred to in this specification.
  • the dimension of the member in each figure does not represent the dimension of an actual structural member, the dimension ratio of each member, etc. faithfully.
  • FIG. 1 shows a liquid crystal display device 10 as an embodiment of the present invention.
  • the liquid crystal display device 10 includes a liquid crystal panel 12 and a backlight 14.
  • the liquid crystal panel 12 includes an active matrix substrate 16, a counter substrate 18, and a liquid crystal layer 20 sealed between these substrates 16 and 18.
  • each pixel 22 includes a plurality of sub-pixels 22r, 22g, and 22b.
  • each pixel 22 includes a red pixel 22r, a green pixel 22g, and a blue pixel 22b.
  • Each of the sub-pixels 22r, 22g, and 22b includes a thin film transistor (not shown) as an active element and a pixel electrode 24.
  • the gate electrode of the thin film transistor is connected to a gate line (not shown) extending from a gate driver (not shown).
  • a source electrode of the thin film transistor is connected to a source line SL extending from a source driver (not shown).
  • the drain electrode of the thin film transistor is connected to the pixel electrode 24.
  • the pixel electrode 24, the counter electrode 58 described later, and the liquid crystal layer 20 form a charge storage capacitor that stores a given charge.
  • a plurality of photodiodes 26 are formed on the active matrix substrate 16.
  • One row formed by arranging several photodiodes 26 in the row direction of the active matrix substrate 16 and one row formed by arranging several pixels 22 in the row direction of the active matrix substrate 16 Are alternately arranged in the column direction of the active matrix substrate 16.
  • the pixel electrode 24 included in each of the sub-pixels 22r, 22g, and 22b and the photodiode 26 are formed at positions that do not overlap in a plan view of the substrate 32 described later. .
  • one photodiode 26 is provided for four pixels 22 (12 sub-pixels 22r, 22g, and 22b).
  • the ratio between the photodiode 26 and the pixel 22 is an arbitrary design item set in consideration of the sensitivity of the photodiode 26 and the like.
  • a storage capacitor Cint (see FIG. 4) used for reading out the output voltage of the photodiode 26 and a read thin film transistor 30 (see FIG. 4).
  • the photosensor portion of the liquid crystal display device 10 is realized by including the photodiode 26, the storage capacitor Cint, and the readout thin film transistor 30.
  • the photodiode 26 is formed on a substrate 32 as a base substrate included in the active matrix substrate 16 as shown in FIG.
  • a substrate 32 for example, a low alkali glass substrate or a quartz substrate can be adopted.
  • the photodiode 26 includes a semiconductor film 34 provided on the substrate 32.
  • the semiconductor film 34 is formed by the same process as a semiconductor film included in a thin film transistor (not shown).
  • the semiconductor film 34 is formed on the substrate 32 through the base layer 36 formed on the substrate 32.
  • the underlayer 36 is provided to prevent impurity diffusion from the glass substrate.
  • the base layer 36 for example, a silicon oxide film, a silicon nitride film, or the like can be employed.
  • the thickness of the underlayer 36 is 100 to 600 nm.
  • the semiconductor film 34 for example, an amorphous silicon film or a crystalline silicon film can be employed.
  • a crystalline silicon film for example, a low-temperature polysilicon film, a high-temperature polysilicon film, a continuous grain boundary silicon film, a microcrystalline silicon film, or the like can be employed.
  • a low-temperature polysilicon film is adopted as the semiconductor film 34.
  • the thickness of the semiconductor film 34 is 25 to 100 nm.
  • a p-type semiconductor region 34p, an intrinsic semiconductor region 34i, and an n-type semiconductor region 34n are formed so as to be arranged along the base layer 36 in this order.
  • the photodiode 26 is a so-called lateral structure PIN diode.
  • the direction in which the p-type semiconductor region 34p, the intrinsic semiconductor region 34i, and the n-type semiconductor region 34n are arranged is the column direction of the active matrix substrate 16.
  • the photodiode 26 is located next to the pixel electrode 24 included in each of the sub-pixels 22r, 22g, and 22b. Therefore, the intrinsic semiconductor region 34i can be enlarged while bringing the p-type semiconductor region 34p and the n-type semiconductor region 34n close to each other. As a result, the light detection accuracy of the photodiode 26 can be improved.
  • the direction in which the p-type semiconductor region 34p, the intrinsic semiconductor region 34i, and the n-type semiconductor region 34n are arranged may be the row direction of the active matrix substrate 16.
  • a gate insulating film 38 is formed on the base layer 36 so as to cover the photodiode 26 (semiconductor film 34).
  • the gate insulating film 38 for example, a silicon oxide film or the like can be employed.
  • the thickness of the gate insulating film 38 is 50 to 120 nm.
  • the gate insulating film 38 also covers a semiconductor film (a semiconductor film having a source region, a channel region, and a drain region) included in a thin film transistor (not shown).
  • An interlayer insulating film 40 is formed on the gate insulating film 38 so as to cover the gate insulating film 38.
  • the interlayer insulating film 40 for example, a film in which a silicon nitride film and a silicon oxide film are stacked in this order can be employed.
  • the thickness of the interlayer insulating film 40 is 500 to 1000 nm.
  • the interlayer insulating film 40 also covers a gate electrode provided in a thin film transistor (not shown).
  • a gate protective film for protecting a gate electrode included in a thin film transistor may be provided below the interlayer insulating film 40.
  • the gate protective film for example, a silicon oxide film or the like can be employed.
  • the thickness of the gate protective film is 20 to 100 nm.
  • contact holes 42 and 44 penetrating the interlayer insulating film 40 and the gate insulating film 38 in the thickness direction are formed.
  • the contact hole 42 is formed at a position overlapping the p-type semiconductor region 34p in the plan view of the substrate 32.
  • the contact hole 44 is formed at a position overlapping the n-type semiconductor region 34n in plan view of the substrate 32.
  • a planarizing film 50 is formed on the interlayer insulating film 40 so as to cover the electrodes / wirings 46 and 48.
  • the planarizing film 50 for example, a silicon oxide film or the like can be employed in addition to an organic insulating film such as a photosensitive acrylic resin.
  • the thickness of the planarizing film 50 is 1000 to 4000 nm.
  • a light shielding film 52 is formed on the planarizing film 50.
  • a metal film can be employed as the light shielding film 52.
  • a metal film formed of refractory metal such as tantalum, tungsten, molybdenum or the like as the light shielding film 52.
  • the thickness of the light shielding film 52 is 50 to 200 nm.
  • the light shielding film 52 is given a constant potential VLS (see FIG. 4) in order to prevent changes in device characteristics due to potential fluctuations.
  • the light shielding film 52 When the liquid crystal display device 10 is a transflective type or a reflective type, the light shielding film 52 also functions as a reflective film. When the liquid crystal display device 10 is a transflective type or a reflective type, the light shielding film 52 can be formed on the same layer as the pixel electrode 24 as a reflective electrode. Thereby, it becomes possible to suppress the increase in the number of manufacturing processes. Even if the liquid crystal display device 10 is a transmissive type, the light shielding film 52 can be formed.
  • the light shielding film 52 is formed so as to cover the photodiode 26 in a plan view of the substrate 32 as indicated by a one-dot chain line in FIG. Thereby, the light of the backlight 14 is prevented from entering the photodiode 26 from the counter substrate 18 side.
  • the width dimension (dimension in the column direction of the active matrix substrate 16) of the light shielding film 52 is preferably larger than the separation distance between the two wirings RST and RWS extending in the row direction of the active matrix substrate 16. If the wirings RST and RWS are formed below the light shielding film 52 (on the side of the substrate 32), one end portion in the width direction of the light shielding film 52 overlaps with the one wiring RST in the plan view of the substrate 32. The other edge in the width direction of the film 52 overlaps the other wiring RWS. Furthermore, if the wirings RST and RWS are formed above the semiconductor film 34 (on the liquid crystal layer 20 side), the light from the backlight 14 can be blocked using the wirings RST and RWS. In the column direction of the active matrix substrate 16, it is not necessary to make the light shielding film 52 larger than necessary.
  • one wiring RST is a wiring for supplying a reset signal, and is connected to the p-type semiconductor region 34p of the photodiode 26 (see FIG. 4).
  • the other wiring RWS is a wiring for supplying a readout signal, and is connected to one electrode of the storage capacitor Cint included in the optical sensor unit of the liquid crystal display device 10 (see FIG. 4).
  • the length dimension of the light shielding film 52 (dimension in the row direction of the active matrix substrate 16) may be substantially the same as the length dimension of the photodiode 26 (dimension in the row direction of the active matrix substrate 16). However, it is preferable that the distance is larger than the distance between two source lines SL and SL adjacent in the row direction of the active matrix substrate 16. If the source lines SL and SL are formed below the light shielding film 52 (on the substrate 32 side), the length of the light shielding film 52 is adjacent to the two source lines SL and SL in the row direction of the active matrix substrate 16.
  • the one edge in the length direction of the light shielding film 52 overlaps with one source line SL, and the other edge in the length direction of the light shielding film 52 overlaps with the other source line SL. .
  • the source lines SL and SL are formed in an upper layer (the liquid crystal layer 20 side) than the semiconductor film 34, the light from the backlight 14 can be shielded using the source line SL. In this way, when the light from the backlight 14 is shielded, one photodiode 26 can be shielded by using the plurality of light shielding films 52.
  • the counter substrate 18 is disposed so as to face the display area of the active matrix substrate 16 (the area where the plurality of pixels 22 are formed).
  • the counter substrate 18 is disposed on the side of the active matrix substrate 16 where the plurality of pixels 22 are formed.
  • the counter substrate 18 includes a substrate 54 as shown in FIG.
  • the substrate 54 for example, a low alkali glass substrate or a quartz substrate can be adopted.
  • a color filter 56 and a counter electrode 58 are laminated on the substrate 54 in this order.
  • the color filter 56 includes a blue colored layer, a green colored layer, and a red colored layer.
  • a black matrix (not shown) is formed between adjacent colored layers.
  • the counter electrode 58 is formed so as to cover the color filter.
  • an ITO (indium tin oxide) film or the like can be employed as the counter electrode 58.
  • a liquid crystal layer 20 is sealed between the active matrix substrate 16 and the counter substrate 18.
  • an operation mode of the liquid crystal for example, a TN (twisted nematic) mode or the like can be adopted.
  • the backlight 14 is arranged so as to illuminate such a liquid crystal panel 12 from the counter substrate 18 side.
  • the backlight 14 for example, a direct type, an edge light type, a planar light source type, or the like can be adopted.
  • a light source of the backlight 14 a cold cathode tube, a light emitting diode (LED), etc. are employable, for example.
  • FIG. 4 shows an equivalent circuit diagram of the optical sensor unit of such a liquid crystal display device 10.
  • the optical sensor unit includes a photodiode 26, a storage capacitor Cint, and a readout thin film transistor 30.
  • the wiring RST is connected to the p-type semiconductor region 34p of the photodiode 26 as described above.
  • the other electrode of the storage capacitor Cint and the gate electrode of the readout thin film transistor 30 are connected to the n-type semiconductor region 34n of the photodiode 26.
  • the wiring RWS is connected to one electrode of the storage capacitor Cint.
  • a constant voltage source VDD for supplying a constant voltage is connected to the source region of the read thin film transistor 30.
  • a wiring VOUT for taking out the output voltage (sensor signal) of the photodiode 26 is connected to the drain region of the reading thin film transistor 30.
  • VA is a potential on the anode side of the photodiode 26 (on the p-type semiconductor region 34p side of the photodiode 26)
  • VC is a cathode side of the photodiode 26 (n-type of the photodiode 26).
  • the VLS is the potential of the light shielding film 52.
  • a sensor signal (output voltage of the photodiode 26) corresponding to the amount of light received by the photodiode 26 can be obtained by supplying a reset signal and a readout signal at a predetermined timing.
  • the reset period starts.
  • a low-level read signal is supplied to the wiring RWS during the reset period.
  • the storage node 60 is a connection point between the storage capacitor Cint, the n-type semiconductor region 34n of the photodiode 26, and the gate electrode of the read thin film transistor 30.
  • the reset period ends.
  • the sensing period starts. Note that in the sensing period, a low-level read signal is supplied to the wiring RWS.
  • a reverse bias is generated in the photodiode 26. Then, the potential of the storage node 60 is changed by the photocurrent generated according to the amount of light incident on the photodiode 26.
  • the potential of the storage node 60 is pulled up via the storage capacitor Cint.
  • the readout thin film transistor 30 is turned on and a sensor signal (output voltage of the photodiode 26) is output.
  • a sensor signal (output voltage of the photodiode 26) can be obtained.
  • a parasitic capacitance Cls is formed between the semiconductor film 34 and the light shielding film 52.
  • the parasitic capacitance Cls and the storage capacitance Cint are discharged for a certain period. That is, as apparent from the relationship shown in the following equation, if the photocurrent ( ⁇ Q) generated according to the amount of light incident on the photodiode 26 is substantially constant, the smaller the parasitic capacitance Cls and the storage capacitance Cint, The amount of change in the potential VC (potential of the storage node 60) on the cathode side (n-type semiconductor region 34n side) of the photodiode 26 increases.
  • Q (Cls + Cint) ⁇ ⁇ VC
  • ⁇ VC represents the amount of change in the cathode side potential VC of the photodiode 26.
  • the storage capacitor Cint cannot be arbitrarily changed, and in order to increase the output voltage (sensor signal) of the photodiode 26, it is necessary to reduce the parasitic capacitance Cls.
  • a light shielding film 52 that shields light from the backlight 14 is formed on the planarizing film 50, and the photodiode 26 (semiconductor film 34) formed on the base layer 36.
  • the gate insulating film 38, the gate insulating film 38, the interlayer insulating film 40, and the planarizing film 50 exist between the gate insulating film 38, the gate insulating film 38, the interlayer insulating film 40, and the planarizing film 50 exist. Thereby, the separation distance between the semiconductor film 34 and the light shielding film 52 can be increased as compared with the case where the light shielding film is formed on the substrate 32.
  • the thickness of the foundation layer 36 existing between the light shielding film and the photodiode 26 (semiconductor film 34) is increased, the stress of the foundation layer 36 Since the substrate 32 is warped and the subsequent manufacturing process cannot be performed, the thickness of the base layer 36 (insulating film) is increased, and the light shielding film and the photodiode 26 (semiconductor film 34) are formed.
  • the insulating film (gate insulating film 38, interlayer insulating film) existing between the light shielding film 52 and the photodiode 26 (semiconductor film 34) is not able to be increased.
  • an insulating film is realized by the gate insulating film 38, the interlayer insulating film 40 and the planarizing film 50.
  • Table 1 shows the parasitic capacitance (parasitic capacitance formed between the photodiode and the light shielding film) of the present embodiment and the conventional configuration.
  • the conventional configuration is a configuration in which the light shielding film 52 is formed on the substrate 32.
  • the base layer 36 exists between the photodiode 26 (semiconductor film 34) and the light shielding film 52.
  • the base layer 36 is formed by laminating a silicon nitride film and a silicon oxide film.
  • Table 1 shows the type of film existing between the photodiode 26 (semiconductor film 34) and the light shielding film 52, the relative dielectric constant of each film, and the film thickness of each film. ing.
  • the parasitic capacitance can be reduced to about 1/10 as compared with the conventional configuration.
  • the output voltage (sensor signal) of the photodiode 26 can be increased. As a result, the sensitivity of the photodiode 26 can be improved.
  • the pixel electrode 24 is formed at a position where it does not overlap the photodiode 26 in the plan view of the substrate 32. Thereby, it is possible to avoid the formation of parasitic capacitance between the pixel electrode 24 and the photodiode 26 (semiconductor film 34).
  • the gate insulating film 38, the interlayer insulating film 40, and the planarizing film 50 exist between the photodiode 26 (semiconductor film 34) and the light shielding film 52, and the substrate 32.
  • the pixel electrode 24 is formed at a position where it does not overlap the photodiode 26 in plan view. Thereby, the adverse effect of the pixel electrode 24 and the light shielding film 52 on the photodiode 26 can be reduced. That is, in a configuration in which an insulating film exists between the photodiode 26 (semiconductor film 34) and an electrode (pixel electrode or light shielding film), the characteristics of the photodiode change when the thickness or quality of the insulating film changes. Although there is a problem of changing (so-called electrode gate action), this embodiment can avoid such a problem.
  • the semiconductor film 34 is a polysilicon film.
  • a method of irradiating an excimer laser to an amorphous silicon film formed on the underlayer 36 by plasma CVD, sputtering, or the like is employed as a method for forming a polysilicon film, the thickness of the polysilicon film is sufficiently increased. Therefore, although the photocurrent generated according to the amount of light received by the photodiode 26 is originally small, in this embodiment, the output voltage of the photodiode 26 can be increased, so even if the generated photocurrent is small. Can be detected.
  • the sensitivity of the photodiode 26 is improved.
  • the number of photodiodes 26 to be employed can be reduced and the transmittance of the liquid crystal panel 12 can be improved.
  • the sensitivity of the photodiode 26 is improved.
  • the number of photodiodes 26 to be employed can be increased and the resolution can be improved.
  • the color filter 56 may be provided on the active matrix substrate 16 side. Accordingly, the liquid crystal display device can be used as a color scanner or an IR (infrared) touch panel.
  • the color filter 56 When the color filter 56 is provided on the active matrix substrate 16 side, for example, the color filter 56 may be formed on the substrate 32 as shown in FIG. In FIG. 5, the color filter 56 is covered with an overcoat film 62, and the base layer 36 is formed so as to cover the overcoat film 62.
  • the overcoat film 62 a silicon oxide film, a silicon nitride film, or the like can be employed.
  • the film thickness of the overcoat film 62 is 1000 to 3000 nm. Note that the overcoat film 62 and the base layer 36 may be formed of the same film.
  • a color filter substrate 64 on which the color filter 56 is formed may be prepared separately, and the color filter substrate 64 may be attached to the active matrix substrate 16 from the outside.
  • the color filter substrate 64 the color filter 56 formed on the substrate 66 is covered with the overcoat film 62.
  • the substrate 66 for example, a glass substrate or an acrylic substrate can be employed.
  • each pixel 22 may include a yellow pixel in addition to the red pixel 22r, the green pixel 22g, and the blue pixel 22b.

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Abstract

The present invention is intended to provide a liquid crystal device that can prevent a reduction of output voltage in a photodiode, while the light from the backlight is circumvented from impinging on the photodiode. This liquid crystal device comprises: an active matrix substrate (16); an opposing substrate (18) that is disposed opposite to the active matrix substrate; a liquid crystal layer (20) that is enclosed between the active matrix substrate and the opposing substrate; and a backlight that is disposed on the opposite side from the active matrix substrate side with respect to the opposing substrate. The active matrix substrate comprises: a base substrate (32); a photodiode (26) comprising a semiconductor film (34) that is formed further toward the liquid crystal layer side than the base substrate; insulating films (38,40,50) that cover the photodiode; and a light excluding film (52) that is formed on the insulating films, and that prevents the light from the backlight from impinging on the photodiode.

Description

液晶表示装置Liquid crystal display
 本発明は、フォトダイオードを備えた液晶表示装置に関する。 The present invention relates to a liquid crystal display device provided with a photodiode.
 従来から、タッチセンサ機能等を実現するために、フォトダイオードを備えた液晶表示装置が知られている。例えば、特開2008-287061号公報(特許文献1)には、n型半導体領域と真性半導体領域とp型半導体領域とを有する半導体膜を備えるフォトダイオードが基板上に形成された液晶装置が開示されている。 Conventionally, in order to realize a touch sensor function or the like, a liquid crystal display device provided with a photodiode is known. For example, Japanese Patent Laying-Open No. 2008-287061 (Patent Document 1) discloses a liquid crystal device in which a photodiode including a semiconductor film having an n-type semiconductor region, an intrinsic semiconductor region, and a p-type semiconductor region is formed on a substrate. Has been.
 ところで、フォトダイオードを備えた液晶表示装置においては、バックライトからの光がフォトダイオードに入射するのを防ぐ必要がある。そこで、特許文献1に記載の液晶装置においては、フォトダイオードが備える半導体膜と基板との間に遮光膜が配置されている。 Incidentally, in a liquid crystal display device provided with a photodiode, it is necessary to prevent light from the backlight from entering the photodiode. Therefore, in the liquid crystal device described in Patent Document 1, a light shielding film is disposed between a semiconductor film included in the photodiode and the substrate.
 しかしながら、基板と半導体膜との間に遮光膜が配置されていると、半導体膜と遮光膜との間において、寄生容量が形成されてしまう。その結果、フォトダイオードの出力電圧が低下してしまうという問題があった。 However, if a light shielding film is disposed between the substrate and the semiconductor film, a parasitic capacitance is formed between the semiconductor film and the light shielding film. As a result, there is a problem that the output voltage of the photodiode is lowered.
 本発明の目的は、バックライトからの光がフォトダイオードに入射するのを回避しつつ、フォトダイオードの出力電圧の低下を防ぐことができる、新規な構造の液晶表示装置を提供することにある。 An object of the present invention is to provide a liquid crystal display device having a novel structure capable of preventing a decrease in output voltage of a photodiode while preventing light from a backlight from entering the photodiode.
 本発明の液晶表示装置は、アクティブマトリクス基板と、前記アクティブマトリクス基板に対向して配置された対向基板と、前記アクティブマトリクス基板と前記対向基板との間に封入された液晶層と、前記対向基板に対して、前記アクティブマトリクス基板側とは反対側に配置されたバックライトとを備え、前記アクティブマトリクス基板は、ベース基板と、前記ベース基板よりも前記液晶層側に形成されて、n型半導体領域と真性半導体領域とp型半導体領域とを有する半導体膜を備えるフォトダイオードと、前記フォトダイオードを覆う絶縁膜と、前記絶縁膜上に形成されて、前記バックライトの光が前記フォトダイオードへ入射するのを防ぐ遮光膜とを備える。 The liquid crystal display device of the present invention includes an active matrix substrate, a counter substrate disposed to face the active matrix substrate, a liquid crystal layer sealed between the active matrix substrate and the counter substrate, and the counter substrate In contrast, a backlight disposed on the side opposite to the active matrix substrate side is provided, the active matrix substrate being formed on the liquid crystal layer side of the base substrate and the n-type semiconductor. A photodiode including a semiconductor film having a region, an intrinsic semiconductor region, and a p-type semiconductor region; an insulating film covering the photodiode; and a light of the backlight incident on the photodiode. And a light-shielding film that prevents this.
 本発明の液晶表示装置によれば、バックライトからの光がフォトダイオードに入射するのを回避しつつ、フォトダイオードの出力電圧の低下を防ぐことができる。 According to the liquid crystal display device of the present invention, it is possible to prevent the output voltage of the photodiode from decreasing while avoiding the light from the backlight entering the photodiode.
本発明の一実施形態としての液晶表示装置の概略構成を示す模式図。1 is a schematic diagram showing a schematic configuration of a liquid crystal display device as one embodiment of the present invention. 図1に示した液晶表示装置が備えるアクティブマトリクス基板の要部を拡大して示す平面図。FIG. 2 is an enlarged plan view showing a main part of an active matrix substrate included in the liquid crystal display device shown in FIG. 1. 図1に示した液晶パネルが備えるフォトダイオードの概略構成を示す模式図。FIG. 2 is a schematic diagram illustrating a schematic configuration of a photodiode included in the liquid crystal panel illustrated in FIG. 1. 図1に示した液晶表示装置における光センサ部の等価回路図。FIG. 2 is an equivalent circuit diagram of an optical sensor unit in the liquid crystal display device shown in FIG. 1. 本発明の一実施形態としての液晶表示装置の応用例を説明するための模式図。The schematic diagram for demonstrating the application example of the liquid crystal display device as one Embodiment of this invention. 本発明の一実施形態としての液晶表示装置の他の応用例を説明するための模式図。The schematic diagram for demonstrating the other application example of the liquid crystal display device as one Embodiment of this invention.
 本発明の一実施形態に係る液晶表示装置は、アクティブマトリクス基板と、前記アクティブマトリクス基板に対向して配置された対向基板と、前記アクティブマトリクス基板と前記対向基板との間に封入された液晶層と、前記対向基板に対して、前記アクティブマトリクス基板側とは反対側に配置されたバックライトとを備え、前記アクティブマトリクス基板は、ベース基板と、前記ベース基板よりも前記液晶層側に形成されて、n型半導体領域と真性半導体領域とp型半導体領域とを有する半導体膜を備えるフォトダイオードと、前記フォトダイオードを覆う絶縁膜と、前記絶縁膜上に形成されて、前記バックライトの光が前記フォトダイオードへ入射するのを防ぐ遮光膜とを備える(第1の構成)。 A liquid crystal display device according to an embodiment of the present invention includes an active matrix substrate, a counter substrate disposed to face the active matrix substrate, and a liquid crystal layer sealed between the active matrix substrate and the counter substrate. And a backlight disposed opposite to the active matrix substrate side with respect to the counter substrate, and the active matrix substrate is formed on the liquid crystal layer side of the base substrate and the base substrate. A photodiode including a semiconductor film having an n-type semiconductor region, an intrinsic semiconductor region, and a p-type semiconductor region, an insulating film covering the photodiode, and the light from the backlight is formed on the insulating film. A light-shielding film that prevents the light from entering the photodiode (first configuration).
 第1の構成においては、遮光膜が形成されている。そのため、バックライトからの光がフォトダイオードに入射するのを防ぐことができる。 In the first configuration, a light shielding film is formed. Therefore, it is possible to prevent light from the backlight from entering the photodiode.
 絶縁膜の膜厚寸法を大きくすることにより、半導体膜と遮光膜との間に形成される寄生容量を小さくすることができる。そのため、フォトダイオードの出力電圧の低下を防ぐことができる。 By increasing the thickness of the insulating film, the parasitic capacitance formed between the semiconductor film and the light shielding film can be reduced. Therefore, it is possible to prevent a decrease in the output voltage of the photodiode.
 第2の構成は、前記第1の構成において、前記アクティブマトリクス基板は、前記フォトダイオードよりも前記液晶層側であって、且つ、前記遮光膜よりも前記ベース基板側に形成された配線をさらに備え、前記ベース基板を正面から見たときに、前記遮光膜が前記配線に重なる。このような構成においては、配線を利用して、バックライトからの光がフォトダイオードに入射するのを防ぐことができる。そのため、バックライトからの光を遮光できる範囲が広がる。 According to a second configuration, in the first configuration, the active matrix substrate further includes wiring formed on the liquid crystal layer side of the photodiode and on the base substrate side of the light shielding film. And the light shielding film overlaps the wiring when the base substrate is viewed from the front. In such a configuration, it is possible to prevent light from the backlight from entering the photodiode by using the wiring. Therefore, the range in which the light from the backlight can be blocked is widened.
 第3の構成は、前記第2の構成において、前記配線が前記アクティブマトリクス基板の行方向に延びる第1配線である。このような構成においては、バックライトからの光を遮光できる範囲がアクティブマトリクス基板の列方向に広がる。 The third configuration is the first wiring in the second configuration in which the wiring extends in the row direction of the active matrix substrate. In such a configuration, the range in which the light from the backlight can be blocked extends in the column direction of the active matrix substrate.
 第4の構成は、前記第3の構成において、前記第1配線が前記アクティブマトリクス基板の列方向に並んで複数形成されており、前記アクティブマトリクス基板を正面から見たときに、前記アクティブマトリクス基板の列方向で隣り合う2つの前記第1配線の間に、前記フォトダイオードが位置する。このような構成においては、バックライトからの光を遮光できる範囲がアクティブマトリクス基板の列方向にさらに広がる。 According to a fourth configuration, in the third configuration, a plurality of the first wirings are formed side by side in the column direction of the active matrix substrate, and the active matrix substrate when the active matrix substrate is viewed from the front. The photodiode is located between two first wirings adjacent in the column direction. In such a configuration, the range in which the light from the backlight can be shielded further expands in the column direction of the active matrix substrate.
 第5の構成は、前記第2~第4の構成の何れか1つにおいて、前記配線が前記アクティブマトリクス基板の列方向に延びる第2配線である。このような構成においては、バックライトからの光を遮光できる範囲がアクティブマトリクス基板の行方向に広がる。 The fifth configuration is the second wiring in any one of the second to fourth configurations, wherein the wiring extends in the column direction of the active matrix substrate. In such a configuration, the range in which the light from the backlight can be shielded extends in the row direction of the active matrix substrate.
 また、第5の構成は、前記第3又は第4の構成と組み合わせて採用することが望ましい。この場合、バックライトからの光を遮光できる範囲がアクティブマトリクス基板の行方向と列方向にそれぞれ広がる。 In addition, it is desirable to adopt the fifth configuration in combination with the third or fourth configuration. In this case, the range in which light from the backlight can be shielded extends in the row direction and the column direction of the active matrix substrate.
 第6の構成は、前記第5の構成において、前記第2配線が前記アクティブマトリクス基板の行方向に並んで複数形成されており、前記アクティブマトリクス基板を正面から見たときに、前記アクティブマトリクス基板の行方向で隣り合う2つの前記第2配線の間に、前記フォトダイオードが位置する。このような構成においては、バックライトからの光を遮光できる範囲がアクティブマトリクス基板の行方向にさらに広がる。 According to a sixth configuration, in the fifth configuration, a plurality of the second wirings are formed side by side in the row direction of the active matrix substrate, and the active matrix substrate when the active matrix substrate is viewed from the front. The photodiode is positioned between two second wirings adjacent in the row direction. In such a configuration, the range in which the light from the backlight can be shielded further expands in the row direction of the active matrix substrate.
 第7の構成は、前記第1~第6の構成の何れか1つにおいて、前記アクティブマトリクス基板は、前記アクティブマトリクス基板を正面から見たときに、前記フォトダイオードとは異なる位置に形成された画素電極をさらに備える。このような構成においては、アクティブマトリクス基板を正面から見たときに、フォトダイオードと画素電極が重ならない。そのため、フォトダイオードと画素電極との間に既成容量が形成されるのを回避できる。 According to a seventh configuration, in any one of the first to sixth configurations, the active matrix substrate is formed at a position different from the photodiode when the active matrix substrate is viewed from the front. A pixel electrode is further provided. In such a configuration, the photodiode and the pixel electrode do not overlap when the active matrix substrate is viewed from the front. Therefore, it is possible to avoid the formation of a pre-made capacitor between the photodiode and the pixel electrode.
 第8の構成は、前記第7の構成において、前記画素電極が特定の方向に並んで複数形成されており、前記アクティブマトリクス基板を正面から見たときに、前記フォトダイオードが複数の前記画素電極の隣に位置し、前記n型半導体領域と、前記真性半導体領域と、前記p型半導体領域とが、前記特定の方向と直交する方向に並んでいる。このような構成においては、n型半導体領域とp型半導体領域を接近させつつ、真性半導体領域を大きくすることができる。その結果、フォトダイオードの光検出精度を向上させることができる。 According to an eighth configuration, in the seventh configuration, a plurality of the pixel electrodes are formed side by side in a specific direction, and the photodiode includes a plurality of the pixel electrodes when the active matrix substrate is viewed from the front. The n-type semiconductor region, the intrinsic semiconductor region, and the p-type semiconductor region are arranged in a direction orthogonal to the specific direction. In such a configuration, the intrinsic semiconductor region can be enlarged while bringing the n-type semiconductor region and the p-type semiconductor region closer to each other. As a result, the photodetection accuracy of the photodiode can be improved.
 第9の構成は、第7又は第8の構成において、前記画素電極が反射電極であり、前記遮光膜が前記反射電極と同じ層に形成されている。このような構成においては、遮光膜の形成が容易になる。 In the ninth configuration, in the seventh or eighth configuration, the pixel electrode is a reflective electrode, and the light shielding film is formed in the same layer as the reflective electrode. In such a configuration, it is easy to form a light shielding film.
 第10の構成は、前記第1~第9の構成の何れか1つにおいて、前記半導体膜が低温ポリシリコン膜とされている。低温ポリシリコン膜は、例えば、プラズマCVDやスパッタ等で形成されたアモルファスシリコン膜にエキシマレーザーを照射することで形成される。この場合、低温ポリシリコン膜の厚さを十分に大きくすることが難しい。そのため、フォトダイオードの受光量に応じて発生する光電流が小さくなる。しかしながら、本発明の一実施形態に係る構成を採用すれば、絶縁膜の膜厚寸法を大きくすることにより、半導体膜と遮光膜との間に形成される寄生容量を小さくすることができる。そのため、フォトダイオードの出力電圧の低下を防ぐことができる。従って、発生する光電流が小さくても検出できる。 In a tenth configuration, in any one of the first to ninth configurations, the semiconductor film is a low-temperature polysilicon film. The low-temperature polysilicon film is formed, for example, by irradiating an excimer laser on an amorphous silicon film formed by plasma CVD, sputtering, or the like. In this case, it is difficult to sufficiently increase the thickness of the low-temperature polysilicon film. Therefore, the photocurrent generated according to the amount of light received by the photodiode is reduced. However, if the configuration according to an embodiment of the present invention is employed, the parasitic capacitance formed between the semiconductor film and the light shielding film can be reduced by increasing the film thickness dimension of the insulating film. Therefore, it is possible to prevent a decrease in the output voltage of the photodiode. Therefore, even if the generated photocurrent is small, it can be detected.
 第11の構成は、前記第1~第10の構成の何れか1つにおいて、カラーフィルタをさらに備える。このような構成においては、カラー画像を表示することができる。 The eleventh configuration further includes a color filter in any one of the first to tenth configurations. In such a configuration, a color image can be displayed.
 第12の構成は、前記第11の構成において、前記カラーフィルタが、前記フォトダイオードに対して、前記遮光膜とは反対側に位置する。このような構成においては、カラースキャナやIR(赤外線)方式のタッチパネルとして、液晶表示装置を利用することができる。 In a twelfth configuration, in the eleventh configuration, the color filter is located on the opposite side of the light shielding film with respect to the photodiode. In such a configuration, a liquid crystal display device can be used as a color scanner or an IR (infrared) touch panel.
 第13の構成は、前記第12の構成において、前記アクティブマトリクスが前記カラーフィルタをさらに備え、前記カラーフィルタが、前記ベース基板よりも前記液晶層側であって、且つ、前記フォトダイオードよりも前記ベース基板側に形成されている。このような構成においては、カラーフィルタをアクティブマトリクス基板と一体的に取り扱うことができる。 In a thirteenth configuration according to the twelfth configuration, the active matrix further includes the color filter, the color filter is closer to the liquid crystal layer than the base substrate, and more than the photodiode. It is formed on the base substrate side. In such a configuration, the color filter can be handled integrally with the active matrix substrate.
 第14の構成は、前記第12の構成において、前記カラーフィルタを有するカラーフィルタ基板をさらに備え、前記アクティブマトリクス基板の前記液晶層側とは反対側の面に、前記カラーフィルタ基板が貼り付けられている。このような構成においては、カラーフィルタとアクティブマトリクス基板を別々に取り扱うことができる。 A fourteenth configuration further includes a color filter substrate having the color filter in the twelfth configuration, and the color filter substrate is attached to a surface of the active matrix substrate opposite to the liquid crystal layer side. ing. In such a configuration, the color filter and the active matrix substrate can be handled separately.
 以下、本発明のより具体的な実施形態について、図面を参照しながら説明する。なお、以下で参照する各図は、説明の便宜上、本発明の実施形態の構成部材のうち、本発明を説明するために必要な主要部材のみを簡略化して示したものである。従って、本発明に係る液晶表示装置は、本明細書が参照する各図に示されていない任意の構成部材を備え得る。また、各図中の部材の寸法は、実際の構成部材の寸法および各部材の寸法比率等を忠実に表したものではない。 Hereinafter, more specific embodiments of the present invention will be described with reference to the drawings. In addition, each figure referred below demonstrates the simplified main component required in order to demonstrate this invention among the structural members of embodiment of this invention for convenience of explanation. Therefore, the liquid crystal display device according to the present invention can include arbitrary constituent members not shown in the drawings referred to in this specification. Moreover, the dimension of the member in each figure does not represent the dimension of an actual structural member, the dimension ratio of each member, etc. faithfully.
 [実施形態]
 図1には、本発明の一実施形態としての液晶表示装置10が示されている。この液晶表示装置10は、液晶パネル12と、バックライト14とを備えている。
[Embodiment]
FIG. 1 shows a liquid crystal display device 10 as an embodiment of the present invention. The liquid crystal display device 10 includes a liquid crystal panel 12 and a backlight 14.
 液晶パネル12は、アクティブマトリクス基板16と、対向基板18と、これらの基板16,18の間に封入された液晶層20とを備えている。 The liquid crystal panel 12 includes an active matrix substrate 16, a counter substrate 18, and a liquid crystal layer 20 sealed between these substrates 16 and 18.
 アクティブマトリクス基板16には、複数の画素22(図2参照)が形成されている。各画素22は、図2に示されているように、複数のサブ画素22r,22g,22bを備えている。本実施形態では、各画素22は、赤色画素22rと、緑色画素22gと、青色画素22bとを備えている。 A plurality of pixels 22 (see FIG. 2) are formed on the active matrix substrate 16. As shown in FIG. 2, each pixel 22 includes a plurality of sub-pixels 22r, 22g, and 22b. In the present embodiment, each pixel 22 includes a red pixel 22r, a green pixel 22g, and a blue pixel 22b.
 各サブ画素22r,22g,22bは、アクティブ素子としての薄膜トランジスタ(図示せず)と、画素電極24とを含んで構成されている。 Each of the sub-pixels 22r, 22g, and 22b includes a thin film transistor (not shown) as an active element and a pixel electrode 24.
 薄膜トランジスタのゲート電極は、図示しないゲートドライバから延び出すゲート線(図示せず)に接続されている。薄膜トランジスタのソース電極は、図示しないソースドライバから延び出すソース線SLに接続されている。薄膜トランジスタのドレイン電極は、画素電極24に接続されている。画素電極24と、後述する対向電極58と、液晶層20とによって、与えられた電荷を蓄積する電荷蓄積容量が形成されている。 The gate electrode of the thin film transistor is connected to a gate line (not shown) extending from a gate driver (not shown). A source electrode of the thin film transistor is connected to a source line SL extending from a source driver (not shown). The drain electrode of the thin film transistor is connected to the pixel electrode 24. The pixel electrode 24, the counter electrode 58 described later, and the liquid crystal layer 20 form a charge storage capacitor that stores a given charge.
 アクティブマトリクス基板16には、複数のフォトダイオード26が形成されている。幾つかのフォトダイオード26がアクティブマトリクス基板16の行方向に並ぶことで形成された一つの行と、幾つかの画素22がアクティブマトリクス基板16の行方向に並ぶことで形成された一つの行とが、アクティブマトリクス基板16の列方向で交互に並んでいる。このことから明らかなように、本実施形態では、各サブ画素22r,22g,22bが備える画素電極24と、フォトダイオード26とが、後述する基板32の平面視で重ならない位置に形成されている。 A plurality of photodiodes 26 are formed on the active matrix substrate 16. One row formed by arranging several photodiodes 26 in the row direction of the active matrix substrate 16 and one row formed by arranging several pixels 22 in the row direction of the active matrix substrate 16 Are alternately arranged in the column direction of the active matrix substrate 16. As is clear from this, in the present embodiment, the pixel electrode 24 included in each of the sub-pixels 22r, 22g, and 22b and the photodiode 26 are formed at positions that do not overlap in a plan view of the substrate 32 described later. .
 アクティブマトリクス基板16においては、四つの画素22(12のサブ画素22r,22g,22b)に対して、一つのフォトダイオード26が設けられている。フォトダイオード26と画素22の比率は、フォトダイオード26の感度等を考慮して設定される任意の設計事項である。 In the active matrix substrate 16, one photodiode 26 is provided for four pixels 22 (12 sub-pixels 22r, 22g, and 22b). The ratio between the photodiode 26 and the pixel 22 is an arbitrary design item set in consideration of the sensitivity of the photodiode 26 and the like.
 なお、図2では示されていないが、フォトダイオード26の形成領域には、フォトダイオード26の出力電圧を読み出す際に用いる蓄積容量Cint(図4参照)と、読み出し用薄膜トランジスタ30(図4参照)とが、形成されている。そして、フォトダイオード26と、蓄積容量Cintと、読み出し用薄膜トランジスタ30とを含んで、液晶表示装置10の光センサ部が実現されている。 Although not shown in FIG. 2, in the formation region of the photodiode 26, a storage capacitor Cint (see FIG. 4) used for reading out the output voltage of the photodiode 26 and a read thin film transistor 30 (see FIG. 4). Are formed. The photosensor portion of the liquid crystal display device 10 is realized by including the photodiode 26, the storage capacitor Cint, and the readout thin film transistor 30.
 フォトダイオード26は、図3に示されているように、アクティブマトリクス基板16が備えるベース基板としての基板32上に形成されている。基板32としては、例えば、低アルカリガラス基板や石英基板を採用することができる。 The photodiode 26 is formed on a substrate 32 as a base substrate included in the active matrix substrate 16 as shown in FIG. As the substrate 32, for example, a low alkali glass substrate or a quartz substrate can be adopted.
 フォトダイオード26は、基板32上に設けられた半導体膜34を備えている。なお、半導体膜34は、図示しない薄膜トランジスタが備える半導体膜と同一のプロセスで形成される。 The photodiode 26 includes a semiconductor film 34 provided on the substrate 32. The semiconductor film 34 is formed by the same process as a semiconductor film included in a thin film transistor (not shown).
 本実施形態では、基板32上に形成された下地層36を介して、半導体膜34が基板32上に形成されている。下地層36は、ガラス基板からの不純物拡散を防ぐために設けられている。下地層36としては、例えば、酸化シリコン膜や窒化シリコン膜等を採用することができる。下地層36の厚さは、100~600nmである。 In the present embodiment, the semiconductor film 34 is formed on the substrate 32 through the base layer 36 formed on the substrate 32. The underlayer 36 is provided to prevent impurity diffusion from the glass substrate. As the base layer 36, for example, a silicon oxide film, a silicon nitride film, or the like can be employed. The thickness of the underlayer 36 is 100 to 600 nm.
 半導体膜34としては、例えば、非晶質シリコン膜や結晶質シリコン膜等を採用することができる。結晶質シリコン膜としては、例えば、低温ポリシリコン膜や高温ポリシリコン膜,連続粒界シリコン膜,微結晶シリコン膜等を採用することができる。因みに、本実施形態では、半導体膜34として、低温ポリシリコン膜が採用されている。半導体膜34の厚さは、25~100nmである。 As the semiconductor film 34, for example, an amorphous silicon film or a crystalline silicon film can be employed. As the crystalline silicon film, for example, a low-temperature polysilicon film, a high-temperature polysilicon film, a continuous grain boundary silicon film, a microcrystalline silicon film, or the like can be employed. Incidentally, in this embodiment, a low-temperature polysilicon film is adopted as the semiconductor film 34. The thickness of the semiconductor film 34 is 25 to 100 nm.
 半導体膜34には、p型半導体領域34pと、真性半導体領域34iと、n型半導体領域34nとが、この順番で下地層36に沿って並ぶように形成されている。このことから明らかなように、フォトダイオード26は、いわゆるラテラル構造のPINダイオードである。 In the semiconductor film 34, a p-type semiconductor region 34p, an intrinsic semiconductor region 34i, and an n-type semiconductor region 34n are formed so as to be arranged along the base layer 36 in this order. As is apparent from this, the photodiode 26 is a so-called lateral structure PIN diode.
 特に本実施形態では、p型半導体領域34pと、真性半導体領域34iと、n型半導体領域34nとが並ぶ方向は、アクティブマトリクス基板16の列方向である。基板32の正面視において、各サブ画素22r,22g,22bが備える画素電極24の隣に、フォトダイオード26が位置している。そのため、p型半導体領域34pとn型半導体領域34nを接近させつつ、真性半導体領域34iを大きくすることができる。その結果、フォトダイオード26の光検出精度を向上させることができる。なお、p型半導体領域34pと、真性半導体領域34iと、n型半導体領域34nとが並ぶ方向は、アクティブマトリクス基板16の行方向であっても良い。 Particularly in this embodiment, the direction in which the p-type semiconductor region 34p, the intrinsic semiconductor region 34i, and the n-type semiconductor region 34n are arranged is the column direction of the active matrix substrate 16. In the front view of the substrate 32, the photodiode 26 is located next to the pixel electrode 24 included in each of the sub-pixels 22r, 22g, and 22b. Therefore, the intrinsic semiconductor region 34i can be enlarged while bringing the p-type semiconductor region 34p and the n-type semiconductor region 34n close to each other. As a result, the light detection accuracy of the photodiode 26 can be improved. Note that the direction in which the p-type semiconductor region 34p, the intrinsic semiconductor region 34i, and the n-type semiconductor region 34n are arranged may be the row direction of the active matrix substrate 16.
 フォトダイオード26(半導体膜34)を覆うようにして、ゲート絶縁膜38が下地層36上に形成されている。ゲート絶縁膜38としては、例えば、酸化シリコン膜等を採用することができる。ゲート絶縁膜38の厚さは、50~120nmである。ゲート絶縁膜38は、図示しない薄膜トランジスタが備える半導体膜(ソース領域,チャネル領域及びドレイン領域を有する半導体膜)も覆っている。 A gate insulating film 38 is formed on the base layer 36 so as to cover the photodiode 26 (semiconductor film 34). As the gate insulating film 38, for example, a silicon oxide film or the like can be employed. The thickness of the gate insulating film 38 is 50 to 120 nm. The gate insulating film 38 also covers a semiconductor film (a semiconductor film having a source region, a channel region, and a drain region) included in a thin film transistor (not shown).
 ゲート絶縁膜38を覆うようにして、層間絶縁膜40がゲート絶縁膜38上に形成されている。層間絶縁膜40としては、例えば、窒化シリコン膜と、酸化シリコン膜とが、この順番で積層されたもの等を採用することができる。層間絶縁膜40の厚さは、500~1000nmである。なお、層間絶縁膜40は、図示しない薄膜トランジスタが備えるゲート電極も覆っている。 An interlayer insulating film 40 is formed on the gate insulating film 38 so as to cover the gate insulating film 38. As the interlayer insulating film 40, for example, a film in which a silicon nitride film and a silicon oxide film are stacked in this order can be employed. The thickness of the interlayer insulating film 40 is 500 to 1000 nm. The interlayer insulating film 40 also covers a gate electrode provided in a thin film transistor (not shown).
 なお、層間絶縁膜40の下層に位置して、図示しない薄膜トランジスタが備えるゲート電極を保護するゲート保護膜を設けるようにしても良い。ゲート保護膜としては、例えば、酸化シリコン膜等を採用することができる。ゲート保護膜の厚さは、20~100nmである。 Note that a gate protective film for protecting a gate electrode included in a thin film transistor (not shown) may be provided below the interlayer insulating film 40. As the gate protective film, for example, a silicon oxide film or the like can be employed. The thickness of the gate protective film is 20 to 100 nm.
 層間絶縁膜40及びゲート絶縁膜38には、層間絶縁膜40及びゲート絶縁膜38を厚さ方向に貫通するコンタクトホール42,44が形成されている。コンタクトホール42は、基板32の平面視において、p型半導体領域34pと重なる位置に形成されている。コンタクトホール44は、基板32の平面視において、n型半導体領域34nと重なる位置に形成されている。このようにして、コンタクトホール42,44が形成されていることにより、p型半導体領域34pとn型半導体領域34nのそれぞれに対して、層間絶縁膜40上に形成された電極・配線46,48が接続されている。電極・配線46,48としては、例えば、窒化チタン膜とアルミニウム膜の二層構造を有するもの等を採用することができる。 In the interlayer insulating film 40 and the gate insulating film 38, contact holes 42 and 44 penetrating the interlayer insulating film 40 and the gate insulating film 38 in the thickness direction are formed. The contact hole 42 is formed at a position overlapping the p-type semiconductor region 34p in the plan view of the substrate 32. The contact hole 44 is formed at a position overlapping the n-type semiconductor region 34n in plan view of the substrate 32. By forming the contact holes 42 and 44 in this way, electrodes / wirings 46 and 48 formed on the interlayer insulating film 40 for the p-type semiconductor region 34p and the n-type semiconductor region 34n, respectively. Is connected. As the electrodes / wirings 46 and 48, for example, those having a two-layer structure of a titanium nitride film and an aluminum film can be employed.
 電極・配線46,48を覆うようにして、平坦化膜50が層間絶縁膜40上に形成されている。平坦化膜50としては、例えば、感光性アクリル樹脂等の有機絶縁膜の他、酸化シリコン膜等を採用することができる。平坦化膜50の厚さは、1000~4000nmである。 A planarizing film 50 is formed on the interlayer insulating film 40 so as to cover the electrodes / wirings 46 and 48. As the planarizing film 50, for example, a silicon oxide film or the like can be employed in addition to an organic insulating film such as a photosensitive acrylic resin. The thickness of the planarizing film 50 is 1000 to 4000 nm.
 平坦化膜50上には、遮光膜52が形成されている。遮光膜52としては、例えば、金属膜を採用することができる。アクティブマトリクス基板16の製造方法を考慮すると、遮光膜52としては、高融点金属であるタンタルやタングステン,モリブデン等で形成された金属膜を採用することが望ましい。遮光膜52の厚さは、50~200nmである。遮光膜52には、電位変動によるデバイス特性の変化を防止するために、一定の電位VLS(図4参照)が与えられている。 A light shielding film 52 is formed on the planarizing film 50. As the light shielding film 52, for example, a metal film can be employed. Considering the manufacturing method of the active matrix substrate 16, it is desirable to employ a metal film formed of refractory metal such as tantalum, tungsten, molybdenum or the like as the light shielding film 52. The thickness of the light shielding film 52 is 50 to 200 nm. The light shielding film 52 is given a constant potential VLS (see FIG. 4) in order to prevent changes in device characteristics due to potential fluctuations.
 液晶表示装置10が半透過型や反射型である場合、遮光膜52は反射膜としても機能する。液晶表示装置10が半透過型や反射型である場合、遮光膜52は、反射電極としての画素電極24と同一層上に形成することができる。これにより、製造工程数の増加を抑えることが可能となる。なお、液晶表示装置10が透過型であっても、遮光膜52は形成することができる。 When the liquid crystal display device 10 is a transflective type or a reflective type, the light shielding film 52 also functions as a reflective film. When the liquid crystal display device 10 is a transflective type or a reflective type, the light shielding film 52 can be formed on the same layer as the pixel electrode 24 as a reflective electrode. Thereby, it becomes possible to suppress the increase in the number of manufacturing processes. Even if the liquid crystal display device 10 is a transmissive type, the light shielding film 52 can be formed.
 遮光膜52は、図2に一点鎖線で示すように、基板32の平面視において、フォトダイオード26を覆うように形成されている。これにより、バックライト14の光が、対向基板18側からフォトダイオード26に入射するのを防止している。 The light shielding film 52 is formed so as to cover the photodiode 26 in a plan view of the substrate 32 as indicated by a one-dot chain line in FIG. Thereby, the light of the backlight 14 is prevented from entering the photodiode 26 from the counter substrate 18 side.
 遮光膜52の幅寸法(アクティブマトリクス基板16の列方向での寸法)は、アクティブマトリクス基板16の行方向に延びる2本の配線RST,RWSの離隔距離よりも大きいほうが好ましい。配線RST,RWSが遮光膜52よりも下層(基板32側)に形成されていれば、基板32の平面視において、遮光膜52の幅方向一方の端縁部が一方の配線RSTに重なり、遮光膜52の幅方向他方の端縁部が他方の配線RWSに重なる。さらに、配線RST,RWSが半導体膜34よりも上層(液晶層20側)に形成されていれば、配線RST,RWSを利用して、バックライト14からの光を遮光することができる。アクティブマトリクス基板16の列方向において、遮光膜52を必要以上に大きくする必要がなくなる。 The width dimension (dimension in the column direction of the active matrix substrate 16) of the light shielding film 52 is preferably larger than the separation distance between the two wirings RST and RWS extending in the row direction of the active matrix substrate 16. If the wirings RST and RWS are formed below the light shielding film 52 (on the side of the substrate 32), one end portion in the width direction of the light shielding film 52 overlaps with the one wiring RST in the plan view of the substrate 32. The other edge in the width direction of the film 52 overlaps the other wiring RWS. Furthermore, if the wirings RST and RWS are formed above the semiconductor film 34 (on the liquid crystal layer 20 side), the light from the backlight 14 can be blocked using the wirings RST and RWS. In the column direction of the active matrix substrate 16, it is not necessary to make the light shielding film 52 larger than necessary.
 上記2本の配線RST,RWSのうち、一方の配線RSTは、リセット信号を供給するための配線であり、フォトダイオード26のp型半導体領域34pに接続されている(図4参照)。他方の配線RWSは、読み出し信号を供給するための配線であり、液晶表示装置10の光センサ部が備える蓄積容量Cintの一方の電極に接続されている(図4参照)。 Of the two wirings RST and RWS, one wiring RST is a wiring for supplying a reset signal, and is connected to the p-type semiconductor region 34p of the photodiode 26 (see FIG. 4). The other wiring RWS is a wiring for supplying a readout signal, and is connected to one electrode of the storage capacitor Cint included in the optical sensor unit of the liquid crystal display device 10 (see FIG. 4).
 遮光膜52の長さ寸法(アクティブマトリクス基板16の行方向での寸法)は、フォトダイオード26の長さ寸法(アクティブマトリクス基板16の行方向での寸法)と略同じ大きさであっても良いが、アクティブマトリクス基板16の行方向で隣り合う二本のソース線SL,SLの離隔距離よりも大きいほうが好ましい。ソース線SL,SLが遮光膜52よりも下層(基板32側)に形成されていると、遮光膜52の長さ寸法がアクティブマトリクス基板16の行方向で隣り合う二本のソース線SL,SLの離隔距離よりも大きい場合に、遮光膜52の長さ方向一方の端縁部が一方のソース線SLに重なり、遮光膜52の長さ方向他方の端縁部が他方のソース線SLに重なる。さらに、ソース線SL,SLが半導体膜34よりも上層(液晶層20側)に形成されていれば、ソース線SLを利用して、バックライト14からの光を遮光することができる。このようにして、バックライト14からの光を遮光する場合、複数の遮光膜52を用いて、一つのフォトダイオード26を遮光することができる。 The length dimension of the light shielding film 52 (dimension in the row direction of the active matrix substrate 16) may be substantially the same as the length dimension of the photodiode 26 (dimension in the row direction of the active matrix substrate 16). However, it is preferable that the distance is larger than the distance between two source lines SL and SL adjacent in the row direction of the active matrix substrate 16. If the source lines SL and SL are formed below the light shielding film 52 (on the substrate 32 side), the length of the light shielding film 52 is adjacent to the two source lines SL and SL in the row direction of the active matrix substrate 16. Is longer than the separation distance, the one edge in the length direction of the light shielding film 52 overlaps with one source line SL, and the other edge in the length direction of the light shielding film 52 overlaps with the other source line SL. . Furthermore, if the source lines SL and SL are formed in an upper layer (the liquid crystal layer 20 side) than the semiconductor film 34, the light from the backlight 14 can be shielded using the source line SL. In this way, when the light from the backlight 14 is shielded, one photodiode 26 can be shielded by using the plurality of light shielding films 52.
 このようなアクティブマトリクス基板16の表示領域(複数の画素22が形成されている領域)に対向して、対向基板18が配置されている。対向基板18は、アクティブマトリクス基板16において複数の画素22が形成されている面側に配置されている。 The counter substrate 18 is disposed so as to face the display area of the active matrix substrate 16 (the area where the plurality of pixels 22 are formed). The counter substrate 18 is disposed on the side of the active matrix substrate 16 where the plurality of pixels 22 are formed.
 対向基板18は、図3に示されているように、基板54を備えている。基板54としては、例えば、低アルカリガラス基板や石英基板を採用することができる。 The counter substrate 18 includes a substrate 54 as shown in FIG. As the substrate 54, for example, a low alkali glass substrate or a quartz substrate can be adopted.
 基板54上には、カラーフィルタ56と、対向電極58とが、この順番で積層されている。 A color filter 56 and a counter electrode 58 are laminated on the substrate 54 in this order.
 カラーフィルタ56には、図示はしていないが、青色の着色層と、緑色の着色層と、赤色の着色層とが、形成されている。隣り合う着色層間には、ブラックマトリクス(図示せず)が形成されている。 Although not shown, the color filter 56 includes a blue colored layer, a green colored layer, and a red colored layer. A black matrix (not shown) is formed between adjacent colored layers.
 対向電極58は、カラーフィルタを覆うように形成されている。対向電極58としては、例えば、例えば、ITO(インジウム錫酸化物)膜等を採用することができる。 The counter electrode 58 is formed so as to cover the color filter. As the counter electrode 58, for example, an ITO (indium tin oxide) film or the like can be employed.
 アクティブマトリクス基板16と対向基板18との間には、液晶層20が封入されている。液晶の動作モードとしては、例えば、TN(twisted nematic)モード等を採用することができる。 A liquid crystal layer 20 is sealed between the active matrix substrate 16 and the counter substrate 18. As an operation mode of the liquid crystal, for example, a TN (twisted nematic) mode or the like can be adopted.
 このような液晶パネル12を対向基板18側から照らすようにして、バックライト14が配置されている。バックライト14としては、例えば、直下型やエッジライト型,平面光源型等を採用することができる。バックライト14の光源としては、例えば、冷陰極管や発光ダイオード(LED)等を採用することができる。 The backlight 14 is arranged so as to illuminate such a liquid crystal panel 12 from the counter substrate 18 side. As the backlight 14, for example, a direct type, an edge light type, a planar light source type, or the like can be adopted. As a light source of the backlight 14, a cold cathode tube, a light emitting diode (LED), etc. are employable, for example.
 このような液晶表示装置10の光センサ部の等価回路図を、図4に示す。光センサ部は、フォトダイオード26と、蓄積容量Cintと、読み出し用薄膜トランジスタ30とを備えている。フォトダイオード26のp型半導体領域34pには、前述のように、配線RSTが接続されている。フォトダイオード26のn型半導体領域34nには、蓄積容量Cintの他方の電極と、読み出し用薄膜トランジスタ30のゲート電極とが接続されている。蓄積容量Cintの一方の電極には、前述のように、配線RWSが接続されている。読み出し用薄膜トランジスタ30のソース領域には、定電圧を供給するための定電圧源VDDが接続されている。読み出し用薄膜トランジスタ30のドレイン領域には、フォトダイオード26の出力電圧(センサ信号)を取り出すための配線VOUTが接続されている。なお、図4において、VAとは、フォトダイオード26のアノード側(フォトダイオード26のp型半導体領域34p側)の電位であり、VCとは、フォトダイオード26のカソード側(フォトダイオード26のn型半導体領域34n側)の電位であり、VLSとは、遮光膜52の電位である。 FIG. 4 shows an equivalent circuit diagram of the optical sensor unit of such a liquid crystal display device 10. The optical sensor unit includes a photodiode 26, a storage capacitor Cint, and a readout thin film transistor 30. The wiring RST is connected to the p-type semiconductor region 34p of the photodiode 26 as described above. The other electrode of the storage capacitor Cint and the gate electrode of the readout thin film transistor 30 are connected to the n-type semiconductor region 34n of the photodiode 26. As described above, the wiring RWS is connected to one electrode of the storage capacitor Cint. A constant voltage source VDD for supplying a constant voltage is connected to the source region of the read thin film transistor 30. A wiring VOUT for taking out the output voltage (sensor signal) of the photodiode 26 is connected to the drain region of the reading thin film transistor 30. In FIG. 4, VA is a potential on the anode side of the photodiode 26 (on the p-type semiconductor region 34p side of the photodiode 26), and VC is a cathode side of the photodiode 26 (n-type of the photodiode 26). The VLS is the potential of the light shielding film 52.
 このような光センサ部においては、リセット信号及び読み出し信号を所定のタイミングで供給することにより、フォトダイオード26での受光量に応じたセンサ信号(フォトダイオード26の出力電圧)を得ることができる。 In such an optical sensor unit, a sensor signal (output voltage of the photodiode 26) corresponding to the amount of light received by the photodiode 26 can be obtained by supplying a reset signal and a readout signal at a predetermined timing.
 具体的には、先ず、ハイレベルのリセット信号が配線RSTに供給されると、リセット期間が開始される。なお、リセット期間中においては、ローレベルの読み出し信号が配線RWSに供給されている。 Specifically, first, when a high-level reset signal is supplied to the wiring RST, the reset period starts. Note that a low-level read signal is supplied to the wiring RWS during the reset period.
 リセット期間において、フォトダイオード26には、順方向電流が流れる。その結果、蓄積ノード60の電位がリセットされる。なお、蓄積ノード60とは、蓄積容量Cintと、フォトダイオード26のn型半導体領域34nと、読み出し用薄膜トランジスタ30のゲート電極との接続点である。 During the reset period, a forward current flows through the photodiode 26. As a result, the potential of the storage node 60 is reset. The storage node 60 is a connection point between the storage capacitor Cint, the n-type semiconductor region 34n of the photodiode 26, and the gate electrode of the read thin film transistor 30.
 ローレベルのリセット信号が配線RSTに供給されると、リセット期間が終了する。リセット期間が終了したら、センシング期間が開始される。なお、センシング期間においては、ローレベルの読み出し信号が配線RWSに供給される。 When the low level reset signal is supplied to the wiring RST, the reset period ends. When the reset period ends, the sensing period starts. Note that in the sensing period, a low-level read signal is supplied to the wiring RWS.
 センシング期間において、フォトダイオード26には、逆バイアスが発生する。そして、フォトダイオード26に入射した光の量に応じて発生する光電流によって、蓄積ノード60の電位が変化する。 During the sensing period, a reverse bias is generated in the photodiode 26. Then, the potential of the storage node 60 is changed by the photocurrent generated according to the amount of light incident on the photodiode 26.
 ハイレベルの読み出し信号が配線RWSに供給されると、読み出し期間が開始される。なお、読み出し期間においては、ローレベルのリセット信号が配線RSTに供給されている。 When a high level read signal is supplied to the wiring RWS, a read period is started. Note that in the reading period, a low-level reset signal is supplied to the wiring RST.
 読み出し期間においては、蓄積ノード60の電位が、蓄積容量Cintを介して、プルアップされる。プルアップされた蓄積ノード60の電位が、読み出し用薄膜トランジスタ30の閾値電圧を超えると、読み出し用薄膜トランジスタ30がON状態となり、センサ信号(フォトダイオード26の出力電圧)が出力される。 In the readout period, the potential of the storage node 60 is pulled up via the storage capacitor Cint. When the pulled-up potential of the storage node 60 exceeds the threshold voltage of the readout thin film transistor 30, the readout thin film transistor 30 is turned on and a sensor signal (output voltage of the photodiode 26) is output.
 このような動作を繰り返すことにより、センサ信号(フォトダイオード26の出力電圧)を得ることができる。 By repeating such an operation, a sensor signal (output voltage of the photodiode 26) can be obtained.
 ところで、半導体膜34と遮光膜52との間には、寄生容量Clsが形成されている。これにより、センシング期間においては、寄生容量Cls及び蓄積容量Cintが一定期間放電される。即ち、下式に示す関係から明らかなように、フォトダイオード26に入射した光の量に応じて発生する光電流(≒Q)が略一定であれば、寄生容量Cls及び蓄積容量Cintが小さい程、フォトダイオード26のカソード側(n型半導体領域34n側)の電位VC(蓄積ノード60の電位)が変化する量は大きくなる。
(数1)
Q=(Cls+Cint)×ΔVC
なお、上式において、ΔVCとは、フォトダイオード26のカソード側電位VCの変化量を示す。
Incidentally, a parasitic capacitance Cls is formed between the semiconductor film 34 and the light shielding film 52. Thereby, in the sensing period, the parasitic capacitance Cls and the storage capacitance Cint are discharged for a certain period. That is, as apparent from the relationship shown in the following equation, if the photocurrent (≈Q) generated according to the amount of light incident on the photodiode 26 is substantially constant, the smaller the parasitic capacitance Cls and the storage capacitance Cint, The amount of change in the potential VC (potential of the storage node 60) on the cathode side (n-type semiconductor region 34n side) of the photodiode 26 increases.
(Equation 1)
Q = (Cls + Cint) × ΔVC
In the above equation, ΔVC represents the amount of change in the cathode side potential VC of the photodiode 26.
 そこにおいて、読み出し用薄膜トランジスタ30をON状態にするには、読み出し用薄膜トランジスタ30のゲート電極に対して、所定の電圧を印加する必要がある。具体的には、下式の値をある一定の値に保つ必要がある。
(数2)
ΔVRW×Cint/(Cint+Cls)
 なお、上式において、ΔVRWとは、読み出し信号におけるハイレベルとローレベルの電位差(読み出し信号のパルスの高さ)である。
Therefore, in order to turn on the reading thin film transistor 30, it is necessary to apply a predetermined voltage to the gate electrode of the reading thin film transistor 30. Specifically, it is necessary to keep the value of the following formula at a certain value.
(Equation 2)
ΔVRW × Cint / (Cint + Cls)
Note that in the above equation, ΔVRW is a potential difference between the high level and the low level in the read signal (the pulse height of the read signal).
 従って、蓄積容量Cintを任意に変更することはできず、フォトダイオード26の出力電圧(センサ信号)を大きくするためには、寄生容量Clsを小さくする必要がある。 Therefore, the storage capacitor Cint cannot be arbitrarily changed, and in order to increase the output voltage (sensor signal) of the photodiode 26, it is necessary to reduce the parasitic capacitance Cls.
 そこにおいて、液晶表示装置10においては、バックライト14からの光を遮光する遮光膜52が平坦化膜50上に形成されており、下地層36上に形成されたフォトダイオード26(半導体膜34)との間には、ゲート絶縁膜38と、層間絶縁膜40と、平坦化膜50とが、存在する。これにより、遮光膜が基板32上に形成されている場合に比して、半導体膜34と遮光膜52との離隔距離を大きくすることができる。即ち、遮光膜が基板32上に形成されている場合においては、遮光膜とフォトダイオード26(半導体膜34)との間に存在する下地層36の膜厚を大きくすると、下地層36の応力により、基板32が反ってしまい、その後の製造工程が実施できなくなるという問題があったので、下地層36(絶縁膜)の膜厚を大きくして、遮光膜とフォトダイオード26(半導体膜34)との離隔距離を大きくすることが出来なかったのであるが、本実施形態においては、遮光膜52とフォトダイオード26(半導体膜34)との間に存在する絶縁膜(ゲート絶縁膜38,層間絶縁膜40及び平坦化膜50)の膜厚を大きくしても、上述のような膜の応力に起因する不具合の発生を回避することができるので、絶縁膜(ゲート絶縁膜38,層間絶縁膜40及び平坦化膜50)の膜厚を大きくして、遮光膜52とフォトダイオード26(半導体膜34)との離隔距離を大きくすることができる。その結果、半導体膜34と遮光膜52との間に形成される寄生容量Clsを小さくすることが可能となる。なお、このことから明らかなように、本実施形態では、ゲート絶縁膜38と、層間絶縁膜40と、平坦化膜50とによって、絶縁膜が実現されている。 Therefore, in the liquid crystal display device 10, a light shielding film 52 that shields light from the backlight 14 is formed on the planarizing film 50, and the photodiode 26 (semiconductor film 34) formed on the base layer 36. Between the gate insulating film 38, the gate insulating film 38, the interlayer insulating film 40, and the planarizing film 50 exist. Thereby, the separation distance between the semiconductor film 34 and the light shielding film 52 can be increased as compared with the case where the light shielding film is formed on the substrate 32. That is, in the case where the light shielding film is formed on the substrate 32, if the thickness of the foundation layer 36 existing between the light shielding film and the photodiode 26 (semiconductor film 34) is increased, the stress of the foundation layer 36 Since the substrate 32 is warped and the subsequent manufacturing process cannot be performed, the thickness of the base layer 36 (insulating film) is increased, and the light shielding film and the photodiode 26 (semiconductor film 34) are formed. However, in this embodiment, the insulating film (gate insulating film 38, interlayer insulating film) existing between the light shielding film 52 and the photodiode 26 (semiconductor film 34) is not able to be increased. 40 and the planarizing film 50) can be prevented from causing the above-described problems caused by the stress of the film, so that the insulating films (gate insulating film 38, interlayer insulating film 4) can be avoided. And by increasing the thickness of the flattening film 50), it is possible to increase the distance between the light shielding film 52 and the photodiode 26 (semiconductor film 34). As a result, the parasitic capacitance Cls formed between the semiconductor film 34 and the light shielding film 52 can be reduced. As is clear from this, in the present embodiment, an insulating film is realized by the gate insulating film 38, the interlayer insulating film 40 and the planarizing film 50.
 因みに、表1には、本実施形態と従来構成の寄生容量(フォトダイオードと遮光膜との間に形成される寄生容量)が示されている。従来構成とは、遮光膜52が基板32上に形成されている構成である。即ち、従来構成では、フォトダイオード26(半導体膜34)と遮光膜52との間には、下地層36だけが存在している。従来構成において、下地層36は、窒化シリコン膜と酸化シリコン膜とが積層されたものである。なお、表1には、寄生容量の他に、フォトダイオード26(半導体膜34)と遮光膜52との間に存在する膜の種類、各膜の比誘電率及び各膜の膜厚も示されている。 Incidentally, Table 1 shows the parasitic capacitance (parasitic capacitance formed between the photodiode and the light shielding film) of the present embodiment and the conventional configuration. The conventional configuration is a configuration in which the light shielding film 52 is formed on the substrate 32. In other words, in the conventional configuration, only the base layer 36 exists between the photodiode 26 (semiconductor film 34) and the light shielding film 52. In the conventional configuration, the base layer 36 is formed by laminating a silicon nitride film and a silicon oxide film. In addition to the parasitic capacitance, Table 1 also shows the type of film existing between the photodiode 26 (semiconductor film 34) and the light shielding film 52, the relative dielectric constant of each film, and the film thickness of each film. ing.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
 表1から明らかなように、本実施形態においては、従来構成に比して、寄生容量の大きさを1/10程度にすることができる。 As is clear from Table 1, in this embodiment, the parasitic capacitance can be reduced to about 1/10 as compared with the conventional configuration.
 従って、液晶表示装置10においては、フォトダイオード26の出力電圧(センサ信号)を大きくすることができる。その結果、フォトダイオード26の感度を向上させることが可能となる。 Therefore, in the liquid crystal display device 10, the output voltage (sensor signal) of the photodiode 26 can be increased. As a result, the sensitivity of the photodiode 26 can be improved.
 特に本実施形態では、基板32の平面視において、画素電極24がフォトダイオード26と重ならない位置に形成されている。これにより、画素電極24とフォトダイオード26(半導体膜34)との間に寄生容量が形成されるのを回避することができる。 Particularly in the present embodiment, the pixel electrode 24 is formed at a position where it does not overlap the photodiode 26 in the plan view of the substrate 32. Thereby, it is possible to avoid the formation of parasitic capacitance between the pixel electrode 24 and the photodiode 26 (semiconductor film 34).
 また、本実施形態では、フォトダイオード26(半導体膜34)と遮光膜52との間において、ゲート絶縁膜38と、層間絶縁膜40と、平坦化膜50とが存在していると共に、基板32の平面視において、画素電極24がフォトダイオード26と重ならない位置に形成されている。これにより、画素電極24及び遮光膜52のフォトダイオード26への悪影響を小さくすることができる。即ち、フォトダイオード26(半導体膜34)と電極(画素電極や遮光膜)との間に絶縁膜が存在する構成においては、絶縁膜の膜厚や膜質が変化した場合に、フォトダイオードの特性が変化してしまう問題(いわゆる電極のゲート作用)があるが、本実施形態では、このような問題を回避することができる。 In the present embodiment, the gate insulating film 38, the interlayer insulating film 40, and the planarizing film 50 exist between the photodiode 26 (semiconductor film 34) and the light shielding film 52, and the substrate 32. The pixel electrode 24 is formed at a position where it does not overlap the photodiode 26 in plan view. Thereby, the adverse effect of the pixel electrode 24 and the light shielding film 52 on the photodiode 26 can be reduced. That is, in a configuration in which an insulating film exists between the photodiode 26 (semiconductor film 34) and an electrode (pixel electrode or light shielding film), the characteristics of the photodiode change when the thickness or quality of the insulating film changes. Although there is a problem of changing (so-called electrode gate action), this embodiment can avoid such a problem.
 また、本実施形態においては、半導体膜34がポリシリコン膜とされている。ポリシリコン膜の形成方法として、プラズマCVDやスパッタ等で下地層36上に形成されたアモルファスシリコン膜にエキシマレーザーを照射する方法が採用されている場合、ポリシリコン膜の厚さを十分に大きくすることができないので、フォトダイオード26の受光量に応じて発生する光電流は元々小さいが、本実施形態では、フォトダイオード26の出力電圧を大きくすることができるので、発生する光電流が小さくても検出することができる。 In the present embodiment, the semiconductor film 34 is a polysilicon film. When a method of irradiating an excimer laser to an amorphous silicon film formed on the underlayer 36 by plasma CVD, sputtering, or the like is employed as a method for forming a polysilicon film, the thickness of the polysilicon film is sufficiently increased. Therefore, although the photocurrent generated according to the amount of light received by the photodiode 26 is originally small, in this embodiment, the output voltage of the photodiode 26 can be increased, so even if the generated photocurrent is small. Can be detected.
 また、本実施形態においては、フォトダイオード26の感度が向上している。その結果、採用するフォトダイオード26の数を少なくして、液晶パネル12の透過率を向上させることができる。 In the present embodiment, the sensitivity of the photodiode 26 is improved. As a result, the number of photodiodes 26 to be employed can be reduced and the transmittance of the liquid crystal panel 12 can be improved.
 また、本実施形態においては、フォトダイオード26の感度が向上している。その結果、採用するフォトダイオード26の数を多くして、解像度を向上させることができる。 In the present embodiment, the sensitivity of the photodiode 26 is improved. As a result, the number of photodiodes 26 to be employed can be increased and the resolution can be improved.
 [実施形態の応用例]
 前記実施形態において、カラーフィルタ56をアクティブマトリクス基板16側に設けるようにしても良い。これにより、カラースキャナやIR(赤外線)方式のタッチパネルとして、液晶表示装置を利用することができる。
[Application example of embodiment]
In the embodiment, the color filter 56 may be provided on the active matrix substrate 16 side. Accordingly, the liquid crystal display device can be used as a color scanner or an IR (infrared) touch panel.
 カラーフィルタ56をアクティブマトリクス基板16側に設ける場合、例えば、図5に示すように、基板32上にカラーフィルタ56を形成するようにしても良い。図5においては、カラーフィルタ56がオーバーコート膜62によって覆われており、このオーバーコート膜62を覆うようにして、下地層36が形成されている。オーバーコート膜62としては、酸化シリコン膜や窒化シリコン膜等を採用することができる。オーバーコート膜62の膜厚は、1000~3000nmである。なお、オーバーコート膜62と下地層36を同じ膜で構成しても良い。 When the color filter 56 is provided on the active matrix substrate 16 side, for example, the color filter 56 may be formed on the substrate 32 as shown in FIG. In FIG. 5, the color filter 56 is covered with an overcoat film 62, and the base layer 36 is formed so as to cover the overcoat film 62. As the overcoat film 62, a silicon oxide film, a silicon nitride film, or the like can be employed. The film thickness of the overcoat film 62 is 1000 to 3000 nm. Note that the overcoat film 62 and the base layer 36 may be formed of the same film.
 或いは、図6に示すように、カラーフィルタ56が形成されたカラーフィルタ基板64を別途用意し、このカラーフィルタ基板64をアクティブマトリクス基板16に対して外側から貼り付けるようにしても良い。カラーフィルタ基板64においては、基板66上に形成されたカラーフィルタ56がオーバーコート膜62で覆われている。基板66としては、例えば、ガラス基板やアクリル基板等を採用することができる。 Alternatively, as shown in FIG. 6, a color filter substrate 64 on which the color filter 56 is formed may be prepared separately, and the color filter substrate 64 may be attached to the active matrix substrate 16 from the outside. In the color filter substrate 64, the color filter 56 formed on the substrate 66 is covered with the overcoat film 62. As the substrate 66, for example, a glass substrate or an acrylic substrate can be employed.
 以上、本発明の実施形態について、詳述してきたが、これらはあくまでも例示であって、本発明は、上述の実施形態によって、何等、限定されない。 As mentioned above, although embodiment of this invention has been explained in full detail, these are illustrations to the last and this invention is not limited at all by the above-mentioned embodiment.
 例えば、前記実施形態において、各画素22として、赤色画素22r,緑色画素22g及び青色画素22bの他に、黄色画素を備えるものを採用しても良い。 For example, in the above-described embodiment, each pixel 22 may include a yellow pixel in addition to the red pixel 22r, the green pixel 22g, and the blue pixel 22b.

Claims (14)

  1.  アクティブマトリクス基板と、
     前記アクティブマトリクス基板に対向して配置された対向基板と、
     前記アクティブマトリクス基板と前記対向基板との間に封入された液晶層と、
     前記対向基板に対して、前記アクティブマトリクス基板側とは反対側に配置されたバックライトとを備え、
     前記アクティブマトリクス基板は、
     ベース基板と、
     前記ベース基板よりも前記液晶層側に形成されて、n型半導体領域と真性半導体領域とp型半導体領域とを有する半導体膜を備えるフォトダイオードと、
     前記フォトダイオードを覆う絶縁膜と、
     前記絶縁膜上に形成されて、前記バックライトの光が前記フォトダイオードへ入射するのを防ぐ遮光膜と
    を備える、液晶表示装置。
    An active matrix substrate;
    A counter substrate disposed opposite to the active matrix substrate;
    A liquid crystal layer sealed between the active matrix substrate and the counter substrate;
    A backlight disposed on the opposite side of the counter substrate with respect to the active matrix substrate side,
    The active matrix substrate is
    A base substrate;
    A photodiode including a semiconductor film formed on the liquid crystal layer side of the base substrate and having an n-type semiconductor region, an intrinsic semiconductor region, and a p-type semiconductor region;
    An insulating film covering the photodiode;
    A liquid crystal display device comprising: a light shielding film that is formed on the insulating film and prevents light from the backlight from entering the photodiode.
  2.  前記アクティブマトリクス基板は、
     前記フォトダイオードよりも前記液晶層側であって、且つ、前記遮光膜よりも前記ベース基板側に形成された配線をさらに備え、
     前記ベース基板を正面から見たときに、前記遮光膜が前記配線に重なる、請求項1に記載の液晶表示装置。
    The active matrix substrate is
    It further includes wiring formed on the liquid crystal layer side of the photodiode and on the base substrate side of the light shielding film,
    The liquid crystal display device according to claim 1, wherein the light-shielding film overlaps the wiring when the base substrate is viewed from the front.
  3.  前記配線が前記アクティブマトリクス基板の行方向に延びる第1配線である、請求項2に記載の液晶表示装置。 3. The liquid crystal display device according to claim 2, wherein the wiring is a first wiring extending in a row direction of the active matrix substrate.
  4.  前記第1配線が前記アクティブマトリクス基板の列方向に並んで複数形成されており、
     前記アクティブマトリクス基板を正面から見たときに、前記アクティブマトリクス基板の列方向で隣り合う2つの前記第1配線の間に、前記フォトダイオードが位置する、請求項3に記載の液晶表示装置。
     
    A plurality of the first wirings are formed side by side in the column direction of the active matrix substrate;
    4. The liquid crystal display device according to claim 3, wherein, when the active matrix substrate is viewed from the front, the photodiode is positioned between two first wirings adjacent in the column direction of the active matrix substrate. 5.
  5.  前記配線が前記アクティブマトリクス基板の列方向に延びる第2配線である、請求項2~4の何れか1項に記載の液晶表示装置。 The liquid crystal display device according to any one of claims 2 to 4, wherein the wiring is a second wiring extending in a column direction of the active matrix substrate.
  6.  前記第2配線が前記アクティブマトリクス基板の行方向に並んで複数形成されており、
     前記アクティブマトリクス基板を正面から見たときに、前記アクティブマトリクス基板の行方向で隣り合う2つの前記第2配線の間に、前記フォトダイオードが位置する、請求項5に記載の液晶表示装置。
    A plurality of the second wirings are formed side by side in the row direction of the active matrix substrate;
    The liquid crystal display device according to claim 5, wherein the photodiode is positioned between two second wirings adjacent in the row direction of the active matrix substrate when the active matrix substrate is viewed from the front.
  7.  前記アクティブマトリクス基板は、
     前記アクティブマトリクス基板を正面から見たときに、前記フォトダイオードとは異なる位置に形成された画素電極をさらに備える、請求項1~6の何れか1項に記載の液晶表示装置。
    The active matrix substrate is
    7. The liquid crystal display device according to claim 1, further comprising a pixel electrode formed at a position different from the photodiode when the active matrix substrate is viewed from the front.
  8.  前記画素電極が特定の方向に並んで複数形成されており、
     前記アクティブマトリクス基板を正面から見たときに、前記フォトダイオードが複数の前記画素電極の隣に位置し、
     前記n型半導体領域と、前記真性半導体領域と、前記p型半導体領域とが、前記特定の方向と直交する方向に並んでいる、請求項7に記載の液晶表示装置。
    A plurality of the pixel electrodes are formed side by side in a specific direction,
    When the active matrix substrate is viewed from the front, the photodiode is located next to the plurality of pixel electrodes,
    The liquid crystal display device according to claim 7, wherein the n-type semiconductor region, the intrinsic semiconductor region, and the p-type semiconductor region are arranged in a direction orthogonal to the specific direction.
  9.  前記画素電極が反射電極であり、
     前記遮光膜が前記反射電極と同じ層に形成されている、請求項7又は8に記載の液晶表示装置。
    The pixel electrode is a reflective electrode;
    The liquid crystal display device according to claim 7, wherein the light shielding film is formed in the same layer as the reflective electrode.
  10.  前記半導体膜が低温ポリシリコン膜である、請求項1~9の何れか1項に記載の液晶表示装置。 The liquid crystal display device according to any one of claims 1 to 9, wherein the semiconductor film is a low-temperature polysilicon film.
  11.  カラーフィルタをさらに備える、請求項1~10の何れか1項に記載の液晶表示装置。 The liquid crystal display device according to any one of claims 1 to 10, further comprising a color filter.
  12.  前記カラーフィルタが、前記フォトダイオードに対して、前記遮光膜とは反対側に位置する、請求項11に記載の液晶表示装置。 The liquid crystal display device according to claim 11, wherein the color filter is located on a side opposite to the light shielding film with respect to the photodiode.
  13.  前記アクティブマトリクスが前記カラーフィルタをさらに備え、
     前記カラーフィルタが、前記ベース基板よりも前記液晶層側であって、且つ、前記フォトダイオードよりも前記ベース基板側に形成されている、請求項12に記載の液晶表示装置。
    The active matrix further comprises the color filter;
    The liquid crystal display device according to claim 12, wherein the color filter is formed closer to the liquid crystal layer than the base substrate and closer to the base substrate than the photodiode.
  14.  前記カラーフィルタを有するカラーフィルタ基板をさらに備え、
     前記アクティブマトリクス基板の前記液晶層側とは反対側の面に、前記カラーフィルタ基板が貼り付けられている、請求項12に記載の液晶表示装置。
    A color filter substrate having the color filter;
    The liquid crystal display device according to claim 12, wherein the color filter substrate is attached to a surface of the active matrix substrate opposite to the liquid crystal layer side.
PCT/JP2011/075956 2010-11-11 2011-11-10 Liquid crystal display device WO2012063910A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001066638A (en) * 1999-08-30 2001-03-16 Sony Corp Liquid crystal display device and its manufacture
WO2008044370A1 (en) * 2006-10-11 2008-04-17 Sharp Kabushiki Kaisha Liquid crystal display

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001066638A (en) * 1999-08-30 2001-03-16 Sony Corp Liquid crystal display device and its manufacture
WO2008044370A1 (en) * 2006-10-11 2008-04-17 Sharp Kabushiki Kaisha Liquid crystal display

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