WO2012062093A1 - 数据映射方法及装置 - Google Patents

数据映射方法及装置 Download PDF

Info

Publication number
WO2012062093A1
WO2012062093A1 PCT/CN2011/073839 CN2011073839W WO2012062093A1 WO 2012062093 A1 WO2012062093 A1 WO 2012062093A1 CN 2011073839 W CN2011073839 W CN 2011073839W WO 2012062093 A1 WO2012062093 A1 WO 2012062093A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
buffer
read
adjustment
buffers
Prior art date
Application number
PCT/CN2011/073839
Other languages
English (en)
French (fr)
Inventor
刘学斌
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2012062093A1 publication Critical patent/WO2012062093A1/zh

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/50Queue scheduling
    • H04L47/62Queue scheduling characterised by scheduling criteria
    • H04L47/621Individual queue per connection or flow, e.g. per VC

Definitions

  • BACKGROUND Optical Transport Network (abbreviated as ⁇ ) is a next-generation transport network.
  • G. 709 defines two modes for transmitting data in Synchronous Digital Hierarchy (SDH) using ⁇ transmission frames: Synchronous mode, Asynchronous mode.
  • Synchronous mode in the asynchronous mode, the OTN frame provides three adjustment control (JC) bytes, a negative adjustment opportunity (NJO) byte, and a positive adjustment opportunity (PJO) byte.
  • the adjustment control signal (JC) is located on the 1st to 3rd rows and 16th column, and its 7th and 8th bits are used to control the two adjustment opportunity bytes NJO and PJO.
  • CBR First Input First Output
  • FIFO First Input First Output
  • FIFO First Input First Output
  • a negative adjustment indication signal is generated when full.
  • the CBR signal must be operated in parallel within the chip.
  • the bit width is usually greater than one byte (8 bits), and the adjustment bytes are single bytes. In the related art, Single-byte adjustments are not implemented in circuits with multi-byte parallel processing.
  • a primary object of the present invention is to provide a data mapping scheme to at least solve the above problems.
  • a data mapping method including: writing fixed rate data CBR to a plurality of buffers, wherein the number of buffers and the number of bytes processed in parallel Similarly, the amount of data written to each buffer is the same; when reading data from the buffer according to the indication information, the data read from each of the buffers is continuously adjusted one by one or Negative adjustment
  • the indication information is used to indicate the amount of data stored in the buffer; and the data read after the positive adjustment or the negative adjustment is spliced to be mapped into the optical path payload unit OPUk data.
  • performing positive or negative adjustments on the data read from each of the buffers one by one includes: indicating, in the indication information, the When the data stored in the buffer exceeds the first threshold, when data is read from the buffer, the data read from each of the buffers is successively negatively adjusted one by one; When the information indicates that the data stored in the buffer is lower than the second threshold, when the data is read from the buffer, the data read from the buffer is continuously adjusted one by one. .
  • the splicing of the data after the positive adjustment or the negative adjustment is performed includes: splicing the data read after the positive adjustment or the negative adjustment according to the splicing indication information, wherein the splicing indication information is used to indicate that the splicing indication information is used for reading A buffer that has a positive or negative adjustment when data is present.
  • the method further includes: putting the data after the splicing into the payload area of the OPUk frame, and inserting the overhead. The number of bytes processed in parallel and the number of buffers are determined based on the data rate of the fixed rate data and the frequency of the processing clock.
  • a data mapping apparatus comprising: a plurality of buffers, set to buffer write fixed rate data CBR, the number of buffers and the number of bytes processed in parallel Similarly, and the amount of data written to each buffer is the same; a read/write controller is configured to read data from the buffer according to the indication information generated by the buffer, The data read in each buffer is continuously adjusted positively or negatively one by one, wherein the indication information is used to indicate the amount of data stored in the buffer; the data splicer is set to perform positive adjustment or The data read after the negative adjustment is spliced to be mapped into the optical path payload unit OPUk data.
  • the read/write controller is configured to, when the indication information indicates that the data stored in the buffer exceeds a first threshold, when reading data from the buffer, The data read in the device is continuously negatively adjusted one by one; and when the indication information indicates that the data stored in the buffer is lower than the second threshold, when reading data from the buffer, The data read in each of the buffers is continuously adjusted one by one.
  • the data splicer is configured to splicing data read after performing the positive adjustment or the negative adjustment according to the splicing indication information, where the splicing indication information is used to indicate that a positive adjustment or a negative adjustment occurs when the data is read. buffer.
  • the above apparatus further includes: an OPUk framer, configured to put the data after the splicing into the payload area of the OPUk frame, and insert the overhead.
  • the number of bytes processed in parallel and the number of buffers are determined based on the data rate of the fixed rate data and the frequency of the processing clock.
  • the fixed rate data CBR is written into a plurality of buffers, wherein the number of buffers is the same as the number of bytes processed in parallel, and the amount of data written to each buffer is the same;
  • the indication information continuously or positively adjusts data read from each buffer continuously when reading data from the buffer, wherein the indication information is used to indicate the amount of data stored in the buffer;
  • the data read after the positive adjustment or the negative adjustment is spliced to be mapped into the optical path payload unit OPUk data, which solves the problem that the single-byte adjustment is not implemented in the multi-byte parallel processing circuit in the related art. , realizes single-byte adjustment of multi-byte parallel processing circuit.
  • FIG. 2 is a schematic diagram of a data mapping apparatus according to an embodiment of the present invention
  • FIG. 3 is a preferred data mapping method according to an embodiment of the present invention. flow chart. BEST MODE FOR CARRYING OUT THE INVENTION
  • the present invention will be described in detail with reference to the accompanying drawings.
  • Step S102 Write fixed rate data CBR into multiple buffers, where The number of buffers is the same as the number of bytes processed in parallel, and the amount of data written to each buffer is the same;
  • Step S104 when data is read from the buffer according to the indication information, the data read from each buffer is continuously adjusted one by one or negatively adjusted, wherein the indication information is used to indicate the buffer.
  • Step S106 splicing the data read after the positive adjustment or the negative adjustment is performed to be mapped into the optical path payload unit OPUk data.
  • the same amount of buffers as the parallel processing bytes are used for buffering, and then the buffers are positively adjusted or negatively adjusted one by one, thereby solving the problem that the multi-byte parallel processing is not performed in the related art.
  • the problem of single-byte adjustments in the circuit Preferably, in implementation, a fast full or fast space indication (these indications may be collectively referred to as indication information) may be issued to control whether a positive adjustment or a negative adjustment is made. The judgment of fast or fast can be carried out according to the comparison of thresholds, and of course other methods can be used.
  • the manner of threshold comparison is exemplified below.
  • the indication information indicates that the data stored in the buffer exceeds the first threshold (for example, 80%)
  • the data read from each buffer is successively negatively performed when the data is read from the buffer.
  • Adjusting when the indication information indicates that the data stored in the buffer is lower than the second threshold (for example, 10%), the data read from each buffer is continuously read when the data is read from the buffer Make positive adjustments one by one.
  • the data read after the positive adjustment or the negative adjustment may be spliced according to the splicing indication information, wherein the splicing indication information is used to indicate a buffer that performs positive adjustment or negative adjustment when reading data. .
  • the number of bytes processed in parallel and the number of buffers may be determined according to the data rate of the fixed rate data and the frequency of the processing clock, for example, a data rate of 10 G, a processing clock of 311 M, and the number of bytes processed in parallel at this time.
  • the data of the buffer is 4; for example, if it is a rate of 10G, 155M clock processing, at this time, the number of bytes processed in parallel and the data of the buffer are both 8.
  • 2 is a schematic diagram of a data mapping apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes: a plurality of buffers, a read/write controller, and a data splicer, which are separately described below.
  • Multiple buffers set to buffer write fixed rate data CBR, the number of buffers is the same as the number of bytes processed in parallel, and the amount of data written to each buffer is the same; read and write controller, When the data is read from the buffer according to the indication information generated by the buffer, the data read from each buffer is continuously adjusted one by one or negatively adjusted, wherein the indication information is used to indicate the slowness In the punch The amount of data stored; the data splicer is configured to splicing the data read after the positive adjustment or the negative adjustment to be mapped into the optical path payload unit OPUk data.
  • the read/write controller is configured to continuously read data read from each buffer when the data stored in the buffer exceeds the first threshold when the indication information indicates that the data stored in the buffer exceeds the first threshold Negative adjustment is performed one by one; and when the data stored in the indication information indicating buffer is lower than the second threshold, the data read from each buffer is successively performed one by one when reading data from the buffer Positive adjustment.
  • the data splicer is configured to splicing data read after performing positive or negative adjustment according to the splicing indication information, wherein the splicing indication information is used to indicate a buffer that performs positive or negative adjustment when reading data. .
  • the splicing indication information is used to indicate a buffer that performs positive or negative adjustment when reading data.
  • the apparatus may further include: an OPUk framer, configured to put the data after the splicing into a payload area of the OPUk frame, and insert an overhead.
  • an OPUk framer configured to put the data after the splicing into a payload area of the OPUk frame, and insert an overhead.
  • the data buffer data buffer completes the conversion of data from the CBR clock domain to the OPUk clock domain.
  • N buffers are provided.
  • the CBR data is written into the buffer by the CBR reception recovery clock, and then read by the OPUk clock.
  • the receive recovery clock and the OPUk clock are an asynchronous clock
  • the read/write rate is different, and the state of the buffer may be indicated by a fast space or a fast full.
  • the fast or fast full state will trigger the positive or negative adjustment of OPUk, and the OPUk side will read less or read more data accordingly.
  • the write speed of each buffer is the same, and the read speed needs to be changed according to the buffer status.
  • the OPUk can only process one byte per adjustment, and the CBR write is not adjustable, the CBR writes N bytes at a fixed rate. Therefore, in order to prevent multiple buffers from independently adjusting the read speed, the state is disordered.
  • N OPUK frames This problem is solved by continuously adjusting N OPUK frames.
  • four buffers e.g., the four buffers are numbered 1, 2, 3, 4) are used to adjust the rate difference between CBR and OPUK.
  • the buffer data is read in the order of 1, 2, 3, and 4 (of course, it can be read in other orders). Since the four buffers have the same read and write speeds, when a negative adjustment occurs, the four buffers will generate an overflow alarm.
  • Read the No. 2 buffer once in position, and so on, and read the Nth buffer at the Nth NJO position.
  • Read and Write Controller In this embodiment, the system uses a read and write controller to control the read and write addresses of the various buffers. Since each buffer address differs when an adjustment occurs, it is required to control the read address based on the state of the buffer. The controller also generates a read enable signal for the buffer and generates a positive adjustment indication or a negative adjustment indication control data to select the splicer to operate properly.
  • the data output by the data splicer is in the order of 1 to N buffers, and no splicing operation is required. However, after the adjustment has taken place, the intervention of the splicing operation is required.
  • the negative adjustment taking the negative adjustment as an example, after the first adjustment occurs, the bytes read from the buffer No. 1 are placed at the position of the NJO, and then according to 2, 3 N, 1 The sequential assembly buffer data is placed in the OPUK frame payload area.
  • the second adjustment occurs, the bytes read from the buffer No. 2 are placed at the position of the NJO, and then the buffer data is assembled in the order of 3, 4 N, 1, and 2 into the OPUK frame. Payload area.
  • OPUk Framer uses the framer to sequentially put the data stream after the data splicer into the payload area of the OPUk frame, and then inserts some OPUk frames of the OPUk to form a reasonable OPUk frame.
  • 3 is a flow chart of a preferred data mapping method in accordance with an embodiment of the present invention, which is described below in conjunction with FIG.
  • the read buffer read empty read full indication if the buffer has the above fast or fast full indication, the PJO and NJO bytes are adjusted according to the indication, the number of loops in this step is the same as the above cached bytes.
  • the NJO or PJO byte is read, the read and write of the last buffer is adjusted, and then The splicing of the OPUk data frame finally determines whether all the buffers have been processed, and if not processed, returns a read buffer read empty read slow indication.
  • a 32-bit parallel CBR to OPUk mapping logic is written in the verilog language.
  • the data buffer module defines four 8-bit wide dual port rams.
  • the read and write of the dual port ram uses different clocks, the write direction unconditionally writes data to the ram, and the read direction reads data according to the payload position of the frame structure of the OPUk.
  • a ram fast (almost_empty) signal, an almost full (almost_fUll) signal, an overflow signal, and an underflow are generated according to the read/write address difference of the ram, and the above signal is used to indicate the state of the ram.
  • the ram will not overflow or underflow. It will only appear when the CBR signal rate deviates from the OPUk bit tolerance. At this time, the circuit will perform a reset operation on the ram.
  • the read/write control module reads and writes the status of the data buffer of the control module to generate various control signals.
  • a positive adjustment indication signal (pjojnd) is generated
  • a negative adjustment indication signal (njojnd) is generated.
  • the above method is used to control the operation of the data splicing module on NJO and PJO.
  • the control module generates a read enable of the data buffer based on the payload position indication signal and the buffer status of the OPUk frame structure. Normally, a read enable is generated at the payload location of the OPUk.
  • the PJO byte When a positive adjustment occurs, the PJO byte does not load the service data, prohibiting reading data from the data buffer; since the circuit is 4 bytes of parallel processing, the remaining three bytes of the PJO position still need to read the data load, so Only three buffer read enable signals are generated, and the read addresses of the three buffers are changed at the same time.
  • the NJO byte needs to read the buffer data, generate a buffer read enable signal at the NJO position, and change its read address. Such an operation is performed four times on different buffers one by one, each time emptying or reading one more buffer, completing one round of adjustment operations.
  • Data splicing module In this embodiment, the implementation of the data splicing module is divided into three cases: 1.
  • Adj_cnt the adjustment count state of the buffer
  • the data stitching of the NJO position follows the following adjustment rules: When there is no negative adjustment indication, the NJO position does not load the business data. When the buffer is in the fast full state (almost_fUll), the first negative adjustment indication is generated.
  • the data is not read; the first buffer has almost disappeared after the read operation (almost_full), but the others continue to generate negative adjustment indication signals.
  • the OPUk framing module designs a row and column counter, constructs an OPUk frame structure by the value of the row and column counter, and gives an indication of the JC and PSI overhead positions, an adjustment position indication, and a payload position indication. Framing module The data that has been spliced by these indications is filled in the payload area or the adjusted position, and the adjustment instruction inserts the correct JC overhead and inserts the PSI overhead.
  • the mapping of CBR fixed rate data to OPUk in the optical transport network can be effectively handled by the above embodiment.
  • modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

本发明公开了数据映射方法及装置,该方法包括:将固定速率数据CBR写入到多个缓冲器中,其中,缓冲器的数量与并行处理的字节数量相同,写入每个缓冲器的数据量相同;根据指示信息在从缓冲器中读取数据时,对从每个缓冲器中读取的数据连续逐一进行正调整或负调整,其中,指示信息用于指示缓冲器中存储数据的多少;对进行正调整或负调整之后读取的数据进行拼接,以映射成光通路净荷单元OPUk数据。通过本发明实现了多字节并行处理电路的单字节调整。

Description

数据映射方法^置 技术领域 本发明涉及通信领域, 具体而言, 涉及一种数据映射方法及装置。 背景技术 光传送网 ( Optical Transport Network , 简称为 ΟΤΝ ) 是下一代传送网络。
G. 709 定义了使用 ΟΤΝ 传输帧来传送同步数字体系 (Synchronous Digital Hierarchy, 简称为 SDH )数据的两种模式: 同步模式、 异步模式。 其中, 在异 步模式中, OTN帧提供了三个调整控制 (JC ) 字节、 一个负调整机会 (NJO ) 字节和一个正调整机会(PJO ) 字节。 调整控制信号 ( JC ) 位于第 1至 3行第 16列, 它的第 7位和第 8位用来控制两个调整机会字节 NJO和 PJO。 当客户 信号速率高于光通路净荷单元 ( Optical Channel Payload Unit, 简称为 OPU ) k 标称值时作负调整, NJO和 PJO为数据字节, 控制信号 JC为 01; 当客户信号 速率氏于 OPUk标称值时作正调整, NJO和 PJO应为调整字节, 控制信号 JC 为 11。 在相关技术中,通常使用专用芯片或 FPGA实现固定速率数据( Constant Bit
Rate, 简称为 CBR )到 OPUk的映射。 常用的办法是使用先进先出 ( First Input First Output , 简称为 FIFO ) 来完成, 才艮据 FIFO的快空快满状态来产生正负调 整指示, FIFO快空时产生正调整指示信号, FIFO快满时产生负调整指示信号。 但由于专用芯片和 FPGA内部的信号速率限制, 导致 CBR信号在芯片内部必 须是并行操作, 位宽通常是大于一个字节 (8bit ), 调整字节都是单字节, 在相 关技术中, 并没有在多字节并行处理的电路中实现单字节的调整。 发明内容 本发明的主要目的在于提供一种数据映射方案, 以至少解决上述问题。 才艮据本发明的一个方面, 提供了一种数据映射方法, 包括: 将固定速率数 据 CBR写入到多个緩冲器中, 其中, 所述緩冲器的数量与并行处理的字节数 量相同, 写入每个緩冲器的数据量相同; 根据指示信息在从所述緩冲器中读取 数据时, 对从所述每个緩冲器中读取的数据连续逐一进行正调整或负调整, 其 中, 所述指示信息用于指示所述緩冲器中存储数据的多少; 对进行正调整或负 调整之后读取的数据进行拼接, 以映射成光通路净荷单元 OPUk数据。 根据所述指示信息在从所述緩冲器中读取数据时, 对从所述每个緩冲器中 读取的数据连续逐一进行正调整或负调整包括: 在所述指示信息指示所述緩冲 器中存储的数据超出第一阈值时, 在从所述緩冲器中读取数据时, 对从所述每 个緩冲器中读取的数据连续逐一进行负调整; 在所述指示信息指示所述緩冲器 中存储的数据低于第二阈值时, 在从所述緩冲器中读取数据时, 对从所述每个 緩冲器中读取的数据连续逐一进行正调整。 对进行正调整或负调整之后读取的数据进行拼接包括: 根据拼接指示信息 对进行所述正调整或负调整之后读取的数据进行拼接, 其中, 所述拼接指示信 息用于指示在读取数据时发生正调整或负调整的緩冲器。 对进行正调整或负调整之后读取的数据进行拼接之后, 还包括: 将进行拼 接之后的数据放入 OPUk帧的净荷区, 并插入开销。 才艮据固定速率数据的数据速率和处理时钟的频率确定所述并行处理的字 节数量和所述緩冲器的数量。 根据本发明的另一方面, 还提供了一种数据映射装置, 包括: 多个緩冲器, 设置为緩存写入的固定速率数据 CBR,所述緩冲器的数量与并行处理的字节数 量相同, 并且, 写入每个緩冲器的数据量相同; 读写控制器, 设置为根据所述 緩冲器产生的指示信息在从所述緩冲器中读取数据时, 对从所述每个緩冲器中 读取的数据连续逐一进行正调整或负调整, 其中, 所述指示信息用于指示所述 緩冲器中存储数据的多少; 数据拼接器, 设置为对进行正调整或负调整之后读 取的数据进行拼接, 以映射成光通路净荷单元 OPUk数据。 所述读写控制器设置为在所述指示信息指示所述緩冲器中存储的数据超 出第一阈值时, 在从所述緩冲器中读取数据时, 对从所述每个緩冲器中读取的 数据连续逐一进行负调整; 并在所述指示信息指示所述緩冲器中存储的数据低 于第二阈值时, 在从所述緩冲器中读取数据时, 对从所述每个緩冲器中读取的 数据连续逐一进行正调整。 所述数据拼接器设置为根据拼接指示信息对进行所述正调整或负调整之 后读取的数据进行拼接, 其中, 所述拼接指示信息用于指示在读取数据时发生 正调整或负调整的緩冲器。 上述装置还包括: OPUk成帧器,设置为将进行拼接之后的数据放入 OPUk 帧的净荷区, 并插入开销。 所述并行处理的字节数量和所述緩冲器的数量是根据固定速率数据的数 据速率和处理时钟的频率确定的。 通过本发明, 釆用将固定速率数据 CBR写入到多个緩冲器中, 其中, 緩 冲器的数量与并行处理的字节数量相同, 写入每个緩冲器的数据量相同; 根据 指示信息在从緩冲器中读取数据时, 对从每个緩冲器中读取的数据连续逐一进 行正调整或负调整, 其中, 指示信息用于指示緩冲器中存储数据的多少; 对进 行正调整或负调整之后读取的数据进行拼接, 以映射成光通路净荷单元 OPUk 数据, 解决了在相关技术中没有在多字节并行处理的电路中实现单字节的调整 的问题, 实现了多字节并行处理电路的单字节调整。 附图说明 此处所说明的附图用来提供对本发明的进一步理解, 构成本申请的一部 分, 本发明的示意性实施例及其说明用于解释本发明, 并不构成对本发明的不 当限定。 在附图中: 图 1是根据本发明实施例的数据映射方法的流程图; 图 2是根据本发明实施例的数据映射装置的示意图; 图 3是根据本发明实施例优选的数据映射方法的流程图。 具体实施方式 下文中将参考附图并结合实施例来详细说明本发明。 需要说明的是, 在不 冲突的情况下, 本申请中的实施例及实施例中的特征可以相互组合。 图 1是根据本发明实施例的数据映射方法的流程图, 如图 1所示, 该流程 包括如下步骤: 步骤 S 102, 将固定速率数据 CBR写入到多个緩冲器中, 其中, 緩冲器的 数量与并行处理的字节数量相同, 写入每个緩冲器的数据量相同; 步骤 S 104,根据指示信息在从緩冲器中读取数据时, 对从每个緩冲器中读 取的数据连续逐一进行正调整或负调整, 其中, 指示信息用于指示緩冲器中存 储数据的多少; 步骤 S 106, 对进行正调整或负调整之后读取的数据进行拼接, 以映射成光 通路净荷单元 OPUk数据。 通过上述步骤, 釆用了与并行处理字节数量相同的緩冲器进行緩存, 然后 在对緩冲器进行逐一的正调整或负调整, 从而解决在相关技术中没有在多字节 并行处理的电路中实现单字节的调整的问题。 优选地, 在实施时, 可以发出快满或者快空指示 (这些指示可以统称为指 示信息), 来控制进行正调整或者负调整。 快满或者快空的判断可以根据阈值 比较的方式进行, 当然也可以釆用其他的方式。 下面对阈值比较的方式进行举 例说明。 在指示信息指示緩冲器中存储的数据超出第一阈值 (例如, 80% ) 时, 在 从緩冲器中读取数据时, 对从每个緩冲器中读取的数据连续逐一进行负调整; 在指示信息指示緩冲器中存储的数据低于第二阈值 (例如, 10% ) 时, 在从緩 冲器中读取数据时, 对从每个緩冲器中读取的数据连续逐一进行正调整。 优选地, 在拼接时, 可以根据拼接指示信息对进行正调整或负调整之后读 取的数据进行拼接, 其中, 拼接指示信息用于指示在读取数据时发生正调整或 负调整的緩冲器。 优选地, 可以才艮据固定速率数据的数据速率和处理时钟的频率确定并行处 理的字节数量和緩冲器的数量, 例如, 10G的数据速率, 311M处理时钟, 此 时并行处理的字节数量和緩冲器的数据均为 4; 又例如, 如果是 10G的速率, 155M时钟处理, 此时并行处理的字节数量和緩冲器的数据均为 8。 图 2是根据本发明实施例的数据映射装置的示意图, 如图 2所示, 该装置 包括: 多个緩冲器、 读写控制器、 数据拼接器, 下面对此进行分别说明。 多个緩冲器, 设置为緩存写入的固定速率数据 CBR, 緩冲器的数量与并行 处理的字节数量相同, 并且, 写入每个緩冲器的数据量相同; 读写控制器, 设 置为根据緩冲器产生的指示信息在从緩冲器中读取数据时, 对从每个緩冲器中 读取的数据连续逐一进行正调整或负调整, 其中, 指示信息用于指示緩冲器中 存储数据的多少; 数据拼接器, 设置为对进行正调整或负调整之后读取的数据 进行拼接, 以映射成光通路净荷单元 OPUk数据。 优选地, 读写控制器设置为在指示信息指示緩冲器中存储的数据超出第一 阈值时, 在从緩冲器中读取数据时, 对从每个緩冲器中读取的数据连续逐一进 行负调整; 并在指示信息指示緩冲器中存储的数据低于第二阈值时, 在从緩冲 器中读取数据时, 对从每个緩冲器中读取的数据连续逐一进行正调整。 优选地, 数据拼接器设置为根据拼接指示信息对进行正调整或负调整之后 读取的数据进行拼接, 其中, 拼接指示信息用于指示在读取数据时发生正调整 或负调整的緩冲器。 优选地, 如图 2所示, 该装置还可以包括: OPUk成帧器, 设置为将进行 拼接之后的数据放入 OPUk帧的净荷区, 并插入开销。 下面结合图 2中的装置对并行处理的字节数量和緩冲器的数量均为 4的优 选实施例进行说明。 数据緩冲器 数据緩冲器完成数据从 CBR时钟域到 OPUk时钟域的转换。 作为一个优 选的实施例, 若芯片内部按照 N个字节并行处理, 那么设置 N个緩冲器。 利 用 CBR接收恢复时钟向緩冲器内写入 CBR数据, 再利用 OPUk时钟读出。 在 上述过程中, 由于接收恢复时钟与 OPUk时钟是一个异步时钟, 读写速率不一 样, 緩冲器的状态会出现快空或者快满的指示。 快空或者快满状态都将会触发 OPUk 的正调整或负调整, OPUk侧会相应的少读出或者多读出一次数据。 每 个緩冲器的写入速度相同, 而读出速度则需根据緩冲器状态变化, 正常读写时 每次都是读写 N个字节。 由于 OPUk每次调整只能处理一个字节, 而 CBR写 入不可调节, CBR按固定速率写入 N个字节, 所以为防止多个緩冲器独立调 整读出速度造成状态混乱, 本实施例利用 N个 OPUK帧连续调整来解决这个 问题。 在本实施例中, 用到 4个緩冲器(例如, 这四个緩冲器的编号为 1、 2、 3、 4 )来调整 CBR与 OPUK的速率差。 緩冲器无溢出时, 緩冲器数据读出按照 1、 2、 3、 4的编号顺序 (当然也可以按照其他顺序来读取)。 由于 4个緩冲器读写 速度相同, 当发生负调整的时候, 4 个緩冲器都会产生溢出告警。 此时在第一 个 OPUK帧 NJO字节的位置上多读一次 1号緩冲器;在第二个 OPUK帧的 NJO 位置上读一次 2号緩冲器, 依次类推, 在第 N个 NJO位置上读一次第 N个緩 冲器。 其余时刻依然读写所有的緩冲器。 同样, 当正调整的时候, 只有 PJO位 置不能装载数据, 相应的数据緩冲器少读一个字节。 这样本实施例就完成 CBR 与 OPUK速率差的调整。 读写控制器 在本实施例中, 该系统用读写控制器来控制各个緩冲器的读写地址。 由于在发生调整时每个緩冲器地址会出现差异, 所以, 需要它根据緩冲器 的状态去控制读地址。 控制器还要产生緩冲器的读使能信号, 并且产生正调整 指示或负调整指示控制数据, 从而选择拼接器正确工作。 数据拼接器 在没发生调整之前, 数据拼接器输出的数据是按照 1至 N緩冲器的顺序, 无需拼接操作。 然而, 在发生调整之后, 在则需要拼接操作的介入。 在本实施例中, 以负调整为例, 当出现第一次调整后, 将从 1号緩冲器多 读出的字节放在 NJO的位置上发送, 然后按照 2、 3 N、 1的顺序拼装緩冲 器数据放入 OPUK帧净荷区。 当出现第二次调整后, 将从 2号緩冲器多读出的 字节放在 NJO的位置上发送, 然后按照 3、 4 N、 1、 2的顺序拼装緩冲器 数据放入 OPUK帧净荷区。 依次类推, 经过 N次调整, 数据拼接器恢复初始 状态。 同样, 当正调整的时候, 在 PJO位置跳过一个数据緩冲器, 改变其它緩 冲器的拼接顺序。 OPUk成帧器 在本实施例中, 系统使用成帧器依次把经过数据拼接器后的数据流放入 OPUk帧的净荷区, 再插入 OPUk的一些开销组成合理的 OPUk帧。 图 3是根据本发明实施例优选的数据映射方法的流程图, 下面结合图 3进 行说明。 首先, 读取緩冲读空读满指示, 若緩冲器有上述快空或快满指示, 则根据 指示进行对 PJO和 NJO字节进行调节, 此步骤循环次数与上述緩存字节数相 同, 当读到 NJO或 PJO字节时, 则调整对最后一个緩冲器的读写, 然后进行 OPUk数据帧的拼接, 最后判断是否处理完所有的緩冲器, 若没处理完, 则返 回读取緩冲读空读慢指示。 作为一个优选的实施例,这里,通过 verilog语言编写了一个 32位并行 CBR 到 OPUk的映射逻辑。 数据緩冲模块 定义四个 8bit宽度的双端口 ram。 其中, 双端口 ram的读写使用不同的时 钟, 写方向无条件向 ram里面写数据, 读方向根据 OPUk的帧结构的净荷位置 往外读数据。 另外根据 ram的读写地址差产生 ram快空( almost_empty )信号、 快满 ( almost_fUll ) 信号、 上溢 (overflow ) 信号和下溢 (underflow ), 上述信 号用于指示 ram的状态。在正常情况下, ram不会出现上溢或下溢,只有在 CBR 信号速率偏离 OPUk的比特容差时才会出现, 这时电路会对 ram做一个复位操 作。 读写控制模块 读写控制模块数据緩冲器的状态指示产生各种控制信号。 当有一个上述緩 冲器快空信号 (almost_empty )有效时, 则产生正调整指示信号 ( pjojnd ), 当 緩冲器快满信号 (almost_full )有效时产生, 则负调整指示信号 ( njojnd )。 用 上述方法来控制数据拼接模块对 NJO和 PJO的操作。 这里, 控制模块根据 OPUk帧结构的净荷位置指示信号和緩冲器状态产生 数据緩冲器的读使能。 正常情况下, 在 OPUk的净荷位置产生读使能。 当发生 正调整时, PJO字节不装载业务数据, 禁止从数据緩冲器读取数据; 由于电路 是 4个字节并行处理, PJO位置剩下三个字节仍需要读取数据装载, 因此只产 生 3个緩冲器的读取使能信号, 同时改变 3个緩冲器的读地址。 类似地, 当发 生负调整时, NJO字节需要读取緩冲器的数据, 在 NJO的位置产生 1个緩冲 器的读取使能信号, 同时改变其读地址。 这样的操作对不同的緩冲器逐一地做 4次, 每次空掉或多读取一个緩冲器, 完成一轮调整操作。 数据拼接模块 在本实施例中, 数据拼接模块的实现分三种情况: 1.净荷区的数据 (不含 PJO位置的数据)拼接、 2.PJO位置的数据拼接。 3.NJO位置的数据拼接。 在 这里, 以上三种情况都是通过判断緩冲器的调整计数状态 (adj_cnt, 即拼接指 示信息一种优选实施方式)来确定拼接的方式。 在无调整时 adj_cnt=0; 在发生 调整时 adj_cnt发生变化, 调整完毕后恢复成 adj_cnt=0。 其中, 净荷区的数据拼接遵循以下调整规则: 当 adj_cnt=0输出的净荷区 数据选择从緩冲器读取的数据 rd_data[31:0] (表示从第 31比特到第 0个比特); 当 adj_cnt=l输出的数据选择为 {rd_data[7:0],rd_data[31:8] }拼接而成的 4字节; 当 adj_cnt=2输出的数据选择为 {rd_data[15:0],rd_data[31 : 16]}拼接而成的 4 字 节; 当 adj_cnt=3输出的数据选择为 {rd_data[23:0],rd_data[3 l:24] }拼接而成的 4 字节;。 在本实施例中, PJO位置的数据拼接遵循以下调整规则: 无正调整指示时, PJO位置数据拼接方法与净荷区的数据拼接方法相同。 第一次正调整时, 设定 adj_cnt=l , PJO位置的低三个字节输出的数据选择从緩冲器读取的数据的高三 个字节緩冲器 _rd_data[31:8] , 剩下的一个字节由于没有 4号緩冲器读取使能信 号, 不会从緩冲器读出; 由于出现第一次正调整指示时仍然从緩冲器读取数据, 部分緩冲器仍处于快空状态( almost_empty ), 所以会继续产生第二次正调整指 示, 此时设定 adj_cnt=2, 拼接的组合为 {rd_data[7:0] , rd_data[31: 16] }, 同第一 次调整类似, 3 号緩冲器没有读取使能信号, 不会从緩冲器读出; 同理第三次 正调整, 此时设定 adj_cnt=3 , 拼接的组合为 { rd_data[ 15:0] ,rd_data[31:24] }; 同 理第四次正调整指示, 此时设定 adj_cnt=0, 拼接的组合为 rd_data[23:0] ; 至此 一个正调整循环结束实现了一次速率调整。 NJO位置的数据拼接遵循以下调整规则: 无负调整指示时, NJO位置不装 载业务数据。 当緩冲器出现快满状态 ( almost_fUll ) 时产生第一次负调整指示, 此时设定 adj_cnt=3 , NJO位置输出的数据选择从 rd_data[31:24] , 剩下的三个 緩冲器不读取数据; 第一个緩冲器经过这次读操作快满的状态 ( almost_full ) 已经消失, 但其他的还在继续产生负调整指示信号。 第二次负调整指示时, 设 定 adj_cnt=2, NJO字节输出的数据选择 rd_data[23: 16]。 第三次负调整指示时, 设定 adj_cnt=l , NJO字节输出的数据选择 rd_data[15:8]。 同理, 第四次负调整 指示时也是同样的操作,设定 adj_cnt=0, NJO字节输出的数据选择 rd_data[7:0]。 经过四次负调整后完成了一次负调整循环。
OPUk成帧模块 设计一个行列计数器, 通过行列计数器的值构建一个 OPUk的帧结构, 同 时给出 JC和 PSI开销位置的指示、 调整位置指示和净荷位置指示。 成帧模块 通过这些指示拼接过了的数据填入净荷区或调整位置, 并 居调整指示插入正 确的 JC开销和插入 PSI开销。 综上所述, 通过上述实施例可以有效地处理在光传送网中, CBR固定速率 数据到 OPUk的映射。 显然, 本领域的技术人员应该明白, 上述的本发明的各模块或各步骤可以 用通用的计算装置来实现, 它们可以集中在单个的计算装置上, 或者分布在多 个计算装置所组成的网络上, 可选地, 它们可以用计算装置可执行的程序代码 来实现, 从而, 可以将它们存储在存储装置中由计算装置来执行, 并且在某些 情况下, 可以以不同于此处的顺序执行所示出或描述的步骤, 或者将它们分别 制作成各个集成电路模块, 或者将它们中的多个模块或步骤制作成单个集成电 路模块来实现。 这样, 本发明不限制于任何特定的硬件和软件结合。 以上所述仅为本发明的优选实施例而已, 并不用于限制本发明, 对于本领 域的技术人员来说, 本发明可以有各种更改和变化。 凡在本发明的 ^"神和原则 之内, 所作的任何修改、 等同替换、 改进等, 均应包含在本发明的保护范围之 内。

Claims

权 利 要 求 书
1. 一种数据映射方法, 包括:
将固定速率数据 CBR写入到多个緩冲器中, 其中, 所述緩冲器的数 量与并行处理的字节数量相同, 写入每个緩冲器的数据量相同;
根据指示信息在从所述緩冲器中读取数据时, 对从所述每个緩冲器 中读取的数据连续逐一进行正调整或负调整, 其中, 所述指示信息用于 指示所述緩冲器中存储数据的多少;
对进行正调整或负调整之后读取的数据进行拼接, 以映射成光通路 净荷单元 OPUk数据。
2. 根据权利要求 1所述的方法, 其中, 根据所述指示信息在从所述緩冲器 中读取数据时, 对从所述每个緩冲器中读取的数据连续逐一进行正调整 或负调整包括:
在所述指示信息指示所述緩冲器中存储的数据超出第一阈值时, 在 从所述緩冲器中读取数据时, 对从所述每个緩冲器中读取的数据连续逐 一进行负调整;
在所述指示信息指示所述緩冲器中存储的数据低于第二阈值时, 在 从所述緩冲器中读取数据时, 对从所述每个緩冲器中读取的数据连续逐 一进行正调整。
3. 才艮据权利要求 1所述的方法, 其中, 对进行正调整或负调整之后读取的 数据进行拼接包括:
根据拼接指示信息对进行所述正调整或负调整之后读取的数据进行 拼接, 其中, 所述拼接指示信息用于指示在读取数据时发生正调整或负 调整的緩冲器。
4. 根据权利要求 1至 3中任一项所述的方法, 其中, 对进行正调整或负调 整之后读取的数据进行拼接之后, 还包括:
将进行拼接之后的数据放入 OPUk帧的净荷区, 并插入开销。
5. 根据权利要求 1至 3中任一项所述的方法, 其中, 根据固定速率数据的 数据速率和处理时钟的频率确定所述并行处理的字节数量和所述緩冲器 的数量。
6. —种数据映射装置, 包括:
多个緩冲器, 设置为緩存写入的固定速率数据 CBR, 所述緩冲器的 数量与并行处理的字节数量相同, 并且, 写入每个緩冲器的数据量相同; 读写控制器, 设置为根据所述緩冲器产生的指示信息在从所述緩冲 器中读取数据时, 对从所述每个緩冲器中读取的数据连续逐一进行正调 整或负调整, 其中, 所述指示信息用于指示所述緩冲器中存储数据的多 少;
数据拼接器, 设置为对进行正调整或负调整之后读取的数据进行拼 接, 以映射成光通路净荷单元 OPUk数据。
7. 根据权利要求 6所述的装置, 其中, 所述读写控制器设置为在所述指示 信息指示所述緩冲器中存储的数据超出第一阈值时, 在从所述緩冲器中 读取数据时, 对从所述每个緩冲器中读取的数据连续逐一进行负调整; 并在所述指示信息指示所述緩冲器中存储的数据低于第二阈值时, 在从 所述緩冲器中读取数据时, 对从所述每个緩冲器中读取的数据连续逐一 进行正调整。
8. 根据权利要求 6所述的装置, 其中, 所述数据拼接器设置为根据拼接指 示信息对进行所述正调整或负调整之后读取的数据进行拼接, 其中, 所 述拼接指示信息用于指示在读取数据时发生正调整或负调整的緩冲器。
9. 根据权利要求 6至 8中任一项所述的装置, 其中, 还包括:
OPUk成帧器, 设置为将进行拼接之后的数据放入 OPUk帧的净荷 区, 并插入开销'。
10. 根据权利要求 6至 8中任一项所述的装置, 其中, 所述并行处理的字节 数量和所述緩冲器的数量是根据固定速率数据的数据速率和处理时钟的 频率确定的。
PCT/CN2011/073839 2010-11-08 2011-05-09 数据映射方法及装置 WO2012062093A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2010105366001A CN101986621A (zh) 2010-11-08 2010-11-08 数据映射方法及装置
CN201010536600.1 2010-11-08

Publications (1)

Publication Number Publication Date
WO2012062093A1 true WO2012062093A1 (zh) 2012-05-18

Family

ID=43710925

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/073839 WO2012062093A1 (zh) 2010-11-08 2011-05-09 数据映射方法及装置

Country Status (2)

Country Link
CN (1) CN101986621A (zh)
WO (1) WO2012062093A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101986621A (zh) * 2010-11-08 2011-03-16 中兴通讯股份有限公司 数据映射方法及装置
CN102316391B (zh) * 2011-09-08 2018-02-09 中兴通讯股份有限公司 一种数据映射、解映射方法及系统
CN102932696B (zh) * 2012-09-29 2015-07-08 西安空间无线电技术研究所 一种星载高速数据复接器系统及实现方法
CN112564769B (zh) * 2020-11-30 2022-08-26 东方红卫星移动通信有限公司 多速率分级调节的低轨卫星高速通信方法、发射端及系统
CN112929765B (zh) * 2021-01-19 2023-05-12 赵晋玲 基于光传输网络的多业务传输方法、系统及存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6819725B1 (en) * 2000-08-21 2004-11-16 Pmc-Sierra, Inc. Jitter frequency shifting Δ-Σ modulated signal synchronization mapper
CN101384093A (zh) * 2008-09-28 2009-03-11 华为技术有限公司 业务数据映射方法和装置及复映射方法
CN101710853A (zh) * 2009-11-27 2010-05-19 中兴通讯股份有限公司 一种数据映射与解映射的方法及装置
CN101719813A (zh) * 2009-11-27 2010-06-02 中兴通讯股份有限公司 一种实现恒定比特率数据的映射装置及方法
CN101986621A (zh) * 2010-11-08 2011-03-16 中兴通讯股份有限公司 数据映射方法及装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1214574C (zh) * 2002-07-29 2005-08-10 华为技术有限公司 一种实现同步数字体系链路接入处理协议的方法
CN101267386B (zh) * 2007-03-15 2011-12-07 华为技术有限公司 传输多路独立以太网数据的方法、装置和系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6819725B1 (en) * 2000-08-21 2004-11-16 Pmc-Sierra, Inc. Jitter frequency shifting Δ-Σ modulated signal synchronization mapper
CN101384093A (zh) * 2008-09-28 2009-03-11 华为技术有限公司 业务数据映射方法和装置及复映射方法
CN101710853A (zh) * 2009-11-27 2010-05-19 中兴通讯股份有限公司 一种数据映射与解映射的方法及装置
CN101719813A (zh) * 2009-11-27 2010-06-02 中兴通讯股份有限公司 一种实现恒定比特率数据的映射装置及方法
CN101986621A (zh) * 2010-11-08 2011-03-16 中兴通讯股份有限公司 数据映射方法及装置

Also Published As

Publication number Publication date
CN101986621A (zh) 2011-03-16

Similar Documents

Publication Publication Date Title
US8571062B1 (en) Multichannel data conversion into packets
US8059684B2 (en) Method and apparatus for signal splitting and combining
US7177314B2 (en) Transmit virtual concatenation processor
US9276874B1 (en) High bandwidth GFP demapper
WO2011075901A1 (zh) 通用映射规程gmp映射方法、解映射方法及装置
WO2012062093A1 (zh) 数据映射方法及装置
US7457390B2 (en) Timeshared jitter attenuator in multi-channel mapping applications
CN102377678B (zh) 一种数据传输处理方法及装置
US8644347B2 (en) Transporting optical data units in an optical transport network
US5535219A (en) Sonet/SDH pointer calculation circuit
CN101252403A (zh) 在光传送网络中业务传送的实现方法
CN105306380B (zh) 数据传输方法及其装置和应用
US8295161B2 (en) Network apparatus that determines whether data is written into buffer based on detection of a memory error
US7379467B1 (en) Scheduling store-forwarding of back-to-back multi-channel packet fragments
US8385472B2 (en) Context-sensitive overhead processor
JP5853788B2 (ja) 伝送装置、伝送方法及び伝送帯域の変更方法
CN1929476B (zh) 一种实现无损伤虚级联恢复的方法
US7016344B1 (en) Time slot interchanging of time slots from multiple SONET signals without first passing the signals through pointer processors to synchronize them to a common clock
EP2533440B1 (en) Method and device for sequencing members of multiple virtual concatenation groups
CN1486000A (zh) 相位调整装置、相位调整方法和用于相位调整方法的程序
JP4673697B2 (ja) デジタル遅延バッファ及びこれに関連する方法
EP1936849A1 (en) Method for mapping and demapping data information over the members of a concatenated group
CN1909429B (zh) 一种延迟光同步数字传送网通道净荷数据的装置
JP5409525B2 (ja) パケット多重化装置
CN1996807B (zh) 一种实现无损伤虚级联延时补偿的方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11839451

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11839451

Country of ref document: EP

Kind code of ref document: A1