WO2012062087A1 - Soc芯片的boot启动装置和soc芯片 - Google Patents
Soc芯片的boot启动装置和soc芯片 Download PDFInfo
- Publication number
- WO2012062087A1 WO2012062087A1 PCT/CN2011/073251 CN2011073251W WO2012062087A1 WO 2012062087 A1 WO2012062087 A1 WO 2012062087A1 CN 2011073251 W CN2011073251 W CN 2011073251W WO 2012062087 A1 WO2012062087 A1 WO 2012062087A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- module
- memory
- interface module
- bus interface
- dma
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Definitions
- the present invention relates to the field of wireless communication technologies, and in particular, to a boot (BOOT) boot device and a SoC chip of a System-on-Chip (SoC) chip.
- BOOT boot
- SoC System-on-Chip
- the SoC chip generally includes a processor, and its working principle is different from the ASIC (Application Specific Integrated Circuit) chip.
- the SoC chip requires software support during its operation.
- the software is compiled into a bit file by the compiler and downloaded to a storage device external to the SoC chip.
- the memory device is generally a flash memory chip.
- the SoC chip is connected to the flash memory chip through the interface. After power-on, the bit file in the flash chip is automatically transferred to the processor's memory, which is the internal storage space of the processor or the flash memory. This process is released in the processor reset. It was previously implemented automatically by the startup module.
- the startup module transfers the data from the external storage device to the SoC chip memory and has a large impact on the performance of the SoC chip and system.
- the existing SoC chip startup implementation device mainly includes the following two modes: First, the bus interface parameter is solidified, the transmission length of the device is not configurable, the transmission address is not configurable, and the use is inflexible in different processor environments; second, BOOT The device has no direct memory access (DMA) interface, and the BOOT device has low transmission efficiency and the transmission address is not configurable, and is inflexible in different processor environments.
- DMA direct memory access
- the main object of the present invention is to provide a BOOT starting device and a SoC chip of a SoC chip, which are intended to improve the startup efficiency of the SoC chip and improve the performance of the SoC chip.
- the present invention provides a BOOT boot device for a SOC chip, the boot device comprising: a memory interface module, a DMA bus interface module, a BOOT processing module, and a parameter configuration module;
- a memory interface module having a memory bus interface for connecting to an external memory
- the DMA bus interface module has a DMA bus interface for carrying data in the external memory to a storage space corresponding to the target address;
- a BOOT processing module respectively connected to the memory interface module and the DMA bus interface module, configured to send a data read/write command to the external memory through the memory interface module, and convert the data transferred by the external memory into the interface with the DMA bus Module adapted data;
- a parameter configuration module configured to configure parameters of the DMA bus interface module, the memory interface module, and the BOOT processing module.
- the parameter configuration module includes: a bus interface configuration module and a DMA configuration module; wherein
- a bus interface configuration module configured to configure parameters of the memory interface module and the DMA bus interface module, where the parameters include a data bus bit width, an address bus bit width parameter, a burst transmission type, and a burst transmission length;
- a DMA configuration module configured to configure parameters of the DMA bus interface module, where the parameters include a transmission destination address and a data transmission length;
- An operation command parameter configuration module is configured to configure an operation command to send a data read/write command to an external memory.
- the bus interface configuration module is further configured to configure the burst transmission type to be an 8-bit mode, a 16-bit mode, a 32-bit mode, or a 64-bit mode.
- the bus interface configuration module is further configured to configure the burst transmission length to be 1 to 16 bits.
- the DMA bus interface module comprises: AMBA2.0, AMBA3.0 or OCP interface MASTER bus.
- the present invention provides a SoC chip, the SoC chip is provided with a BOOT starting device, and the BOOT starting device comprises: a memory interface module, a DMA bus interface module, a BOOT processing module and a parameter configuration module;
- a memory interface module having a memory bus interface for connecting to an external memory
- a DMA bus interface module having a DMA bus interface for carrying data in the external memory to a storage space corresponding to the target address
- a BOOT processing module respectively connected to the memory interface module and the DMA bus interface module, configured to send a data read/write command to the external memory through the memory interface module, and convert the data transferred by the external memory into the interface with the DMA bus Module adapted data;
- a parameter configuration module for configuring the DMA bus interface module, the memory interface module, and
- the parameters of the BOOT processing module are the parameters of the BOOT processing module.
- the SoC chip further comprises an activation device of any of the above.
- the BOOT starting device or the SoC chip of the SoC chip provided by the present invention is set by
- the DMA bus interface and parameter configuration module can improve the BOOT startup efficiency and the system performance of the system where the SoC chip is located.
- FIG. 1 is a schematic structural view of a BOOT starting device of a SOC chip according to an embodiment of the present invention
- FIG. 2 is a schematic structural diagram of a BOOT starting device of a SOC chip according to an embodiment of the present invention. detailed description
- the boot device includes: a memory interface module 10, a DMA bus interface module 20, a BOOT processing module 30, and a parameter configuration module 40, wherein
- the memory interface module 10 is provided with a memory bus interface for connecting to the external memory 50; the external memory 50 may be a FLASH memory.
- the memory interface module 10 realizes the connection function of the SOC chip and the external FLASH chip, and mainly includes a data bus, an address bus, a data indication signal, and the like.
- the DMA bus interface module 20 is provided with a DMA bus interface for carrying data in the external memory to a storage space corresponding to the target address; the DMA is a method of transferring data between the memory and the peripheral device, and is different from the interrupt transmission mode, and does not occupy CPU time. In this way, the reading and writing of data does not require the processor to execute instructions, nor does it go through the internal registers of the processor, but uses the data bus of the system to directly write or read the memory to the memory, thereby achieving extremely high transmission efficiency.
- the bus cycle is generated by the device itself or by the DMA controller.
- a DMA device that generates its own bus cycle is called a master device, and a DMA device that relies on a DMA controller to generate a data transfer cycle is called a slave device.
- the invention preferably uses the Master device.
- the DMA bus interface module 20 can realize data transfer from the external FLASH to the corresponding processor storage space of the target address, and the data bus and address bus operation modes of the DMA bus interface module 20 can be configured.
- the BOOT processing module 30 is connected to the memory interface module 10 and the DMA bus interface module 20, respectively, for transmitting data read/write commands to the external memory 50 through the memory interface module 10, and converting the data transmitted by the external memory 50 to the DMA bus interface.
- the parameter configuration module 40 is configured to configure parameters of the memory interface module 10, the DMA bus interface module 20, and the BOOT processing module 30.
- the parameter configuration module 40 can configure parameters of the DMA bus interface module 20, the memory interface module 10, and the BOOT processing module 30 by code.
- the transmission efficiency can be improved, and the parameters of each part can be flexibly configured, thereby improving
- the BOOT startup efficiency improves the system performance of the system in which the SoC chip is located.
- the parameter configuration module 40 may include:
- the bus interface configuration module 41 is configured to configure parameters of the memory interface module 10 and the DMA bus interface module 20, and the configured parameters include a data bus bit width, an address bus bit width parameter, a burst transmission type, and a burst transmission length;
- the bus interface configuration module 41 can configure a FLASH interface parameter, where the FLASH interface parameter includes a data bus bit width and an address bus bit width, and can be configured to be in a mode of 8, 16, 32, 64, etc., respectively, indicating that the data or the address bus respectively It is 8-bit, 16-bit, 32-bit, and 64-bit.
- the bus interface configuration module 41 can also implement DMA interface bus parameter configuration, and the DMA interface bus parameters include a data bus bit width and an address bus bit width, which can be configured in modes of 8, 16, 32, 64, respectively, to represent data or
- the address bus is 8 bits, 16 bits, 32 bits, and 64 bits, respectively.
- the bus interface configuration module 41 can also perform configurations including a burst transmission type, a burst transmission length, etc., and a burst transmission type can be configured in an 8-bit mode, a 16-bit mode, 16-bit mode, 32-bit mode, burst transfer length can be configured from 1 to 16.
- the DMA configuration module 42 is configured to configure parameters of the DMA bus interface module 20, and the configured parameters include a transmission destination address and a data transmission length;
- the operation command parameter configuration module 43 is configured to configure an operation command to send a data read/write command to the external memory 50.
- the operation command parameter configuration module 43 can be configured to at least 10
- the operation commands are used to implement operations on the external memory 50 (e.g., external FLASH), which are freely definable.
- the DMA bus interface module 20 can be any bus, and the bus includes an Advanced Microcontroller Bus Architecture (AMBA) 2.0, ⁇ 3 ⁇ 0, and an Open Core Protocol (OCP) bus. Main (MASTER) interface, etc.
- AMBA Advanced Microcontroller Bus Architecture
- OCP Open Core Protocol
- Main (MASTER) interface etc.
- the present invention also provides a SoC chip, including the above BOOT boot device.
- the BOOT boot device includes: a memory interface module 10, a DMA bus interface module 20, a BOOT processing module 30, and a parameter configuration module 40. , among them,
- the memory interface module 10 is provided with a memory bus interface for connecting to the external memory 50; the external memory 50 may be a FLASH memory.
- the memory interface module 10 realizes the connection function between the SoC chip and the external FLASH chip, and mainly includes a data bus, an address bus, a data indication signal, and the like.
- the DMA bus interface module 20 is provided with a DMA bus interface for carrying data in the external memory to a storage space corresponding to the target address; the DMA is a method of transferring data between the memory and the peripheral device, and is different from the interrupt transmission mode, and does not occupy CPU time. In this way, the reading and writing of data does not require the processor to execute instructions, nor does it go through the internal registers of the processor, but uses the data bus of the system to directly write or read the memory to the memory, thereby achieving extremely high transmission efficiency.
- the bus cycle is generated by the device itself or by the DMA controller.
- a DMA device that generates its own bus cycle is called a Master device, and a DMA device that relies on a DMA controller to generate a data transfer cycle is called a Slave device.
- the invention preferentially uses the Master device.
- the DMA bus interface module 20 can transfer data from the external FLASH to the processor memory space corresponding to the target address.
- the data bus and address bus operation modes of the DMA bus interface module 20 can be configured.
- BOOT processing module 30 respectively with memory interface module 10 and DMA bus interface module 20 connected, for transmitting a data read/write command to the external memory 50 through the memory interface module, and converting the data transmitted by the external memory 50 into data adapted to the DMA bus interface module; the parameter configuration module 40, configured to configure the memory interface module 10. Parameters of the DMA bus interface module 20 and the BOOT processing module 30. In an embodiment, parameter configuration module 40 may configure parameters of DMA bus interface module 10, memory interface module 20, and BOOT processing module 30 by code.
- the SoC chip of the present invention further includes the above-described starting device shown in Fig. 2.
- the transmission efficiency can be improved, and the parameters of each part can be flexibly configured, the BOOT startup efficiency is improved, and the system performance of the system where the SoC chip is located is improved.
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP11839380.0A EP2639703B1 (en) | 2010-11-08 | 2011-04-25 | Device for booting soc chip and soc chip |
RU2013123648/08A RU2554569C2 (ru) | 2010-11-08 | 2011-04-25 | Устройство для загрузки интегральной схемы soc и интегральная схема типа soc |
BR112013011317-0A BR112013011317A2 (pt) | 2010-11-08 | 2011-04-25 | dispositivo de boot para um chip de sistema em chip (soc) e chip sistema em chip (soc), provido de um dispositivo de boot |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010535369.4 | 2010-11-08 | ||
CN201010535369.4A CN102467472B (zh) | 2010-11-08 | 2010-11-08 | SoC芯片的BOOT启动装置和SoC芯片 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012062087A1 true WO2012062087A1 (zh) | 2012-05-18 |
Family
ID=46050359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2011/073251 WO2012062087A1 (zh) | 2010-11-08 | 2011-04-25 | Soc芯片的boot启动装置和soc芯片 |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP2639703B1 (zh) |
CN (1) | CN102467472B (zh) |
BR (1) | BR112013011317A2 (zh) |
RU (1) | RU2554569C2 (zh) |
WO (1) | WO2012062087A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112711550A (zh) * | 2021-01-07 | 2021-04-27 | 无锡沐创集成电路设计有限公司 | Dma自动配置模块和片上系统soc |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104965798B (zh) * | 2015-06-10 | 2018-03-09 | 上海华为技术有限公司 | 一种数据处理方法、相关设备以及系统 |
CN114064534A (zh) | 2017-04-17 | 2022-02-18 | 伊姆西Ip控股有限责任公司 | 一种用于存储设备的转接卡 |
TWI755695B (zh) * | 2020-03-12 | 2022-02-21 | 智微科技股份有限公司 | 系統單晶片的開機方法 |
CN111814208B (zh) * | 2020-07-02 | 2023-07-28 | 国家广播电视总局广播电视科学研究院 | 一种soc国密安全芯片安全启动时防御故障注入的方法 |
CN114036096B (zh) * | 2021-11-04 | 2024-05-03 | 珠海一微半导体股份有限公司 | 一种基于总线接口的读控制器 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1661580A (zh) * | 2004-02-25 | 2005-08-31 | 中国科学院计算技术研究所 | 直接存储器访问传输装置及其方法 |
CN1761222A (zh) * | 2005-11-22 | 2006-04-19 | 华中科技大学 | 一种支持虚拟接口的存储网络适配器 |
CN101051275A (zh) * | 2006-01-23 | 2007-10-10 | 奇梦达股份公司 | 新存储器体系结构中用直接存储器访问来系统引导的方法 |
Family Cites Families (4)
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CA2284044A1 (en) * | 1997-03-21 | 1998-10-01 | Canal + Societe Anonyme | Computer memory organization |
JP3826859B2 (ja) * | 2002-08-19 | 2006-09-27 | ソニー株式会社 | 情報処理方法とその方法を実現するプログラム及び記録媒体 |
US7206928B2 (en) * | 2003-06-03 | 2007-04-17 | Digi International Inc. | System boot method |
KR100708128B1 (ko) * | 2005-04-30 | 2007-04-17 | 삼성전자주식회사 | 낸드 플래시 메모리 제어 장치 및 방법 |
-
2010
- 2010-11-08 CN CN201010535369.4A patent/CN102467472B/zh not_active Expired - Fee Related
-
2011
- 2011-04-25 EP EP11839380.0A patent/EP2639703B1/en active Active
- 2011-04-25 RU RU2013123648/08A patent/RU2554569C2/ru active
- 2011-04-25 BR BR112013011317-0A patent/BR112013011317A2/pt not_active Application Discontinuation
- 2011-04-25 WO PCT/CN2011/073251 patent/WO2012062087A1/zh active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1661580A (zh) * | 2004-02-25 | 2005-08-31 | 中国科学院计算技术研究所 | 直接存储器访问传输装置及其方法 |
CN1761222A (zh) * | 2005-11-22 | 2006-04-19 | 华中科技大学 | 一种支持虚拟接口的存储网络适配器 |
CN101051275A (zh) * | 2006-01-23 | 2007-10-10 | 奇梦达股份公司 | 新存储器体系结构中用直接存储器访问来系统引导的方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112711550A (zh) * | 2021-01-07 | 2021-04-27 | 无锡沐创集成电路设计有限公司 | Dma自动配置模块和片上系统soc |
CN112711550B (zh) * | 2021-01-07 | 2023-12-29 | 无锡沐创集成电路设计有限公司 | Dma自动配置模块和片上系统soc |
Also Published As
Publication number | Publication date |
---|---|
EP2639703A4 (en) | 2014-04-16 |
EP2639703B1 (en) | 2017-06-21 |
CN102467472B (zh) | 2015-01-28 |
RU2013123648A (ru) | 2014-12-20 |
BR112013011317A2 (pt) | 2021-05-25 |
EP2639703A1 (en) | 2013-09-18 |
RU2554569C2 (ru) | 2015-06-27 |
CN102467472A (zh) | 2012-05-23 |
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