WO2012049669A1 - Procédé et circuit pour augmenter la résolution de la modulation d'impulsions en durée dans des convertisseurs continu-continu à commande numérique - Google Patents

Procédé et circuit pour augmenter la résolution de la modulation d'impulsions en durée dans des convertisseurs continu-continu à commande numérique Download PDF

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Publication number
WO2012049669A1
WO2012049669A1 PCT/IL2010/000825 IL2010000825W WO2012049669A1 WO 2012049669 A1 WO2012049669 A1 WO 2012049669A1 IL 2010000825 W IL2010000825 W IL 2010000825W WO 2012049669 A1 WO2012049669 A1 WO 2012049669A1
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WO
WIPO (PCT)
Prior art keywords
pwm
duty cycle
cycles
converter
sequence
Prior art date
Application number
PCT/IL2010/000825
Other languages
English (en)
Inventor
Efri Vaturi
Yachin Afek
Original Assignee
Dsp Group Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dsp Group Ltd. filed Critical Dsp Group Ltd.
Priority to PCT/IL2010/000825 priority Critical patent/WO2012049669A1/fr
Publication of WO2012049669A1 publication Critical patent/WO2012049669A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

Definitions

  • the present invention relates to PWM digital controlled DC to DC
  • DC2DC converter in general, and more particularly to method and system for increasing PWM resolution in PWM digital controlled DC to DC (DC2DC) converters.
  • BACKGROUND PWM digital controlled DC2DC converters are devices/systems that convert a given input voltage to required output voltage, by controlling the ratio between a positive phase (logic “1” or “HIGH”) and the negative phase (logic “0” or “LOW”) of a control signal, known as Pulse Width Modulation (PWM).
  • PWM Pulse Width Modulation
  • the ratio between HIGH and LOW periods is served as control signal that increases or decreases the output voltage.
  • the system typically uses a given clock and defines the number of cycles in which the control signal is kept high and the number of cycles in which the signal is kept low.
  • the system is typically a closed-loop system that adjusts the control signal continuously responsive to the gap between the actual output voltage and a reference voltage.
  • the clock (hereinafter “reference clock”) frequency is a constraint that affects the accuracy of DC2DC converters. In many systems the clock frequency is provided by the system and the DC2DC converter must function under this constraint. If the reference clock has a relative low frequency it will limit the resolution of the PWM when specific PWM cycle time/period is required. (The terms PWM cycle time and PWM cycle period are interchangeable in the following text).
  • DC2DC converters usually include a Capacitor and an Inductor having a capacitance C and an inductance L respectively.
  • the PWM frequency is the working frequency of the DC2DC. Usually this frequency is defined according to the values of L and C and the system requirements. Increasing PWM cycle time (with specific L) will increase PWM resolution (more reference clock cycles) but will increase AIL which is not desirable. AIL is defined as the amplitude of the inductance current, which is normally a triangle wave. Large AIL affects the minimum supported Iload in continuous conduction mode (CCM - Continuous-conduction-mode. CCM means that the current in the energy transfer inductor never goes to zero between switching cycles) and increases the output ripple - unless the capacitor C is increased. Another effect of lower PWM frequency is slower response time causing big drop or overshoot in load transition.
  • An aspect of an embodiment of the invention relates to a system and method for providing an increased PWM duty cycle resolution in a Digital controlled to DC to DC (DC2DC) converter by defining and generating a sequence of PWM cycles with varying duty cycles.
  • DC2DC Digital controlled to DC to DC
  • a method for increasing PWM duty cycle resolution in a Digital controlled to DC to DC (DC2DC) converter comprising: defining a calculated PWM duty cycle D wherein D > Df; and generating a sequence of n (integer) PWM cycles with varying duty cycles.
  • k (k ⁇ n) PWM cycles have a duty cycle of D f and (n-k) PWM cycles have a duty cycle of Df
  • n ⁇ L max ; L max is defined according to the converter's conditions.
  • the converter includes a capacitance component and an inductance component, and the converter's conditions include capacitance and inductance that are associated with said capacitance and inductance components respectively.
  • the converter's conditions include the characteristic of load change.
  • the converter's conditions include the characteristic of Vout drift.
  • the converter generates PWM cycles according to a reference clock, wherein both edges of said clock are used for generation of said PWM cycles.
  • a digital controlled DC to DC (DC2DC) converter comprising a digital control unit for generating a sequence of n (integer) PWM cycles, with varying PWM duty cycles;
  • n is calculated by the digital control unit.
  • n is provided to the converter as a constant.
  • the digital control unit defines a calculated duty cycle and generates each of the n PWM cycles with a duty cycle to result with an average duty cycle that is close to said calculated duty cycle.
  • the digital control unit generates the sequence of n PWM cycles by a final state machine (FSM).
  • FSM final state machine
  • the digital control unit generates the sequence of n PWM cycles using a F/W.
  • Fig. 1 is a schematic illustration of general circuit that implements PWM digital controlled DC2DC converter in accordance with the prior art
  • Fig. 2 is a schematic view of duty cycle planning in accordance with the prior art.
  • Fig. 3 is a schematic view of an improved duty cycle planning in accordance with the disclosed subject matter.
  • Fig. 4A is a graphic view of Vout versus time in a digital controlled DC2DC in accordance with the disclosed subject matter.
  • Fig. 4B is a graphic view of Vout versus time wherein Vout is drifting down in a digital controlled DC2DC in accordance with the disclosed subject matter.
  • Fig. 4C is a graphic view of Vout versus time wherein Vout interleaving sequence enables to reduce Vout deviations in accordance with the disclosed subject matter.
  • Fig. 5 is a flow chart describing the steps of implementing an increased PWM resolution in digital controlled DC2DC converters in accordance with the disclosed subject matter.
  • Fig. 1 is a schematic illustration of a circuit that implements PWM digital controlled DC2DC converter in accordance with the prior art.
  • Fig. 1 shows a digital control unit 105 that contains a Final State Machine (FSM) 108 and a PWM generator 111.
  • the digital unit receives feedback from the output of two comparators 120, 123.
  • Comparator 120 gets a hi-ref voltage input 129 that is a few percents higher than an output level that is defined as a target output voltage level (hereinafter "target output level"), and comparator 123 gets a low-ref voltage input 132 that is a few percent lower than the target output level.
  • target output level a target output voltage level
  • FSM 108 provides controls to PWM generator 111 that creates an output control signal 120 reflecting the duty cycle that is calculated by FSM 108.
  • Output control signal 120 is an input to a Non-Overlap unit 140 that splits output control signal 120 into two signals 143,146 which assure that there is dead time between the positive and the negative working phases.
  • the two pulse signals are being inputs to a switcher driver 149 that provides control voltage signals to a switcher unit 155.
  • Switcher unit 155 is a kind of current amplification device that gets an input voltage Vin 150 and provides a switcher output voltage 158 that depends on the voltages on transistor 153 and 156.
  • switcher output voltage 158 passes through an LC circuit that includes an inductance element 159 and a capacitor 165 to provide a voltage output level Vout 160 which is the DC2DC converter output.
  • Output voltage level undergoes a voltage division by resistors 162 and 171 to provide a feedback voltage 168 that is provided to comparators 120 and 123.
  • the circuit that is shown in Fig. 1 functions as follows: FSM 108 calculates a duty cycle (hereinafter "calculated PWM duty cycle”) that is expected to yield the target output level and accordingly a switcher output level will be created characterized by the calculated PWM duty cycle.
  • fig. 1 shows a general structure of common DC2DC converter with digital loop control.
  • fig. 1 shows a general structure of common DC2DC converter with digital loop control.
  • the present disclosure is not limited to the implementation that is shown in fig.1 or to any other specific implementation.
  • Fig. 2 is a schematic view of duty cycle planning in accordance with the prior art.
  • Fig.2 shows an example of how a prior art circuit controls the duty cycle in order to provide a certain target output level.
  • the circuit is set to drive a duty cycle of 7 high/positive cycles (and 9 low/negative cycles) until at a certain point in time feedback signals 185 and 187 (fig. 1) will provide an indication that the voltage output level 155 is too high (feedback voltage 168 is higher than the hi-ref voltage 129) and then FSM 108 will issue controls to provide a duty cycle of 6/16 (6 high/positive cycles)
  • Fig. 2 shows an example where the circuit created six cycles of duty cycle 7 marked as 255 258 261 264 267 and 270, and then switched to two PWM cycles with duty cycle of 6(shown as 273 and 276 in fig. 2).
  • the present disclosure suggests a method and circuit that defines a sequence of varying PWM cycles that together define a more accurate duty cycle that results with a more stable output voltage level.
  • Fig. 3 is a schematic view of an improved duty cycle planning in accordance with the disclosed subject matter.
  • the circuit works on both edges of the reference clock, i.e. rising edges and falling edges of the reference clock and therefore, working on 32 half cycles (while PWM cycle time is kept unchanged) provides a resolution of about 3% (compared to a resolution of 6% when the circuit works on only one edge of the clock e.g. rising edges).
  • Fig. 3 refers to an example where the calculated duty cycle is 13.75 (which is equivalent to having a calculated duty cycle of 6.875 when only rising or falling edges are counted).
  • Fig. 3 describes a method and circuit that defines a sequence of four PWM cycles wherein at the first PWM cycle the duty cycle is chosen as thirteen 355 and then the following three PWM cycles are chosen with a duty cycle of fourteen 358,361 and 364, and then the sequence repeats itself starting with a PWM cycle with a duty cycle of thirteen 367.
  • fig. 3 refers to an example of duty cycle 13.75
  • the present disclosure is not limited to any length of the sequence.
  • other sequence length could be chosen.
  • a duty cycle of 11.3 it would be possible to use a sequence of ten PWM cycles, of which three would have been generated with a duty cycle of twelve and seven would have been generated with a duty cycle of eleven.
  • the length of the sequence by the bandwidth of the loop derived from L and C and by the requirement of the system on the allowed ripple (and accuracy). Meaning, as much as the sequence will be longer, the larger the ripple on the voltage output level 160 will be, until the two averaged duty cycles will be reflected completely by their two corresponding output voltage level.
  • Fig. 4A is a graphic view of Vout versus time in a digital controlled DC2DC in accordance with the disclosed subject matter.
  • Fig. 4 shows a typical behavior of Vout 160, shown along axis 405 as a function of time 402.
  • Fig, 4 shows two exemplary Vout voltages 408,458 that may apply to two different circuits, or to a specific circuit functioning under different conditions.
  • Each one of the two Vouts 408, 458 is described by two graphs. Referring to the upper graph 408, the graph describes the general behavior of Vout along time, where Vout starts at a certain level 407 and climbs to a maximal level at Ti l, 41 1 and goes down to a minimal level at T 12, 414, rises to the maximal level at T13 417 and returns to its initial value at T14, 409.
  • Graph 408 may describe the behavior of Vout when applying the method that is shown in Fig. 3, However graph 408 may describe a duty cycle of 13.25 wherein one cycle is activated with duty cycle of 14 and three cycles are activated with duty cycle of 13 resulting with an overall (average) duty cycle of 13.25.
  • a duty cycle of 14 is activated by the control until Ti l 411 and then three PWM cycles are activated with a duty cycle of 13 until T12, 414.
  • Vout will return exactly to its initial level 407 after four PWM cycles and then the same sequence of duty cycles will be applied again moving from T12 to T14, 409.
  • FIG. 427 shows the rotation of Vout around or above the general graph 408.
  • Graph 427 shows that the actual Vout is continuously rising and decreasing around general graph 408, the rotation of Vout around graph 408 describes the ripple on the capacitor as result of AIL as previously mentioned.
  • the cycles of graph 427 are sinus-like shaped with a period that corresponds to a single PWM cycle.
  • the rotation of graph 427 is the result of the PWM algorithm that consists on an average value that is composed by a period of "HIGH” followed by a period of "LOW", at the "HIGH” part the graph shows an increase of voltage while at the "LOW” part of the cycle the graph shows a decrease of voltage. While the "HIGH” and "LOW” are relatively short the result is a sinus-like wave that follows an average value.
  • graphs 458 and 477 show another circuit behavior, where the general Vout behavior changes in a slower rate compared to 408.
  • Fig. 4B is a graphic view of Vout versus time wherein Vout is drifting down in a digital controlled DC2DC in accordance with the disclosed subject matter.
  • Fig. 4B shows the behavior of Vout 487 when the circuit suffers from a drift downwards, thus, when the same method as shown in Fig. 4A is applied, Vout continuously drifts down and a full sequence of four PWM cycles is ended at T12, 484 when Vout is noticeably lower than its initial value.
  • Such drift of Vout can practically happen due to increase in load current or decreasing Vin, In this disclosure it will generally referred to as Vout drift as a result of the converter conditions.
  • Fig. 4C is a graphic view of Vout versus time wherein Vout interleaving sequence enables to reduce Vout deviations in accordance with the disclosed subject matter.
  • Fig. 4C shows another aspect of the invention, where interleaving is used for reducing Vout deviations.
  • Fig. 5 is a flow chart 500 describing the steps of implementing an increased PWM resolution in digital controlled DC2DC converters in accordance with the disclosed subject matter.
  • the first step is to calculate a calculated PWM duty cycle (503) D.
  • PWM duty cycle 503
  • D is not an integer but a fractional number D > Df wherein Df stands for D floor, i.e. the nearest integer that is smaller than D or equals D.
  • a number of allowed PWM cycles which is a Max sequence length L max is defined (506). As shown before, this number is dictated by the circuit conditions (e.g. capacitance of capacitor 165, inductance of inductor 159, the characteristic of the load changes, characteristic of Vout drift etc.). This limitation is a constraint that limits the PWM duty cycle resolution. It should be noted that steps (503) and (506) do not depend on each other, thus they can be performed at any order.
  • the system determines an interleaved sequence as previously described with reference to fig. 4C.
  • these types of calculations for creating an interleaved sequence do not involve any mathematical expertise it won't be further detailed in this disclosure.
  • a sequence of PWM duty cycles is generated by the circuit accordingly (512). Feedback from the output voltage level is provided by the circuit (515) and an updated calculated PWM duty cycle is calculated (503).
  • L max may be redefined over time if certain conditions that affect L max changes. However, practically it is not likely to change L max frequently and typically a system will be working with a fixed value of L max .
  • condition in the present disclosure refer to both circuit parameters such as capacitance as inductance and also to external conditions such as changes of Vin changes of the load etc.
  • implementing digital control unit 105 in accordance to the disclosed subject matter can be performed in many ways, for example, definition of the sequence of n (integer) PWM cycles with varying duty cycles could be part of either FSM (Final State Machine) 108 or PWM generator 111 or may be implemented as a separate unit.
  • the length n of the sequence of n PWM cycles may be supplied to the circuit as a constant value or may be defined by the circuit according to the circuit conditions.
  • Defining the sequence of n PWM cycles may be implemented by H/W such as a common state machine or may be implemented by a F W that is executed on controller

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

La présente invention concerne un procédé permettant d'augmenter la résolution du cycle de service de la modulation d'impulsions en durée (PWM) dans un convertisseur continu-continu (CC/CC). Ce procédé consiste d'abord à définir un cycle de service calculé D de la modulation d'impulsions en durée, tel que D ≥ Df. Le procédé consiste ensuite à générer une suite constituée d'un nombre entier n de cycles de modulation d'impulsions en durée comportant des cycles de service variables. Selon l'invention, d'une part un nombre k de cycles de modulation d'impulsions en durée, tel que k < n, ont un cycle de service de Df, d'autre part un nombre n-k de cycles de modulation d'impulsions en durée ont un cycle de service de Df+1, et enfin, Df + (n-k)/n est très proche de D.
PCT/IL2010/000825 2010-10-11 2010-10-11 Procédé et circuit pour augmenter la résolution de la modulation d'impulsions en durée dans des convertisseurs continu-continu à commande numérique WO2012049669A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/IL2010/000825 WO2012049669A1 (fr) 2010-10-11 2010-10-11 Procédé et circuit pour augmenter la résolution de la modulation d'impulsions en durée dans des convertisseurs continu-continu à commande numérique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IL2010/000825 WO2012049669A1 (fr) 2010-10-11 2010-10-11 Procédé et circuit pour augmenter la résolution de la modulation d'impulsions en durée dans des convertisseurs continu-continu à commande numérique

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998044622A2 (fr) * 1997-03-27 1998-10-08 Koninklijke Philips Electronics N.V. Transformateur en mode commute a commande numerique
US6538484B1 (en) * 2002-03-18 2003-03-25 Lynx-Photonic Networks Ltd. High-frequency PWM voltage control
US20060152263A1 (en) * 2003-01-22 2006-07-13 Markus Rademacher Pulse-width modulator circuit and method for controlling a pulse width modulator circuit
DE102006056785A1 (de) * 2006-12-01 2008-06-05 Conti Temic Microelectronic Gmbh Verfahren und Vorrichtung zum Erzeugen eines Ansteuersignals für einen Leistungsschalter
WO2009122333A2 (fr) * 2008-03-31 2009-10-08 Nxp B.V. Modulateur numérique

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998044622A2 (fr) * 1997-03-27 1998-10-08 Koninklijke Philips Electronics N.V. Transformateur en mode commute a commande numerique
US6538484B1 (en) * 2002-03-18 2003-03-25 Lynx-Photonic Networks Ltd. High-frequency PWM voltage control
US20060152263A1 (en) * 2003-01-22 2006-07-13 Markus Rademacher Pulse-width modulator circuit and method for controlling a pulse width modulator circuit
DE102006056785A1 (de) * 2006-12-01 2008-06-05 Conti Temic Microelectronic Gmbh Verfahren und Vorrichtung zum Erzeugen eines Ansteuersignals für einen Leistungsschalter
WO2009122333A2 (fr) * 2008-03-31 2009-10-08 Nxp B.V. Modulateur numérique

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