WO2012046427A1 - Active matrix substrate, method for manufacturing active matrix substrate, and liquid crystal display device - Google Patents

Active matrix substrate, method for manufacturing active matrix substrate, and liquid crystal display device Download PDF

Info

Publication number
WO2012046427A1
WO2012046427A1 PCT/JP2011/005548 JP2011005548W WO2012046427A1 WO 2012046427 A1 WO2012046427 A1 WO 2012046427A1 JP 2011005548 W JP2011005548 W JP 2011005548W WO 2012046427 A1 WO2012046427 A1 WO 2012046427A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal line
active matrix
insulating film
matrix substrate
film
Prior art date
Application number
PCT/JP2011/005548
Other languages
French (fr)
Japanese (ja)
Inventor
智 堀内
一順 光本
吉田　昌弘
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2012046427A1 publication Critical patent/WO2012046427A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to an active matrix substrate, a method for manufacturing the active matrix substrate, and a liquid crystal display device including the active matrix substrate, and in particular, an active matrix substrate having excellent yield and reliability by protecting signal lines, and active
  • the present invention relates to a method for manufacturing a matrix substrate and a liquid crystal display device including the active matrix substrate.
  • the liquid crystal display device can be reduced in thickness and has low power consumption, it is widely used as a display for OA devices such as TVs and personal computers, mobile information devices such as mobile phones and PDAs (Personal Digital Assistants).
  • OA devices such as TVs and personal computers
  • mobile information devices such as mobile phones and PDAs (Personal Digital Assistants).
  • a liquid crystal display device has a configuration in which a TFT substrate, which is an active matrix substrate on which a plurality of TFTs (Thin Film Transistors) are formed, and a counter substrate facing the TFT substrate are bonded together by a sealing material. A liquid crystal material is sealed in a space formed between the two substrates.
  • a counter substrate a substrate that is slightly smaller than the active matrix substrate is employed, and a drive circuit is mounted on the terminal region of the active matrix substrate exposed by this.
  • a display area in which a plurality of pixels are arranged to perform display and a non-display area provided around the display area are formed.
  • a source signal line, a semiconductor film, and a gate signal line are arranged and laminated so as to have a predetermined layout to form a plurality of TFTs.
  • An interlayer insulating film is further formed to cover the plurality of TFTs, and a pixel electrode made of a transparent conductive film such as ITO (Indium (Tin Oxide) is formed on the surface thereof.
  • ITO Indium (Tin Oxide
  • a gate insulating film and an interlayer insulating film are provided on the source signal line and the gate signal line, respectively, but these insulating films may be defective.
  • these insulating films may be defective.
  • pinholes are generated in the thinned portion, and a defective portion is easily formed.
  • an etchant used for forming the pixel electrode may enter the signal line from the defective portion, and the signal line may be damaged to cause problems such as disconnection.
  • Patent Document 1 discloses a configuration in which a protective film is formed at the same time as the pixel electrode is formed of the same material as the pixel electrode on the upper surface of the overcoat film in a portion slightly larger than the portion where the signal line overlaps the drain electrode. It is disclosed. According to this configuration, even if the overcoat film covering the portion where the signal line overlaps the drain electrode has a defect, the protective film is present on the defect, so that the ITO etching is performed when the pixel electrode is formed. It is described that the liquid does not permeate into the defective portion of the overcoat film, and as a result, disconnection due to the Al-ITO battery reaction can be prevented from occurring in the signal line made of Al.
  • the active matrix substrate of the present invention includes a substrate body, A first signal line provided on the substrate body; A first insulating film provided to cover the substrate body and the first signal line; A second signal line provided on the first insulating film; A second insulating film provided to cover the first insulating film and the second signal line; A pixel electrode provided on the second insulating film; An active matrix substrate in which a switching element is configured at a portion where the first signal line and the second signal line intersect, Over the second insulating film, a floating protective film formed of the same material as the pixel electrode so as to correspond to the first signal line and the second signal line is intermittent along the corresponding signal line. It is provided in.
  • the protective film formed of the same material as the pixel electrode is provided on the second insulating film so as to correspond to the first signal line and the second signal line. Even if the first insulating film and the second insulating film on the signal line or the second insulating film on the second signal line has a defect such as a pinhole, the etching solution passes through the defect of the insulating film when the pixel electrode is etched. Reaching the first signal line and the second signal line can be suppressed. Therefore, the first signal line and the second signal line can be prevented from being damaged by the etching solution, and a good yield of the active matrix substrate can be obtained.
  • the protective film provided so as to correspond to the first signal line and the second signal line is in a floating state that is not electrically connected to other wirings, the protective film is formed with a structure such as another pixel electrode. The influence on the parasitic capacitance is suppressed.
  • the protective film provided so as to correspond to the first signal line and the second signal line is provided intermittently along the corresponding signal line, the protective film leaks with other metal members. In this case, an increase in parasitic capacitance can be suppressed as compared with the case where the protective film does not have an intermittent portion.
  • the signal lines are often arranged adjacent to each other in parallel, and a protective film is provided adjacent to the upper layer of the adjacent signal lines.
  • the protective film is provided intermittently along the signal line, even if the adjacent protective films leak and the parasitic capacitance increases, the parasitic protection is caused by the leakage of the adjacent protective films. The increase in capacity can be greatly suppressed.
  • the protective film covers the outside of the first signal line or the second signal line in the width direction.
  • the insulating film provided in the upper layer is often thin, so that pinholes and the like are likely to occur in the insulating film.
  • the protective film is provided so as to cover the outer side in the width direction of the first signal line and the second signal line, the insulating film is thinned, and a defect such as a pinhole is likely to occur. This is also protected by the protective film, and it is possible to prevent the signal line from being damaged by the etchant entering the signal line from the defective portion during etching.
  • adjacent protective films are preferably separated by a distance of 3 to 20 ⁇ m.
  • the adjacent protective films are provided with a distance of 3 to 20 ⁇ m, so that the protective films are prevented from leaking. Therefore, it is possible to suppress the occurrence of parasitic capacitance between the adjacent signal lines (between different signal lines) due to leakage of the protective films and the potential of the signal lines being affected.
  • each of the protective films preferably has a length in the direction along either the first signal line or the second signal line of 10 to 500 ⁇ m.
  • the protective film is provided intermittently so that the length in the direction along each of the first signal line and the second signal line is 10 to 500 ⁇ m. In this case, even if leakage with other metal members occurs, the influence does not reach all the protective films provided on the signal line, and the increase in parasitic capacitance can be suppressed.
  • the thickness of the second insulating film disposed between the protective film provided above the second signal line and the second signal line among the plurality of protective films is , 0.1 to 1 ⁇ m.
  • the thickness of the second insulating film is as thin as about 0.1 to 1 ⁇ m, even if the second insulating film is provided on the second signal line, a pinhole or the like is generated on the second insulating film.
  • the signal line is not completely covered and the signal line may be damaged by the etchant.
  • the protective layer is provided on the upper layer of the signal line to prevent the signal line from being damaged. can do.
  • the active matrix substrate of the present invention includes a first insulating film and a second insulating film disposed between a protective film provided on an upper layer of the first signal line and a first signal line among the plurality of protective films. This is suitable when the sum of the thicknesses of the films is 0.2 to 1 ⁇ m.
  • the pin is formed on the first insulating film even if the first insulating film is provided on the first signal line.
  • the signal line is not completely covered by the generation of holes or the like, and the signal line may be damaged by the etchant.
  • the signal line is formed by providing a protective film on the upper layer of the signal line. Can suppress the problem of damage.
  • a part of the first signal line may be a gate signal line for supplying a control signal to the switching element.
  • a part of the second signal line may be a source signal line for supplying a data signal to the switching element.
  • a part of the first signal line and the second signal line may be a lead line for drawing out the gate signal line and the source signal line to the frame region.
  • the active matrix substrate manufacturing method of the present invention includes a first signal line forming step of forming a first signal line on a substrate body, A first insulating film forming step of forming a first insulating film so as to cover the substrate body and the first signal line; A semiconductor film forming step of forming a semiconductor film on the substrate body and the first signal line; A second signal line forming step of forming a second signal line on the first insulating film; A second insulating film forming step of forming a second insulating film so as to cover the first insulating film and the second signal line; A pixel electrode forming step of forming a pixel electrode and a protective film on the second insulating film; Comprising: an active matrix substrate according to claim 1, comprising: In the pixel electrode formation process, After forming a conductive film on the second insulating film, By applying a resist on the entire surface of the conductive film, and subsequently exposing and developing the resist using a mask having an opening corresponding to a region other than the region
  • etching is performed using the formed resist as a mask to remove a region of the conductive film corresponding to the opening of the resist, Further, the pixel electrode is formed and the protective film is formed by removing the resist on the conductive film.
  • the method for manufacturing an active matrix substrate of the present invention uses a mask that is set so that the region where the protective film is disposed is a region that covers the outside in the width direction of the first signal line and the second signal line in the resist formation step. It is preferable to perform exposure and development of the resist.
  • the active matrix substrate of the present invention is suitable for a liquid crystal display device including an active matrix substrate, a counter substrate disposed opposite to the active matrix substrate, and a liquid crystal layer provided between the active matrix substrate and the counter substrate. Used for.
  • the protective film made of the same material as the pixel electrode is provided on the second insulating film so as to correspond to the first signal line and the second signal line. Even when the first insulating film and the second insulating film on the signal line or the second insulating film on the second signal line has a defect such as a pinhole, the etching liquid is insulated when the conductive film constituting the pixel electrode is etched. Reaching the first signal line or the second signal line through a film defect can be suppressed. Therefore, the first signal line and the second signal line can be prevented from being damaged by the etching solution, and a good yield of the active matrix substrate can be obtained.
  • the protective film provided so as to correspond to the first signal line and the second signal line is in a floating state that is not electrically connected to other wirings, the protective film is formed with a structure such as another pixel electrode. The influence on the parasitic capacitance is suppressed.
  • the protective film provided so as to correspond to the first signal line and the second signal line is provided intermittently along the corresponding signal line, the protective film leaks with other metal members. In this case, an increase in parasitic capacitance can be suppressed as compared with the case where the protective film does not have an intermittent portion.
  • the signal lines are often arranged adjacent to each other in parallel, and a protective film is provided adjacent to the upper layer of the adjacent signal lines.
  • the protective film is provided intermittently along the signal line, even if the adjacent protective films leak and the parasitic capacitance increases, the parasitic protection is caused by the leakage of the adjacent protective films. The increase in capacity can be greatly suppressed.
  • FIG. 1 is a schematic plan view of a liquid crystal display device according to Embodiment 1.
  • FIG. 2 is a cross-sectional view taken along line II-II in FIG. 3 is a schematic plan view of the TFT substrate of Embodiment 1.
  • FIG. FIG. 4 is a plan view in a region IV of FIG. 3 and shows a display region of a TFT substrate.
  • FIG. 5 is a sectional view taken along line VV in FIG. 4.
  • FIG. 5 is a sectional view taken along line VI-VI in FIG. 4.
  • FIG. 5 is a sectional view taken along line VII-VII in FIG. 4.
  • FIG. 4 is a plan view in a region VIII in FIG. 3 and shows a non-display region of the TFT substrate.
  • (A) is a top view which shows the example of another layout of the lead line in the non-display area
  • (b) is a top view which expands and shows the area
  • (A)-(f) is explanatory drawing which shows the manufacturing method of a TFT substrate. It is a top view of the TFT substrate concerning the modification of this embodiment. It is a top view of the TFT substrate concerning the modification of this embodiment. It is a top view of the TFT substrate used for an X-ray sensor apparatus or electronic paper.
  • Embodiment 1 a liquid crystal display device 10 including a TFT substrate 20 as an active matrix substrate will be described as an example of a display device.
  • FIG. 1 is a plan view showing an external appearance of a main part of the liquid crystal display device 10 according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing a main part structure of the liquid crystal display device 10 including a cross section taken along line II-II in FIG.
  • the liquid crystal display device 10 includes a liquid crystal display panel and a backlight unit (not shown) that is a lighting device disposed to face the liquid crystal display panel.
  • the liquid crystal display panel includes a TFT substrate 20 that is an active matrix substrate, a counter substrate 30 disposed so as to face the TFT substrate 20, and the TFT substrate 20 and the counter substrate 30. And an encapsulated liquid crystal layer 50.
  • a display area 11 for displaying an image.
  • a plurality of pixels (not shown) arranged in a matrix are formed.
  • a frame-like area outside the display area 11 and including the seal area 13 is a non-display area 12 where no image display is performed.
  • a plurality of terminals (not shown) are formed in the non-display area 12, which is a terminal area 14 on which a driver chip (not shown) for driving the liquid crystal display panel is mounted.
  • FIG. 3 is a schematic plan view of the TFT substrate 20.
  • 4 shows an enlarged plan view of the display region 11 of the TFT substrate 20 in the region IV of FIG. 5 to 7 show cross sections taken along lines VV, VI-VI, and VII-VII in FIG. 4, respectively.
  • FIG. 8 shows an enlarged plan view of the non-display area 12 of the TFT substrate 20 in the area VIII of FIG.
  • the TFT substrate 20 includes, on the substrate body 21, each signal including a first insulating film 23 (gate insulating film 23), a semiconductor film 31, and a source signal line 24a, such as signal lines including a common electrode 21a and a gate signal line 22a. It has a configuration in which a line, an electrode including the second insulating film 25, the pixel electrode 26a, a wiring, and the like are sequentially stacked.
  • the structure indicated by the 22nd series such as reference numerals 22a and 22b is a structure formed of the same material as that of the gate signal line 22a.
  • the configuration shown in the 24th series such as reference numerals 24a and 24b is a configuration formed of the same material as that of the source signal line 24a.
  • the configuration indicated by the 26th series such as reference numerals 26a and 26b is a configuration formed of the same material as the pixel electrode 26a.
  • the substrate body 21 is made of, for example, a glass substrate.
  • the common electrode 21a is provided on the substrate body 21 so as to correspond to each pixel.
  • the common electrode 21a is made of a transparent conductive film such as an ITO film, for example.
  • each signal line including the gate signal line 22a includes the first signal line such as the gate signal line 22a, the storage capacitor signal line 22b, and the lead line 22c provided in the non-display area 12 shown in FIG. 22d, COM wiring not shown, inspection wiring, and the like.
  • the conductive film constituting the gate signal line 22a and the like is formed of, for example, an Al alloy single layer film, an Al film, a Cu film, a Mo film, a Ti film, or a laminated film thereof.
  • a plurality of gate signal lines 22a are arranged so as to extend in parallel with each other.
  • the gate signal line 22a has a function of supplying a control signal to the TFT.
  • the storage capacitor signal line 22b is provided between the gate signal lines 22a so as to extend in parallel with each of the plurality of gate signal lines 22a.
  • the storage capacitor signal line 22b is a wiring for applying a predetermined voltage to the auxiliary capacitor formed in each pixel.
  • each of the storage capacitor signal lines 22b is electrically connected to the storage capacitor wiring 24e via the contact portion 24ec.
  • the lead line 22 c is a wiring for drawing the gate signal line 22 a and the storage capacitor signal line 22 b to the terminals 22 t and 24 t provided in the terminal region 14.
  • the region corresponding to the TFT in the gate signal line 22a is formed to be the gate electrode 22d.
  • the gate insulating film 23 is made of an inorganic insulating film such as a silicon oxide film (SiOx film) or a silicon nitride film (SiNx film), and has a thickness of about 0.4 ⁇ m, for example.
  • each signal line including the source signal line 24a including the source signal line 24a, the source signal line 24a shown in FIG. 3, the second signal line such as the lead line 24b provided in the non-display area 12, the auxiliary capacity trunk wiring 24e, FIG. Source electrode 24c, drain electrode 24d, and inspection wiring (not shown).
  • the conductive film constituting the source signal line 24a and the like is made of, for example, an Al alloy single layer film, an Al film, a Cu film, a Mo film, a Ti film, or a laminated film thereof.
  • a plurality of source signal lines 24a are arranged so as to extend in parallel with each other, and are arranged so as to be orthogonal to each of the gate signal lines 22a.
  • the source signal line 24a has a function of supplying a data signal to the TFT.
  • the lead line 24 b is a wiring for drawing the source signal line 24 a to the terminal 24 t provided in the terminal region 14.
  • the source electrode 24c and the drain electrode 24d are disposed so as to face the upper layer of the gate electrode 22d as shown in FIG.
  • the second insulating film 25 (interlayer insulating film 25) is composed of, for example, a silicon oxide film (SiOx film) and a silicon nitride film (SiNx film). A contact hole 25c reaching the drain electrode 24d is formed in the interlayer insulating film 25.
  • the conductive film constituting the pixel electrode 26a and the like is composed of a transparent conductive film such as ITO (IndiumITOTin Oxide) or IZO (Indium Zinc Oxide), a laminated film of an Al alloy, an Al film, and a Mo film, for example. ing.
  • a transparent conductive film such as ITO (IndiumITOTin Oxide) or IZO (Indium Zinc Oxide)
  • IZO Indium Zinc Oxide
  • the pixel electrode 26a is provided so as to correspond to each pixel in the display area.
  • the pixel electrode is provided so as to cover the surface of the contact hole 25c provided in the interlayer insulating film 25, and is thereby electrically connected to the drain electrode 24d.
  • the pixel electrode 26a is provided with a plurality of elongated holes 26ac shown in FIGS. 4 and 7 in parallel for alignment of the liquid crystal material of the liquid crystal layer 50.
  • the hole 26ac is not an essential configuration for the present invention.
  • the protective film 26b is intermittently provided along the signal lines so as to correspond to the first signal lines such as the gate signal lines 22a and the lead lines 22c and the second signal lines such as the source signal lines 24a and the lead lines 24b. Is provided.
  • the protective film 26b is provided in a floating state that is not electrically connected to other wiring.
  • the protective film 26b is provided so as to cover the outside in the width direction of the corresponding signal line.
  • the gate insulating film 23 and the interlayer insulating film 25 are formed on the upper layer of the gate signal line 22a.
  • a laminated film is formed, and a protective film 26b is further provided thereon.
  • the thickness of the insulating film between the gate signal line 22a and the protective film 26b that is, the total thickness of the gate insulating film 23 and the interlayer insulating film 25 is as thin as about 0.2 to 1 ⁇ m, for example.
  • a protective film 26b is provided so as to correspond to the gate signal line 22a, an etching solution enters the gate signal line 22a from the defective portion of the insulating film, thereby causing a gate. The problem that the signal line 22a is damaged is suppressed.
  • the protective film 26b preferably has a length in the direction along the gate signal line 22a of 10 to 500 ⁇ m. Since the length of the protective film 26b in the direction along the gate signal line 22a is 500 ⁇ m or less, even if leakage occurs between the protective film 26b and another metal member, the influence is provided on the gate signal line 22a. Therefore, the increase in the parasitic capacitance can be suppressed without reaching the entire protective film.
  • the distance between the protective film 26b and the pixel electrode 26a is preferably 3 to 20 ⁇ m. By separating the distances from each other, the protective film 26b and the pixel electrode 26a can be prevented from leaking and affecting the potential of the pixel electrode 26a.
  • an interlayer insulating film 25 is formed on the source signal line 24a as shown in FIG.
  • a protective film 26b is further provided thereon.
  • the thickness of the insulating film between the source signal line 24a and the protective film 26b that is, the thickness of the interlayer insulating film 25 is as thin as about 0.1 to 1 ⁇ m, for example, the insulating film has defects such as pinholes.
  • the protective film 26b is provided so as to correspond to the source signal line 24a, the etchant enters the source signal line 24a from the defective portion of the insulating film, and the source signal line 24a is damaged. The problem is suppressed.
  • the protective film 26b preferably has a length in the direction along the source signal line 24a of 10 to 500 ⁇ m. Since the length of the protective film 26b in the direction along the source signal line 24a is 500 ⁇ m or less, even if leakage occurs between the protective film 26b and another metal member, the influence is provided on the source signal line 24a. Therefore, the increase in the parasitic capacitance can be suppressed without reaching the entire protective film.
  • the distance between the protective film 26b and the pixel electrode 26a is preferably 3 to 20 ⁇ m. By separating the distances from each other, the protective film 26b and the pixel electrode 26a can be prevented from leaking and affecting the potential of the pixel electrode 26a.
  • a plurality of protective films 26b are preferably provided intermittently in the direction.
  • the length of the protective film 26b that is intermittently received is preferably 10 to 500 ⁇ m. Since the length of the protective film 26b in the direction along the lead line 24b is 500 ⁇ m or less, even if a leak occurs between the protective film 26b and another metal member, the influence is provided on the lead line 24b. The amount of increase in parasitic capacitance can be suppressed without reaching the entire protective film.
  • the distance between adjacent protective films is preferably 3 to 20 ⁇ m.
  • the adjacent protective films 26b are separated from each other by this distance, it is possible to prevent the two from leaking and greatly increasing the parasitic capacitance.
  • FIG. 3 shows a drawing in which the lead line 22c is provided in parallel with the gate signal line 22a.
  • the present invention is not limited to this.
  • Lead wires 22c and 24b may be provided so as to extend in the direction along the line.
  • the protective film 26b can be formed so as to correspond to the lead lines 22c and 24b.
  • a TFT is formed for each pixel at a position where the gate signal line 22a and the source signal line 24a intersect.
  • the TFT is, for example, a bottom gate type, and includes a gate electrode 22d, a gate insulating film 23, and a semiconductor film 31 formed on the surface of the gate insulating film 23.
  • An alignment film (not shown) is formed on the surface of the TFT substrate 20 on the liquid crystal layer 50 side.
  • the counter substrate 30 has a rectangular glass substrate (not shown) that is an insulating substrate on which a color filter (not shown), a black matrix (not shown), and the like are formed.
  • An alignment film (not shown) is formed on the surface of the counter substrate 30 on the liquid crystal layer 50 side.
  • the common electrode 21a is provided on the TFT substrate 20.
  • the common electrode is not provided on the TFT substrate 20.
  • the common electrode is provided on the entire surface of the counter substrate 30.
  • sealing material 40 Between the TFT substrate 20 and the counter substrate 30, a frame-shaped sealing material 40 that interposes the TFT substrate 20 and the counter substrate 30 is interposed.
  • the sealing material 40 is made of, for example, an ultraviolet curable epoxy resin.
  • the liquid crystal layer 50 is made of, for example, nematic liquid crystal.
  • the liquid crystal display device 10 is manufactured by laminating a TFT substrate 20 and a counter substrate 30 that are manufactured in advance through a liquid crystal layer 50 and a sealing material 40, respectively.
  • the sealing material 40 is drawn in a rectangular frame shape on the counter substrate 30, and the liquid crystal material is dropped and supplied into the frame of the sealing material 40.
  • the counter substrate 30 is aligned and bonded to the TFT substrate 20.
  • the sealing material 40 is irradiated with ultraviolet rays to cure the sealing material 40, and the liquid crystal display device 10 is manufactured.
  • sealing material 40 may be drawn not on the counter substrate 30 but on the TFT substrate 20.
  • the liquid crystal material is injected by the dropping method.
  • an injection port (not shown) is formed in the frame-shaped sealing member and the dip vacuum injection is performed, the injection is performed.
  • a method of sealing the inlet may be used.
  • the TFT substrate manufacturing process includes a gate signal line forming process, a first insulating film forming process, a source signal line 24a forming process, a second insulating film forming process, and a conductive film forming process.
  • a transparent conductive film such as an ITO film is formed on the substrate body 21 and patterned so as to have a predetermined layout for each pixel, thereby forming the common electrode 21a.
  • a conductive film is provided by a known photolithography process, and wirings and electrodes such as a gate signal line 22a, a storage capacitor signal line 22b, a lead line 22c, and a gate electrode 22d are formed.
  • the storage capacitor signal line 22b is formed in contact with the common electrode 21a.
  • a gate insulating film 23 is formed on the substrate body 21 on which the gate signal lines 22a and the like are formed using a known method.
  • a semiconductor film is formed on the gate insulating film 23 by stacking, for example, an intrinsic semiconductor and an n + semiconductor in a predetermined region using a known method.
  • Source signal line 24a forming step Subsequently, a conductive film is provided on the gate insulating film 23 by a known photolithography process. Thereby, wirings and electrodes such as the source signal line 24a, the lead line 24b, the source electrode 24c, and the drain electrode 24d are formed.
  • an interlayer insulating film 25 is formed on the gate insulating film 23 on which the source signal line 24a and the like are formed using a known method. Then, a contact hole 25c is formed in a region corresponding to the drain electrode 24d of the interlayer insulating film 25.
  • a conductive film 26 is formed so as to cover the entire surface of the interlayer insulating film 25 by a known method.
  • a resist material is formed on the entire upper surface of the conductive film 26 to form a resist film.
  • the resist film was exposed using an etching mask M having an opening so as to correspond to a region other than the region where the pixel electrode 26a and the protective film 26b are to be formed.
  • Post-development is performed to form a resist R.
  • the resist R is provided so as to cover the region of the conductive film 26 where the pixel electrode 26a and the protective film 26b are to be formed.
  • the conductive film 26 is etched by wet etching through the opening Rc of the resist R formed as described above. Thereby, as shown in FIG. 10E, portions of the conductive film 26 other than the pixel electrode and the protective film are removed.
  • etching process for example, acid etching (SLA: Sand-blasted Large-grit Acid-etched) or ferric chloride can be used as an etching solution.
  • SLA Sand-blasted Large-grit Acid-etched
  • ferric chloride can be used as an etching solution.
  • the TFT substrate 20 is obtained.
  • the first signal line such as the gate signal line 22a and the lead line 22c and the second signal such as the source signal line 24a and the lead line 24b are formed on the interlayer insulating film 25.
  • the resist for patterning the protective film 26b formed of the same material as the pixel electrode 26a is provided so as to correspond to the line, the gate insulating film 23 and the interlayer insulating film 25 on the first signal line, Alternatively, even if the interlayer insulating film 25 on the second signal line has a defect such as a pinhole or the like, when the conductive film constituting the pixel electrode is etched, the etchant passes through the defect of the insulating film to the first signal line or the second signal line. Reaching the signal line can be suppressed. Therefore, the first signal line and the second signal line can be prevented from being damaged by the etching solution, and a good yield of the TFT substrate 20 can be obtained.
  • the protective film 26b provided so as to correspond to the first signal line and the second signal line is in a floating state in which it is not electrically connected to other wiring, the structure of the other pixel electrode 26a or the like is used. An influence on the formed parasitic capacitance is suppressed.
  • the protective film 26b provided so as to correspond to the first signal line and the second signal line is provided intermittently along the corresponding signal line, the protective film 26b is connected to other metal members.
  • an increase in parasitic capacitance can be suppressed as compared with the case where the protective film 26b does not have an intermittent portion.
  • the signal lines are often arranged adjacent to each other in parallel, and the protective film 26b is adjacent to the upper layer of the adjacent signal lines.
  • the protective film 26b is intermittently provided along the signal line, even if the adjacent protective films 26b leak and the parasitic capacitance increases, the adjacent protective films 26b An increase in parasitic capacitance due to leakage can be significantly suppressed.
  • the protective film 26b is provided so as to cover the outside in the width direction of the corresponding signal line.
  • the protective film 26b is provided above the interlayer insulating film 25 so as to correspond to each signal line. It only has to be.
  • the insulating film provided in the upper layer is often thin, and therefore it is easy for pinholes and the like to occur in the insulating film.
  • the protective film 26b is preferably provided so as to cover the outside in the width direction of the signal line.
  • the protective film 26b provided so as to correspond to the source signal line 24a may be provided so as to be formed of a plurality of protective films 26b on one side of one pixel.
  • the other protective film 26b is not affected. Deterioration can be suppressed.
  • the conductive film provided on the gate electrode 22d may be formed integrally with the pixel electrode 26a as a part of the pixel electrode 26a without being independent as the protective film 26b.
  • the conductive film (protective film 26b) provided on the gate signal line 22a and the pixel electrode 26a are formed separately. It is preferable.
  • the liquid crystal display device 10 is configured using the TFT substrate 20 which is the active matrix substrate of the present invention.
  • the present invention is not limited to this, and the present invention is applied to a display device such as an organic EL display device.
  • the TFT substrate 20 may be used.
  • the liquid crystal display device 10 is configured using the TFT substrate 20 that is the active matrix substrate of the present invention.
  • the present invention is not limited to this.
  • the active matrix substrate of the present invention may be used as a TFT substrate constituting an X-ray sensor device or electronic paper.
  • a TFT substrate 120 shown in FIG. 13 can be used. Also in this case, since the protective film 126b is provided above the interlayer insulating film 25 so as to correspond to each signal line, the etching solution is supplied from the defective portion of the insulating film when the conductive film constituting the pixel electrode 126a is etched. It is possible to suppress a problem that the signal line is damaged due to intrusion, and it is possible to suppress a decrease in the yield of the TFT substrate.
  • a TFT substrate 120 having a layout shown in FIG. 13 can be used. Also in this case, since the protective film 126b is provided above the interlayer insulating film 125 so as to correspond to each signal line, the etching solution is supplied from the defective portion of the insulating film when the conductive film constituting the pixel electrode 126a is etched. It is possible to suppress a problem that the signal line is damaged due to intrusion, and it is possible to suppress a decrease in the yield of the TFT substrate.
  • the present invention is useful for an active matrix substrate, a method for manufacturing the active matrix substrate, and a liquid crystal display device including the active matrix substrate, and in particular, an active matrix having excellent yield and reliability by protecting signal lines.
  • the present invention is useful for a substrate, a method for manufacturing an active matrix substrate, and a liquid crystal display device including the active matrix substrate.
  • TFT substrate active matrix substrate
  • Substrate body 22a Gate signal line (first signal line) 22c Lead line (first signal line) 22d Gate electrode 23 Gate insulating film (first insulating film) 24a Source signal line 24b Lead line (first signal line) 25 Interlayer insulation film (second insulation film) 26a pixel electrode 26b protective film 30 counter substrate 50 liquid crystal layer M etching mask R resist

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

An active matrix substrate (20) of the present invention comprises: a substrate (21); a first signal line (22a) that is provided on the substrate; a first insulating film (23) that is provided so as to cover the substrate and the first signal line; a second signal line (24a) that is provided on the first insulating film; a second insulating film (25) that is provided so as to cover the first insulating film and the second signal line; and a pixel electrode (26a) that is provided on the second insulating film. A switching element (30) is configured at a position where the first signal line (22a) and the second signal line (24a) intersect each other, and protective films (26b) in a floating state are provided above the second insulating film (25) at intervals along the first signal line (22a) and the second signal line (24a) so as to correspond to the first signal line (22a) and the second signal line (24a), said protective films (26b) being formed of the same material as the pixel electrode (26a). According to the present invention, the first signal line (22a) and the second signal line (24a) can be prevented from being damaged by an etching liquid, and good yield can therefore be achieved.

Description

アクティブマトリックス基板、アクティブマトリックス基板の製造方法、及び液晶表示装置Active matrix substrate, method for manufacturing active matrix substrate, and liquid crystal display device
　本発明は、アクティブマトリックス基板、アクティブマトリックス基板の製造方法、及びそのアクティブマトリックス基板を備えた液晶表示装置に関し、特に、信号線を保護することにより優れた歩留まりや信頼性を有するアクティブマトリックス基板、アクティブマトリックス基板の製造方法、及びそのアクティブマトリックス基板を備えた液晶表示装置に関する。 The present invention relates to an active matrix substrate, a method for manufacturing the active matrix substrate, and a liquid crystal display device including the active matrix substrate, and in particular, an active matrix substrate having excellent yield and reliability by protecting signal lines, and active The present invention relates to a method for manufacturing a matrix substrate and a liquid crystal display device including the active matrix substrate.
　液晶表示装置は、薄型化が可能で低消費電力であるため、テレビ、パーソナルコンピュータ等のＯＡ機器や携帯電話、ＰＤＡ（Personal Digital Assistant）等の携帯情報機器のディスプレイとして広く用いられている。 Since the liquid crystal display device can be reduced in thickness and has low power consumption, it is widely used as a display for OA devices such as TVs and personal computers, mobile information devices such as mobile phones and PDAs (Personal Digital Assistants).
　一般に、液晶表示装置は、複数のＴＦＴ（Thin Film Transistor：薄膜トランジスタ）が形成されたアクティブマトリックス基板であるＴＦＴ基板と、これに対向する対向基板と、がシール材により貼り合わされた構成を有し、両基板間に構成される空間には液晶材料が封入されている。対向基板はアクティブマトリックス基板よりも一回り小さい基板が採用されており、これによって露出したアクティブマトリックス基板の端子領域上に、駆動回路が実装されている。 In general, a liquid crystal display device has a configuration in which a TFT substrate, which is an active matrix substrate on which a plurality of TFTs (Thin Film Transistors) are formed, and a counter substrate facing the TFT substrate are bonded together by a sealing material. A liquid crystal material is sealed in a space formed between the two substrates. As the counter substrate, a substrate that is slightly smaller than the active matrix substrate is employed, and a drive circuit is mounted on the terminal region of the active matrix substrate exposed by this.
　また、液晶表示装置には、複数の画素が配置されて表示が行われる表示領域と、その周囲に設けられた非表示領域とが形成されている。 Further, in the liquid crystal display device, a display area in which a plurality of pixels are arranged to perform display and a non-display area provided around the display area are formed.
　ＴＦＴ基板のガラス基板上には、ソース信号線、半導体膜、ゲート信号線が所定のレイアウトとなるように配置されて積層され、複数のＴＦＴが形成されている。そして、複数のＴＦＴを覆うようにさらに層間絶縁膜が形成され、その表面にＩＴＯ（Indium Tin Oxide）等の透明導電膜からなる画素電極が形成されている。 On the glass substrate of the TFT substrate, a source signal line, a semiconductor film, and a gate signal line are arranged and laminated so as to have a predetermined layout to form a plurality of TFTs. An interlayer insulating film is further formed to cover the plurality of TFTs, and a pixel electrode made of a transparent conductive film such as ITO (Indium （Tin Oxide) is formed on the surface thereof.
　ところで、ソース信号線やゲート信号線上にはそれぞれゲート絶縁膜や層間絶縁膜が設けられているが、これらの絶縁膜に欠陥があることがある。特に、これらの絶縁膜の厚さが薄くなっていると、薄くなった部分でピンホールが発生して欠陥部分となりやすくなる。そして、絶縁膜に欠陥が存在すると、画素電極の形成する際に用いるエッチング液が欠陥部分から信号線に浸入し、信号線が損傷を受けて断線等の問題が生じる原因となりうる。 Incidentally, a gate insulating film and an interlayer insulating film are provided on the source signal line and the gate signal line, respectively, but these insulating films may be defective. In particular, when the thickness of these insulating films is reduced, pinholes are generated in the thinned portion, and a defective portion is easily formed. If there is a defect in the insulating film, an etchant used for forming the pixel electrode may enter the signal line from the defective portion, and the signal line may be damaged to cause problems such as disconnection.
　特許文献１には、信号線がドレイン電極と重なる部分よりもやや大きめの部分におけるオーバーコート膜の上面には、保護膜が画素電極と同一の材料によって画素電極の形成と同時に形成された構成が開示されている。そして、この構成によれば、信号線がドレイン電極と重なる部分を覆うオーバーコート膜に欠陥があっても、当該欠陥上に保護膜が存在することにより、画素電極を形成する際のＩＴＯのエッチング液がオーバーコート膜の当該欠陥部に染みこむことがなく、ひいてはＡｌからなる信号線にＡｌ－ＩＴＯ電池反応による断線が生じないようにすることができると記載されている。 Patent Document 1 discloses a configuration in which a protective film is formed at the same time as the pixel electrode is formed of the same material as the pixel electrode on the upper surface of the overcoat film in a portion slightly larger than the portion where the signal line overlaps the drain electrode. It is disclosed. According to this configuration, even if the overcoat film covering the portion where the signal line overlaps the drain electrode has a defect, the protective film is present on the defect, so that the ITO etching is performed when the pixel electrode is formed. It is described that the liquid does not permeate into the defective portion of the overcoat film, and as a result, disconnection due to the Al-ITO battery reaction can be prevented from occurring in the signal line made of Al.
特開２０００－１７１８３２号公報JP 2000-171832 A
　しかしながら、特許文献１の図７の構成の場合、隣接して設けられた保護膜同士がリークする虞がある。保護膜同士がリークすると、保護膜と当該保護膜が保護しようとする信号線との間の寄生容量が大きく増加してしまい、表示特性が劣化してしまう虞がある。 However, in the case of the configuration shown in FIG. 7 of Patent Document 1, there is a risk that adjacent protective films may leak. If the protective films leak, the parasitic capacitance between the protective film and the signal line to be protected by the protective film is greatly increased, which may deteriorate the display characteristics.
　本発明は、絶縁膜にピンホール等の欠陥があっても、その欠陥の下に配置された信号線に断線が生じるのを抑制し、優れた歩留まりを得ることを目的とする。 It is an object of the present invention to suppress the occurrence of disconnection in a signal line arranged under a defect even if the insulating film has a defect such as a pinhole, and to obtain an excellent yield.
　本発明のアクティブマトリックス基板は、基板本体と、
　基板本体上に設けられた第１信号線と、
　基板本体及び第１信号線を覆うように設けられた第１絶縁膜と、
　第１絶縁膜上に設けられた第２信号線と、
　第１絶縁膜及び第２信号線を覆うように設けられた第２絶縁膜と、
　第２絶縁膜上に設けられた画素電極と、
を備え、第１信号線及び第２信号線が交差する部分にスイッチング素子が構成されたアクティブマトリックス基板であって、
　第２絶縁膜の上層には、第１信号線及び第２信号線に対応するように、画素電極と同一の材料で形成されるフローティング状態の保護膜が、対応する信号線に沿って間欠的に設けられていることを特徴とする。 The active matrix substrate of the present invention includes a substrate body,
A first signal line provided on the substrate body;
A first insulating film provided to cover the substrate body and the first signal line;
A second signal line provided on the first insulating film;
A second insulating film provided to cover the first insulating film and the second signal line;
A pixel electrode provided on the second insulating film;
An active matrix substrate in which a switching element is configured at a portion where the first signal line and the second signal line intersect,
Over the second insulating film, a floating protective film formed of the same material as the pixel electrode so as to correspond to the first signal line and the second signal line is intermittent along the corresponding signal line. It is provided in.
　上記の構成によれば、第２絶縁膜の上層には第１信号線及び第２信号線に対応するように、画素電極と同一材料で形成される保護膜が設けられているので、第１信号線上の第１絶縁膜及び第２絶縁膜、或いは、第２信号線上の第２絶縁膜にピンホール等の欠陥があっても、画素電極のエッチング時、エッチング液が絶縁膜の欠陥を介して第１信号線や第２信号線に到達するのを抑制することができる。従って、エッチング液によって第１信号線や第２信号線が損傷を受けるのを抑制することができ、アクティブマトリックス基板の良好な歩留まりを得ることができる。 According to the above configuration, the protective film formed of the same material as the pixel electrode is provided on the second insulating film so as to correspond to the first signal line and the second signal line. Even if the first insulating film and the second insulating film on the signal line or the second insulating film on the second signal line has a defect such as a pinhole, the etching solution passes through the defect of the insulating film when the pixel electrode is etched. Reaching the first signal line and the second signal line can be suppressed. Therefore, the first signal line and the second signal line can be prevented from being damaged by the etching solution, and a good yield of the active matrix substrate can be obtained.
　また、第１信号線及び第２信号線に対応するように設けられた保護膜が、他の配線と電気的に接続されていないフローティング状態であるので、他の画素電極等の構成により形成される寄生容量に影響を与えるのが抑制される。 In addition, since the protective film provided so as to correspond to the first signal line and the second signal line is in a floating state that is not electrically connected to other wirings, the protective film is formed with a structure such as another pixel electrode. The influence on the parasitic capacitance is suppressed.
　さらに、第１信号線及び第２信号線に対応するように設けられた保護膜は、当該対応する信号線に沿って間欠的に設けられているので、保護膜が他の金属部材とリークした場合に、保護膜が間欠部分を有さない場合よりも寄生容量の増加を抑制することができる。特に、アクティブマトリックス基板の非表示領域においては、各信号線が隣接して並行するように配置されていることが多く、隣接する信号線の上層には並行して保護膜が隣接して設けられることとなるが、保護膜が信号線に沿って間欠的に設けられているので、隣接する保護膜同士がリークして寄生容量が増加しても、当該隣接保護膜同士がリークしたことによる寄生容量の増加を大幅に抑制することができる。 Furthermore, since the protective film provided so as to correspond to the first signal line and the second signal line is provided intermittently along the corresponding signal line, the protective film leaks with other metal members. In this case, an increase in parasitic capacitance can be suppressed as compared with the case where the protective film does not have an intermittent portion. In particular, in the non-display area of the active matrix substrate, the signal lines are often arranged adjacent to each other in parallel, and a protective film is provided adjacent to the upper layer of the adjacent signal lines. However, since the protective film is provided intermittently along the signal line, even if the adjacent protective films leak and the parasitic capacitance increases, the parasitic protection is caused by the leakage of the adjacent protective films. The increase in capacity can be greatly suppressed.
　本発明のアクティブマトリックス基板は、保護膜は、第１信号線または第２信号線の幅方向の外側まで覆っていることが好ましい。 In the active matrix substrate of the present invention, it is preferable that the protective film covers the outside of the first signal line or the second signal line in the width direction.
　信号線の幅方向断面の端部においては、その上層に設けられる絶縁膜が薄くなっている場合が多く、そのため、絶縁膜にピンホール等が発生しやすくなっている。上記の構成によれば、保護膜が第１信号線及び第２信号線の幅方向の外側まで覆うように設けられているので、絶縁膜が薄くなってピンホール等の欠陥が発生しやすい部分も保護膜により保護されることとなり、エッチング時に欠陥部分から信号線にエッチャントが浸入して信号線が損傷を受けるのを抑制することができる。 At the end of the cross section in the width direction of the signal line, the insulating film provided in the upper layer is often thin, so that pinholes and the like are likely to occur in the insulating film. According to the above configuration, since the protective film is provided so as to cover the outer side in the width direction of the first signal line and the second signal line, the insulating film is thinned, and a defect such as a pinhole is likely to occur. This is also protected by the protective film, and it is possible to prevent the signal line from being damaged by the etchant entering the signal line from the defective portion during etching.
　本発明のアクティブマトリックス基板は、隣り合う保護膜同士は、３～２０μｍの距離を隔てていることが好ましい。 In the active matrix substrate of the present invention, adjacent protective films are preferably separated by a distance of 3 to 20 μm.
　上記の構成によれば、隣り合う保護膜同士は、３～２０μｍの距離を隔てて設けられているので、保護膜同士がリークするのが抑制される。そのため、保護膜同士がリークすることにより隣接する信号線間(異なる信号線間)で寄生容量が発生して信号線の電位が影響を受けるのを抑制することができる。 According to the above configuration, the adjacent protective films are provided with a distance of 3 to 20 μm, so that the protective films are prevented from leaking. Therefore, it is possible to suppress the occurrence of parasitic capacitance between the adjacent signal lines (between different signal lines) due to leakage of the protective films and the potential of the signal lines being affected.
　本発明のアクティブマトリックス基板は、保護膜のそれぞれは、第１信号線及び第２信号線のいずれかに沿った方向の長さが１０～５００μｍであることが好ましい。 In the active matrix substrate of the present invention, each of the protective films preferably has a length in the direction along either the first signal line or the second signal line of 10 to 500 μm.
　上記の構成によれば、保護膜のそれぞれの第１信号線及び第２信号線に沿った方向の長さが１０～５００μｍとなるように間欠的に設けられているので、ある特定の保護膜において、他の金属部材とのリークが発生しても、その影響は、当該信号線上に設けられた保護膜全部に及ぶことがなく、寄生容量の増加量を抑制することができる。 According to the above configuration, the protective film is provided intermittently so that the length in the direction along each of the first signal line and the second signal line is 10 to 500 μm. In this case, even if leakage with other metal members occurs, the influence does not reach all the protective films provided on the signal line, and the increase in parasitic capacitance can be suppressed.
　また、本発明のアクティブマトリックス基板は、複数の保護膜のうち第２信号線の上層に設けられた保護膜と、第２信号線と、の間に配された第２絶縁膜の厚さが、０．１～１μｍである場合に好適である。 In the active matrix substrate of the present invention, the thickness of the second insulating film disposed between the protective film provided above the second signal line and the second signal line among the plurality of protective films is , 0.1 to 1 μm.
　第２絶縁膜の厚さが０．１～１μｍ程度に薄い場合には、第２信号線上に第２絶縁膜が設けられていても、第２絶縁膜上にピンホール等が発生することにより、信号線が完全に被覆されていないこととなり、エッチャントにより信号線が損傷を受ける虞があるが、信号線の上層に保護膜が設けられていることにより、信号線が損傷を受ける問題を抑制することができる。 When the thickness of the second insulating film is as thin as about 0.1 to 1 μm, even if the second insulating film is provided on the second signal line, a pinhole or the like is generated on the second insulating film. The signal line is not completely covered and the signal line may be damaged by the etchant. However, the protective layer is provided on the upper layer of the signal line to prevent the signal line from being damaged. can do.
　また、本発明のアクティブマトリックス基板は、複数の保護膜のうち第１信号線の上層に設けられた保護膜と、第１信号線と、の間に配された第１絶縁膜及び第２絶縁膜の厚さの和が、０．２～１μｍである場合に好適である。 The active matrix substrate of the present invention includes a first insulating film and a second insulating film disposed between a protective film provided on an upper layer of the first signal line and a first signal line among the plurality of protective films. This is suitable when the sum of the thicknesses of the films is 0.2 to 1 μm.
　第１絶縁膜と第２絶縁膜の厚さの和が０．２～１μｍ程度に薄い場合には、第１信号線上に第１絶縁膜が設けられていても、第１絶縁膜上にピンホール等が発生することにより、信号線が完全に被覆されていないこととなり、エッチャントにより信号線が損傷を受ける虞があるが、信号線の上層に保護膜が設けられていることにより、信号線が損傷を受ける問題を抑制することができる。 When the sum of the thicknesses of the first insulating film and the second insulating film is as thin as about 0.2 to 1 μm, the pin is formed on the first insulating film even if the first insulating film is provided on the first signal line. The signal line is not completely covered by the generation of holes or the like, and the signal line may be damaged by the etchant. However, the signal line is formed by providing a protective film on the upper layer of the signal line. Can suppress the problem of damage.
　本発明のアクティブマトリックス基板は、第１信号線の一部は、スイッチング素子に制御信号を与えるゲート信号線であってもよい。 In the active matrix substrate of the present invention, a part of the first signal line may be a gate signal line for supplying a control signal to the switching element.
　また、本発明のアクティブマトリックス基板は、第２信号線の一部は、スイッチング素子にデータ信号を与えるソース信号線であってもよい。 Further, in the active matrix substrate of the present invention, a part of the second signal line may be a source signal line for supplying a data signal to the switching element.
　また、本発明のアクティブマトリックス基板は、第１信号線及び第２信号線の一部は、ゲート信号線及びソース信号線を額縁領域に引き出す引き出し線であってもよい。 Further, in the active matrix substrate of the present invention, a part of the first signal line and the second signal line may be a lead line for drawing out the gate signal line and the source signal line to the frame region.
　本発明のアクティブマトリックス基板の製造方法は、基板本体上に第１信号線を形成する第１信号線形成工程と、
　基板本体及び第１信号線を覆うように第１絶縁膜を形成する第１絶縁膜形成工程と、
　基板本体及び第１信号線上に半導体膜を形成する半導体膜形成工程と、
　第１絶縁膜上に第２信号線を形成する第２信号線形成工程と、
　第１絶縁膜及び第２信号線を覆うように第２絶縁膜を形成する第２絶縁膜形成工程と、
　第２絶縁膜に画素電極及び保護膜を形成する画素電極形成工程と、
を備え、請求項１に記載されたアクティブマトリックス基板を製造するものであって、
　画素電極形成工程では、
　第２絶縁膜上に導電膜を成膜した後、
　導電膜上の全面にレジストを塗布し、続いて、画素電極及び保護膜を配置しようとする領域以外の領域に対応する開口部を有するマスクを使用して、レジストの露光及び現像を行うことによりレジストを形成し、
　次いで、形成したレジストをマスクとしてエッチングを行って、導電膜のうち該レジストの開口部に対応する領域を除去し、
　さらに、導電膜上のレジストを除去する
ことにより、画素電極を形成すると共に保護膜を形成することを特徴とする。 The active matrix substrate manufacturing method of the present invention includes a first signal line forming step of forming a first signal line on a substrate body,
A first insulating film forming step of forming a first insulating film so as to cover the substrate body and the first signal line;
A semiconductor film forming step of forming a semiconductor film on the substrate body and the first signal line;
A second signal line forming step of forming a second signal line on the first insulating film;
A second insulating film forming step of forming a second insulating film so as to cover the first insulating film and the second signal line;
A pixel electrode forming step of forming a pixel electrode and a protective film on the second insulating film;
Comprising: an active matrix substrate according to claim 1, comprising:
In the pixel electrode formation process,
After forming a conductive film on the second insulating film,
By applying a resist on the entire surface of the conductive film, and subsequently exposing and developing the resist using a mask having an opening corresponding to a region other than the region where the pixel electrode and the protective film are to be disposed. Forming a resist,
Next, etching is performed using the formed resist as a mask to remove a region of the conductive film corresponding to the opening of the resist,
Further, the pixel electrode is formed and the protective film is formed by removing the resist on the conductive film.
　本発明のアクティブマトリックス基板の製造方法は、レジスト形成ステップにおいて、保護膜を配置する領域が第１信号線及び第２信号線の幅方向の外側まで覆う領域となるように設定したマスクを使用して、レジストの露光及び現像を行うことが好ましい。 The method for manufacturing an active matrix substrate of the present invention uses a mask that is set so that the region where the protective film is disposed is a region that covers the outside in the width direction of the first signal line and the second signal line in the resist formation step. It is preferable to perform exposure and development of the resist.
　本発明のアクティブマトリックス基板は、アクティブマトリックス基板と、アクティブマトリックス基板と対向配置された対向基板と、アクティブマトリックス基板と対向基板との間に設けられた液晶層と、を備えた液晶表示装置に好適に用いられる。 The active matrix substrate of the present invention is suitable for a liquid crystal display device including an active matrix substrate, a counter substrate disposed opposite to the active matrix substrate, and a liquid crystal layer provided between the active matrix substrate and the counter substrate. Used for.
　本発明によれば、第２絶縁膜の上層には第１信号線及び第２信号線に対応するように、画素電極と同一の材料で形成された保護膜が設けられているので、第１信号線上の第１絶縁膜及び第２絶縁膜、或いは、第２信号線上の第２絶縁膜にピンホール等の欠陥があっても、画素電極を構成する導電膜のエッチング時、エッチング液が絶縁膜の欠陥を介して第１信号線や第２信号線に到達するのを抑制することができる。従って、エッチング液によって第１信号線や第２信号線が損傷を受けるのを抑制することができ、アクティブマトリックス基板の良好な歩留まりを得ることができる。 According to the present invention, the protective film made of the same material as the pixel electrode is provided on the second insulating film so as to correspond to the first signal line and the second signal line. Even when the first insulating film and the second insulating film on the signal line or the second insulating film on the second signal line has a defect such as a pinhole, the etching liquid is insulated when the conductive film constituting the pixel electrode is etched. Reaching the first signal line or the second signal line through a film defect can be suppressed. Therefore, the first signal line and the second signal line can be prevented from being damaged by the etching solution, and a good yield of the active matrix substrate can be obtained.
　また、第１信号線及び第２信号線に対応するように設けられた保護膜が、他の配線と電気的に接続されていないフローティング状態であるので、他の画素電極等の構成により形成される寄生容量に影響を与えるのが抑制される。 In addition, since the protective film provided so as to correspond to the first signal line and the second signal line is in a floating state that is not electrically connected to other wirings, the protective film is formed with a structure such as another pixel electrode. The influence on the parasitic capacitance is suppressed.
　さらに、第１信号線及び第２信号線に対応するように設けられた保護膜は、当該対応する信号線に沿って間欠的に設けられているので、保護膜が他の金属部材とリークした場合に、保護膜が間欠部分を有さない場合よりも寄生容量の増加を抑制することができる。特に、アクティブマトリックス基板の非表示領域においては、各信号線が隣接して並行するように配置されていることが多く、隣接する信号線の上層には並行して保護膜が隣接して設けられることとなるが、保護膜が信号線に沿って間欠的に設けられているので、隣接する保護膜同士がリークして寄生容量が増加しても、当該隣接保護膜同士がリークしたことによる寄生容量の増加を大幅に抑制することができる。 Furthermore, since the protective film provided so as to correspond to the first signal line and the second signal line is provided intermittently along the corresponding signal line, the protective film leaks with other metal members. In this case, an increase in parasitic capacitance can be suppressed as compared with the case where the protective film does not have an intermittent portion. In particular, in the non-display area of the active matrix substrate, the signal lines are often arranged adjacent to each other in parallel, and a protective film is provided adjacent to the upper layer of the adjacent signal lines. However, since the protective film is provided intermittently along the signal line, even if the adjacent protective films leak and the parasitic capacitance increases, the parasitic protection is caused by the leakage of the adjacent protective films. The increase in capacity can be greatly suppressed.
実施形態１にかかる液晶表示装置の概略平面図である。1 is a schematic plan view of a liquid crystal display device according to Embodiment 1. FIG. 図１のＩＩ－ＩＩ線における断面図である。FIG. 2 is a cross-sectional view taken along line II-II in FIG. 実施形態１のＴＦＴ基板の概略平面図である。3 is a schematic plan view of the TFT substrate of Embodiment 1. FIG. 図３の領域ＩＶにおける平面図であり、ＴＦＴ基板の表示領域を示す。FIG. 4 is a plan view in a region IV of FIG. 3 and shows a display region of a TFT substrate. 図４のＶ－Ｖ線における断面図である。FIG. 5 is a sectional view taken along line VV in FIG. 4. 図４のＶＩ－ＶＩ線における断面図である。FIG. 5 is a sectional view taken along line VI-VI in FIG. 4. 図４のＶＩＩ－ＶＩＩ線における断面図である。FIG. 5 is a sectional view taken along line VII-VII in FIG. 4. 図３の領域ＶＩＩＩにおける平面図であり、ＴＦＴ基板の非表示領域を示す。FIG. 4 is a plan view in a region VIII in FIG. 3 and shows a non-display region of the TFT substrate. （ａ）はＴＦＴ基板の非表示領域における引き出し線の他のレイアウトの例を示す平面図であり、（ｂ）は（ａ）の領域ＩＸを拡大して示す平面図である。(A) is a top view which shows the example of another layout of the lead line in the non-display area | region of a TFT substrate, (b) is a top view which expands and shows the area | region IX of (a). （ａ）～（ｆ）はＴＦＴ基板の製造方法を示す説明図である。(A)-(f) is explanatory drawing which shows the manufacturing method of a TFT substrate. 本実施形態の変形例にかかるＴＦＴ基板の平面図である。It is a top view of the TFT substrate concerning the modification of this embodiment. 本実施形態の変形例にかかるＴＦＴ基板の平面図である。It is a top view of the TFT substrate concerning the modification of this embodiment. Ｘ線センサ装置や電子ペーパーに用いるＴＦＴ基板の平面図である。It is a top view of the TFT substrate used for an X-ray sensor apparatus or electronic paper.
　以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は、以下の実施形態に限定されるものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment.
　　《実施形態１》
　本実施形態では、アクティブマトリックス基板としてのＴＦＴ基板２０を備えた液晶表示装置１０を、表示装置の例として説明する。 Embodiment 1
In the present embodiment, a liquid crystal display device 10 including a TFT substrate 20 as an active matrix substrate will be described as an example of a display device.
　　＜液晶表示装置＞
　図１は、本実施形態１の液晶表示装置１０の要部外観を示す平面図である。図２は、図１におけるＩＩ－ＩＩ線断面を含み、液晶表示装置１０の要部構造を示す断面図である。 <Liquid crystal display device>
FIG. 1 is a plan view showing an external appearance of a main part of the liquid crystal display device 10 according to the first embodiment. FIG. 2 is a cross-sectional view showing a main part structure of the liquid crystal display device 10 including a cross section taken along line II-II in FIG.
　液晶表示装置１０は、液晶表示パネルと、この液晶表示パネルに対向して配置された照明装置であるバックライトユニット（不図示）とを有している。 The liquid crystal display device 10 includes a liquid crystal display panel and a backlight unit (not shown) that is a lighting device disposed to face the liquid crystal display panel.
　液晶表示パネルは、図１及び２に示すように、アクティブマトリックス基板であるＴＦＴ基板２０と、このＴＦＴ基板２０に対向して配置された対向基板３０と、ＴＦＴ基板２０及び対向基板３０の間に封入された液晶層５０とを有している。 As shown in FIGS. 1 and 2, the liquid crystal display panel includes a TFT substrate 20 that is an active matrix substrate, a counter substrate 30 disposed so as to face the TFT substrate 20, and the TFT substrate 20 and the counter substrate 30. And an encapsulated liquid crystal layer 50.
　液晶表示装置１０は、シール材４０が設けられる枠形状の領域であるシール領域１３の内側が、画像の表示を行う表示領域１１となっている。表示領域１１には、マトリクス状に配置された複数の画素（不図示）が形成されている。また、表示領域１１の外側であってシール領域１３を含む額縁状の領域は、画像表示を行わない非表示領域１２となっている。非表示領域１２には複数の端子（不図示）が形成され、液晶表示パネルを駆動するためのドライバチップ（不図示）が実装される端子領域１４となっている。 In the liquid crystal display device 10, the inside of the seal area 13, which is a frame-shaped area where the seal material 40 is provided, is a display area 11 for displaying an image. In the display area 11, a plurality of pixels (not shown) arranged in a matrix are formed. Further, a frame-like area outside the display area 11 and including the seal area 13 is a non-display area 12 where no image display is performed. A plurality of terminals (not shown) are formed in the non-display area 12, which is a terminal area 14 on which a driver chip (not shown) for driving the liquid crystal display panel is mounted.
　　（ＴＦＴ基板）
　図３は、ＴＦＴ基板２０の概略平面図である。図４は、図３の領域ＩＶにおけるＴＦＴ基板２０の表示領域１１の拡大平面図を示す。図５～７は、それぞれ、図４のＶ－Ｖ線、ＶＩ－ＶＩ線、及びＶＩＩ－ＶＩＩ線における断面を示す。図８は、図３の領域ＶＩＩＩにおけるＴＦＴ基板２０の非表示領域１２の拡大平面図を示す。 (TFT substrate)
FIG. 3 is a schematic plan view of the TFT substrate 20. 4 shows an enlarged plan view of the display region 11 of the TFT substrate 20 in the region IV of FIG. 5 to 7 show cross sections taken along lines VV, VI-VI, and VII-VII in FIG. 4, respectively. FIG. 8 shows an enlarged plan view of the non-display area 12 of the TFT substrate 20 in the area VIII of FIG.
　ＴＦＴ基板２０は、基板本体２１上に、共通電極２１ａ，ゲート信号線２２ａを含む各信号線等、第１絶縁膜２３（ゲート絶縁膜２３）、半導体膜３１、ソース信号線２４ａを含む各信号線等、第２絶縁膜２５、画素電極２６ａを含む電極や配線等が順に積層された構成を有する。なお、各図中において、参照符号２２ａ、２２ｂ等の２２番台で示す構成は、ゲート信号線２２ａと同一の材料で形成された構成を示す。参照符号２４ａ、２４ｂ等の２４番台で示す構成は、ソース信号線２４ａと同一の材料で形成された構成を示す。参照符号２６ａ、２６ｂ等の２６番台で示す構成は、画素電極２６ａと同一の材料で形成された構成を示す。 The TFT substrate 20 includes, on the substrate body 21, each signal including a first insulating film 23 (gate insulating film 23), a semiconductor film 31, and a source signal line 24a, such as signal lines including a common electrode 21a and a gate signal line 22a. It has a configuration in which a line, an electrode including the second insulating film 25, the pixel electrode 26a, a wiring, and the like are sequentially stacked. In each figure, the structure indicated by the 22nd series such as reference numerals 22a and 22b is a structure formed of the same material as that of the gate signal line 22a. The configuration shown in the 24th series such as reference numerals 24a and 24b is a configuration formed of the same material as that of the source signal line 24a. The configuration indicated by the 26th series such as reference numerals 26a and 26b is a configuration formed of the same material as the pixel electrode 26a.
　基板本体２１は、例えばガラス基板等で構成されている。 The substrate body 21 is made of, for example, a glass substrate.
　共通電極２１ａは、図４や図７に示すように、基板本体２１上に各画素に対応するように設けられている。共通電極２１ａは、例えば、ＩＴＯ膜等の透明導電膜で構成されている。 As shown in FIGS. 4 and 7, the common electrode 21a is provided on the substrate body 21 so as to correspond to each pixel. The common electrode 21a is made of a transparent conductive film such as an ITO film, for example.
　ゲート信号線２２ａを含む各信号線等の構成としては，図３に示すゲート信号線２２ａ，保持容量信号線２２ｂ，非表示領域１２に設けられた引き出し線２２ｃ等の第１信号線，図４に示すゲート電極２２ｄ，図示しないＣＯＭ配線，検査用配線等が挙げられる。ゲート信号線２２ａ等を構成する導電膜は，例えば，Ａｌ合金の単層膜，またはＡｌ膜，Ｃｕ膜，Ｍｏ膜，Ｔｉ膜若しくはこれらの積層膜によって構成されている。 The configuration of each signal line including the gate signal line 22a includes the first signal line such as the gate signal line 22a, the storage capacitor signal line 22b, and the lead line 22c provided in the non-display area 12 shown in FIG. 22d, COM wiring not shown, inspection wiring, and the like. The conductive film constituting the gate signal line 22a and the like is formed of, for example, an Al alloy single layer film, an Al film, a Cu film, a Mo film, a Ti film, or a laminated film thereof.
　ゲート信号線２２ａは，図３に示すように，複数が互いに並行して延びるように配置されている。ゲート信号線２２ａは、ＴＦＴに制御信号を与える機能を有する。 As shown in FIG. 3, a plurality of gate signal lines 22a are arranged so as to extend in parallel with each other. The gate signal line 22a has a function of supplying a control signal to the TFT.
　保持容量信号線２２ｂは，図３に示すように，ゲート信号線２２ａの間に，複数のゲート信号線２２ａのそれぞれと並行して延びるように設けられている。保持容量信号線２２ｂは，各画素に形成される補助容量に所定の電圧を印加するための配線である。保持容量信号線２２ｂのそれぞれは、図３に示すように、コンタクト部２４ｅｃを介して保持容量間配線２４ｅに電気的に接続されている。 As shown in FIG. 3, the storage capacitor signal line 22b is provided between the gate signal lines 22a so as to extend in parallel with each of the plurality of gate signal lines 22a. The storage capacitor signal line 22b is a wiring for applying a predetermined voltage to the auxiliary capacitor formed in each pixel. As shown in FIG. 3, each of the storage capacitor signal lines 22b is electrically connected to the storage capacitor wiring 24e via the contact portion 24ec.
　引き出し線２２ｃは、図３に示すように、ゲート信号線２２ａや保持容量信号線２２ｂを、端子領域１４に設けられた端子２２ｔ，２４ｔに引き出すための配線である。 As shown in FIG. 3, the lead line 22 c is a wiring for drawing the gate signal line 22 a and the storage capacitor signal line 22 b to the terminals 22 t and 24 t provided in the terminal region 14.
　図４に示すように，ゲート信号線２２ａのうちＴＦＴに対応する領域は，ゲート電極２２ｄとなるように形成されている。 As shown in FIG. 4, the region corresponding to the TFT in the gate signal line 22a is formed to be the gate electrode 22d.
　ゲート絶縁膜２３は，例えば，酸化ケイ素膜（ＳｉＯｘ膜）、窒化ケイ素膜（ＳｉＮｘ膜）等の無機絶縁膜により構成され，例えば０．４μｍ程度の厚さに形成されている。 The gate insulating film 23 is made of an inorganic insulating film such as a silicon oxide film (SiOx film) or a silicon nitride film (SiNx film), and has a thickness of about 0.4 μm, for example.
　ソース信号線２４ａを含む各信号線等の構成としては，図３に示すソース信号線２４ａ，非表示領域１２に設けられた引き出し線２４ｂ等の第２信号線，補助容量幹配線２４ｅ、図４に示すソース電極２４ｃ，ドレイン電極２４ｄ，図示しない検査用配線等が挙げられる。ソース信号線２４ａ等を構成する導電膜は，例えば，Ａｌ合金の単層膜，またはＡｌ膜，Ｃｕ膜，Ｍｏ膜，Ｔｉ膜若しくはこれらの積層膜によって構成されている。 As the configuration of each signal line including the source signal line 24a, the source signal line 24a shown in FIG. 3, the second signal line such as the lead line 24b provided in the non-display area 12, the auxiliary capacity trunk wiring 24e, FIG. Source electrode 24c, drain electrode 24d, and inspection wiring (not shown). The conductive film constituting the source signal line 24a and the like is made of, for example, an Al alloy single layer film, an Al film, a Cu film, a Mo film, a Ti film, or a laminated film thereof.
　ソース信号線２４ａは，図３に示すように，複数が互いに並行して延びるように配置されると共に，ゲート信号線２２ａのそれぞれと直交するように配置されている。ソース信号線２４ａは、ＴＦＴにデータ信号を与える機能を有する。 As shown in FIG. 3, a plurality of source signal lines 24a are arranged so as to extend in parallel with each other, and are arranged so as to be orthogonal to each of the gate signal lines 22a. The source signal line 24a has a function of supplying a data signal to the TFT.
　引き出し線２４ｂは、図３に示すように、ソース信号線２４ａを端子領域１４に設けられた端子２４ｔに引き出すための配線である。 As shown in FIG. 3, the lead line 24 b is a wiring for drawing the source signal line 24 a to the terminal 24 t provided in the terminal region 14.
　ソース電極２４ｃとドレイン電極２４ｄは、図３に示すように、ゲート電極２２ｄの上層に対向するように配置されている。 The source electrode 24c and the drain electrode 24d are disposed so as to face the upper layer of the gate electrode 22d as shown in FIG.
　第２絶縁膜２５（層間絶縁膜２５）は，例えば、酸化ケイ素膜（ＳｉＯｘ膜）、窒化ケイ素膜（ＳｉＮｘ膜）により構成されている。層間絶縁膜２５にはドレイン電極２４ｄに達するコンタクトホール２５ｃが形成されている。 The second insulating film 25 (interlayer insulating film 25) is composed of, for example, a silicon oxide film (SiOx film) and a silicon nitride film (SiNx film). A contact hole 25c reaching the drain electrode 24d is formed in the interlayer insulating film 25.
　画素電極２６ａを含む電極や配線の構成としては，図４に示す画素電極２６ａや保護膜２６ｂが挙げられる。画素電極２６ａ等を構成する導電膜の構成としては，例えば，ＩＴＯ（Indium Tin Oxide）やＩＺＯ（Indium Zinc Oxide）等の透明導電膜、Ａｌ合金、Ａｌ膜及びＭｏ膜の積層膜等によって構成されている。 As the configuration of the electrode and wiring including the pixel electrode 26a, the pixel electrode 26a and the protective film 26b shown in FIG. The conductive film constituting the pixel electrode 26a and the like is composed of a transparent conductive film such as ITO (IndiumＩＴＯTin Oxide) or IZO (Indium Zinc Oxide), a laminated film of an Al alloy, an Al film, and a Mo film, for example. ing.
　画素電極２６ａは，表示領域における各画素に対応するように設けられている。画素電極は，層間絶縁膜２５に設けられたコンタクトホール２５ｃの表面をも覆うように設けられ，これにより，ドレイン電極２４ｄと電気的に接続される。画素電極２６ａには、液晶層５０の液晶材料の配向のために、図４及び図７に示す細長形状の孔部２６ａｃが並行して複数設けられている。なお、この孔部２６ａｃは、本発明に必須の構成ではない。 The pixel electrode 26a is provided so as to correspond to each pixel in the display area. The pixel electrode is provided so as to cover the surface of the contact hole 25c provided in the interlayer insulating film 25, and is thereby electrically connected to the drain electrode 24d. The pixel electrode 26a is provided with a plurality of elongated holes 26ac shown in FIGS. 4 and 7 in parallel for alignment of the liquid crystal material of the liquid crystal layer 50. The hole 26ac is not an essential configuration for the present invention.
　保護膜２６ｂは，ゲート信号線２２ａや引き出し線２２ｃ等の第１信号線や、ソース信号線２４ａや引き出し線２４ｂ等の第２信号線に対応するように、当該信号線に沿って間欠的に設けられている。保護膜２６ｂは、他の配線と電気的に接続されていないフローティング状態となるように設けられている。保護膜２６ｂは、当該対応する信号線の幅方向の外側まで覆うように設けられている。 The protective film 26b is intermittently provided along the signal lines so as to correspond to the first signal lines such as the gate signal lines 22a and the lead lines 22c and the second signal lines such as the source signal lines 24a and the lead lines 24b. Is provided. The protective film 26b is provided in a floating state that is not electrically connected to other wiring. The protective film 26b is provided so as to cover the outside in the width direction of the corresponding signal line.
　保護膜２６ｂが第１信号線のうちゲート信号線２２ａに対応するように設けられている場合、図５に示すように、ゲート信号線２２ａの上層にはゲート絶縁膜２３及び層間絶縁膜２５が積層形成され、その上にさらに保護膜２６ｂが設けられることとなる。ゲート信号線２２ａと保護膜２６ｂとの間の絶縁膜の厚さ、すなわち、ゲート絶縁膜２３及び層間絶縁膜２５の厚さの合計が例えば０．２～１μｍ程度に薄い場合には、絶縁膜にピンホール等の欠陥が発生しやすくなるが、ゲート信号線２２ａに対応するように保護膜２６ｂが設けられているので、絶縁膜の欠陥部分からゲート信号線２２ａにエッチング液が浸入してゲート信号線２２ａが損傷を受ける問題が抑制される。 When the protective film 26b is provided so as to correspond to the gate signal line 22a among the first signal lines, as shown in FIG. 5, the gate insulating film 23 and the interlayer insulating film 25 are formed on the upper layer of the gate signal line 22a. A laminated film is formed, and a protective film 26b is further provided thereon. When the thickness of the insulating film between the gate signal line 22a and the protective film 26b, that is, the total thickness of the gate insulating film 23 and the interlayer insulating film 25 is as thin as about 0.2 to 1 μm, for example, However, since a protective film 26b is provided so as to correspond to the gate signal line 22a, an etching solution enters the gate signal line 22a from the defective portion of the insulating film, thereby causing a gate. The problem that the signal line 22a is damaged is suppressed.
　保護膜２６ｂは、ゲート信号線２２ａに沿った方向の長さが１０～５００μｍであることが好ましい。保護膜２６ｂのゲート信号線２２ａに沿った方向の長さが５００μｍ以下であるので、保護膜２６ｂと他の金属部材とのリークが発生しても、その影響は、ゲート信号線２２ａ上に設けられた保護膜全部に及ぶことがなく、寄生容量の増加量を抑制することができる。 The protective film 26b preferably has a length in the direction along the gate signal line 22a of 10 to 500 μm. Since the length of the protective film 26b in the direction along the gate signal line 22a is 500 μm or less, even if leakage occurs between the protective film 26b and another metal member, the influence is provided on the gate signal line 22a. Therefore, the increase in the parasitic capacitance can be suppressed without reaching the entire protective film.
　また、保護膜２６ｂと画素電極２６ａとの間の距離は、３～２０μｍであることが好ましい。両者がこれだけの距離を隔てることにより、保護膜２６ｂと画素電極２６ａとがリークして、画素電極２６ａの電位に影響するのを抑制することができる。 The distance between the protective film 26b and the pixel electrode 26a is preferably 3 to 20 μm. By separating the distances from each other, the protective film 26b and the pixel electrode 26a can be prevented from leaking and affecting the potential of the pixel electrode 26a.
　保護膜２６ｂが第２信号線のうちソース信号線２４ａに対応するように設けられている場合、図６に示すように、ソース信号線２４ａの上層には層間絶縁膜２５が積層形成され、その上にさらに保護膜２６ｂが設けられることとなる。ソース信号線２４ａと保護膜２６ｂとの間の絶縁膜の厚さ、すなわち、層間絶縁膜２５の厚さが例えば０．１～１μｍ程度に薄い場合には、絶縁膜にピンホール等の欠陥が発生しやすくなるが、ソース信号線２４ａに対応するように保護膜２６ｂが設けられているので、絶縁膜の欠陥部分からソース信号線２４ａにエッチング液が浸入してソース信号線２４ａが損傷を受ける問題が抑制される。 When the protective film 26b is provided so as to correspond to the source signal line 24a among the second signal lines, an interlayer insulating film 25 is formed on the source signal line 24a as shown in FIG. A protective film 26b is further provided thereon. When the thickness of the insulating film between the source signal line 24a and the protective film 26b, that is, the thickness of the interlayer insulating film 25 is as thin as about 0.1 to 1 μm, for example, the insulating film has defects such as pinholes. However, since the protective film 26b is provided so as to correspond to the source signal line 24a, the etchant enters the source signal line 24a from the defective portion of the insulating film, and the source signal line 24a is damaged. The problem is suppressed.
　保護膜２６ｂは、ソース信号線２４ａに沿った方向の長さが１０～５００μｍであることが好ましい。保護膜２６ｂのソース信号線２４ａに沿った方向の長さが５００μｍ以下であるので、保護膜２６ｂと他の金属部材とのリークが発生しても、その影響は、ソース信号線２４ａ上に設けられた保護膜全部に及ぶことがなく、寄生容量の増加量を抑制することができる。 The protective film 26b preferably has a length in the direction along the source signal line 24a of 10 to 500 μm. Since the length of the protective film 26b in the direction along the source signal line 24a is 500 μm or less, even if leakage occurs between the protective film 26b and another metal member, the influence is provided on the source signal line 24a. Therefore, the increase in the parasitic capacitance can be suppressed without reaching the entire protective film.
　また、保護膜２６ｂと画素電極２６ａとの間の距離は、３～２０μｍであることが好ましい。両者がこれだけの距離を隔てることにより、保護膜２６ｂと画素電極２６ａとがリークして、画素電極２６ａの電位に影響するのを抑制することができる。 The distance between the protective film 26b and the pixel electrode 26a is preferably 3 to 20 μm. By separating the distances from each other, the protective film 26b and the pixel electrode 26a can be prevented from leaking and affecting the potential of the pixel electrode 26a.
　保護膜２６ｂが第１信号線のうちの引き出し線２２ｃや、第２信号線のうちの引き出し線２４ｂに対応するように設けられている場合、図８に示すように、引き出し線２４ｂに沿った方向に間欠的に複数の保護膜２６ｂが設けられていることが好ましい。そして、間欠的に複数も受けられた保護膜２６ｂの長さは、１０～５００μｍであることが好ましい。保護膜２６ｂの引き出し線２４ｂに沿った方向の長さが５００μｍ以下であるので、保護膜２６ｂと他の金属部材とのリークが発生しても、その影響は、引き出し線２４ｂ上に設けられた保護膜全部に及ぶことがなく、寄生容量の増加量を抑制することができる。 When the protective film 26b is provided so as to correspond to the lead line 22c of the first signal line and the lead line 24b of the second signal line, as shown in FIG. A plurality of protective films 26b are preferably provided intermittently in the direction. The length of the protective film 26b that is intermittently received is preferably 10 to 500 μm. Since the length of the protective film 26b in the direction along the lead line 24b is 500 μm or less, even if a leak occurs between the protective film 26b and another metal member, the influence is provided on the lead line 24b. The amount of increase in parasitic capacitance can be suppressed without reaching the entire protective film.
　また、隣接する保護膜との間の距離が３～２０μｍであることが好ましい。隣接する保護膜２６ｂ同士がこれだけの距離を隔てることにより、両者とがリークして寄生容量が大幅に増加するのを抑制することができる。 Further, the distance between adjacent protective films is preferably 3 to 20 μm. When the adjacent protective films 26b are separated from each other by this distance, it is possible to prevent the two from leaking and greatly increasing the parasitic capacitance.
　なお、図３では、引き出し線２２ｃがゲート信号線２２ａと平行に設けられている図を示したが、特にこれに限られず、例えば、図９（ａ）に示すように、非表示領域１２に沿った方向に延びるように引き出し線２２ｃ、２４ｂが設けられていてもよい。この場合でも、図９（ｂ）に示すように、引き出し線２２ｃ、２４ｂに対応するように保護膜２６ｂを形成することができる。 FIG. 3 shows a drawing in which the lead line 22c is provided in parallel with the gate signal line 22a. However, the present invention is not limited to this. For example, as shown in FIG. Lead wires 22c and 24b may be provided so as to extend in the direction along the line. Even in this case, as shown in FIG. 9B, the protective film 26b can be formed so as to correspond to the lead lines 22c and 24b.
　基板本体２１上には，ゲート信号線２２ａとソース信号線２４ａとが交差する位置に各画素毎にＴＦＴが形成されている。ＴＦＴは，例えばボトムゲート型であり，ゲート電極２２ｄ，ゲート絶縁膜２３，及びゲート絶縁膜２３の表面に形成された半導体膜３１で構成されている。 On the substrate body 21, a TFT is formed for each pixel at a position where the gate signal line 22a and the source signal line 24a intersect. The TFT is, for example, a bottom gate type, and includes a gate electrode 22d, a gate insulating film 23, and a semiconductor film 31 formed on the surface of the gate insulating film 23.
　なお，ＴＦＴ基板２０の液晶層５０側表面には，配向膜（不図示）が形成されている。 An alignment film (not shown) is formed on the surface of the TFT substrate 20 on the liquid crystal layer 50 side.
　　（対向基板）
　対向基板３０は、カラーフィルタ（不図示）やブラックマトリクス（不図示）等が形成された絶縁性基板である矩形状のガラス基板（不図示）を有している。また、対向基板３０の液晶層５０側表面には、配向膜（不図示）が形成されている。 (Opposite substrate)
The counter substrate 30 has a rectangular glass substrate (not shown) that is an insulating substrate on which a color filter (not shown), a black matrix (not shown), and the like are formed. An alignment film (not shown) is formed on the surface of the counter substrate 30 on the liquid crystal layer 50 side.
　なお、本実施形態ではＴＦＴ基板２０に共通電極２１ａが設けられている場合について説明したが、ＴＦＴ基板２０に共通電極が設けられていない場合には対向基板３０の全面に共通電極が設けられる。 In the present embodiment, the case where the common electrode 21a is provided on the TFT substrate 20 has been described. However, when the common electrode is not provided on the TFT substrate 20, the common electrode is provided on the entire surface of the counter substrate 30.
　　（シール材）
　ＴＦＴ基板２０及び対向基板３０の間には、これらのＴＦＴ基板２０及び対向基板３０同士を互いに接着する枠形状のシール材４０が介在されている。シール材４０は、例えば紫外線硬化型のエポキシ系樹脂によって構成されている。 (Seal material)
Between the TFT substrate 20 and the counter substrate 30, a frame-shaped sealing material 40 that interposes the TFT substrate 20 and the counter substrate 30 is interposed. The sealing material 40 is made of, for example, an ultraviolet curable epoxy resin.
　　（液晶層）
　液晶層５０は、例えば、ネマチック液晶等で構成されている。 (Liquid crystal layer)
The liquid crystal layer 50 is made of, for example, nematic liquid crystal.
　　＜液晶表示装置の製造方法＞
　次に、上記ＴＦＴ基板２０及び液晶表示装置１０の製造方法について説明する。液晶表示装置１０は、それぞれ予め製造したＴＦＴ基板２０と対向基板３０とを液晶層５０及びシール材４０を介して貼り合わせることによって製造する。 <Method for manufacturing liquid crystal display device>
Next, a method for manufacturing the TFT substrate 20 and the liquid crystal display device 10 will be described. The liquid crystal display device 10 is manufactured by laminating a TFT substrate 20 and a counter substrate 30 that are manufactured in advance through a liquid crystal layer 50 and a sealing material 40, respectively.
　例えば対向基板３０にシール材４０を矩形枠状に描画し、そのシール材４０の枠内に液晶材料を滴下して供給する。次に、対向基板３０を位置合わせしてＴＦＴ基板２０に貼り合わせる。その後、シール材４０に紫外線を照射して当該シール材４０を硬化させ、液晶表示装置１０を製造する。 For example, the sealing material 40 is drawn in a rectangular frame shape on the counter substrate 30, and the liquid crystal material is dropped and supplied into the frame of the sealing material 40. Next, the counter substrate 30 is aligned and bonded to the TFT substrate 20. Thereafter, the sealing material 40 is irradiated with ultraviolet rays to cure the sealing material 40, and the liquid crystal display device 10 is manufactured.
　なお、シール材４０を描画するのは、対向基板３０でなく、ＴＦＴ基板２０であってもよい。 Note that the sealing material 40 may be drawn not on the counter substrate 30 but on the TFT substrate 20.
　また、本実施形態では、液晶材料の注入を滴下方式で行う場合について説明したが、枠状のシール部材に注入口（不図示）を形成し、ディップ式の真空注入を行った後に、その注入口を封止する方法を用いてもよい。 In the present embodiment, the case where the liquid crystal material is injected by the dropping method has been described. However, after an injection port (not shown) is formed in the frame-shaped sealing member and the dip vacuum injection is performed, the injection is performed. A method of sealing the inlet may be used.
　以下，ＴＦＴ基板２０の製造工程について詳細に説明する。ＴＦＴ基板の製造工程は，ゲート信号線形成工程，第１絶縁膜形成工程，ソース信号線２４ａ形成工程，第２絶縁膜形成工程，導電膜形成工程を備えている。 Hereinafter, the manufacturing process of the TFT substrate 20 will be described in detail. The TFT substrate manufacturing process includes a gate signal line forming process, a first insulating film forming process, a source signal line 24a forming process, a second insulating film forming process, and a conductive film forming process.
　　（ゲート信号線形成工程）
　まず，基板本体２１上に，ＩＴＯ膜等の透明導電膜を形成して画素毎に所定のレイアウトとなるようにパターンニングすることにより、共通電極２１ａを形成する。そして、公知のフォトリソ工程によって導電膜を設け，ゲート信号線２２ａ，保持容量信号線２２ｂ，引き出し線２２ｃ，ゲート電極２２ｄ等の配線や電極が形成される。このとき、保持容量信号線２２ｂは共通電極２１ａと接触するように形成される。 (Gate signal line formation process)
First, a transparent conductive film such as an ITO film is formed on the substrate body 21 and patterned so as to have a predetermined layout for each pixel, thereby forming the common electrode 21a. Then, a conductive film is provided by a known photolithography process, and wirings and electrodes such as a gate signal line 22a, a storage capacitor signal line 22b, a lead line 22c, and a gate electrode 22d are formed. At this time, the storage capacitor signal line 22b is formed in contact with the common electrode 21a.
　　（第１絶縁膜形成工程）
　次に，ゲート信号線２２ａ等を形成した基板本体２１上に，公知の方法を用いてゲート絶縁膜２３を形成する。 (First insulating film forming step)
Next, a gate insulating film 23 is formed on the substrate body 21 on which the gate signal lines 22a and the like are formed using a known method.
　　（半導体膜形成工程）
　次いで、ゲート絶縁膜２３上に、公知の方法を用いて所定の領域に、例えば真性半導体及びｎ＋半導体を積層形成することにより、半導体膜を形成する。 (Semiconductor film formation process)
Next, a semiconductor film is formed on the gate insulating film 23 by stacking, for example, an intrinsic semiconductor and an n + semiconductor in a predetermined region using a known method.
　　（ソース信号線２４ａ形成工程）
　続いて，ゲート絶縁膜２３上に，公知のフォトリソ工程によって導電膜を設ける。これにより，ソース信号線２４ａ，引き出し線２４ｂ，ソース電極２４ｃ，ドレイン電極２４ｄ等の配線や電極が形成される。 (Source signal line 24a forming step)
Subsequently, a conductive film is provided on the gate insulating film 23 by a known photolithography process. Thereby, wirings and electrodes such as the source signal line 24a, the lead line 24b, the source electrode 24c, and the drain electrode 24d are formed.
　　（第２絶縁膜形成工程）
　次いで，ソース信号線２４ａ等を形成したゲート絶縁膜２３上に，公知の方法を用いて層間絶縁膜２５を形成する。そして，層間絶縁膜２５のドレイン電極２４ｄに対応する領域に，コンタクトホール２５ｃを形成する。 (Second insulating film forming step)
Next, an interlayer insulating film 25 is formed on the gate insulating film 23 on which the source signal line 24a and the like are formed using a known method. Then, a contact hole 25c is formed in a region corresponding to the drain electrode 24d of the interlayer insulating film 25.
　　（画素電極形成工程）
　次に，画素電極２６ａや保護膜２６ｂを形成する。この画素電極形成工程について，図１０（ａ）～（ｆ）を用いて詳細に記述する。 (Pixel electrode formation process)
Next, the pixel electrode 26a and the protective film 26b are formed. This pixel electrode forming process will be described in detail with reference to FIGS.
　　―導電膜形成―
　まず，図１０（ａ）に示すように，公知の方法により層間絶縁膜２５上の全面を覆うように導電膜２６を成膜する。 -Conductive film formation-
First, as shown in FIG. 10A, a conductive film 26 is formed so as to cover the entire surface of the interlayer insulating film 25 by a known method.
　　―レジスト形成―
　次に、図１０（ｂ）に示すように、導電膜２６の上層の全面にレジスト材料を成膜して、レジスト膜とする。そして、図１０（ｃ）に示すように、画素電極２６ａや保護膜２６ｂを形成しようとする領域以外の領域に対応するように開口部を有するエッチングマスクＭを使用して、レジスト膜を露光した後現像を行い、レジストＲを形成する。これにより、図１０（ｄ）に示すように、レジストＲは、導電膜２６のうち画素電極２６ａや保護膜２６ｂを形成する領域を覆うように設けられることとなる。 -Resist formation-
Next, as shown in FIG. 10B, a resist material is formed on the entire upper surface of the conductive film 26 to form a resist film. Then, as shown in FIG. 10C, the resist film was exposed using an etching mask M having an opening so as to correspond to a region other than the region where the pixel electrode 26a and the protective film 26b are to be formed. Post-development is performed to form a resist R. Thus, as shown in FIG. 10D, the resist R is provided so as to cover the region of the conductive film 26 where the pixel electrode 26a and the protective film 26b are to be formed.
　　―エッチング―
　続いて、上記形成したレジストＲの開口部Ｒｃを介して、ウェットエッチングにより導電膜２６のエッチングを行う。これにより、図１０（ｅ）に示すように、導電膜２６のうち、画素電極や保護膜以外の部分は除去される。 -etching-
Subsequently, the conductive film 26 is etched by wet etching through the opening Rc of the resist R formed as described above. Thereby, as shown in FIG. 10E, portions of the conductive film 26 other than the pixel electrode and the protective film are removed.
　このエッチング工程においては、例えば、酸エッチング（ＳＬＡ：Sand-blasted Large-grit Acid-etched）や塩化第２鉄等をエッチング液として用いることができる。 In this etching process, for example, acid etching (SLA: Sand-blasted Large-grit Acid-etched) or ferric chloride can be used as an etching solution.
　　―レジスト除去―
　最後に、導電膜の画素電極２６ａや保護膜２６ｂ上に残ったレジストを、レジスト剥離液を用いて剥離することにより、レジストの除去を行う。これにより、図１０（ｆ）に示すように、画素電極２６ａ及び保護膜２６ｂが形成される。 ―Resist removal―
Finally, the resist remaining on the pixel electrode 26a and the protective film 26b of the conductive film is stripped using a resist stripping solution to remove the resist. Thereby, as shown in FIG. 10F, the pixel electrode 26a and the protective film 26b are formed.
　以上の工程により、ＴＦＴ基板２０が得られる。 Through the above steps, the TFT substrate 20 is obtained.
　　（実施形態１の効果）
　実施形態１の構成のＴＦＴ基板２０によれば、層間絶縁膜２５の上層にはゲート信号線２２ａや引き出し線２２ｃ等の第１信号線、及びソース信号線２４ａや引き出し線２４ｂ等の第２信号線に対応するように、画素電極２６ａと同一の材料で形成された保護膜２６ｂをパターンニングするためのレジストが設けられているので、第１信号線上のゲート絶縁膜２３及び層間絶縁膜２５、或いは、第２信号線上の層間絶縁膜２５にピンホール等の欠陥があっても、画素電極を構成する導電膜のエッチング時、エッチング液が絶縁膜の欠陥を介して第１信号線や第２信号線に到達するのを抑制することができる。従って、エッチング液によって第１信号線や第２信号線が損傷を受けるのを抑制することができ、ＴＦＴ基板２０の良好な歩留まりを得ることができる。 (Effect of Embodiment 1)
According to the TFT substrate 20 having the configuration of the first embodiment, the first signal line such as the gate signal line 22a and the lead line 22c and the second signal such as the source signal line 24a and the lead line 24b are formed on the interlayer insulating film 25. Since the resist for patterning the protective film 26b formed of the same material as the pixel electrode 26a is provided so as to correspond to the line, the gate insulating film 23 and the interlayer insulating film 25 on the first signal line, Alternatively, even if the interlayer insulating film 25 on the second signal line has a defect such as a pinhole or the like, when the conductive film constituting the pixel electrode is etched, the etchant passes through the defect of the insulating film to the first signal line or the second signal line. Reaching the signal line can be suppressed. Therefore, the first signal line and the second signal line can be prevented from being damaged by the etching solution, and a good yield of the TFT substrate 20 can be obtained.
　また、第１信号線及び第２信号線に対応するように設けられた保護膜２６ｂが、他の配線と電気的に接続されていないフローティング状態であるので、他の画素電極２６ａ等の構成により形成される寄生容量に影響を与えるのが抑制される。 Further, since the protective film 26b provided so as to correspond to the first signal line and the second signal line is in a floating state in which it is not electrically connected to other wiring, the structure of the other pixel electrode 26a or the like is used. An influence on the formed parasitic capacitance is suppressed.
　さらに、第１信号線及び第２信号線に対応するように設けられた保護膜２６ｂは、当該対応する信号線に沿って間欠的に設けられているので、保護膜２６ｂが他の金属部材とリークした場合に、保護膜２６ｂが間欠部分を有さない場合よりも寄生容量の増加を抑制することができる。特に、ＴＦＴ基板２０の非表示領域１２においては、各信号線が隣接して並行するように配置されていることが多く、隣接する信号線の上層には並行して保護膜２６ｂが隣接して設けられることとなるが、保護膜２６ｂが信号線に沿って間欠的に設けられているので、隣接する保護膜２６ｂ同士がリークして寄生容量が増加しても、当該隣接保護膜２６ｂ同士がリークしたことによる寄生容量の増加を大幅に抑制することができる。 Furthermore, since the protective film 26b provided so as to correspond to the first signal line and the second signal line is provided intermittently along the corresponding signal line, the protective film 26b is connected to other metal members. In the case of leakage, an increase in parasitic capacitance can be suppressed as compared with the case where the protective film 26b does not have an intermittent portion. In particular, in the non-display region 12 of the TFT substrate 20, the signal lines are often arranged adjacent to each other in parallel, and the protective film 26b is adjacent to the upper layer of the adjacent signal lines. Although the protective film 26b is intermittently provided along the signal line, even if the adjacent protective films 26b leak and the parasitic capacitance increases, the adjacent protective films 26b An increase in parasitic capacitance due to leakage can be significantly suppressed.
　そして、本実施形態１にかかるＴＦＴ基板２０を液晶表示装置１０に適用することにより、液晶表示装置１０についても良好な歩留まりを得ることができる。 Then, by applying the TFT substrate 20 according to the first embodiment to the liquid crystal display device 10, it is possible to obtain a good yield also for the liquid crystal display device 10.
　　＜実施形態１の変形例＞
　なお、実施形態１では、保護膜２６ｂは、対応する信号線の幅方向の外側まで覆うように設けられているとしたが、層間絶縁膜２５の上層に各信号線に対応するように設けられていればよい。但し、信号線の幅方向の断面の端部においては、その上層に設けられる絶縁膜が薄くなっている場合が多く、そのため、絶縁膜にピンホール等が発生しやすくなっているため、絶縁膜が薄くなっている部分を保護する観点からは、保護膜２６ｂは、信号線の幅方向の外側まで覆うように設けられていることが好ましい。 <Modification of Embodiment 1>
In the first embodiment, the protective film 26b is provided so as to cover the outside in the width direction of the corresponding signal line. However, the protective film 26b is provided above the interlayer insulating film 25 so as to correspond to each signal line. It only has to be. However, at the end of the cross section in the width direction of the signal line, the insulating film provided in the upper layer is often thin, and therefore it is easy for pinholes and the like to occur in the insulating film. From the viewpoint of protecting the thinned portion, the protective film 26b is preferably provided so as to cover the outside in the width direction of the signal line.
　また、図１１に示すように、ソース信号線２４ａに対応するように設ける保護膜２６ｂが、１つの画素の１辺においても複数の保護膜２６ｂから形成されるように設けられていてもよい。この場合、ある保護膜２６ｂが画素電極２６ａとリークしたり、ある保護膜２６ｂに欠損部分が生じたりしても、他の保護膜２６ｂにその影響は及ばないので、当該リークや欠損による特性の劣化を抑制することができる。但し、保護膜２６ｂ間に、ソース信号線２４ａが保護膜２６ｂで覆われない部分ができてしまう点からは、保護膜２６ｂ１つあたりの面積を小さくしすぎることは好ましくない。 Further, as shown in FIG. 11, the protective film 26b provided so as to correspond to the source signal line 24a may be provided so as to be formed of a plurality of protective films 26b on one side of one pixel. In this case, even if a certain protective film 26b leaks with the pixel electrode 26a or a defective portion occurs in a certain protective film 26b, the other protective film 26b is not affected. Deterioration can be suppressed. However, it is not preferable to make the area per protective film 26b too small because a portion where the source signal line 24a is not covered with the protective film 26b is formed between the protective films 26b.
　また、図１２に示すように、ゲート電極２２ｄ上に設ける導電膜を保護膜２６ｂとして独立させないで、画素電極２６ａの一部として画素電極２６ａと一体に形成してもよい。但し、画素電極２６ａがゲート電極２２ｄの電界の影響を受けるため、図４に示すように、ゲート信号線２２ａ上に設ける導電膜（保護膜２６ｂ）と画素電極２６ａとは、分離して形成することが好ましい。 Further, as shown in FIG. 12, the conductive film provided on the gate electrode 22d may be formed integrally with the pixel electrode 26a as a part of the pixel electrode 26a without being independent as the protective film 26b. However, since the pixel electrode 26a is affected by the electric field of the gate electrode 22d, as shown in FIG. 4, the conductive film (protective film 26b) provided on the gate signal line 22a and the pixel electrode 26a are formed separately. It is preferable.
　　＜その他の実施形態＞
　実施形態１では、本発明のアクティブマトリックス基板であるＴＦＴ基板２０を用いて液晶表示装置１０を構成する場合について説明したが、特にこれに限られず、例えば有機ＥＬ表示装置等の表示装置に本発明のＴＦＴ基板２０を用いてもよい。 <Other embodiments>
In the first embodiment, the case where the liquid crystal display device 10 is configured using the TFT substrate 20 which is the active matrix substrate of the present invention has been described. However, the present invention is not limited to this, and the present invention is applied to a display device such as an organic EL display device. The TFT substrate 20 may be used.
　また、実施形態１では、本発明のアクティブマトリックス基板であるＴＦＴ基板２０を用いて液晶表示装置１０を構成する場合について説明したが、特にこれに限られない。例えば、Ｘ線センサ装置や電子ペーパーを構成するＴＦＴ基板として本発明のアクティブマトリックス基板を用いてもよい。 In the first embodiment, the case where the liquid crystal display device 10 is configured using the TFT substrate 20 that is the active matrix substrate of the present invention has been described. However, the present invention is not limited to this. For example, the active matrix substrate of the present invention may be used as a TFT substrate constituting an X-ray sensor device or electronic paper.
　Ｘ線センサ装置に用いるＴＦＴ基板としては、例えば、図１３に示すＴＦＴ基板１２０を用いることができる。この場合にも、各信号線に対応するように層間絶縁膜２５の上層に保護膜１２６ｂが設けられているので、画素電極１２６ａを構成する導電膜のエッチング時に絶縁膜の欠陥部分からエッチング液が侵入して信号線が損傷を受ける問題を抑制することができ、ＴＦＴ基板の歩留まりが低下するのを抑制することができる。 As the TFT substrate used in the X-ray sensor device, for example, a TFT substrate 120 shown in FIG. 13 can be used. Also in this case, since the protective film 126b is provided above the interlayer insulating film 25 so as to correspond to each signal line, the etching solution is supplied from the defective portion of the insulating film when the conductive film constituting the pixel electrode 126a is etched. It is possible to suppress a problem that the signal line is damaged due to intrusion, and it is possible to suppress a decrease in the yield of the TFT substrate.
　また、本発明のアクティブマトリックス基板を電子ペーパーのＴＦＴ基板として採用する場合にも、例えば、図１３に示すレイアウトのＴＦＴ基板１２０を用いることができる。この場合にも、各信号線に対応するように層間絶縁膜１２５の上層に保護膜１２６ｂが設けられているので、画素電極１２６ａを構成する導電膜のエッチング時に絶縁膜の欠陥部分からエッチング液が侵入して信号線が損傷を受ける問題を抑制することができ、ＴＦＴ基板の歩留まりが低下するのを抑制することができる。 Also, when the active matrix substrate of the present invention is adopted as a TFT substrate of electronic paper, for example, a TFT substrate 120 having a layout shown in FIG. 13 can be used. Also in this case, since the protective film 126b is provided above the interlayer insulating film 125 so as to correspond to each signal line, the etching solution is supplied from the defective portion of the insulating film when the conductive film constituting the pixel electrode 126a is etched. It is possible to suppress a problem that the signal line is damaged due to intrusion, and it is possible to suppress a decrease in the yield of the TFT substrate.
　本発明は、アクティブマトリックス基板、アクティブマトリックス基板の製造方法、及びそのアクティブマトリックス基板を備えた液晶表示装置について有用であり、特に、信号線を保護することにより優れた歩留まりや信頼性を有するアクティブマトリックス基板、アクティブマトリックス基板の製造方法、及びそのアクティブマトリックス基板を備えた液晶表示装置について有用である。 INDUSTRIAL APPLICABILITY The present invention is useful for an active matrix substrate, a method for manufacturing the active matrix substrate, and a liquid crystal display device including the active matrix substrate, and in particular, an active matrix having excellent yield and reliability by protecting signal lines. The present invention is useful for a substrate, a method for manufacturing an active matrix substrate, and a liquid crystal display device including the active matrix substrate.
　　　　　２０　　　ＴＦＴ基板（アクティブマトリックス基板）
　　　　　２１　　　基板本体
　　　　　２２ａ　　ゲート信号線（第１信号線）
　　　　　２２ｃ　　引き出し線（第１信号線）
　　　　　２２ｄ　　ゲート電極
　　　　　２３　　　ゲート絶縁膜（第１絶縁膜）
　　　　　２４ａ　　ソース信号線
　　　　　２４ｂ　　引き出し線（第１信号線）
　　　　　２５　　　層間絶縁膜（第２絶縁膜）
　　　　　２６ａ　　画素電極
　　　　　２６ｂ　　保護膜
　　　　　３０　　　対向基板
　　　　　５０　　　液晶層
　　　　　Ｍ　　　　エッチングマスク
　　　　　Ｒ　　　　レジスト 20 TFT substrate (active matrix substrate)
21 Substrate body 22a Gate signal line (first signal line)
22c Lead line (first signal line)
22d Gate electrode 23 Gate insulating film (first insulating film)
24a Source signal line 24b Lead line (first signal line)
25 Interlayer insulation film (second insulation film)
26a pixel electrode 26b protective film 30 counter substrate 50 liquid crystal layer M etching mask R resist

Claims (12)

  1. 　基板本体と、
    　上記基板本体上に設けられた第１信号線と、
    　上記基板本体及び第１信号線を覆うように設けられた第１絶縁膜と、
    　上記第１絶縁膜上に設けられた第２信号線と、
    　上記第１絶縁膜及び第２信号線を覆うように設けられた第２絶縁膜と、
    　上記第２絶縁膜上に設けられた画素電極と、
    を備え、上記第１信号線及び第２信号線が交差する部分にスイッチング素子が構成されたアクティブマトリックス基板であって、
    　上記第２絶縁膜の上層には、上記第１信号線及び第２信号線に対応するように、上記画素電極と同一の材料で形成されるフローティング状態の保護膜が、該対応する信号線に沿って間欠的に設けられていることを特徴とするアクティブマトリックス基板。     A substrate body;
    A first signal line provided on the substrate body;
    A first insulating film provided to cover the substrate body and the first signal line;
    A second signal line provided on the first insulating film;
    A second insulating film provided to cover the first insulating film and the second signal line;
    A pixel electrode provided on the second insulating film;
    An active matrix substrate in which a switching element is configured at a portion where the first signal line and the second signal line intersect with each other,
    A floating protective film formed of the same material as that of the pixel electrode is formed on the second insulating film so as to correspond to the first signal line and the second signal line. An active matrix substrate provided intermittently along the active matrix substrate.
  2. 　請求項１に記載されたアクティブマトリックス基板において、
    　上記保護膜は、上記第１信号線または第２信号線の幅方向の外側まで覆っていることを特徴とするアクティブマトリックス基板。     The active matrix substrate according to claim 1,
    The active matrix substrate, wherein the protective film covers the outside in the width direction of the first signal line or the second signal line.
  3. 　請求項１または２に記載されたアクティブマトリックス基板において、
    　上記隣り合う保護膜同士は、３～２０μｍの距離を隔てていることを特徴とするアクティブマトリックス基板。     The active matrix substrate according to claim 1 or 2,
    An active matrix substrate, wherein the adjacent protective films are separated by a distance of 3 to 20 μm.
  4. 　請求項１～３のいずれかに記載されたアクティブマトリックス基板において、
    　上記保護膜のそれぞれは、上記第１信号線及び第２信号線のいずれかに沿った方向の長さが１０～５００μｍであることを特徴とするアクティブマトリックス基板。     The active matrix substrate according to any one of claims 1 to 3,
    Each of the protective films has a length in a direction along one of the first signal line and the second signal line of 10 to 500 μm.
  5. 　請求項１～４のいずれかに記載されたアクティブマトリックス基板において、
    　上記複数の保護膜のうち上記第２信号線の上層に設けられた保護膜と、該第２信号線と、の間に配された第２絶縁膜の厚さが、０．１～１μｍであることを特徴とするアクティブマトリックス基板。     The active matrix substrate according to any one of claims 1 to 4,
    Of the plurality of protective films, the thickness of the protective film provided above the second signal line and the second insulating film disposed between the second signal line is 0.1 to 1 μm. An active matrix substrate characterized in that:
  6. 　請求項１～５のいずれかに記載されたアクティブマトリックス基板において、
    　上記複数の保護膜のうち上記第１信号線の上層に設けられた保護膜と、該第１信号線と、の間に配された第１絶縁膜及び第２絶縁膜の厚さの和が、０．２～１μｍであることを特徴とするアクティブマトリックス基板。     The active matrix substrate according to any one of claims 1 to 5,
    Of the plurality of protective films, the sum of the thicknesses of the first insulating film and the second insulating film disposed between the protective film provided on the first signal line and the first signal line is An active matrix substrate characterized by having a thickness of 0.2 to 1 μm.
  7. 　請求項１～６のいずれかに記載されたアクティブマトリックス基板において、
    　上記第１信号線の一部は、上記スイッチング素子に制御信号を与えるゲート信号線であることを特徴とするアクティブマトリックス基板。     The active matrix substrate according to any one of claims 1 to 6,
    An active matrix substrate, wherein a part of the first signal line is a gate signal line for supplying a control signal to the switching element.
  8. 　請求項１～７のいずれかに記載されたアクティブマトリックス基板において、
    　上記第２信号線の一部は、上記スイッチング素子にデータ信号を与えるソース信号線であることを特徴とするアクティブマトリックス基板。     The active matrix substrate according to any one of claims 1 to 7,
    An active matrix substrate, wherein a part of the second signal line is a source signal line for supplying a data signal to the switching element.
  9. 　請求項１～８のいずれかに記載されたアクティブマトリックス基板において、
    　上記第１信号線及び第２信号線の一部は、ゲート信号線及びソース信号線を額縁領域に引き出す引き出し線であることを特徴とするアクティブマトリックス基板。     The active matrix substrate according to any one of claims 1 to 8,
    An active matrix substrate, wherein a part of the first signal line and the second signal line is a lead line for drawing out a gate signal line and a source signal line to a frame region.
  10. 　基板本体上の第１信号線を形成する第１信号線形成工程と、
    　上記基板本体及び第１信号線を覆うように第１絶縁膜を形成する第１絶縁膜形成工程と、
    　上記基板本体及び第１信号線上に半導体膜を形成する半導体膜形成工程と、
    　上記第１絶縁膜上の第２信号線を形成する第２信号線形成工程と、
    　上記第１絶縁膜及び第２信号線を覆うように第２絶縁膜を形成する第２絶縁膜形成工程と、
    　上記第２絶縁膜の画素電極及び保護膜を形成する画素電極形成工程と、
    を備え、請求項１に記載されたアクティブマトリックス基板を製造するアクティブマトリックス基板の製造方法であって、
    　上記画素電極形成工程では、
    　上記第２絶縁膜上に導電膜を成膜した後、
    　上記導電膜上の全面にレジストを塗布し、続いて、画素電極及び保護膜を配置しようとする領域以外の領域に対応する開口部を有するマスクを使用して、上記レジストの露光及び現像を行うことによりレジストを形成し、
    　次いで、上記形成したレジストをマスクとしてエッチングを行って、上記導電膜のうち該レジストの開口部に対応する領域を除去し、
    　さらに、上記導電膜上のレジストを除去する
    ことにより、上記画素電極を形成すると共に上記保護膜を形成することを特徴とするアクティブマトリックス基板の製造方法。     A first signal line forming step of forming a first signal line on the substrate body;
    A first insulating film forming step of forming a first insulating film so as to cover the substrate body and the first signal line;
    A semiconductor film forming step of forming a semiconductor film on the substrate body and the first signal line;
    A second signal line forming step of forming a second signal line on the first insulating film;
    A second insulating film forming step of forming a second insulating film so as to cover the first insulating film and the second signal line;
    A pixel electrode forming step of forming a pixel electrode and a protective film of the second insulating film;
    An active matrix substrate manufacturing method for manufacturing the active matrix substrate according to claim 1, comprising:
    In the pixel electrode formation step,
    After forming a conductive film on the second insulating film,
    A resist is applied to the entire surface of the conductive film, and then the resist is exposed and developed using a mask having an opening corresponding to a region other than the region where the pixel electrode and the protective film are to be disposed. To form a resist,
    Next, etching is performed using the formed resist as a mask to remove a region of the conductive film corresponding to the opening of the resist,
    Furthermore, by removing the resist on the conductive film, the pixel electrode is formed and the protective film is formed.
  11. 　請求項１０に記載されたアクティブマトリックス基板の製造方法において、
    　上記レジスト形成ステップにおいて、保護膜を配置する領域が上記第１信号線及び第２信号線の幅方向の外側まで覆う領域となるように設定したマスクを使用して、上記レジストの露光及び現像を行うことを特徴とするアクティブマトリックス基板の製造方法。     In the manufacturing method of the active-matrix board | substrate described in Claim 10,
    In the resist forming step, exposure and development of the resist are performed using a mask that is set so that a region where the protective film is disposed is a region that covers the outside in the width direction of the first signal line and the second signal line. A method for producing an active matrix substrate, comprising:
  12. 　請求項１に記載されたアクティブマトリックス基板と、
    　上記アクティブマトリックス基板と対向配置された対向基板と、
    　上記アクティブマトリックス基板と対向基板との間に設けられた液晶層と、
    を備えたことを特徴とする液晶表示装置。     An active matrix substrate according to claim 1;
    A counter substrate disposed opposite to the active matrix substrate;
    A liquid crystal layer provided between the active matrix substrate and the counter substrate;
    A liquid crystal display device comprising:
PCT/JP2011/005548 2010-10-08 2011-09-30 Active matrix substrate, method for manufacturing active matrix substrate, and liquid crystal display device WO2012046427A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-228189 2010-10-08
JP2010228189 2010-10-08

Publications (1)

Publication Number Publication Date
WO2012046427A1 true WO2012046427A1 (en) 2012-04-12

Family

ID=45927434

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/005548 WO2012046427A1 (en) 2010-10-08 2011-09-30 Active matrix substrate, method for manufacturing active matrix substrate, and liquid crystal display device

Country Status (1)

Country Link
WO (1) WO2012046427A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362923A (en) * 1991-01-30 1992-12-15 Nec Corp Liquid crystal display element
JPH10161149A (en) * 1996-12-05 1998-06-19 Toshiba Corp Manufacture of array substrate for display device
JP2000171832A (en) * 1998-12-01 2000-06-23 Casio Comput Co Ltd Display panel and its manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362923A (en) * 1991-01-30 1992-12-15 Nec Corp Liquid crystal display element
JPH10161149A (en) * 1996-12-05 1998-06-19 Toshiba Corp Manufacture of array substrate for display device
JP2000171832A (en) * 1998-12-01 2000-06-23 Casio Comput Co Ltd Display panel and its manufacture

Similar Documents

Publication Publication Date Title
KR100884118B1 (en) Electro?optical device, electronic apparatus, and method of manufacturing electro?optical device
JP4277874B2 (en) Manufacturing method of electro-optical device
EP3488478B1 (en) Method of fabricating display panel
JP5392670B2 (en) Liquid crystal display device and manufacturing method thereof
US10444579B2 (en) Display substrate and manufacturing method thereof, and display device
US9366923B2 (en) Array substrate and method of fabricating the same, and display device
JP2008026869A (en) Display device
WO2014034512A1 (en) Thin film transistor substrate and display device
JP5450825B2 (en) Active matrix substrate, method for manufacturing the same, and display device
JP2007293072A (en) Method of manufacturing electro-optical device and the electro-optical device, and electronic equipment
US9064751B2 (en) Thin film transistor array substrate and manufacturing method thereof
JP5275517B2 (en) Substrate, manufacturing method thereof, and display device
JP2007212812A (en) Electrooptical device
JP5243665B2 (en) Manufacturing method of display device
JP2007293073A (en) Method of manufacturing electrooptical device and electrooptical device, and electronic equipment
JP2007013083A (en) Thin film transistor and its manufacturing method
US9224824B2 (en) Display device substrate and display device equipped with same
US9684216B2 (en) Pixel structure and fabrication method thereof
WO2012046427A1 (en) Active matrix substrate, method for manufacturing active matrix substrate, and liquid crystal display device
KR100558713B1 (en) Liquid crystal display panel apparatus of horizontal electronic field applying type and fabricating method thereof
KR100637061B1 (en) Liquid crystal display panel of horizontal electronic field applying type and fabricating method thereof
KR20140095357A (en) Thin film transistor array substrate and method for manufacturing the same
WO2013076940A1 (en) Active matrix substrate and liquid crystal display device
JP2008275940A (en) Electro-optical device, manufacturing method thereof and electronic equipment
JP4910706B2 (en) Manufacturing method of electro-optical device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11830361

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11830361

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP