WO2012041694A1 - Circuit de commande d'un transistor à effet de champ à jonction - Google Patents

Circuit de commande d'un transistor à effet de champ à jonction Download PDF

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Publication number
WO2012041694A1
WO2012041694A1 PCT/EP2011/065822 EP2011065822W WO2012041694A1 WO 2012041694 A1 WO2012041694 A1 WO 2012041694A1 EP 2011065822 W EP2011065822 W EP 2011065822W WO 2012041694 A1 WO2012041694 A1 WO 2012041694A1
Authority
WO
WIPO (PCT)
Prior art keywords
effect transistor
field effect
quadrupole
circuit arrangement
gate
Prior art date
Application number
PCT/EP2011/065822
Other languages
German (de)
English (en)
Inventor
Oliver Heid
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to RU2012101462/08A priority Critical patent/RU2591013C2/ru
Publication of WO2012041694A1 publication Critical patent/WO2012041694A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2176—Class E amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/07—Shaping pulses by increasing duration; by decreasing duration by the use of resonant circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/12—Shaping pulses by steepening leading or trailing edges

Definitions

  • the present invention relates to a circuit arrangement for driving a junction field effect transistor according to the preamble of patent claim 1, a method for driving a junction field effect transistor according to the preamble of patent claim 7, and an amplifier for amplifying an electrical signal according to the preamble of patent claim 9.
  • junction field effect transistors are known in the art. Field effect transistors are semiconductor switches that can be controlled without power with an electric field. In junction field-effect transistors ⁇ a control electrode (gate) by a pn or np junction of the channel between the source contact (source) and the drain contact (drain) is separated. In blocking ⁇ layer field effect transistors, the largest drain current flows when a control voltage of 0 volts is applied between the gate and source. They are therefore referred to as self-conducting. Junction field effect transistors have a substantially quadratic control characteristic.
  • the object of the present invention is therefore to provide an improved circuit arrangement for driving a junction field effect transistor. This object is achieved by a circuit arrangement with the features of claim 1. It is further object of the present ⁇ invention to provide an improved method for driving a
  • a circuit arrangement for driving a junction field-effect transistor having a gate terminal comprises a driver which is designed to generate a voltage signal with a defined frequency.
  • the circuit arrangement further comprises a quadrupole having an input terminal connected to the driver and an output terminal connected to the gate terminal and having a transfer function having a pole at an odd multiple of the frequency.
  • this circuit arrangement causes an increase in the edge steepness of the control signal. Characterized a transition ⁇ time is shortened between a control and a blocking phase of the Feldef ⁇ Anlagentransistors, whereby the power loss of the field effect transistor decreases.
  • the voltage signal is sinusoidal. Before ⁇ geous enough, the circuit then causes a change of the voltage signal towards a rechteckförmi- Geren course.
  • the voltage signal has a peak value which exceeds a gate breakdown voltage of the field effect transistor.
  • the distance between the gate contact and the source contact of the junction field effect transistor behaves similar to a Zener diode. This diode limits the control signal, whereby unacceptably high currents are avoided and a Re ⁇ sonanzschwingung the quadrupole is triggered.
  • the quadrupole has a parallel resonant circuit.
  • a parallel resonant circuit can be easily adapted to ⁇ .
  • circuit arrangement of the four-pole has a plurality of series-connected Paral ⁇ lelschwing Vietnamesee.
  • hö ⁇ here harmonic orders can be excited then, whereby the power supplied to the field effect transistor control signal can still make quite ⁇ square.
  • the quadrupole has a cavity resonator.
  • a cavity resonator is particularly suitable for high frequencies.
  • An inventive method for driving an insulated gate field effect transistor which has a gate terminal ⁇ is characterized in that the gate terminal is connected to an output terminal of a two-port circuit, a one ⁇ through terminal of the quadripole with a voltage signal having a predetermined frequency is applied, and the quadrupole has a transfer function having a pole at an odd multiple of the frequency.
  • this method is suitable to operate the junction field effect transistor ⁇ with a signal with an increased slope. This shortens the transitional period between the leading and the blocking phase of the field effect transistor. gate, whereby the power loss of the field effect transistor decreases.
  • the voltage signal has a peak value which exceeds a gate breakdown voltage of the field effect transistor.
  • the voltage signal then triggers a resonant oscillation of the quadrupole, which is superimposed with the voltage signal in such a way that a more rectangular signal is produced.
  • the intrinsic gate-source diode of the field effect transistor limits the control signal without causing excessive currents.
  • An inventive amplifier for amplifying an electrical signal has a circuit arrangement of the type described above.
  • this amplifier has a reduced power loss.
  • the amplifier is a class F amplifier.
  • such amplifiers provide high efficiency and good gain characteristics.
  • FIG. 1 is a schematic representation of an amplifier
  • Figure 2 shows two characteristics of a junction field effect transistor
  • Figure 3 is a schematic representation of the Fourier synthesis
  • FIG. 5 shows a schematic drive circuit according to a second embodiment; and an illustration of electrical characteristics of a drive circuit according to the invention which is triggered by a junction field effect transistor.
  • FIG. 1 shows a schematic representation of an amplifier circuit 100.
  • the amplifier circuit 100 is a source circuit.
  • the amplifier circuit 100 may be, for example, a class F amplifier.
  • the amplifier circuit 100 can be used for power amplification of high-frequency signals.
  • the amplifier circuit 100 includes a junction field effect transistor (JFET) 110.
  • the junction field effect transistor 110 is an n-channel field effect transistor.
  • the invention can also be applied to p-channel field-effect transistors.
  • the field effect transistor 110 has a control contact (gate contact) 120, a source contact (source contact) 130 and a drain contact (drain contact) 140.
  • the source contact 130 is connected to a ground contact 150. Between the gate contact 120 and the source contact 130 or the ground contact 150, a control voltage for controlling the field effect transistor 110 can be applied.
  • the drain contact 140 is connected to a power supply contact 180. Between the power supply contact 180 and the ground contact 150, a supply voltage to the
  • a throttle not shown in Figure 1 or a similar Bauele ⁇ ment can be inserted to limit the current.
  • the drain contact 140 is connected to the ground contact 150 via an output network 160 and a load 170. Between the drain contact 140 and the ground contact 150, an output voltage 142 may be measured. If a control signal with a sinusoidal voltage profile is applied between the gate contact 120 and the ground contact 150, an output voltage 142 results which differs from zero only approximately during every second half-cycle of the control signal. During the rest of the time, the source-drain path of the field effect transistor 110 is turned on, so that no output voltage 142 drops.
  • the output network 160 characterizes the amplifier scarf ⁇ processing 100.
  • a class F amplifier driving the output network formed 160 a current flowing at the drain contact 140, drain power 141 so that it has a non-zero semi-sinusoidal curve only when the output voltage 142 is approximately equal to zero.
  • the source-drain path of the field ⁇ effect transistor 110 is high impedance and there is no drain current 141th
  • both the output voltage 142 and the drain current 141 are greater than zero only during short switching phases. Only during these switching phases does a power loss occur at the field effect transistor 110. In order to further reduce the power loss, the fastest possible switching of the field effect transistor 110 between the open and the closed state is desirable. To this end, the profile of the output voltage 142 should have steep edges in the region in which the output voltage 142 is different from zero, so that the field effect transistor 110 as soon as possible from the conductive to the locked and the locked in the conductive state.
  • Figure 2 shows a schematic representation of two characteristics of the junction field effect transistor 110.
  • the upper graph of FIG. 2 shows the drain current 141 flowing into the drain contact 140 as a function of the gate-source voltage 121.
  • the lower graph of FIG. 2 shows a gate current 122 flowing into the gate contact 120 in dependence the gate-source voltage 121.
  • the junction field effect transistor 110 has an approximately quadratic characteristic. This means that the drain current 141 grows approximately quadratically with decreasing negative gate-source voltage 121.
  • This quadratic characteristic has the disadvantage that with a sinusoidal voltage signal at the gate contact 120, only during a relatively small phase angle does a significant drain current 141 flow. The switching of the junction field effect transistor 110 from the blocked to the conductive state thus takes place relatively slowly. A faster switching of the field effect transistor to he rich ⁇ 110, it would be desirable to pressurize the gate contact 120 with a Ga ⁇ te-source voltage 121, which is steeper than sinusoidal.
  • a characteristic of the gate diode of the field effect transistor 110 shown in the lower graph of FIG. 2 can be used for this purpose.
  • the lower graph of FIG. 2 shows that the gate current 122 flowing into the gate contact 120 is approximately equal to zero in wide regions of the gate-source voltage 121. Only at a forward breakdown voltage 123 and at a reverse breakdown voltage 124 does the gate diode break through, leading to a sharp increase in the gate current 122. This behavior of the gate diode is similar to the behavior of a zener diode.
  • a control range 190 of the gate-source voltage 121 between the gate contact 120 and the source contact 130 of the field effect transistor 110 is selected such that the peak values of the gate-source voltage 121 reach or slightly exceed the breakdown voltages 123, 124, then occurs at the vertices of the gate-source voltage 121 to a short non-zero gate current 122 without damaging the field effect transistor 110.
  • This non-zero gate current 122 can be used to trigger a re ⁇ sonanzschwingung a series resonant member, as will be explained below.
  • Figure 3 shows a schematic representation of a Fourier synthesis 200 to produce a nearly rectangular Sig ⁇ Nals of two sinusoidal signals. On the horizontal axis of Figure 3, a time 201 is plotted. On the vertical axis of Figure 3, a time 201 is plotted. On the vertical axis of Figure 3, a time 201 is plotted. On the vertical axis of Figure 3, a time 201 is plotted. On the vertical axis of Figure 3, a time 201 is plotted. On the vertical
  • Axis of the graph of Figure 3 is placed 202 ⁇ carry an amplitude.
  • Numeral 210 designates a sinusoidal fundamental signal 210 at a first frequency.
  • a harmonic signal 220 has a lower amplitude than the fundamental wave signal 210 and a second frequency.
  • the second frequency is an odd multiple of Ers ⁇ th frequency.
  • the second frequency is three times the first frequency.
  • Reference numeral 213 represents a total signal 230 resulting from the addition of the fundamental signal 210 and the harmonic signal 220. It can be seen that the Ge ⁇ Sammlungsignal 230 has the periodicity of the fundamental wave signal 210, however, is legal eckförmiger configured with respect to a sinusoidal signal.
  • Figure 4 shows a first drive circuit 300 for driving the junction field-effect transistor 110.
  • the term ausgangssei- circuit parts of Figure 1 are the overview ⁇ friendliness not shown for simplicity.
  • the first drive circuit 300 has a driver 320, which is designed to generate a sinusoidal drive signal with respect to the ground contact 150.
  • the output signal of the driver 320 may already be suitably biased, so be shifted from the zero point.
  • the first drive circuit 300 has a first quadrupole 310, which is used as oscillating circle is formed.
  • a first input terminal 313 of the quadrupole 310 is connected to a first output of the driver 320.
  • a second input terminal 315 of the resonant circuit 310 is connected to the second output of the driver.
  • a first output terminal 314 of the quadrupole 310 is connected to the gate contact 120.
  • a second output terminal 316 of the resonant circuit 310 is connected to the ground contact 150.
  • the quadrupole 310 is thus arranged between the driver 320 and the gate contact 120 and the source contact 130 of the junction field effect transistor 110.
  • FIG. 5 shows a second drive circuit 400 according to an alternative embodiment.
  • the driver 320 is replaced by a driver 420, which is likewise designed to output a sinusoidal voltage signal, compared to the first drive circuit 300.
  • the first quadrupole 310 of the first drive circuit 300 is replaced by a second quadrupole 410 in the second drive circuit 400.
  • the second quadrupole 410 has ei ⁇ ne third input terminal 413 which is connected to a first gear of the driver from ⁇ 420th
  • a fourth input terminal 415 of the second quadrupole 410 is connected to a second input terminal 415
  • the second quadrupole 410 has a third output terminal 414, which is connected to the gate contact 120 of the junction field effect transistor 110.
  • a fourth output terminal 416 of the second quadrupole 410 is connected to the source contact 130 of the junction field effect transistor 110 and the ground contact 150 verbun ⁇ .
  • the second quadrupole 410 is thus between the driver 420 and the gate contact 120 and the source contact 130 of the junction field effect transistor 110.
  • the second quadrupole 410 has a through terminal between the third inlet 413 and the third output terminal 414 is arrange ⁇ th lambda / 4 resonator.
  • the lambda / 4 resonator may, for example, be a cavity resonator and has a pole at an odd multiple of the frequency of the sine signal output by the second driver 420.
  • FIG. 6 shows a schematic graph for explaining the operation of the drive circuits 300, 400 of FIGS. 4 and 5.
  • a negative value is present between the gate contact 120 and the source contact 130 or the ground contact 150 applied gate source voltage 521 applied.
  • the already known from ⁇ Fi gur 2 quadratic dependence of the drain current 141 is shown again by the negative gate-source voltage 521st
  • a time 510 is shown on a vertical axis pointing downwards.
  • a horizontal axis pointing to the right also shows time 510. Corresponding times 511 on both axes are interconnected by quadrants for better orientation.
  • an unmodified sinusoidal control signal 550 is output that is output by the drivers 320, 420 of the drive circuits 300, 400. It can be seen that the unmodified sinusoidal control signal 550 completely exploits the starting region 190 of the gate-source voltage 521, ie the peak values of the unmodified control signal 550 reach or slightly exceed the reverse breakdown voltage 124 and the forward breakdown voltage 123. As a result, the drain diode of the field effect transistor 110 becomes conductive at the times at which the unmodified control signal 550 reaches the breakdown voltages 123, 124, as explained with reference to FIG. 2.
  • the respectively resulting short current flow triggers a resonant oscillation of the resonant circuit in the first quadrupole 310 or the lambda / 4 resonator in the second quadrupole 410.
  • This triggered vibration has an odd multiple of the frequency of the unmodified control signal 515.
  • a vibration voltage of the triggered vibration is shown in FIG. 6 with a curve 552.
  • Numeral 551 designates the modified control signal resulting from the addition of the unmodified control signal 550 and the oscillation voltage of the quadrupole 310, 410.
  • the modified control signal 551 is more rectangular with respect to the unmodified control signal 550 and has steeper edges. This has the advantage that the driven with the modified control signal 551 junction field effect transistor 110 rapidly switches between the gesche ⁇ NEN and the open state. This is shown in the upper right quadrant of the graph of FIG. There, the time-dependent drain current 141 is carried ⁇ .
  • the unmodified drain current 540 results when the junction field effect transistor 110 is driven with the unmodified control signal 550.
  • the output network 160 of the amplifier circuit causes the unmodified drain current 540 to occur only during every second half cycle of the unmodified control signal Control signal 550 is different from zero. In the regions where the unmodified drain current 540 is different from zero, it has an approximately sinusoidal profile.
  • the curve 541 shows the time profile of a modified drain current that results when the junction field effect transistor 110 is driven by the modified control signal 551. It can be seen that the modified drain current has a more rectangular profile with steeper edges. In addition, the time ranges in which the modified drain current 541 is different from zero are opposite. over the time ranges in which the unmodified drain current 540 is different from zero, widened.
  • the Umschal ⁇ th of the junction field-effect transistor 110 between a guide and a locking phase is carried out at activation of the locking ⁇ layer field effect transistor 110 with the modified STEU ⁇ ersignal 551 so rapidly than when driven with the UNMO ⁇ -modified control signal 550. This causes the loss Leis ⁇ tion of the junction field effect transistor 110 is lowered.
  • the first driving circuit 300 of the first quadrupole 310 may have not only a purely parallel ⁇ resonant circuit, but a plurality of series-parallel resonant circuits. In this case, should have resonances at different Harmon ⁇ African the frequency of the signal output by the driver 320 sine signal, the single parallel resonant circuits. This means that in the Fou ⁇ riersynthese the modified control signal 551 received higher orders, leading to an even more rectangular waveform.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un circuit de commande d'un transistor à effet de champ à jonction comportant une borne de grille, ledit circuit comprenant un étage d'attaque conçu pour générer un signal de tension à une fréquence prédéfinie. Ce circuit comprend en outre un quadripôle qui comporte une borne d'entrée connectée à l'étage d'attaque et une borne de sortie connectée à la borne de grille, et possède une fonction de transfert qui comporte un pôle à un multiple impair de la fréquence.
PCT/EP2011/065822 2010-09-30 2011-09-13 Circuit de commande d'un transistor à effet de champ à jonction WO2012041694A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
RU2012101462/08A RU2591013C2 (ru) 2010-09-30 2011-09-13 Схемное устройство для управления полевым транзистором с запирающим слоем

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE201010041759 DE102010041759A1 (de) 2010-09-30 2010-09-30 Schaltungsanordnung zum Ansteuern eines Sperrschicht-Feldeffekttransistors
DE102010041759.9 2010-09-30

Publications (1)

Publication Number Publication Date
WO2012041694A1 true WO2012041694A1 (fr) 2012-04-05

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PCT/EP2011/065822 WO2012041694A1 (fr) 2010-09-30 2011-09-13 Circuit de commande d'un transistor à effet de champ à jonction

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RU (1) RU2591013C2 (fr)
WO (1) WO2012041694A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0547871A1 (fr) * 1991-12-16 1993-06-23 Texas Instruments Incorporated Perfectionnements relatifs aux amplificateurs
US6671505B1 (en) * 1999-04-06 2003-12-30 Matsushita Electric Industrial Co., Ltd. Frequency converter

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2054211C1 (ru) * 1992-12-23 1996-02-10 Тагаевский Александр Тимурович Способ управления полевым транзистором
US5767743A (en) * 1995-10-13 1998-06-16 Matsushita Electric Industrial Co., Ltd. Radio frequency power amplifier having a tertiary harmonic wave feedback circuit
JP2001203542A (ja) * 2000-01-18 2001-07-27 Sanyo Electric Co Ltd 帰還回路、増幅器および混合器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0547871A1 (fr) * 1991-12-16 1993-06-23 Texas Instruments Incorporated Perfectionnements relatifs aux amplificateurs
US6671505B1 (en) * 1999-04-06 2003-12-30 Matsushita Electric Industrial Co., Ltd. Frequency converter

Also Published As

Publication number Publication date
RU2012101462A (ru) 2014-11-10
RU2591013C2 (ru) 2016-07-10
DE102010041759A1 (de) 2012-04-05

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