WO2012013049A1 - Procédé et système de détection de mémoire à capacité trompeuse - Google Patents

Procédé et système de détection de mémoire à capacité trompeuse Download PDF

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Publication number
WO2012013049A1
WO2012013049A1 PCT/CN2011/072831 CN2011072831W WO2012013049A1 WO 2012013049 A1 WO2012013049 A1 WO 2012013049A1 CN 2011072831 W CN2011072831 W CN 2011072831W WO 2012013049 A1 WO2012013049 A1 WO 2012013049A1
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memory
data
sector
address
read
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PCT/CN2011/072831
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English (en)
Chinese (zh)
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覃敏
邓恩华
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深圳市江波龙电子有限公司
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Publication of WO2012013049A1 publication Critical patent/WO2012013049A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic

Definitions

  • the invention belongs to the technical field of detection, and in particular relates to a method and a system for detecting a dummy capacity memory.
  • Flash is a storage medium, such as a USB flash drive, memory card, SSD, etc. It has the advantages of anti-vibration, low power consumption, long-term storage and so on.
  • Nand Flash Flash is a non-volatile memory that can be erased and reprogrammed for blocks of memory cells called blocks. Any Flash The device's write operations can only be performed in empty or erased cells, so in most cases, the erase must be performed before the write operation.
  • the firmware program in order to provide a continuous logical operation space, you need to use Flash.
  • the blocks are effectively managed, including the identification of bad blocks, the management of the zones, and the balancing of the frequency of use of the blocks.
  • These algorithms require blocks that occupy Nand Flash, and the firmware is also saved in Nand In Flash, it also occupies blocks of Nand Flash. So, a piece of Nand Flash with a capacity of M, private data takes up N The size of the space, then after the firmware management, the effective space provided to the customer is only the remaining capacity of the M-N.
  • Nand Flash With the popularity of management technology and the emergence of more storage masters, the competition in the memory field is becoming increasingly fierce. Under the influence of interests, some criminals exploit the vulnerabilities in the firmware or the false capacity setting function provided by the unscrupulous master, using M.
  • the capacity of Nand Flash after mass production, the false report capacity is X (X>M) size, and then sold in X-capacity memory to obtain huge profits.
  • M capacity of Nand The memory produced by Flash is impossible to provide free space beyond M capacity.
  • the memory with the false report capacity is X. In fact, only M size data can be saved. Those X minus M The space obtained cannot save the data, and the fake capacity memory will not report that it cannot be saved. The data stored by the user into the device will be lost, causing irreparable damage to the user, sometimes even Can't be measured by money.
  • An object of the present invention is to provide a method for detecting a dummy capacity memory, which aims to solve the continuous improvement and improvement of the pseudo capacity technology in the prior art.
  • the detection method of the fake capacity memory is not perfect, and the detection speed is slow.
  • the embodiment of the present invention is implemented by the method for detecting a dummy capacity memory, and the method includes the following steps:
  • Reading out data corresponding to the memory high address data area when the data corresponding to the read memory high address data area is different from the written test data, determining that the memory is a dummy type dummy Capacity storage, ending the inspection process;
  • the preset test data is written in a plurality of sectors in the tail area and the middle area of the memory;
  • the address sector begins, and the read sector data is compared with the test flag to determine whether the memory is cyclically written to the dummy capacity memory.
  • Another object of the embodiments of the present invention is to provide a detection system for a dummy capacity memory, the system comprising:
  • a first test data writing module configured to write pre-set test data in a high address data area of the memory
  • a dummy write type memory determining module configured to read data corresponding to the memory high address data area, when the data corresponding to the read memory high address data area is different from the written test data, determine The memory is a dummy capacity type of a dummy write type, ending the detection process;
  • a second test data writing module configured to: when the data corresponding to the memory high address data area read by the dummy type memory determining module is the same as the written test data, in the tail area and the middle area of the memory Writing a predetermined number of test data to a plurality of sectors;
  • Cyclic write type memory judgment module for 0 from memory
  • the address sector begins, and the read sector data is compared with the test flag to determine whether the memory is cyclically written to the dummy capacity memory.
  • the test data set in advance is written in the high address data area of the memory; the data corresponding to the high address data area of the memory is read out, and the data corresponding to the high address data area of the read memory is
  • the written test data is different, it is determined that the memory is a dummy write type memory; when the data corresponding to the read memory high address data area is the same as the written test data, in the memory
  • the sector of the tail region and the middle region writes the preset test data; starting from the 0 address sector of the memory, performing comparison of the test identifiers on the read sector data, and determining whether the memory is cyclically written Type of fake capacity memory, fast and convenient to detect.
  • FIG. 1 is a flowchart of an implementation of a method for detecting a dummy capacity memory according to an embodiment of the present invention
  • FIG. 2 is a flowchart of implementing preset generation test data according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a test data area provided by an embodiment of the present invention.
  • Figure 4 It is a flowchart of implementing the comparison of the test identifiers of the read sector data from the 0 address sector of the memory provided by the embodiment of the present invention, and determining whether the memory is cyclically written to the dummy capacity memory;
  • FIG. 5 is a structural block diagram of a detection system of a dummy capacity memory according to an embodiment of the present invention.
  • FIG. 6 is a structural block diagram of a test data generating module according to an embodiment of the present invention.
  • FIG. 7 is a structural block diagram of a loop write type dummy capacity memory judging module according to an embodiment of the present invention.
  • a test identifier is added to the test data, the test data is written into the memory, and then read for comparison to determine whether the memory is a dummy capacity memory.
  • An object of the embodiments of the present invention is to provide a method for detecting a dummy capacity memory, the method comprising the following steps:
  • Reading out data corresponding to the memory high address data area when the data corresponding to the read memory high address data area is different from the written test data, determining that the memory is a dummy type dummy Capacity storage, ending the inspection process;
  • the preset test data is written in a plurality of sectors in the tail area and the middle area of the memory;
  • the address sector begins, and the read sector data is compared with the test flag to determine whether the memory is cyclically written to the dummy capacity memory.
  • Another object of the embodiments of the present invention is to provide a detection system for a dummy capacity memory, the system comprising:
  • a first test data writing module configured to write pre-set test data in a high address data area of the memory
  • a dummy write type memory determining module configured to read data corresponding to the memory high address data area, when the data corresponding to the read memory high address data area is different from the written test data, determine The memory is a dummy capacity type of a dummy write type, ending the detection process;
  • a second test data writing module configured to: when the data corresponding to the memory high address data area read by the dummy type memory determining module is the same as the written test data, in the tail area and the middle area of the memory Writing a predetermined number of test data to a plurality of sectors;
  • Cyclic write type memory judgment module for 0 from memory
  • the address sector begins, and the read sector data is compared with the test flag to determine whether the memory is cyclically written to the dummy capacity memory.
  • the test data set in advance is written in the high address data area of the memory; the data corresponding to the high address data area of the memory is read out, and the data corresponding to the high address data area of the read memory is
  • the written test data is different, it is determined that the memory is a dummy type memory of a dummy write type; when the data corresponding to the read high memory address data area is the same as the written test data, Writing the pre-set test data in a plurality of sectors in the tail region and the middle region of the memory; starting from the 0-address sector of the memory, performing comparison of the test flags on the read sector data, and determining whether the memory is A pseudo-type memory of the cyclic write type.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 1 is a flowchart showing an implementation process of a method for detecting a dummy capacity memory according to an embodiment of the present invention, and the specific steps are as follows:
  • step S101 pre-set test data is written in the high address data area of the memory.
  • test data needs to be set in advance before the step is performed.
  • the specific implementation steps are given below, and are not described herein again, but are not intended to limit the present invention.
  • the memory can be a Nand Flash flash memory, and the following is Nand Flash
  • Nand Flash Nand Flash
  • the flash memory is described as an embodiment.
  • step S102 Reading the data corresponding to the high address data area of the memory.
  • the data corresponding to the read high address data area of the memory is different from the written test data, determining that the memory is of a dummy type
  • the fake capacity memory ends the inspection process.
  • the memory when the data corresponding to the read high address data area of the memory is different from the written test data, it indicates that the memory is a dummy type memory of a dummy type.
  • step S103 when the data corresponding to the read memory high address data area is the same as the written test data, the preset test data is written in a plurality of sectors in the tail area and the middle area of the memory.
  • the sector selected in the middle area of the memory may be a randomly selected sector, and the present invention is not limited thereto.
  • step S104 0 from the memory
  • the address sector begins, and the read sector data is compared with the test flag to determine whether the memory is cyclically written to the dummy capacity memory.
  • the sector data is read from the sector address starting from the 0 sector, and the identifier of the specified location included in the read sector data is compared with the test identifier of the written test data.
  • the sector data of the next address is continuously read, and the judgment is continued; when the two are the same, it is determined that the memory is a pseudo-type memory of a cyclic write type.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG. 2 shows an implementation flow of pre-set generation test data provided by an embodiment of the present invention, and the specific steps are as follows:
  • step S201 a test identifier is randomly generated, and the test data includes a test identifier for detecting a false capacity of the memory.
  • the test identifier is saved in a length of 512.
  • the test identifier can adopt 2 DWORDs (double word ) when using 2 DWORDs.
  • the random repetition probability is set to one of 64's 64th power, which is 1/18446744073709551616.
  • step S202 the test identifier is added to the sector template.
  • a test data area of 64 KB is written with 512 bytes as a unit of the buffer, as shown in FIG. 3, wherein 64 KB is the maximum transmission unit of the SCSI command for reading and writing the memory disk.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 4 shows a slave memory 0 provided by an embodiment of the present invention.
  • the address sector begins, the comparison of the test identifiers is performed on the read sector data, and the implementation flow of determining whether the memory is cyclically written to the dummy capacity memory is as follows:
  • step S401 the sector data of the 0 address of the memory is read.
  • sector data is read starting from a logical address 0 sector.
  • step S402 it is determined whether the data of the location specified by the sector data includes the test identifier included in the test data, and the step is performed. S403, otherwise step S404 is performed.
  • the identifier bit (the data that must be carried in the sector data) of the specified position of the read sector data is determined whether the identifier bit is the same as the test identifier included in the test data, if the same It means that the memory is a cyclic type of dummy capacity memory in which test data written to a specified sector is mapped to other sectors.
  • step S403 when the 0 When the data of the address sector designation location includes the test identifier included in the test data, it is determined that the memory is a loop type dummy capacity memory, and the detection flow is ended.
  • step S404 when the 0 When the data of the specified location of the address sector does not include the test identifier included in the test data, the sector address to be read is calculated in a fixed step increment manner.
  • the next sector data is continuously read, wherein the sector of the next sector data to be read may be selected in a skip mode, that is, in a fixed step increment manner. , here you can choose a fixed step size 2MB, the current step size is 2MB, and the read address of the next sector data can be increased by (2+2) MB on the existing basis, which is merely an embodiment of the present invention.
  • step S405 In the process of determining whether the calculated sector address to be read is located in the address of the sector in the tail region and the middle region of the memory in which the test data is written, if yes, step S406 is performed; otherwise, S407 is performed.
  • the sector address to be read by the data when the sector address to be read by the data is calculated, it is determined whether the sector is located in the address of the sector in the tail region and the middle region of the memory in which the test data is written, that is, when reading The sector to be fetched is the sector in which the test data is written, and the reading of the sector data of the address is skipped, and the next sector data is read.
  • step S406 When the calculated sector address to be read is located in the tail region of the memory in which the test data is written and the addresses of the sectors in the middle region, the control skips reading the sector data, and calculates the next The address of the read sector data is continued, and the step of judging whether the calculated sector address to be read is located in the tail region of the memory in which the test data is written and the addresses of the plurality of sectors in the middle region are performed.
  • the manner of calculating the address of the sector data to be read next is also a fixed step increment manner, and details are not described herein again.
  • step S407 it is determined whether the calculated sector address to be read is greater than the capacity of the memory, and if yes, step S409 is performed. Otherwise, go to step S408.
  • step S408 When the calculated sector address to be read is less than or equal to the capacity of the memory, the sector data corresponding to the sector address is read, and the process returns to step S402. That is, it is judged whether the data of the specified position of the sector data contains the test identifier included in the test data.
  • step S402. when the calculated sector address to be read is not located in the tail region of the memory in which the test data is written and the addresses of the plurality of sectors in the middle region, the process of determining is as described above in step S402. The details are not described herein.
  • step S409 When the calculated sector address to be read is greater than the capacity of the memory, the control ends the detection flow and determines that the memory is a real memory.
  • the pseudo-capacity memory provided by the embodiment for determining whether the memory is of a cyclic write type is a cyclic progressive detection process, that is, traversing the sector data of the entire memory, when traversing the complete After the sector data, the read sector data is not found to contain the test identifier, the memory identifying the detection is a normal memory, and when the read sector data is found to contain the test identifier, it indicates that the memory is a dummy capacity memory ( Loop-write type of dummy capacity storage).
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • test data when test data is written to the tail region of the memory and a plurality of sectors of the randomly selected middle region, the test data should not appear at other locations in the memory.
  • test data will be mapped to other logical addresses, and once the test data is read at an address outside the write area, the memory is a dummy capacity memory.
  • Nand Flash 10 times longer when writing test data The block size will be saved in a continuous write mode, so you can follow Nand Flash when reading The block size is read incrementally without worrying about missing test data that is cyclically mapped. Based on this condition, it is theoretically only 1/10 of the total read time to complete the test, and only 1 for each read. Sectors, so there is no need to access too many Nand Flash blocks, so the detection speed can be further improved.
  • the detection speed is improved again, and it is beneficial in the resource.
  • the algorithm is implemented on a lack of embedded devices.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • FIG. 5 A block diagram of a structure of a detection system for a dummy capacity memory according to an embodiment of the present invention is shown. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the first test data writing module 11 writes the preset test data in the high address data area of the memory; the dummy type memory determining module 12 Reading out data corresponding to the memory high address data area, when the data corresponding to the read memory high address data area is different from the written test data, determining that the memory is a dummy type dummy Capacity storage, ending the detection process; when the dummy type memory decision module 12 When the data corresponding to the read memory high address data area is the same as the written test data, the second test data is written to the module 13
  • the pre-set test data is written in a plurality of sectors of the tail region and the middle region of the memory; the cyclic write type memory judging module 14 is 0 from the memory
  • the address sector begins, and the read sector data is compared with the test flag to determine whether the memory is cyclically written to the dummy capacity memory.
  • the test data generating module 15 The test data is generated in advance, and the test data includes a test identifier for detecting a false capacity of the memory.
  • FIG. 6 The structural block diagram of the test data generating module provided by the embodiment of the present invention is shown. For the convenience of description, only parts related to the embodiment of the present invention are given in the figure.
  • the test identifier generation module 151 randomly generates a test identifier; the test identifier joins the module 152 Adding the test identifier to the sector template; the test data acquisition module 153 copies the sector template to the 64K
  • the test data area of the zone length obtains test data written to several sectors of the memory tail area and the middle area.
  • FIG. 7 The block diagram of the loop write type memory judging module provided by the embodiment of the present invention is shown. For the convenience of description, only parts related to the embodiment of the present invention are shown in the figure.
  • the sector data reading module 141 reads the sector data of the 0 address of the memory; the first judging module 142 Determining whether the data of the specified location of the sector data includes the test identifier included in the test data; when the first determining module 142 determines the 0 When the data of the address sector specified location contains the test identifier included in the test data, the first loop write type memory decision module 143 Determining that the memory is a loop type dummy capacity memory, ending the detection process; when the first determining module 142 determines the 0 When the data of the location specified by the address sector does not include the test identifier included in the test data, the sector address calculation module 144 calculates the sector address to be read in a fixed step increment manner; the second determination module 145 Determining whether the sector address to be read calculated by the sector address calculation module 144 is located in the tail region of the memory in which the test data is written and the addresses of the sectors in the middle region; when the second judging module 145 The control skip module 146 is determined to determine that the calculated
  • the control skips the reading of the sector data, and the execution sector address calculation module 144 calculates the address of the sector data to be read next, and continues to execute the second determination module 145. Determining whether the calculated sector address to be read is located in the tail region of the memory in which the test data is written and the addresses of the plurality of sectors in the middle region; when the second judging module 145 When it is judged that the calculated sector address to be read is not located in the tail region of the memory in which the test data is written and the addresses of the plurality of sectors in the middle region, the third judging module 147 It is judged whether the calculated sector address to be read is greater than the capacity of the memory.
  • the control module 148 ends. Controlling the end of the detection process, and determining that the memory is a real memory; when the sector address to be read calculated by the third determining module 147 is less than or equal to the capacity of the memory, the sector data reading module 141 is executed. And reading the sector data corresponding to the sector address, and continuing to perform the step of the first determining module 142 determining whether the data of the location specified by the sector data includes the test identifier included in the test data.
  • Writing pre-set test data in a high address data area of the memory Reading data corresponding to the memory high address data area, when the read data of the memory high address data area corresponds to the written test data If the difference is not the same, determining that the memory is a dummy-type dummy memory, ending the detection process; when the data corresponding to the read high address data area is the same as the written test data, in the memory Several sectors of the tail region and the middle region are written to the preset test data; from the memory The address sector starts with a comparison of the test flags of the read sector data, and determines whether the memory is cyclically written to the dummy capacity memory, and the detection speed is fast and convenient.

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Abstract

L'invention porte sur un procédé et un système de détection d'une mémoire à capacité trompeuse. Le procédé comprend les opérations suivantes : les données de test préréglées sont écrites dans une zone de données d'adresse haute de la mémoire ; les données qui correspondent à la zone de données d'adresse haute de la mémoire sont lues, et lorsque les données lues qui correspondent à la zone de données d'adresse haute de la mémoire sont différentes des données de test écrites, il est déterminé que la mémoire est une mémoire à capacité trompeuse de type écrit mensongé, et le flux de détection est terminé ; lorsque les données lues qui correspondent à la zone de données d'adresse haute de la mémoire sont identiques aux données de test écrites, les données de test préréglées sont écrites dans certains secteurs de la zone d'extrémité et d'une zone intermédiaire de la mémoire ; pour les données de secteur lues, une marque de test est comparée à partir d'un secteur d'adresse 0 de la mémoire, et il est déterminé si la mémoire est ou non la mémoire à capacité trompeuse de type écrit circulaire.
PCT/CN2011/072831 2010-07-30 2011-04-15 Procédé et système de détection de mémoire à capacité trompeuse WO2012013049A1 (fr)

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CN103116536B (zh) * 2013-02-25 2016-02-24 杭州华澜微电子股份有限公司 存储装置的容量检测方法
CN103500586B (zh) * 2013-09-26 2016-04-13 北京奇虎科技有限公司 检测移动存储装置容量的方法及设备
CN104331061A (zh) * 2014-08-28 2015-02-04 航天科工深圳（集团）有限公司 配网终端装置核心板的测试方法及其测试装置
WO2017024459A1 (fr) * 2015-08-10 2017-02-16 华为技术有限公司 Procédé d'authentification de carte mémoire et terminal mobile associé, ainsi que dispositif de terminal
CN106558348A (zh) * 2016-11-11 2017-04-05 北京京存技术有限公司 一种eMMC读写测试方法和装置
CN108335721B (zh) * 2018-03-14 2021-04-20 烽火通信科技股份有限公司 一种实时检测随机存取存储器地址线故障的方法及系统
CN111273852A (zh) * 2018-12-04 2020-06-12 智微科技股份有限公司 存储器区块大小判定方法
CN109634534B (zh) * 2019-01-02 2022-04-01 威胜集团有限公司 存储芯片的容量快速判定方法
CN110109785B (zh) * 2019-04-16 2023-03-31 晶晨半导体(上海)股份有限公司 内存容量获取方法、装置、计算机设备及可读存储介质
CN110598473B (zh) * 2019-09-18 2022-08-16 深圳市网心科技有限公司 一种移动存储介质管理方法、装置及设备和存储介质
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