WO2011149215A3 - 다결정 실리콘 박막의 제조방법 - Google Patents

다결정 실리콘 박막의 제조방법 Download PDF

Info

Publication number
WO2011149215A3
WO2011149215A3 PCT/KR2011/003693 KR2011003693W WO2011149215A3 WO 2011149215 A3 WO2011149215 A3 WO 2011149215A3 KR 2011003693 W KR2011003693 W KR 2011003693W WO 2011149215 A3 WO2011149215 A3 WO 2011149215A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal
oxide film
formation step
thin film
Prior art date
Application number
PCT/KR2011/003693
Other languages
English (en)
French (fr)
Other versions
WO2011149215A9 (ko
WO2011149215A2 (ko
Inventor
이원태
조한식
김상규
Original Assignee
노코드(주)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 노코드(주) filed Critical 노코드(주)
Publication of WO2011149215A2 publication Critical patent/WO2011149215A2/ko
Publication of WO2011149215A3 publication Critical patent/WO2011149215A3/ko
Publication of WO2011149215A9 publication Critical patent/WO2011149215A9/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

본 발명에 따른 다결정 실리콘 박막의 제조방법은, 절연 기판상에 금속 플루오르화물(fluoride)로 이루어진 결정화 촉진층을 형성하는 결정화 촉진층 형성단계; 상기 결정화 촉진층 위에 실리콘 화합물로 이루어진 완충층을 형성하는 완충층 형성단계; 상기 완충층 위에 금속층을 형성시키는 금속층 형성단계; 상기 금속층을 열처리하여 그 금속층의 표면에 금속 산화막을 형성하거나, 상기 금속층 위에 금속 산화막을 증착하여 금속 산화막을 형성하는 산화막 형성단계; 상기 산화막 형성단계에서 형성된 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및 상기 금속층 또는 상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 것을 특징으로 한다.
PCT/KR2011/003693 2010-05-24 2011-05-19 다결정 실리콘 박막의 제조방법 WO2011149215A2 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2010-0048195 2010-05-24
KR1020100048195A KR101064325B1 (ko) 2010-05-24 2010-05-24 다결정 실리콘 박막의 제조방법

Publications (3)

Publication Number Publication Date
WO2011149215A2 WO2011149215A2 (ko) 2011-12-01
WO2011149215A3 true WO2011149215A3 (ko) 2012-04-19
WO2011149215A9 WO2011149215A9 (ko) 2012-06-07

Family

ID=44957283

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2011/003693 WO2011149215A2 (ko) 2010-05-24 2011-05-19 다결정 실리콘 박막의 제조방법

Country Status (2)

Country Link
KR (1) KR101064325B1 (ko)
WO (1) WO2011149215A2 (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102038494B1 (ko) * 2017-07-25 2019-10-30 울산과학기술원 실리콘 박판, 이의 제조 방법, 및 이를 포함하는 리튬 이차 전지
KR102221607B1 (ko) * 2019-08-05 2021-03-02 울산과학기술원 실리콘 박판, 이의 제조 방법, 및 이를 포함하는 리튬 이차 전지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04349616A (ja) * 1991-05-28 1992-12-04 Tonen Corp 多結晶シリコン薄膜の形成方法
KR100496287B1 (ko) * 2002-08-03 2005-06-20 삼성에스디아이 주식회사 실리콘 박막의 결정화 방법, 이를 이용한 박막 트랜지스터및 상기 박막 트랜지스터를 구비한 평판 디스플레이 소자
KR20080052769A (ko) * 2006-12-08 2008-06-12 엘지디스플레이 주식회사 실리콘 결정화 방법 및 이를 이용한 박막 트랜지스터제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04349616A (ja) * 1991-05-28 1992-12-04 Tonen Corp 多結晶シリコン薄膜の形成方法
KR100496287B1 (ko) * 2002-08-03 2005-06-20 삼성에스디아이 주식회사 실리콘 박막의 결정화 방법, 이를 이용한 박막 트랜지스터및 상기 박막 트랜지스터를 구비한 평판 디스플레이 소자
KR20080052769A (ko) * 2006-12-08 2008-06-12 엘지디스플레이 주식회사 실리콘 결정화 방법 및 이를 이용한 박막 트랜지스터제조방법

Also Published As

Publication number Publication date
KR101064325B1 (ko) 2011-09-14
WO2011149215A9 (ko) 2012-06-07
WO2011149215A2 (ko) 2011-12-01

Similar Documents

Publication Publication Date Title
WO2012102809A3 (en) Polysilicon films by hdp-cvd
EA201071184A1 (ru) Способ осаждения тонкого слоя
WO2014016489A3 (fr) Film de chalcogenure(s) metallique(s) cristallise(s) a gros grains, solution colloïdale de particules amorphes et procedes de preparation
WO2011133965A3 (en) Passivation methods and apparatus for achieving ultra-low surface recombination velocities for high-efficiency solar cells
UA95942C2 (ru) Способ получения солнечного элемента применение тетрахлорида кремния в нем и тонкопленочный солнечный элемент полученный данным способом
WO2011092402A3 (fr) Cellule photovoltaïque comprenant un film mince de passivation en oxyde cristallin de silicium et procédé de réalisation
WO2013061313A8 (en) Method for manufacturing a protective layer against hf etching, semiconductor device provided with the protective layer and method for manufacturing the semiconductor device
EP2525391A3 (en) Method for producing ferroelectric thin film
EP2533305A3 (en) Method for blister-free passivation of a silicon surface
WO2011143449A3 (en) Method of manufacturing crystalline silicon solar cells using epitaxial deposition
EP2600395A4 (en) PRECURSOR COMPOSITION FOR FORMING AN AMORPHOUS METAL OXIDE SEMICONDUCTOR LAYER, AMORPH METAL OXIDE SEMICONDUCTOR LAYER, METHOD FOR THE PRODUCTION THEREOF, AND SEMICONDUCTOR DEVICE
JP2013536151A5 (ko)
WO2012050322A3 (ko) 3차원 구조의 메모리 소자를 제조하는 방법 및 장치
WO2014064263A3 (fr) Procede de croissance d'au moins un nanofil a partir d'une couche d'un metal de transition nitrure obtenue en deux etapes
WO2011092017A8 (de) Verfahren zur herstellung eines beschichteten gegenstands mit texturätzen
JP2010283337A5 (ko)
JP2011100985A5 (ko)
WO2012051113A3 (en) ATOMIC LAYER DEPOSITION OF CRYSTALLINE PrCaMnO (PCMO) AND RELATED STRUCTURES AND METHODS
JP2010103514A5 (ko)
WO2010134691A3 (ko) 다결정 실리콘 박막의 제조방법
MY161427A (en) Method for producing silicon layers
WO2011149215A3 (ko) 다결정 실리콘 박막의 제조방법
EP2086014A3 (en) Conductive oxide-deposited substrate and method for producing the same, and MIS laminated structure and method for producing the same
JP2015516928A5 (ko)
WO2012166732A3 (en) Method of forming high growth rate, low resistivity germanium film on silicon substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11786848

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 18/03/2013)

122 Ep: pct application non-entry in european phase

Ref document number: 11786848

Country of ref document: EP

Kind code of ref document: A2