WO2011144938A2

WO2011144938A2 - Avalanche photodiode structure and method

Info

Publication number: WO2011144938A2
Application number: PCT/GB2011/050948
Authority: WO
Inventors: Chee Hing Tan
Original assignee: The University Of Sheffield
Priority date: 2010-05-19
Filing date: 2011-05-19
Publication date: 2011-11-24
Also published as: WO2011144938A3; GB201008349D0

Abstract

Embodiments of the invention provide an avalanche photodiode having a multiplication layer and an absorption layer provided on a substrate, wherein the multiplication layer has a thickness less than or substantially equal to 1000 Angstroms (100nm), and the multiplication layer comprises a layer of Al As Sb, Al PSb or Ga PSb.

Description

AVALANCHE PHOTODIODE STRUCTURE AND METHOD

FIELD OF THE INVENTION The present invention relates to avalanche photodiode structures and to a method of detecting radiation using an avalanche photodiode structure. In particular the invention relates to an avalanche photodiode having a multiplication layer comprising a layer of AIAsSb, AlPSb or GaPSb. BACKGROUND

It is known to detect radiation using an avalanche photodiode structure. Avalanche photodiode (APD) structures are photodiode structures that have an internal current gain due to the phenomenon of impact ionization (known as an 'avalanche effect') when operated under appropriate reverse bias conditions.

APDs can be used for detecting visible radiation and infrared radiation. High sensitivity APDs for detecting visible radiation may be fabricated from silicon. They are typically operated at reverse-bias voltages in excess of 50V which presents an obstacle to integration of APDs with CMOS IC technology operating at much lower voltages. Some silicon APDs employ bevelling techniques that permit a reverse bias in excess of 200V to be applied in order to enhance performance of the devices, by having a large electron- to-hole ionization coefficient ratio to achieve low avalanche excess noise. For applications at incident radiation wavelengths of 1 .1 μηι to 1 .55μηι, InGaAs/lnP APDs are currently the preferred technology due to the poor detection of silicon devices at these wavelengths. However the ionization coefficient ratio in InGaAs/lnP APDs is close to unity leading to relatively large avalanche excess noise. APDs suitable for the detection of radiation of wavelengths above 1 .55μηι can be fabricated from cadmium mercury telluride (CMT). However, CMT APDs suffer from a number of problems. The devices are highly costly to manufacture, particularly when large wafer uniformity is critical. The devices must also be stored at temperatures below 70 Ό to prevent degradation. Furthermore the devices must be operated at around 77K, necessitating the use of expensive cooling systems. For optical communications applications commercial APDs typically use InP or InAIAs to form the avalanche region. The avalanche region may be formed to be around 150- 200nm in order to reduce avalanche duration and gain-bandwidth products (GBPs) of less than around 140-200GHz are currently achievable.

Reduction of the avalanche region to less than around 150nm is impractical in these devices due to the onset of a tunnelling current which results in an increase in dark current and hence the device shot noise. APDs may be characterised using a range of parameters including quantum efficiency, leakage current, gain and excess noise factors.

The quantum efficiency of a device indicates the efficiency with which incident optical photons are absorbed by the structure resulting in the generation of primary charge carriers in the material. This is determined by the absorption coefficient of the material used at the wavelength of interest. InGaAs is typically used as the absorption layer in APDs for optical communications.

Leakage current is given by the sum of the dark current (the current flowing through an APD for a given reverse bias condition in the absence of incident photons) and leakage current flowing through the surface.

Sources of noise in photodiodes include shot noise and excess avalanche noise. An excess noise factor F(M) describes the noise inherent in the APD multiplication process (a stochastic process) as a function of an avalanche multiplication factor M. F(M) may be written:

F(M) = kM + (2-(1 /M))(1 -k) where k=3/a is the ratio of the hole ionization coefficient (β) to the electron ionization coefficient (a) in the case that the multiplication process is initiated by electrons. If k=0 (i.e. β=0), only an electron can initiate impact ionization events and the lowest excess noise factor F=2 is obtained. In silicon APDs, electrons are primarily responsible for the initiation of impact ionization, whilst holes are primarily responsible in InP/lnGaAs APDs. Conventional silicon APDs are fabricated with a so-called 'reach through' structure in which the electric field increases as a function of distance along the device structure. The region in which avalanche multiplication occurs is located at a pn junction where the peak electric field occurs.

It is desirable to provide an APD structure having a low excess noise factor and enhanced GBP.

STATEMENT OF THE INVENTION

In a first aspect of the present invention there is provided an avalanche photodiode structure having a multiplication layer and an absorption layer provided on the substrate, wherein the multiplication layer has a thickness less than or substantially equal to 1000 Angstroms (100nm), and the multiplication layer comprises a layer of AIAsSb, AlPSb or GaPSb.

Preferably the absorption layer comprises InGaAs. More preferably, the absorption layer comprises InGaAs and GaAsSb. The InGaAs and GaAsSb may be lattice matched to a substrate, which may be InP. This allows detection up to wavelengths of 1 .65μηι.

Preferably, the absorption layer comprises an InGaAs/GaAsSb superlattice layer, said superlattice layer comprising sub-layers of InGaAs and GaAsSb. This can allow detection of wavelengths up to 2.6μηι. The InGaAs/GaAsSb superlattice layer may be a type II superlattice layer. The GaAsSb sub-layers are preferably arranged to be lattice matched to the InGaAs sub-layers. The GaAsSb sub-layers may be arranged to be lattice mismatched to the substrate. The respective compositions of the GaAsSb and InGaAs layers may be arranged to reduce an effective optical bandgap of the type II superlattice. A concentration of In in the InGaAs sub-layer may be increased relative to a concentration of In for which the InGaAs sub-layer is lattice matched to the substrate.

A concentration of As in the GaAsSb sub-layer is increased relative to a composition in which the GaAsSb sub-layer is lattice matched to the substrate. The sub-layers of the superlattice layer may each have a thickness in the range of from around 1 nm to around 20 nm, and preferably the sublayers have a thickness in the range of around 5 nm. The superlattice may comprise from around 10 to around 400 periods of InGaAs sublayers and sublayers of GaAsSb, AIAsSb, AlPSb or GaPSb, preferably around 100 to around 300 periods, more preferably from around 150 to around 200 periods.

The structure preferably comprises one or more charge sheet layers between the multiplication layer and the absorption layer, wherein each of the one or more charge sheet layers has a doping density N_ch(i) and thickness x_ch(i), and the sum over the one or more charge sheet layers of the product of the doping density of each charge sheet layer N_ch(i) and the corresponding thickness of the charge sheet layer x_ch(i), ¾N_ch(i)x_ch(i) is around 5.17x10¹⁶m^"2 or greater. Accordingly, it is possible to achieve an electric field >1 MV/cm in the AIAsSb avalanche region and an electric field <150kV/cm in the narrower bandgap absorption region, which is desirable in AIAsSb based APDs.

Preferably, the substrate comprises InP, consists substantially of InP. The multiplication layer preferably comprises a layer of AIAsSb, and the AIAsSb layer is preferably formed from AIAs_xSbi-_x wherein either x is the range of from around 0.5 to around 0.6, preferably around 0.56, or x is in the range from around 0.1 to around 0.2, preferably 0.16. Values of x around 0.56 or about 0.16 respectively allow lattice matching to InP or InAs.

According to another aspect of the invention, avalanche photodiode structure described above is provided.

The use of APDs having a structure according to embodiments of the present invention has the advantage that excess noise may be reduced and gain-bandwidth product (GBP) increased compared with InP or InAIAs multiplication layers.

The increase in GBP is understood to be due to reduced carrier transit time whilst the low excess noise factor is a consequence of reduced statistical fluctuation in the avalanche process due to the dead space effect in very thin avalanche regions. Since the avalanche region can be reduced to below 100nm the dead space, defined as the distance required to accumulate sufficient energy to initiate an avalanche process, is a significant fraction of the mean distance between successive ionisation events. This localisation of the position at which ionisation takes place reduces the excess noise factor to values below those that can be achieved in InP and InAIAs. The dead space effect in an avalanche region having a thickness less than or substantially equal to 100nm has not been considered previously in these materials.

The multiplication layer may have a thickness less than or substantially equal to 75nm or 50nm. The multiplication layer may have a thickness greater than or substantially equal to 10nm, 20nm or 30nm.

BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described with reference to the accompanying figures in which:

FIGURE 1 shows an AIAsSb-based separate absorption and multiplication avalanche photodiode (SAMAPD) having a mesa diode structure;

FIGURE 2 shows an AIAsSb-based SAMAPD having a planar diode structure;

FIGURE 3 shows an AIAsSb-based SAMAPD having a planar diode structure arranged to provide pure hole injection;

FIGURE 4 shows an AIAsSb-based SAMAPD having a resonant cavity formed by GaAsSb/AIAsSb Bragg stacks;

FIGURE 5 is a graph showing a plot of measured values of excess noise factor F (from predominantly electron injection) as a function of avalanche multiplication factor M for a series of structures together with plots of k_eff from 0 to 1 in steps of 0.1 ;

FIGURE 6 shows a plot of gain measured on a pin diode with an avalanche region 100nm in length as a function of applied potential using wavelengths of 532nm, 708nm and 1064nm to produce predominantly electron injection, mixed injection and pure hole injection respectively; and FIGURE 7 shows a plot of measured values of current flow as a function of applied reverse bias for an AIAsSb APD with an avalanche region 100nm in length. The sharp increase in current due to the avalanche breakdown indicates that there is no observable band to band tunnelling.

FIGURE 8a shows the variation of the electric field with depth in a structure according to an embodiment of the invention with a single charge sheet layer. FIGURE 8b shows the variation of the electric field with depth in a structure according to an embodiment of the invention with two charge sheet layers.

FIGURE 9a shows measured dark current and photomultiplication in an APD according to an embodiment of the invention.

FIGURE 9b shows measured dark current and photomultiplication in an APD according to another embodiment of the invention.

DETAILED DESCRIPTION

In some embodiments of the invention an avalanche photodiode structure is provided having a separate absorption and multiplication avalanche photodiode (SAMAPD) structure. The devices shown schematically in FIGs 1 to 4 are each formed with such a structure. The devices incorporate an AIAsSb multiplication layer that is less than 100nm thick in some embodiments (i.e. the multiplication region is less than 100nm wide). A device having a multiplication layer formed from AIAsSb may be referred to as an 'AIAsSb-based APD'. Similarly devices having multiplication regions formed from InP or InAIAs may be referred to as InP-based APDs and InAIAs-based APDs respectively. Herein, AIAsSb should be understood to mean AIAs_xSbi-_x, where 0<x<1 . In preferred embodiments, 0<x<1 , as x=0 is likely to induce strain, which may lead to defects. Herein, the terms avalanche region and multiplication layer have the same meaning.

FIG. 1 shows a device having a mesa diode structure whilst FIG. 2 and FIG. 3 show devices having a planar diode structure. In the case of devices having the mesa diode structure, passivation dielectrics such as SiN, Si0₂, benzocyclobutene (BCB) or SU8 are preferably used to reduce surface leakage current and to enhance device reliability. Other dielectrics could be used.

The use of an overgrowth technique to passivate the surface of the mesa diode is also possible.

The structure 100 of FIG. 1 has an InP substrate 101 over which a lower contact layer 105 has been formed, the term lower being used with respect to the structure in the orientation shown in FIG. 1 . In the embodiment of FIG. 1 the lower contact layer is formed from n+ doped InGaAs.

A lower cladding layer 1 10 is provided over the lower contact layer 105, the lower cladding layer 1 10 being formed from n+ doped AIAsSb. A multiplication layer 1 15 is formed over the lower cladding layer 1 10, the multiplication layer being formed from undoped AIAsSb. The multiplication layer is formed to have a thickness of around 100nm or less.

A charge sheet layer 120 is provided over the multiplication layer, the charge sheet layer 120 being formed from p doped AIAsSb. In some embodiments, two charge sheet layers may be used, by doping the second lower grading layer 135. The charge sheet in intended to keep the electric field in each layer such that band to band tunnelling is negligible. In an example the field is kept below 700kV/cm in InAIAs to suppress band to band tunnelling and impact ionisation that could lead to unwanted ionisation feedback. Table 1 shows an embodiment having a structure with two charge sheets (layers 6 and 8). The embodiment of Table 1 differs from the embodiment of FIG. 1 (the embodiment of Figure 1 uses InAIGaAsP in the grading layers, for example), but two or more charge sheets could be incorporated into the embodiment of FIG. 1 by the skilled person without undue experimentation.

Table 1

Returning to the embodiment of FIG. 1 , a first lower grading layer 130 is formed over the charge sheet layer 120 and a second lower grading layer 135 is formed over the first lower grading layer 130. The first and second lower grading layers 130, 135 are formed from undoped InAIGaAsP of different respective compositions. The grading layers (e.g. layers 130 and 135) may be doped with p dopant to control the electric fields in the multiplication layer (e.g. above l OOOkV.cm) and in the InGaAs absorption layer, (e.g. below 150kV/cm). The number of grading layers may be different in other embodiments. For example, more grading layers can be used to provide smooth carrier transport.

The purpose of the grading layers 130, 135, is to provide bandgap grading between relatively narrow bandgap layers and layers having a larger bandgap. Thus, the first and second lower grading layers 130, 135 provide bandgap grading between an absorption layer 140 formed over the second lower grading layer 135 and the charge sheet layer 120. The layers 130, 135 are useful because the charge sheet layer has a larger bandgap than the absorption layer 140 which is formed from InGaAs.

In some embodiments each grading layer has a thickness in the range from around 10nm to around 10Onm. Other thicknesses are also useful.

Bandgap grading is useful in order to reduce carrier trapping at heterojunctions. Respective grading layers are formed to have a composition

(0<x, y, z<1 ) arranged to provide a layer having a bandgap intermediate between that of the layers immediately above and below said grading layer. It is to be understood that in some cases more than one grading layer is advantageous in order to reduce the difference in bandgap between respective successive layers. In some embodiments the bandgap is arranged to be of an intermediate value that is substantially midway between the bandgap of the layers directly above and the bandgap of the layer directly below the particular grading layer under consideration.

A composition of each grading layer is chosen to provide a layer that is lattice matched as closely as may reasonably be achieved to the layers directly above and below whilst providing a bandgap that is of a value between those of the layers directly above and below.

In some embodiments the grading layers are each in the region of from around 10nm to around 100nm in thickness. As described above absorption layer 140 is provided over the second lower grading layer 130. The purpose of the absorption layer 140 is to absorb photons incident upon the structure. A thickness of the absorption layer 140 typically has an influence on a quantum efficiency of the APD at a given wavelength. In some embodiments of the invention the absorption layer 140 has a thickness of at least 1000nm. This enables devices with relatively high quantum efficiencies at wavelengths of 1 .3um and 1 .55um to be produced. InGaAs in the absorption layer can be replaced by GaAsSb, InGaAs/AIAsSb superlattice, or InGaAs/GaAsSb superlattice to provide detection at different wavelengths. Accordingly, detection of wavelengths up to 2.5μηι is possible. An upper grading layer 150 is provided over the absorption layer 140. The upper grading layer 150 is formed from InAIGaAsP.

A first upper cladding layer 160 is formed over the upper grading layer 150. The first upper cladding layer 160 is formed from p+ doped InAIGaAsP.

A second upper cladding layer 165 is formed over the first upper cladding layer 160. The second upper cladding layer 165 is formed from p+doped InAIAs.

The cladding layer 160 has a larger bandgap than the absorption layer 140 and the upper grading layer 150 formed therebetween provides bandgap grading between cladding layer 160 and absorption layer 140. Other embodiments may have different numbers of grading layers. The number of grading layers may be selected to produce a gradual change in the bandgap.

In some embodiments, the grading layers may have a thickness of around 10nm to around 50nm. The thickness of the grading layers may be selected based on the electric field profile, to ensure that the fields in the grading layers are sufficiently low to avoid large band to band tunnelling current. The thickness of the grading layers may also take into consideration the energy of the electrons, to ensure that they can overcome the band discontinuities at the interfaces. A further design consideration may include transport via quantum mechanical tunnelling if the band discontinuity is too large.

Finally an upper contact layer 170 is provided over the second upper cladding layer 165 to which electrical contact may be made. The upper contact layer 170 is formed from p+ doped InGaAs.

Electrical contact is made to the device by means of upper contact layer 170 and lower contact layer 105.

The embodiment of FIG. 2 differs from that of FIG. 1 in that an InP layer 280 is formed directly over an upper grading layer 250 of the structure instead of cladding layers 160, 165 and contact layer 170 as per the embodiment of FIG. 1 . It is to be understood that layers 201 to 250 of the structure of FIG. 2 correspond to layers 101 to 150 of the structure of FIG. 1 . InP layer 280 (FIG. 2) has a p+ doped contact region 285 forming an upper contact layer 285 that is bounded by an n-type doped InP (e.g. doped to a level of around 1 x10¹⁶ to around 5x10¹⁶) peripheral cladding region 282. Electrical contact is made to the device by means of upper contact layer 285 and lower contact layer 205. It is to be understood that variations in the material type and/or composition of one or more of the layers described with respect to specific embodiments of the invention may be useful for forming APDs according to other embodiments of the present invention.

It is to be noted that the valence band offset between InGaAs and AIAsSb is smaller than the conduction band offset. Accordingly, it is possible to achieve increased carrier collection efficiency by using pure hole injection as opposed to pure electron injection. This may also allow a reduction in the number of grading layers, simplifying the structure. In some cases it is possible that no grading layers would be needed.

FIG. 3 is a schematic illustration of a planar diode designed to achieve pure hole injection. The structure has a substrate 301 formed from InP upon which a lower contact layer 305 is provided similar to that of the embodiments of FIG. 1 and FIG. 2.

Over the lower contact layer 305 there is formed a lower cladding layer 310 formed from n+ doped InP.

A lower grading layer 330 is formed over the lower cladding layer 310, the lower grading layer 330 being formed from undoped InAIGaAsP.

An absorption layer 340 is formed over the lower grading layer 330, the absorption being formed from undoped InGaAs. The lower grading layer is arranged to be lattice matched to the lower cladding layer 310 and absorption layer 340 but to have a bandgap intermediate between that of the respective lower cladding layer 310 and absorption layer 340. A first upper grading layer 350 is formed over the absorption layer 340 and a second upper grading layer 355 is formed over the first upper grading layer 350. The first and second upper grading layers 350, 355 are formed from InAIGaAsP.

A charge sheet layer 320 is formed over the second upper grading layer 355. The charge sheet layer 320 is formed from n-type doped AIAsSb.

A multiplication layer 315 is formed over the charge sheet layer 320, the multiplication layer 315 being formed from undoped AIAsSb. Finally, an InP layer 380 is formed over the multiplication layer 315. As in the case of the embodiment of FIG. 2 the InP layer 380 has a p+ doped contact region 385 forming an upper contact layer 385 that is bounded by an n-type doped InP peripheral cladding region 382 (for example, doped with n-dopant to the level of around 1 x10¹⁶cm^"3 to 5x10¹⁶cm^"3). InAIGaAsP grading layers may be inserted between the InP layer 308 and AIAsSb multiplication layer 315. Electrical contact is made to the device by means of upper contact layer 385 and lower contact layer 305.

In the embodiments of FIG. 2 and FIG. 3 the upper contact layer 285, 385 may be formed by diffusion of Zn into an InP layer 280, 380. Ion implantation using Zn (or other group II) ions is possible to form an InP p+ contact layer.

In some embodiments a concentration of dopant in the p+ layer should be at least 10¹⁸cm^"3.

Similarly, a concentration of dopant in the n+ layer in some embodiments should also be at least 10¹⁸cm^"3.

In the embodiments of FIG. 1 to FIG. 3 the charge sheet layers 120, 220, 320 preferably have a dopant concentration arranged such that an electric field in the InGaAs absorption layer 140, 240, 340 is sufficiently low to avoid significant tunnelling current and impact ionisation in the absorption layer 140, 240, 340, whilst the field in the multiplication layer 1 15, 215, 315 is sufficiently high to achieve a required gain. In some embodiments the dopant concentration is arranged to ensure the field in the absorption layer 140, 240, 340 is below around 150kVcm^"1 , and preferably below around

whilst the field in the multiplication layer is above 1 MVcm^"1. In some embodiments the charge sheet layer has a dopant concentration of around 1 x10¹⁷cm^"3 to 10x10¹⁷cm^"3. Preferably, the product of charge sheet doping and charge sheet thickness is at least 5.17x1 ο¹⁶ m^"2.

In some embodiments with a plurality of charge sheet layers, each of the charge sheet layers has a dopant concentration of around 1 x10¹⁷cm^"3 to 10x10¹⁷cm^"3. In some embodiments with a plurality of charge sheet layers, when charge sheet layer i has a doping density N_ch(i) and thickness x_ch(i), the sum over the one or more charge sheet layers of the product of the doping density of each charge sheet layer N_ch(i) and the corresponding thickness of the charge sheet layer x_ch(i), ¾N_ch(i)x_ch(i) is around 5.17x10¹⁶m^"2 or greater.

Figure 8a shows an example of the relation between the electric field and the depth in an embodiment of the structure having a single charge sheet layer 120, 220, 320. Figure 8b shows an example of the relation between the electric field and the depth in an embodiment of the structure when there are two charge sheet layers. The overall change in the electric field is the same in Figures 8a and 8b, but is achieved in two steps in Figure 8b, where two charge sheet layers have been used. In some embodiments the absorption layer 140, 240, 340 is provided by a superlattice structure. In one embodiment the absorption layer is provided by an InGaAs/GaAsSb type II superlattice layer. The superlattice layer is formed from alternating sub-layers of InGaAs and GaAsSb. In some embodiments the GaAsSb sub-layers are lattice matched to InGaAs and InP.

In some embodiments the InGaAs sub-layers are around 5nm in thickness and the GaAsSb sub-layers are also around 5nm in thickness. Other thicknesses are also useful.

In some embodiments, GaAsSb is replaced by AIAsSb. This allows interband absorption.

A single InGaAs sub-layer over a single GaAsSb sub-layer (or vice-versa) defines a single 'period' of the superlattice structure. In some embodiments the number of periods forming the superlattice layer is from around 150 to around 200.

The use of a superlattice layer in some embodiments allows the range of wavelengths that may be detected using AIAsSb-based APDs to be extended to wavelengths up to around 2.6um.

In order to extend the wavelength of radiation that may be detected by means of an avalanche photodiode structure according to embodiments of the present invention a strain balanced technique may be employed. The technique may be employed to grow a strained layer InGaAs/GaAsSb superlattice by increasing the concentration of In in the InGaAs sub-layers and reducing the concentration of As in the GaAsSb sub-layers.

This has the effect of reducing the effective optical bandgap of the superlattice layer. In some embodiments GaAs and/or InSb are inserted at an interface between sub-layers to control the overall strain in the superlattice. FIG. 4 shows an embodiment of the invention in which Bragg stack portions 491 , 492 have been incorporated into an APD structure in order to achieve still further improved quantum efficiency. The Bragg stack layers are arranged to bracket respective upper and lower contact layers 405, 470 of the structure.

It is to be understood that reference signs used to label features of the structure of FIG. 4 correspond to those of the structure of FIG. 1 (also a planar diode structure) in respect of like features, the reference signs of FIG. 4 being prefixed by the numeral 4 instead of the numeral 1 .

In some embodiments the Bragg stacks 491 , 492 of an embodiment of a structure according to FIG. 4 are formed of alternating layers of GaAsSb and AIAsSb, the thicknesses of the layers being arranged to achieve high reflectivity at the required wavelength. In some embodiments layers of a Bragg stack are arranged to have a thickness of around 100nm. In some embodiments, InGaAs is used in place of GaAsSb.

The use of Bragg stacks 491 , 492 has the advantage that a width of the absorption layer may be reduced thereby reducing a carrier transit time. This allows a further increase in bandwidth of APDs to be achieved according to embodiments of the invention.

FIG. 5 is a graph showing excess noise data obtained from an APD structure according to an embodiment of the invention having a multiplication layer 315 formed from undoped AIAsSb having a thickness of 100nm.

The plot shows measured values of excess noise factor F (from predominantly electron injection) as a function of avalanche multiplication factor M for a series of structures together with plots of k_eff from 0 to 1 in steps of 0.1 . The structures used were AIAsSb homojunction pin diodes with an n-type doped InGaAs absorption layer arranged to absorb predominantly optical radiation having a wavelength of 1064nm thereby to provide substantially pure hole injection.

It can be seen that the value of k_eff is around 0.15 for the devices tested. This compares with values of around 0.2 and 0.15 for optimised InP and InAIAs APDs respectively. Smaller k_eff is expected using pure electron injection. Further reduction in k_eff is expected when the multiplication layer thickness is reduced below 100nm. FIG. 6 shows a plot of gain measured on a pin diode with an avalanche region 100nm in length as a function of applied potential using wavelengths of 532nm, 708nm and 1064nm to produce predominantly electron injection, mixed injection and pure hole injection respectively. The plot indicates that a significantly larger gain can be achieved using predominantly electron injection compared to mixed injection and pure hole injection. The results show that α » β in AIAsSb confirming the potential of AIAsSb as a low excess noise multiplication layer. FIG. 7 shows a plot of current flow as a function of applied potential for an AIAsSb APD with an avalanche region 100nm in width. The insignificant band to band tunnelling current in devices according to preferred embodiments of the invention will reduce shot noise originating from dark current. In InP-based APDs and InAIAs-based APDs the onset of tunneling current at low multiplication region widths places a lower limit on this width of around 200nm and 150nm, respectively. However, as can be seen in FIG. 7 substantially no tunnelling current occurs in AIAsSb with an avalanche region 100nm in width. This is a considerable improvement over the prior art and enables devices having reduced excess noise and higher GBP to be produced.

APDs are attractive for use in optical communication systems. Since the impact ionization process is strongly dependent on temperature, T, in most semiconductors the temperature coefficient of breakdown voltage, C_bd = AVbd/ΔΤ, is used to characterize the temperature dependence of the avalanche multiplication. Smaller C_bci in the thinner GaAs avalanche region widths have been observed and attributed to the reduced effects of phonon scattering at high electric fields. Thin avalanche regions also yield lower excess noise factors due to deadspace effect and higher gain-bandwidth products due to reduced carrier transit times. Typical optimized InP and InAIAs based APDs showed C_bci of 46mV/K and 25mV/K respectively. Further reduction of C_bd by using thinner avalanche region is impeded by the onset of band to band tunnelling current.

The use of AIAsSb, as described herein provides higher thermal stability due to its wider bandgap. AIAsSb lattice matched to the substrate (e.g. InP), achieves a remarkably small C_bd in thin AIAsSb avalanche regions. FIG. 9a shows measured dark current and photomultiplication using a 633nm laser measured on the homojunction AIAsSb (AIAso.5eSbo.44) APDs with an avalanche region width of 80nm and a radius of 200μηι at temperatures of 77K, 140K, 200K, 250K and 295K. The dark current reduces with decreasing temperature confirming the absence of tunneling current. Well defined breakdown voltage, V_bd, corresponding to a current level of 100μΑ, is observed at each temperature. Avalanche gain shown in FIG. 9a is relatively insensitive to temperature. The deduced value for C_bci is ~ 1 mV/K, significantly smaller than those of InP and InAIAs. This is the smallest C_bd value reported with no significant band to band tunnelling for compound semiconductors that the inventors are aware of. A Cbd = 7mV/K was obtained in a InGaAs/AIAsSb separate-absorption-charge sheet- multiplication (SACM) APD with a 50nm AIAsSb avalanche region and a radius of 200μηι. This value of C_bci includes the influence of the 500nm thick InGaAs absorption region. FIG. 9b shows measured dark current and photomultiplication at temperatures of 77K, 145K, 200K, 250K and 295K.

AIAsSb avalanche regions, show very low tunnelling current and exhibit an unusually weak temperature dependence of avalanche multiplication, making AIAsSb APDs attractive for very high speed applications. In the embodiments described herein, AIAsSb could be replaced with AlPSb or GaPSb. AlPSb or GaPSb, preferably with compositions lattice matched to the substrate (e.g. InP), can be used as sub-1 00nm thick avalanche layers to achieve high GBPs, low noise and small temperature coefficient of breakdown voltage. It is expected that AlPSb will show similar or smaller C_bd than AIAsSb, and GaPSb will show higher C_bd than AIAsSb.

Throughout the description and claims of this specification, the words "comprise" and "contain" and variations of the words, for example "comprising" and "comprises", means "including but not limited to", and is not intended to (and does not) exclude other moieties, additives, components, integers or steps.

Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise. Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith.

Annexe

Low noise avalanche photodiodes incorporating a 40nm AIAsSb avalanche region Introduction

Weak optical signals in long haul high speed optical networks are converted into electrical currents that are typically amplified using bipolar junction or field effect transistors. The performance of the receiver module at 40 Gb/s can be enhanced via optimization of photodiode, the amplifier and minimizing parasitic components in the module. While intense development of the amplifier, in the form of transimpedance amplifier (TIA), has led to various TIA options capable of providing high transimpedance gains of 40-70 dB with bandwidths above 30 GHz [1 ], side illuminated InGaAs pin the only viable photodiode technology to provide sufficient sensitivity and bandwidth to meet the requirements of 40 Gb/s. Combining an InGaAs absorption region with an InP avalanche region in an avalanche photodiode (APD) has long been adopted to significantly enhance the sensitivity of the 10 Gb/s receiver modules. Unfortunately InGaAs/lnP APD is unable to provide sufficient bandwidth with appreciable gain at 40 Gb/s due to a low gain-bandwidth product (GBP) that is typically 120-160 GHz. More recent APDs with InAIAs avalanche regions can increase the GBP to around 160-180 GHz [2].

Further improvement in the GBPs of InP and InAIAs based APDs, by reducing the avalanche region thickness, is impeded by the rapid increase in the band to band tunnelling current which imposes a lower avalanche region width of 150 nm [3]. New materials either with significantly superior ionization coefficient ratios or much lower tunneling currents to achieve much thinner avalanche regions will be necessary to increase the GBPs significantly above 300 GHz to provide major improvement over InGaAs pin at 40 Gb/s. Recent work by Kang et al. [4] reported a GBP of 340GHz using a Si avalanche region with an effective hole to electron ionization coefficients ratio, k = 0.08, and a Ge absorption region. However in this Ge/Si APD the dark current is higher and the quantum efficiency is lower at 1 .55 μηι than conventional InGaAs/lnP APD. InAs electron-APDs have demonstrated negligible hole ionization leading to a gain independent excess noise factor below 2 [5]. In our InAs electron-APDs the bandwidth is determined by the total time taken for electrons and holes to transit the avalanche region, independent of gain and hence in theory can provide unlimited GBP. However there are several challenges in InAs APDs before their unlimited GBP can be utilized in 40 and 100 Gbs optical networks. These include reduction of the surface leakage current and optimization of microwave bond pads due to the absence of semi-insulating lattice matched substrate. We have recently reported the current-voltage and breakdown characteristics of a thin AIAso.56Sbo.44 (hereafter referred to as AIAsSb) avalanche regions [6]. The breakdown field in APDs with avalanche region widths of 80 nm was found to be 1 .1 MV/cm and no measureable band to band tunneling current was observed at this field, which is significantly higher than the fields of -600 kV/cm in InP and 650 kV/cm in InAIAs APDs when onset of tunneling was observed. In addition to low tunneling current the AIAsSb APDs also exhibit an extremely small temperature dependence of breakdown voltage varying by only 0.95 mK/K. In this work we demonstrate for the first time the potential of combining the wide bandgap AIAsSb with an InGaAs absorption layer on an InP substrate, for future high performance APDs. Experimental Details and Results

A separate absorption and multiplication (SAM) APD structure comprising a 500 nm InGaAs absorption layer, 50 nm InGaAIAs (with a bandgap of 1 eV) grading layer, 105 nm InAIAs bandgap grading/field control layers, a 44 nm AIAsSb field control and a 50 nm AIAsSb avalanche region was grown by molecular beam epitaxy. Circular mesa diodes with diameters of 50, 100, 200, 400 μηι were fabricated by wet etching using 1 : 8: 80 mixture of Sulphuric acid: Hydrogen peroxide: deionized water, followed by a finishing etch using 1 :1 :5 mixture of Hydrochloric acid: Hydrogen peroxide: deionized water. Ti/Au (20 nm/200 nm) was deposited to form the top and bottom electrical contacts without annealing. The dark current-voltage characteristics of these unpassivated mesa diodes are shown in figure 1 (a). Dark current measurements showed incomplete suppression of surface leakage current. However an acceptable number of devices, particularly those with radius > 25 μηι, showed reasonably low dark current which scales with the area indicating the dominance of bulk dark current. The diodes show an apparent punch- through voltage of -8.2 V, corresponding to the voltage required to achieve a full depletion of the InGaAs absorption layer as shown in figure 1 (b). A step increase in the dark current, associated with the higher dark current from the InGaAs layer, was

is

(a) (b)

Figure 1 : (a) Dark current density obtained from diodes with radius of 25 to 200μηι and (b) Comparison between dark current, photocurrent and calculated tunneling current from the InGaAs absorption layer.

Capacitance-voltage (C-V) measurements were performed on a number of diodes as shown in figure 2(a). The capacitance is proportional to the diode area as expected. A rapid drop in the capacitance, corresponding to the increase in the depletion region was measured between 6.0 to 8.2 V. A full depletion was achieved at -8.2 V corroborating the punch-through voltage deduced from the current-voltage measurements. Relatively constant capacitance was obtained at voltages above 8.2 V since the diode is fully depleted. Modeling of C-V was performed to estimate the doping and electric field profile of the SAM-APD. Dielectric constants of 10.95, 12.5 and 13.5 were assumed for AIAsSb, InAIAs and InGaAs respectively. Good fit to measured C-V, as shown in figure 2(b), was achieved when the following assumptions; a doping concentration of 1 x10 ⁷ cm ³ in the AIAsSb field control layer, lower than the intended value, higher doping concentrations in the InGaAs absorption and InAIGaAs grading layers and thinner AIAsSb multiplication layer were used. The last two assumptions were thought to be reasonable to account for diffusion of dopants from the high doped p and n layers. A comparison of parameters used in the C-V fitting and nominal values is provided in table 1 .

0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 Reverse bias (v) Reverse bias (V)

(a) (b)

Figure 2: (a) Measured capacitance for diodes with radius of 25, 50, 100 and 200 μηι and (b) Comparisons between measured, modelled and targeted C-V.

A customised circuit [7,8] was used for avalanche gain, M, and excess noise, F, measurements. Using the phase sensitive detection, the gain and excess noise can be measured independent of the dark current and system noise. A 1 .55 μηι He-Ne laser was used to provide pure electron injection profile for the measurements. In order to deduce the avalanche gain in our SAM-APD, it is necessary to measure the responsivity value at the punch-through voltage to provide a reference for photocurrent value at unity gain. A responsivity value of -436 mA/W was measured under optical powers ranging from 200-260 μ\Λ , assuming a semiconductor reflectivity of 0.3. This responsivity value is higher than the theoretical maximum value of 413 mA/W expected in our 500 nm InGaAs absorption layer, assuming an absorption coefficient of 8.0x10³ /cm [9] suggesting an avalanche gain of at least /W~1 .06 at the punch-through voltage. Typical avalanche gain and the associated excess noise factors measured using a 1 .55 μηι laser are shown in figure 3. The breakdown voltage of this SAM-APD is -26.5 V. Low excess noise factors falling between the lines k = 0.1 to 0.15 in the local noise theory [10] were measured at M > 6.

Figure 3: Measured avalanche gain (left) and excess noise factor (right). The lines corresponding to k = 0 to 0.20 (with an increment of 0.05), in the local noise theory [10] and excess noise measured on an InAIAs pin diode with an avalanche region of 100 nm are included for comparison. Discussion

The measured dark current is thought to be predominantly due to the generation recombination currents, at low bias voltage and band to band tunneling current from the narrow band gap InGaAs absorption layer at high bias. To estimate the tunneling current we modeled our C-V to extract the doping profile and calculate the electric field profile as shown in figure 4. The targeted C-V and electric field profiles are also shown for comparison in figures 2(a) and 4 respectively. It can be seen from figure 2(b) that the full depletion should be achieved at a punch-through voltage of 12.4 V compared to 8.2 V. The intended doping profile should produce two distinct drops in the capacitance at voltages of 4.4 and 1 1 .9 V as the device depletion region extends beyond the AIAsSb and InAIAs charge sheets respectively. The deduced and intended electric field profiles are significantly different. These deviations can be predominantly attributed to the low Be doping concentration in the AIAsSb field control layer of ~1 x10¹⁷cm ³ compared to the targeted value of 1 x10¹⁸cm^"3. This leads to high electric fields, significantly above 200 kV/cm, in the InGaAs layer resulting in high tunneling current which can be estimated using [1 1 ]

(1 )

where m is the effective electron mass, q is the electron charge, F is the electric field, A is the device area, h is the Plank's constant, E₉ is the direct band gap and στ- is the constant dependent on the barrier shape. σ_τ = 1 .21 was found to yield good fit to the measured dark current at the voltages above 22.0 V, confirming the presence of tunneling current in the InGaAs layer, as shown in figure 1 (b).

At the punch-through voltage of 8.2 V, our model suggests that the electric fields in the InAIAs and AIAsSb i-regions are 442 and 516 kV/cm respectively. The onset of avalanche gain in an InAIAs pin diode with an avalanche region of 100 nm has been measured at a field of -363 kV/cm (/W=1 .01 ) [12] while our recent work on AIAsSb pin diode with an avalanche region of 80nm suggested that avalanche gain is measurable when the field exceeds 489 kV/cm (/W=1 .01 ) [6]. It is therefore not surprising that /W-1 .06 was measured at -8.2 V in our SAM-APD as small gains can be expected from both InAIAs and AIAsSb i-regions. Using a 633nm laser we have also performed shot noise measurements of our SAM-APD biased at 8.2 V and compared the measured noise to that of a commercial Si pin diode. At a given photocurrent the ratio of the shot noise of our SAM-APD to that of a Si pin diode yields /W~1 .05 consistent with the value derived from the responsivity data.

The simulated electric field profiles also showed that the field in the InGaAs absorption layer exceeds 200 kV/cm at 22.0 V consistent with the onset of significant tunneling current observed in figure 1 (b). Increasing the charge density in both the InAIAs and AIAsSb field control layers will be necessary to suppress the tunneling current. Two field control layers were adopted in our design since the field required to achieve high gain in thin AIAsSb is > 1 MV/cm while field < 200 kV/cm in the InGaAs absorption layer is essential to control the tunneling current. Moreover the InAIAs layers also act as bandgap grading layers to minimize carrier trapping at the heterojunctions.

2e-7 4e-7 6e-7 4e-7 6e-7

Depletion width (m) Depletion width (m)

Figure 4: Deduced and intended electric field profiles at punch-through voltages (left) and at a higher bias of 22.0 V (right).

The measured excess noise is slightly lower than those measured in an InAIAs pin diode with a 100 nm avalanche region. This is encouragingly low despite the low Be doping in the AIAsSb charge sheet that leads to higher than intended electric fields in both the InAIAs i-region and the InGaAs absorption region. The former leads to a wider avalanche region than the targeted design while the latter give rise to tunneling current at high voltage as shown in figure 1 (b). We believe the low measured excess noise can be attributed to the dead space effects in the 50 nm InAIAs and 40 nm AIAsSb i-regions. Further reduction in the excess noise should be possible by increasing the Be doping concentration in the AIAsSb charge sheet to confine the avalanche multiplication in the AIAsSb i-region only. This should enhance the dead space effects leading to further reduction in excess noise.

In addition to the improved excess noise, we have recently shown that a thin 80 nm

AIAsSb avalanche region exhibits a temperature coefficient of breakdown voltage as low as 0.95 mK/V [6]. This is significantly lower than the temperature coefficients of InP and InAIAs avalanche regions. Therefore we believe that AIAsSb avalanche regions thinner than 100 nm are highly promising for reducing the excess noise factors, achieve a sub mV/K temperature coefficient of breakdown voltage and to reduce avalanche built up time so that the gain-bandwidth product can be enhanced significantly.

Table 1 : Structural details of the SAM-APD

Layer Material Dopant Doping concentration (cm^"3) Thickness (nm

Nominal Fitted Nominal Fitted p⁺ cap InGaAs Be 1 x10 ^{I M} 1 x10 ^{I M} 10 10 p⁺ cladding InAIAs Be >5x10 ^{I B} 5 x10 ^{I B} 300 300 grading InAIGaAs — undoped 1 x10 ^{I B} 50 50

(E_g =1 .1 eV)

i-absorber InGaAs -- undoped 6x10 '^a 500 500 grading InAIGaAs — undoped 6 x10 '^a 50 50

(E_g =1 .1 eV)

p charge sheet InAIAs Be 5 x10 " 5 x10 " 55 55 intrinsic InAIAs -- undoped 1 x10 '^a 50 50 p charge sheet AIAsSb Be 1 x10 ^{I B} 1 x10 " 44 44 i multiplication AIAsSb -- undoped 1 x10 '^a 50 40 n⁺ cladding AIAsSb Si >5 x10 ^{I B} 5 x10 ^{I B} 100 100 n⁺ etch stop InGaAs Si 1 x10 ^{I M} 1 x10 ^{I M} 300 300

Conclusions

A SAM APD incorporating a 40 nm AIAsSb avalanche region and a 500 nm InGaAs absorption region has been grown and characterized. A reasonably low dark current density of 8x10^"6 A/cm² was measured at the punch-through voltage of 8.2 V. A high responsivity of 436 mA/W was measured at 8.2 V using a 1 .55 μηι laser. This suggests no significant carrier trapping at the heterojunctions and a non-unity gain at punch- through. A gain of /W~1 .06 was deduced by comparing the measured and theoretical responsivities and corroborated by shot noise measurements on Si pin diodes.

The lower than intended doping concentration in the AIAsSb field control layer increases the fields in the InGaAs layer above 200 kV/cm leading to significant tunneling current as well as higher than intended field in the InAIAs layers. Consequently avalanche multiplication from both the InAIAs and AIAsSb i-layers contribute to the overall mean gain. Despite this excess noise lower than that from an InAIAs pin diode with a 100nm avalanche region was measured. The measured excess noise yields an effective k -0.1 to 0.15. Use of thinner avalanche region should improve the excess noise. Therefore we believe AIAsSb avalanche regions with thicknesses below 100nm are highly promising for low noise APD as well as providing high thermal stability due to their small temperature coefficients of breakdown.

Acknowledgement

Shiyu Xie and Jingjing Xie would like to thank University of Sheffield and Chinese Scholarship Council (CSC) funding their PhD studentships. We would like acknowledge IQE for technical contribution to wafer growth, The EPSRC National Centre for lll-V Technologies, U.K. for access to fabrication facilities and J.S.Ng for critical proof reading. This work is funded by a University Of Sheffield Proof of Concept fund

(X004142-1 ).

References

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Claims

CLAIMS:

1 . An avalanche photodiode structure having a multiplication layer and an absorption layer provided on a substrate, wherein

the multiplication layer has a thickness less than or substantially equal to 1000

Angstroms (100nm), and

the multiplication layer comprises a layer of AIAsSb, AlPSb or GaPSb.

2. A structure as claimed in claim 1 wherein the absorption layer comprises an InGaAs/GaAsSb superlattice layer, said superlattice layer comprising sub-layers of

InGaAs and GaAsSb.

3. A structure as claimed in claim 2 wherein the InGaAs/GaAsSb superlattice layer is a type II superlattice layer.

4. A structure as claimed in claim 3 wherein the GaAsSb sub-layers are arranged to be lattice matched to the InGaAs sub-layers.

5. A structure as claimed in claimed in claim 4 wherein the GaAsSb sub-layers are further arranged to be lattice mismatched to the substrate.

6. A structure as claimed in any one of claims 3 to 5 wherein the respective compositions of the GaAsSb and InGaAs layers are arranged to reduce an effective optical bandgap of the type II superlattice.

7. A structure as claimed in claim 6 wherein a concentration of In in the InGaAs sub-layer is increased relative to a concentration of In for which the InGaAs sub-layer is lattice matched to the substrate.

8. A structure as claimed in claim 6 or claim 7 wherein a concentration of As in the GaAsSb sub-layer is increased relative to a composition in which the GaAsSb sub-layer is lattice matched to the substrate.

9. A structure as claimed in any one of claims 2 to 8 wherein the sub-layers of the superlattice layer each have a thickness in the range of from around 1 nm to around 20 nm.

10. A structure as claimed in claim 9 wherein the sublayers have a thickness in the range of around 5 nm.

1 1 . A structure as claimed in any one of claims 2 to 1 0 wherein the superlattice comprises from around 10 to around 400 periods of InGaAs sublayers and sublayers of GaAsSb, AIAsSb, AlPSb or GaPSb, preferably around 1 00 to around 300 periods, more preferably from around 1 50 to around 200 periods.

12. A structure as claimed in any preceding claim further comprising one or more charge sheet layers between the multiplication layer and the absorption layer, wherein

each of the one or more charge sheet layers has a doping density N_ch(i) and thickness x_ch(i), and

the sum over the one or more charge sheet layers of the product of the doping density of each charge sheet layer N_ch(i) and the corresponding thickness of the charge sheet layer x_ch(i),∑iN_ch(i)x_Ch(i) is around 5.1 7x10¹⁶m^"2 or greater.

13. A structure as claimed in any preceding claim wherein the substrate comprises InP, or wherein the substrate consists substantially of InP.

14. A structure as claimed in any preceding claim wherein the multiplication layer comprises a layer of AIAsSb, and the AIAsSb layer is formed from

wherein either

x is the range of from around 0.5 to around 0.6, preferably around 0.56, or x is in the range from around 0.1 to around 0.2, preferably 0.1 6.

15. A method of detecting radiation, comprising :

providing an avalanche photodiode structure according to any of claims 1 to 14.