WO2011142331A1 - 入力装置及びその製造方法 - Google Patents
入力装置及びその製造方法 Download PDFInfo
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- WO2011142331A1 WO2011142331A1 PCT/JP2011/060701 JP2011060701W WO2011142331A1 WO 2011142331 A1 WO2011142331 A1 WO 2011142331A1 JP 2011060701 W JP2011060701 W JP 2011060701W WO 2011142331 A1 WO2011142331 A1 WO 2011142331A1
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- insulating layer
- layer
- electrode layer
- electrode
- substrate
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/045—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
- G06F3/0354—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
- G06F3/03547—Touch pads, in which fingers can move on a surface
Definitions
- the present invention relates to an input device formed by bonding a lower substrate and an upper substrate having a transparent conductive layer and an electrode layer formed on the surface of a substrate via an adhesive layer.
- the electrode layer is electrically connected to the transparent conductive layer formed in the input area and routed around in the non-input area.
- the lower substrate 5 is a lower substrate 9 having a transparent conductive layer such as ITO formed on the substrate surface, and a lower substrate And an insulating layer 4 formed from the surface of the electrode layers 1 and 2 to the surface of the lower base material 9 extending around the electrode layers 1 and 2 Ru.
- the lower substrate 5 and the upper substrate 7 are bonded through the adhesive layer 8 to complete the input device.
- a step is formed between each electrode layer 1, 2 and the lower base material 9 extending around the electrode layer 1, 2.
- the space 10 is a vent that leads from the input region between the lower substrate 5 and the upper substrate 7 to the outside, which causes a problem that the sealing performance between the lower substrate and the upper substrate is reduced.
- the decrease in the adhesion between the insulating layer 4 and the adhesive layer 8 has become a problem.
- Patent Document 1 a configuration in which a sealing material is interposed between the upper and lower substrates located outside the electrode layer is disclosed, but with such a configuration, the sealing material and the electrode layer There is a gap between them.
- the configuration in which the upper and lower substrates outside the electrode layer are joined with a single layer of sealing material it becomes difficult to control the film thickness of the sealing material, and the one sealing material stabilizes between the upper and lower substrates located outside the electrode layer. Sealing is considered difficult.
- Patent Document 1 since it is a single adhesive layer interposed between the electrode layer on the lower substrate side and the electrode layer on the upper substrate side, sufficient electrical insulation between the upper and lower electrode layers is secured. It is considered impossible.
- Patent Document 6 discloses a configuration in which an insulating layer (symbol 12 in FIG. 1 of Patent Document 6) is formed between bus bars provided on a transparent conductive layer.
- This insulating layer is provided as a countermeasure against Newton rings.
- the present invention is intended to solve the above-mentioned conventional problems, and in particular, an input device capable of effectively improving the sealability and adhesion between the lower substrate and the upper substrate as compared with the prior art, and the manufacture thereof Intended to provide a method.
- a pair of substrates are disposed opposite to each other in the height direction, and each substrate is formed in the base on which the transparent conductive layer is formed on the surface, and in the non-input area outside the input area on the surface of the base
- an input device configured to have the following electrode layers, and the respective substrates are joined via the adhesive layer
- a first insulating layer is formed in a step between the electrode layer and the base material, and a second insulating layer is formed from the surface of the first insulating layer to the surface of the electrode layer.
- the adhesion layer is provided on the surface side of the second insulation layer.
- a pair of substrates are disposed opposite to each other in the height direction, and each substrate is a substrate having a transparent conductive layer formed on the surface, and a non-input area outside the input area on the surface of the substrate.
- a method of manufacturing an input device having a formed electrode layer and bonding the substrates together via an adhesive layer Forming a first insulating layer in a step between the electrode layer and the base material in a non-input area of at least one of the substrates; Forming a second insulating layer from the surface of the first insulating layer to the surface of the electrode layer;
- the pressure-sensitive adhesive layer is interposed between the pair of substrates, and at this time, the surface side of the second insulating layer is directed to the pressure-sensitive adhesive layer, and the pair of substrates is bonded by the pressure-sensitive adhesive layer Process, It is characterized by having.
- the second insulating layer is formed by filling the step between the electrode layer and the base material with the first insulating layer and forming the second insulating layer from the surface of the first insulating layer to the surface of the electrode layer.
- Surface flatness can be improved. Therefore, in a state where the second insulating layer is directed to the adhesive layer side, by bonding the respective substrates via the adhesive layer, the adhesive layer and the second insulating layer can be properly adhered over the entire area.
- the bonding area between the adhesive layer and the second insulating layer can be expanded. Therefore, according to the configuration of the present invention, it is possible to effectively improve the sealing property and adhesion between the substrates as compared with the prior art.
- both of the pair of substrates are configured to include the first insulating layer and the second insulating layer, and the second insulating layer provided on one of the substrates, and the other. It is preferable that the second insulating layer provided on the substrate is joined via the adhesive layer. This makes it possible to more effectively improve the sealability and adhesion between the substrates.
- a plurality of the electrode layers are disposed to face each other at an interval on the surface of the same base material, and the first insulating layer is provided in the interval.
- the second insulating layer is formed from the surface of the electrode layer to the surface of the first insulating layer located between the electrode layers.
- the electrode layer is formed from the side portion of the input area to a connection portion with an external connection terminal, and the electrode layer is formed outside the electrode layer facing the input area via the electrode layer.
- the first insulating layer is provided, and the second insulating layer is formed from the surface of the electrode layer to the surface of the first insulating layer located outside the electrode layer.
- a gap be formed between the first insulating layer and the electrode layer.
- the uneven shape becomes large from the surface of the first insulating layer to the surface of the electrode layer due to the saddle phenomenon or the like.
- the electrode layer is electrically connected to the transparent conductive layer located in the input region, and an extended electrode layer extended to a connection portion with an external connection terminal, and the extended electrode layer And a dummy electrode layer formed integrally with or separately from
- the first insulating layer is formed on both the step between the extension electrode layer and the base and the step between the dummy electrode layer and the base, and
- the second insulating layer is formed from the surface to the surface of the first insulating layer and from the surface of the dummy electrode layer to the surface of the first insulating layer.
- the dummy electrode layer is provided so that the substrates can be joined with flat surfaces as much as possible, with the height being equal to that of the extended electrode layer.
- the first insulating layer is also formed on the step formed between the dummy electrode layer and the base material, and the second insulating layer is formed from the surface of the first insulating layer to the surface of the dummy electrode layer.
- Form an insulating layer In the present invention, the effect of providing the dummy electrode layer is also added, and the surface of the second insulating layer can be further planarized, and sealing and adhesion between the substrates can be more effectively improved.
- first insulating layer and the second insulating layer it is preferable to form the first insulating layer and the second insulating layer by screen printing.
- both the first insulating layer and the second insulating layer can be appropriately formed, and the flatness of the surface of the second insulating layer can be effectively improved.
- the first insulating layer and the second insulating layer can be formed of a UV curing resin.
- the input device of the present invention it is possible to effectively improve the sealing property and the adhesion between the upper and lower substrates, as compared with the prior art.
- FIG. 2 An enlarged perspective view showing a lower electrode layer and a first insulating layer, A partial longitudinal sectional view when the input device shown in FIG. 1 is cut along line AA and viewed from the arrow direction, A partially enlarged plan view showing an enlarged part of the lower substrate; A partially enlarged back view showing an enlarged part of the upper substrate,
- FIG. 6 is a partially enlarged longitudinal sectional view of the input device of the present embodiment taken along the line B-B in FIG.
- FIG. 8 is a partially enlarged longitudinal sectional view showing an enlarged region surrounded by a symbol C in FIG.
- FIG. 10 is a partially enlarged vertical cross-sectional view showing the vicinity of the lower substrate in an enlarged manner for explaining problems of the input device in the related art.
- FIG. 1 is a perspective view of an input device (touch panel) in the present embodiment
- FIG. 2 is an exploded perspective view of the input device in the present embodiment
- FIG. 3 shows a lower electrode layer and a first insulating layer in FIG. 4 is a partial vertical cross-sectional view of the input device shown in FIG. 1 cut along the line AA and viewed from the arrow direction
- FIG. 5 is an enlarged view of a part of the lower substrate 6 is a partial enlarged back view showing a part of the upper substrate in an enlarged manner
- FIG. 7 is a sectional view of the input device of this embodiment taken along the line B--B in FIG.
- FIG. 8 is a partially enlarged longitudinal sectional view showing an enlarged region surrounded by reference symbol C in FIG. 7 when partially enlarged.
- the input device 20 shown in FIG. 1 constitutes a resistive input device.
- the input device 20 is configured to have a lower substrate 22, an upper substrate 21, a surface member 60, and a flexible printed circuit 54.
- each layer (each member) constituting the lower substrate 22 is disassembled and shown. Was shown without disassembly.
- the lower substrate 22 is a film-like lower substrate 50 in which a transparent conductive layer such as ITO is formed on the surface of a translucent substrate, lower electrode layers 32, 33, and a first insulating layer. 52 and the second insulating layer 53 are configured.
- a transparent conductive layer such as ITO
- “translucent” or “transparent” refers to a state in which the visible light transmittance is 80% or more. Furthermore, it is preferable that the haze value is 6 or less.
- a support plate 55 made of a translucent base material is provided on the lower surface side of the lower substrate 22, and an optical transparent adhesive (OCA) is provided between the lower substrate 22 and the support plate 55. It is joined through.
- OCA optical transparent adhesive
- the upper substrate 21 is opposed to the lower substrate 22 at a predetermined distance in the height direction (Z).
- the upper substrate 21 also has the same configuration as the lower substrate 22. That is, the upper substrate 21 includes a film-like upper substrate in which a transparent conductive layer such as ITO is formed on the surface of a light-transmissive substrate, an upper electrode layer, a first insulating layer, and a second insulating layer. It is configured to have.
- the translucent base material used for the lower substrate 22 and the upper substrate 21 is polycarbonate resin (PC resin), polyethylene terephthalate resin (PET resin), polyethylene naphthalate resin (PEN resin), cyclic polyolefin (COP resin), polymethacrylic acid It is formed of a transparent base material such as methyl resin (acrylic) (PMMA) and has a thickness of about 38 ⁇ m to 300 ⁇ m. At least the light-transmissive substrate used for the upper substrate 21 needs to be formed of a film or the like in order to ensure flexibility.
- PC resin polycarbonate resin
- PET resin polyethylene terephthalate resin
- PEN resin polyethylene naphthalate resin
- COP resin cyclic polyolefin
- PMMA methyl resin
- At least the light-transmissive substrate used for the upper substrate 21 needs to be formed of a film or the like in order to ensure flexibility.
- the transparent conductive layer used for the lower substrate 22 and the upper substrate 21 is formed by depositing an inorganic transparent conductive material such as ITO (Indium Tin Oxide), SnO 2 or ZnO by sputtering or vapor deposition. Alternatively, fine powders of these inorganic transparent conductive materials may be fixed. Alternatively, the organic transparent conductive material may be coated with an organic conductive polymer such as carbon nanotubes, polythiophine, or polypyrrole.
- each lower substrate and upper substrate is formed, for example, by screen printing an Ag coating film.
- Each electrode layer is formed on the transparent conductive layer formed on the surface of the light-transmissive substrate. Alternatively, a part of the electrode layer may be formed on the surface of the transparent substrate exposed by removing the transparent conductive layer.
- the lower substrate 22 and the upper substrate 21 are joined via the adhesive layer 40 in a non-input area 20b located on the outer periphery of the input area 20a.
- the adhesive layer 40 is an acrylic double-sided tape or an acrylic adhesive.
- an air layer 44 is provided between the lower substrate 22 and the upper substrate 21. Although not shown, a large number of dot spacers are provided in the air layer 44.
- the surface member 60 shown in FIG. 4 is configured to have a surface layer 61 and a decorative layer 62 formed on the lower surface of the surface layer 61.
- the surface layer 61 is formed of a flexible translucent substrate.
- the decorative layer 62 is formed in the non-input area 20b.
- the surface member 60 and the upper substrate 21 are bonded to each other via a translucent adhesive layer 63.
- the upper substrate 21 bends downward, and each of the lower substrate 22 and the upper substrate 21 located in the input area 20a.
- the transparent conductive layers abut on each other.
- a detection output (voltage) corresponding to the contact position between the transparent conductive layers can be obtained by the electrode layer electrically connected to each transparent conductive layer, and based on the detection output, in the input area 20a It is possible to detect the operation position.
- the configuration of the lower substrate 22 will be described in more detail.
- the lower electrode layers 32 and 33 constituting the lower substrate 22 shown in FIGS. 2 and 3 are on the lower substrate 50 on the surface of which a transparent conductive layer such as ITO is formed, and on the outer periphery of the input region 20a. It is formed in the non-input area 20b located.
- the electrode layer and the first insulating layer will be partially described with names and symbols attached.
- the lower electrode layer 32 is provided with an X1 side extended electrode layer 32a formed in a slender shape parallel to the Y1-Y2 direction at the side portion on the X1 side of the input region 20a. .
- the X1 side extended electrode layer 32a and the transparent conductive layer located in the input area 20a are electrically connected.
- the lower electrode layer 32 is integrally formed with the X1 side extending electrode layer 32a and the Y2 side end portion of the X1 side extending electrode layer 32a, and the external connection terminal portion of the flexible printed circuit 54 (see FIG. 2)
- a connection portion 32c to be connected and a dummy electrode layer 32b formed extending in the X1-X2 direction from the Y1 side end of the X1 side extension electrode layer 32a are formed.
- the dummy electrode layer 32 b may be formed integrally with or separately from the X1 side extended electrode layer 32 a.
- an X2 side extended electrode layer 33a formed in a slender shape parallel to the Y1-Y2 direction is formed on the side portion on the X2 side of the input region 20a.
- the X2-side extended electrode layer 33a and the transparent conductive layer located in the input area 20a are electrically connected.
- the lower electrode layer 33 is integrally formed with the X2-side extending electrode layer 33a and the Y2-side end portion of the X2-side extending electrode layer 33a, and is formed to extend in the X1-X2 direction.
- a connection portion 33c which is formed in the middle of the electrode layer 33b and the Y2 side extension electrode layer 33b and connected to the external connection terminal portion of the flexible printed board 54 (see FIG. 2), and the X2 side extension electrode layer 33a
- a dummy electrode layer 33d is integrally formed with the Y2 side end portion, and is formed to extend in the X1-X2 direction at a position outside the Y2 side extended electrode layer 33b.
- the dummy electrode layer 33d may be formed integrally with or separately from the X2 side extended electrode layer 33a.
- FIG. 5 shows a planar shape in the vicinity of the connection portion 32c of the lower electrode layer 32, the connection portion 33c of the lower electrode layer 33, the Y2 side extended electrode layer 33b, and the dummy electrode layer 33d.
- the second insulating layer 53 described later is indicated by a dotted line, and the planar shapes of the lower electrode layers 32 and 33 appearing under the second insulating layer 53 and the first insulating layer 52 are illustrated.
- the first insulating layer 52 shown in FIGS. 2, 3 and 5 is located in the non-input area 20b on the X1 side of the input area 20a and extends in the Y1-Y2 direction, and the input area A Y1 side insulating layer 52b located in the Y1 side non-input area 20b of 20a and extending in the X1-X2 direction integrally formed with the X1 side insulating layer 52a, and a non-input area 20b on the X2 side of the input area 20a Located in the non-input area 20b on the Y2 side of the input area 20a, the X2 side insulation layer 52c, which is located integrally with the Y1 side insulation layer 52b and extends in the Y1-Y2 direction.
- the first insulating layer 52 is integrated with both the protruding insulating layer 52g formed integrally in the middle of the Y1 side insulating layer 52b, and the inner Y2 side insulating layer 52d and the outer Y2 side insulating layer 52e. , And the island-like insulating layers 52h and 52i formed separately.
- the first insulating layer 52 does not overlap the lower electrode layers 32 and 33 in the height direction, and is formed at a step between the lower electrode layers 32 and 33 and the lower base material 50.
- the X1 side insulating layer 52a is formed on the outer side of the X1 side extending electrode layer 32a of the lower electrode layer 32 in a step between the X1 side extending electrode layer 32a and the lower base material 50.
- the outer Y 2 -side insulating layer 52 e is formed outside the dummy electrode layer 33 d of the lower electrode layer 33 in a step between the dummy electrode layer 33 d and the lower base 50.
- the inner Y2-side insulating layer 52d is formed in the space D between the Y2-side extending electrode layer 33b and the dummy electrode layer 33d that constitute the lower electrode layer 33.
- the protruding insulating layer 52f and the island-shaped insulating layer 52h are formed on the outside of the Y2-side extending electrode layer 33b that constitutes the lower electrode layer 33, with the Y2-side extending electrode layer 33b and the lower group. It is formed in the level
- the island-shaped insulating layer 52 i is a space between the X1-side extending electrode layer 32 a and the connection portion 32 c of the lower electrode layer 32 and the Y2-side extending electrode layer 33 b of the lower electrode layer 33. Formed in E.
- the Y1 side insulating layer 52b is formed outside the dummy electrode layer 32b of the lower electrode layer 32 in the dummy electrode layer 32b and the lower base material 50.
- the X2-side insulating layer 52c is formed on the outer side of the X2-side extending electrode layer 33a of the lower electrode layer 33 in the step between the X2-side extending electrode layer 33a and the lower base material 50. Ru.
- a protruding insulating layer 52g shown in FIG. 3 (not shown in FIG. 5) is formed in the space F between the dummy electrode layer 32b and the X2 side extending electrode layer 33a.
- the gap G between the lower electrode layers 32 and 33 and the first insulating layer 52 (in FIG. 5, the X1 side extended electrode layer 32a of the lower electrode layer 32 is representatively shown).
- the gap between the first insulating layer 52 and the X1 side insulating layer 52a is marked with a symbol).
- the gap G is about 50 to 400 ⁇ m.
- the second insulating layer 53 shown in FIGS. 2 and 5 is formed from the surface of each lower electrode layer 32, 33 in the non-input area 20b to the surface of the first insulating layer 52. As shown in FIG. 5, the second insulating layer 53 is not formed at the positions of the connection portions 32c and 33c of the lower electrode layers 32 and 33, and the connection portions 32c and 33c are exposed. This makes it possible to electrically connect the connection portions 32 c and 33 c and the external connection terminal portions of the flexible printed circuit 54.
- the inner side surface 53b of the second insulating layer 53 is formed more inward than the inner side surfaces 32g and 33g of the lower electrode layers 32 and 33, and the inner side surfaces 32g and 33g of the lower electrode layers 32 and 33 are the second It is preferable to be covered by the insulating layer 53 of
- FIG. 6 is a partially enlarged rear view of the upper substrate 21. As shown in FIG. In FIG. 6, the second insulating layer 65 formed on the upper substrate 21 is indicated by a dotted line, and the planar shapes of the upper electrode layer and the first insulating layer are illustrated.
- the upper substrate 21 is formed on the upper substrate 66 on which a transparent conductive layer such as ITO is formed on the surface of the translucent substrate, and the surface of the upper substrate 66 (the surface on the side facing the lower substrate 22).
- a pair of upper electrode layers 45 and 46, a first insulating layer 67, and a second insulating layer 65 are provided.
- the upper electrode layers 45 and 46 are formed in the non-input area 20 b located on the outer periphery of the input area 20 a of the upper base 66.
- a Y2-side extended electrode layer 45a extending in the X1-X2 direction is formed in the non-input area 20b on the Y2 side of the input area 20a.
- the Y2 side extended electrode layer 45a is electrically connected to the transparent conductive layer located in the input area 20a. Then, the upper electrode layer 45 is connected to the X1 side end of the Y2 side extended electrode layer 45a in the Y2 side extended electrode layer 45a and the non-input area 20b on the X1 side of the input area 20a.
- the dummy electrode layer 45b extending in the direction, and the connection portion 45c formed in the middle of the Y2-side extension electrode layer 45a and electrically connected to the external connection terminal portion of the flexible printed circuit 54 Be done.
- the dummy electrode layer 45b and the Y2 side extended electrode layer 45a may be integrally formed or separately formed.
- a Y1 side extended electrode layer (not shown) extending in the X1-X2 direction is formed in the non-input area 20b on the Y1 side of the input area 20a.
- the Y1 side extension electrode layer is electrically connected to the transparent conductive layer located in the input area 20a.
- the upper electrode layer 46 is connected to the X1 side end portion of the Y1 side extending electrode layer in the Y1 side extending electrode layer and the non-input area 20b on the X2 side of the input area 20a in the Y1-Y2 direction.
- the Y2-side extending electrode formed integrally with the extending X2-side extending electrode layer (not shown) and the Y2-side end portion of the X2-side extending electrode layer and located outside the Y2-side extending electrode layer 45a
- a layer 46a and a connection portion 46b located at the tip of the Y2-side extended electrode layer 46a and electrically connected to the external connection terminal portion of the flexible printed circuit 54 are configured.
- the first insulating layer 67 is formed on the X1-side insulating layer 67a formed on the step between the dummy electrode layer 45b and the upper base 66 outside the dummy electrode layer 45b, or on the Y2 side. It is located inside the outer Y 2 side insulating layer 67 b and the outer Y 2 side insulating layer 67 b formed in the step between the Y 2 side extended electrode layer 46 a and the upper base 66 outside the outgoing electrode layer 46 a. And Y2 side insulating layer 67c etc. which are formed in the space H between the Y2 side extending electrode layer 45a and the Y2 side extending electrode layer 46a.
- the first insulating layer 67 is also formed outside the upper electrode layers 45 and 46 not appearing in FIG. 6 or in the space between the upper electrode layers.
- the second insulating layer 65 is formed from the surface of each of the upper electrode layers 45 and 46 to the surface of the first insulating layer 67.
- the second insulating layer 65 is not formed at the positions of the connection portions 45c and 46b, and the connection portions 45c and 46b are exposed. Therefore, the connection portions 45 c and 46 b can be electrically connected to the external connection terminal portions of the flexible printed circuit 54.
- the inner side surface 65b of the second insulating layer 65 is formed inward of the inner side surface 45g of the upper electrode layers 45 and 46 (only the inner side surface 45g of the upper electrode layer 45 is shown in FIG. 6).
- the inner side surface 45 g of the upper electrode layers 45 and 46 is covered by the second insulating layer 65.
- FIG. 7 is a partial vertical cross-sectional view of the input area 20 in the present embodiment taken along the line AA shown in FIG. In FIG. 7, the surface member 60 shown in FIG. 2 and FIG. 4 is not shown.
- FIG. 8 is a partially enlarged vertical sectional view of a region enclosed by reference symbol C shown in FIG.
- the X1-side insulating layer 52a and the island-like insulating layer 52i constituting the first insulating layer 52 formed on the lower substrate 22 side shown in FIGS. 7 and 8 extend the X1 side constituting the lower electrode layers 32 and 33.
- the electrode layer 32a and the Y2-side extended electrode layer 33b are formed to have substantially the same height dimension.
- the X1-side insulating layer 67a forming the first insulating layer 67 formed on the upper substrate 21 side shown in FIGS. 7 and 8 is substantially equivalent to the Y2-side extending electrode layer 45a forming the upper electrode layer 45. It is formed in the height dimension.
- the other first insulating layers 52 and 67 are also formed to have substantially the same height as the lower electrode layers 32 and 33 and the upper electrode layers 45 and 46.
- the first insulating layers 52 and 67 and the second insulating layers 53 and 65 can be formed at predetermined positions by screen printing, for example.
- first insulating layers 52 and 67 and the second insulating layers 53 and 65 have surfaces of the respective electrode layers 32, 33, 45 and 46, and the surface of the translucent base 30 shown in FIG.
- a material is used which does not weaken the adhesion between the transparent conductive layer 31 and each electrode layer even if it is superimposed on the transparent conductive layer 31 provided on the substrate.
- a resist material, a thermosetting resin, a thermoplastic resin or the like can be used for each of the first insulating layers 52 and 67 and each of the second insulating layers 53 and 65, but a UV curing resin is particularly preferable. is there.
- the first insulating layers 52 and 67 and the second insulating layers 53 and 65 may be the same material or different materials.
- the gap G is opened between each of the first insulating layers 52, 67 and the lower electrode layers 32, 33 and the upper electrode layers 45, 46.
- the end portions of the first insulating layers 52 and 67 swell due to the saddle phenomenon. Therefore, adjustment is made so that no gap is formed between the first insulating layers 52 and 67 and each electrode layer, and temporarily, a part of the end of the first insulating layers 52 and 67 overlaps the surface of the electrode layer. Then, the film thickness at that portion becomes very large, and the unevenness becomes large from the surface of each of the first insulating layers 52 and 67 to the surface of each of the electrode layers.
- each of the first insulating layers 52, 67 from the surface is formed.
- Flatness of the surface of the second insulating layers 53 and 65 formed over the surface of the electrode layer can be effectively improved.
- FIG. 9 is an experimental result which shows the surface shape of the electrode layer in an Example, a 1st insulating layer, and a 2nd insulating layer.
- FIG. 9 (a) shows the surface shapes of the electrode layer and the first insulating layer
- FIG. 9 (b) is formed from the surface of the electrode layer shown in FIG. 9 (a) to the surface of the first insulating layer.
- the surface shape of the 2nd insulating layer is shown.
- FIG. 9A a gap G is formed between the electrode layer and the first insulating layer so that the electrode layer and the first insulating layer do not overlap. By providing the gap G in this manner, it was found that the flatness of the surface of the second insulating layer can be improved as shown in FIG. 9B.
- the gaps G formed between the first insulating layers 52 and 67 and the lower electrode layers 32 and 33 and the upper electrode layers 45 and 46 are filled with the second insulating layers 53 and 65.
- the second insulating layer 53 on the lower substrate 22 side and the second insulating layer 65 on the upper substrate 21 face each other, and between the second insulating layers 53 and 65.
- the adhesive layer 40 is interposed between the lower substrate 22 and the upper substrate 21 via the adhesive layer 40.
- the surfaces 53a and 65a of the second insulating layers 53 and 65 are bonding surfaces with the adhesive layer 40, and the planarity of the second insulating layers 53 and 65 can be effectively improved as described above.
- the bonding area can be increased, and the adhesion between the adhesive layer 40 and the second insulating layer 53, 65 is improved. It is possible.
- the first insulating layers 52 and 67 are formed in the step between the electrode layer and the base material, and the second insulating layers 53 and 65 are formed from the first insulating layers 52 and 67 to the surface of the electrode layer.
- the second insulating layer in the example when a peel strength test was conducted in a comparative example in which one insulating layer was formed from the surface of the electrode layer to the step between the electrode layer and the base material, the second insulating layer in the example and It has been found that the adhesive strength between the adhesive layers can be made about 2 to 5 times larger than the adhesive strength between the insulating layer and the adhesive layers in the comparative example.
- both the lower substrate 22 and the upper substrate 21 may have a configuration in which the first insulating layers 52 and 67 and the second insulating layers 53 and 65 are provided on the surface of the base material, it is shown in the above embodiment.
- both the lower substrate 22 and the upper substrate 21 are provided with the first insulating layers 52, 67 and the second insulating layers 53, 65, and the second insulating layer 53 of the lower substrate 22 and the upper substrate 21 are By bonding between the second insulating layers 65 via the adhesive layer 40, it is possible to more effectively improve the sealability and adhesion between the lower substrate 22 and the upper substrate 21. .
- the electrode layer can be appropriately filled with the insulating layer to suppress formation of a space between the adhesive layer 40 and the sealing property and adhesion between the lower substrate 22 and the upper substrate 21 at the position between the electrode layers. It is possible to improve effectively.
- the same configuration and effects are provided for the portion between the electrode layers of the lower substrate 22 which does not appear in FIG. 5 and the upper substrate 21 side in FIG.
- the first insulating layer 52 is formed outside the X1 side extending electrode layer 32a of the lower electrode layer 32 or outside the dummy electrode layer 33d.
- the side insulating layer 52a and the Y2 side insulating layer 52e are formed, and the second insulating layer 53 is formed on the side insulating layer 52a and the Y2 side insulating layer 52e.
- the input region 20a can be formed large.
- the same configuration and effects are provided for the outside portion of the electrode layer of the lower substrate 22 which does not appear in FIG. 5 and the upper substrate 21 side in FIG.
- dummy electrode layers 32b and 33d are provided.
- the formation of the dummy electrode layers 32b and 33d is not essential. However, by forming the dummy electrode layers 32b and 33d, the heights are made equal to those of the extended electrode layers 32a, 33a and 33b, and bonding of the substrates is performed as much as possible. It can be performed on flat surfaces.
- the first insulating layer 52 is also formed on the steps formed between the dummy electrode layers 32b and 33d and the lower base material 50, and the first insulating layer is formed on the dummy electrode layers 32b and 33d.
- a second insulating layer 53 is formed on the surface 52.
- the planarity of the surface of the second insulating layer 53 can be more effectively improved by adding the effect of providing the dummy electrode layers 32 b and 33 d, and the space between the lower substrate 22 and the upper substrate 21 can be improved. It is possible to more effectively improve the sealing performance and the adhesion.
- the same configuration and effects are provided for the stepped portion between the dummy electrode layer formed on the upper substrate 21 side of FIG. 6 and the upper base 66.
- the first shape of the shape shown in FIG. 3 is due to the step between the lower electrode layers 32 and 33 of the shape shown in FIG.
- the insulating layer 52 is formed by screen printing, for example. At this time, as shown in FIG. 5, FIG. 7 and FIG. 8, a gap G is formed between the lower electrode layers 32 and 33 and the first insulating layer 52.
- the first insulating layer 52 is formed of a UV curing resin, and the first insulating layer 52 is UV cured after being formed by screen printing.
- the second insulating layer 53 is formed on the first insulating layer 52 formed in the non-input area 20b and on the lower electrode layers 32 and 33.
- the second insulating layer 53 is formed by screen printing, for example.
- the second insulating layer 53 is formed of a UV curing resin, and the second insulating layer 53 is UV cured after being formed by screen printing.
- the step between the lower electrode layers 32, 33 and the lower base 50 in the non-input area 20b is filled with the first insulating layer 52, and further, the lower electrode from above the first insulating layer 52.
- the second insulating layer 53 By forming the second insulating layer 53 over the layers 32 and 33, the flatness of the surface of the second insulating layer 53 can be improved.
- the upper substrate 21 can also be formed by the same manufacturing method as described above. Then, with the second insulating layers 53 and 65 of the lower substrate 22 and the upper substrate 21 facing each other, and with the adhesive layer 40 interposed between the second insulating layers 53 and 65, the lower substrate 22. And the upper substrate 21 are bonded by the adhesive layer 40.
- the surfaces of the second insulating layers 53 and 65 having high flatness and a large bonding area are used as the bonding surface with the adhesive layer 40, the sealing property and adhesion between the lower substrate 22 and the upper substrate 21 are It becomes possible to improve more effectively.
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Abstract
Description
少なくとも一方の前記基板の非入力領域では、前記電極層と前記基材との間の段差に第1の絶縁層が形成され、前記第1の絶縁層の表面から前記電極層の表面にかけて第2の絶縁層が形成されており、前記第2の絶縁層の表面側に前記粘着層が設けられることを特徴とするものである。
少なくとも一方の前記基板の非入力領域であって、前記電極層と前記基材との間の段差に第1の絶縁層を形成する工程、
前記第1の絶縁層の表面から前記電極層の表面にかけて第2の絶縁層を形成する工程、
前記粘着層を、一対の前記基板の間に介在させ、このとき、前記第2の絶縁層の表面側を前記粘着層に向けた状態にして、一対の前記基板間を前記粘着層により接合する工程、
を有することを特徴とするものである。
前記延出電極層と前記基材との間の段差、及び、前記ダミー電極層と前記基材との間の段差の双方に前記第1絶縁層が形成されており、前記延出電極層の表面から前記第1の絶縁層の表面にかけて、及び、前記ダミー電極層の表面から前記第1の絶縁層の表面にかけて、前記第2絶縁層が形成されていることが好ましい。ダミー電極層は、延出電極層と高さを揃えて、できる限り基板間の接合を平坦面同士で行うことができるように設けられたものである。ダミー電極層を形成したことで、ダミー電極層と基材間に形成される段差にも第1の絶縁層を形成し、前記第1の絶縁層の表面からダミー電極層の表面にかけて第2の絶縁層を形成する。本発明ではダミー電極層を設けた効果も加わって、第2の絶縁層の表面をより平坦化でき、各基板間の密閉性及び密着性をより効果的に向上させることが可能になる。
図2、図3図5に示す下部基板22を構成する下部電極層32,33は、表面にITO等の透明導電層が形成された下部基材50上であって、入力領域20aの外周に位置する非入力領域20bに形成される。
20a 入力領域
20b 非入力領域
21 上部基板
22 下部基板
30 透光性基材
31 透明導電層
32、33 下部電極層
32b、33d、45b ダミー電極層
40 粘着層
45、46 上部電極層
50 下部基材
52,67 第1の絶縁層
53、65 第2の絶縁層
54 フレキシブルプリント基板
55 支持板
60 表面部材
Claims (10)
- 一対の基板が高さ方向に対向配置され、各基板は、表面に透明導電層が形成された基材と、前記基材の表面にて入力領域の外側の非入力領域に形成された電極層とを有して構成され、各基板間が粘着層を介して接合される入力装置において、
少なくとも一方の前記基板の非入力領域では、前記電極層と前記基材との間の段差に第1の絶縁層が形成され、前記第1の絶縁層の表面から前記電極層の表面にかけて第2の絶縁層が形成されており、前記第2の絶縁層の表面側に前記粘着層が設けられることを特徴とする入力装置。 - 一対の前記基板の双方が、前記第1の絶縁層と前記第2の絶縁層とを備えた構成であり、一方の前記基板に設けられた前記第2の絶縁層と、他方の前記基板に設けられた前記第2の絶縁層との間が前記粘着層を介して接合されている請求項1記載の入力装置。
- 前記非入力領域では、同一基材の表面に複数の前記電極層が間隔を空けて対向配置されており、前記間隔内に前記第1の絶縁層が設けられており、複数の前記電極層の表面から前記電極層間に位置する前記第1の絶縁層の表面にかけて前記第2の絶縁層が形成されている請求項1又は2に記載の入力装置。
- 前記電極層が、前記入力領域の側部から外部接続端子との接続部にかけて形成されており、前記電極層を介して前記入力領域と対向する前記電極層の外側に前記第1の絶縁層が設けられており、前記電極層の表面から前記電極層の外側に位置する前記第1の絶縁層の表面にかけて前記第2の絶縁層が形成されている請求項1ないし3のいずれか1項に記載の入力装置。
- 前記第1の絶縁層と前記電極層との間には隙間が形成されている請求項1ないし4のいずれか1項に記載の入力装置。
- 前記電極層は、前記入力領域に位置する前記透明導電層に電気的に接続され、外部接続端子との接続部にまで延出する延出電極層と、前記延出電極層と一体にあるいは別体で形成されたダミー電極層とを有しており、
前記延出電極層と前記基材との間の段差、及び、前記ダミー電極層と前記基材との間の段差の双方に前記第1絶縁層が形成されており、前記延出電極層の表面から前記第1の絶縁層の表面にかけて、及び、前記ダミー電極層の表面から前記第1の絶縁層の表面にかけて、前記第2絶縁層が形成されている請求項1ないし5のいずれか1項に記載の入力装置。 - 一対の基板を高さ方向に対向配置し、各基板を、表面に透明導電層が形成された基材と、前記基材の表面にて入力領域の外側の非入力領域に形成された電極層とを有して構成し、各基板間を、粘着層を介して接合する入力装置の製造方法において、
少なくとも一方の前記基板の非入力領域であって、前記電極層と前記基材との間の段差に第1の絶縁層を形成する工程、
前記第1の絶縁層の表面から前記電極層の表面にかけて第2の絶縁層を形成する工程、
前記粘着層を、一対の前記基板の間に介在させ、このとき、前記第2の絶縁層の表面側を前記粘着層に向けた状態にして、一対の前記基板間を前記粘着層により接合する工程、
を有することを特徴とする入力装置の製造方法。 - 前記第1の絶縁層と前記電極層との間に隙間を形成する請求項7記載の入力装置の製造方法。
- 前記第1の絶縁層及び前記第2の絶縁層をスクリーン印刷で形成する請求項7又は8に記載の入力装置の製造方法。
- 前記第1の絶縁層及び前記第2の絶縁層をUV硬化樹脂により形成する請求項7ないし9のいずれか1項に記載の入力装置の製造方法。
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JP2003196030A (ja) * | 2001-12-28 | 2003-07-11 | Kawaguchiko Seimitsu Co Ltd | タッチパネル |
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JP2002196886A (ja) * | 2000-10-18 | 2002-07-12 | Hitachi Ltd | タッチパネルおよび画面入力型表示装置 |
JP2003196030A (ja) * | 2001-12-28 | 2003-07-11 | Kawaguchiko Seimitsu Co Ltd | タッチパネル |
JP2005071123A (ja) * | 2003-08-26 | 2005-03-17 | Matsushita Electric Ind Co Ltd | タッチパネルおよびこれを用いた電子機器 |
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