WO2011140730A1

WO2011140730A1 - Analog front end device for low frequency signal detection and transmission system

Info

Publication number: WO2011140730A1
Application number: PCT/CN2010/073717
Authority: WO
Inventors: 潘文杰; 赵辉; 蒋宇; 任腾龙; 沈晔; 李超林
Original assignee: 国民技术股份有限公司
Priority date: 2010-05-10
Filing date: 2010-06-09
Publication date: 2011-11-17
Also published as: CN103023584A; CN103023584B

Abstract

An analog front end device for low frequency signal detection and transmission system is provided by the present invention, which is applied to short distance communication system, and includes: at least one magnetic induction module, at least one low pass filtering module, at least one amplifier, at least one digital/analog converter and at least one comparator, said magnetic induction module, said low pass filtering module, and said amplifier are connected in succession, the output port of said amplifier is connected with the positive input port of said comparator, the output port of said digital/analog converter is connected with the negative input port of said comparator, said amplifier is an amplifier with double input port and single output port. The present invention can reduce the interference of circuit noise and environment noise on the low frequency signal received by the low frequency signal detection and transmission system, thereby can improve the accuracy of distance detection and control of low frequency alternating magnetic field.

Description

Analog front end device for low frequency signal detection and transmission system

The present invention relates to the field of communications, and more particularly to an analog front end apparatus for a low frequency signal detection and transmission system. Background technique

Nowadays, there has been a radio frequency function (called a radio frequency SIM card) on the SIM (Subscr iber Ident I ty Module) card in the mobile phone or a short-range communication module on the mobile phone motherboard to realize the short-range communication of the mobile phone. The method, the emergence of this method makes the mobile phone a super smart terminal that can be recharged, consumed, traded and authenticated, which greatly meets the urgent needs of the market.

Among them, the RF SIM-based mobile phone proximity solution has received extensive attention due to its advantages such as the single-sheet and no need to change the mobile phone. In this solution, the RF SIM adopts UHF (Ultra-Ra High Frequency) technology to make the RF. RF signal is still embedded when the SIM card is embedded inside the phone

It can make the mobile phone have close-range communication function. However, different mobile phones have large differences in the transmission effect of radio frequency signals due to different internal structures. The radio frequency SIM card radio communication distance of a mobile phone with strong transmission may reach a distance of several meters, and the radio frequency S IM card communication distance of a mobile phone with weak transmission can also A few tens of centimeters. In mobile payment applications, such as bus and subway card, there are usually strict requirements on the transaction distance to ensure the security of the transaction, such as the transaction distance requirement is limited to 10cm or less, in order to prevent users from accidentally brushing and causing losses; On the other hand, it is also required to ensure the reliability of communication below the prescribed distance to improve the efficiency of the transaction. Therefore, mobile phone SIM-based mobile phones must be able to effectively control the distance range of their transactions while increasing the short-range communication function. Therefore, a system and method for low-frequency alternating magnetic field short-range communication combined with RF high-frequency communication is proposed, which solves the above problems. The system uses low-frequency alternating magnetic field to realize distance detection and control, and realizes one-way communication between the card reader and the card. The RF channel is combined with low-frequency communication to achieve reliable binding of the terminal, and the RF channel is used to realize the card reader and the card. High-speed data communication. However, in this scheme, the low-frequency signal received by the low-frequency signal detection and transmission system (on one side of the card) is mixed with circuit noise and environmental noise, which affects the accuracy of distance detection and control. Therefore, how to effectively reduce the circuit The interference of noise and environmental noise on low-frequency signals has become one of the urgent problems to be solved. Summary of the invention

The technical problem to be solved by the present invention is to provide an analog front end device for a low frequency signal detection and transmission system, which reduces interference of circuit noise and environmental noise on low frequency signal detection and low frequency signals received in a transmission system, and improves low frequency. The accuracy of the alternating magnetic field distance detection and control.

In order to solve the above technical problem, the present invention provides an analog front end device for a low frequency signal detection and transmission system, which is applied to a short-range communication system, including at least one magnetic induction module, at least one low-pass filter module, at least one amplifier, at least a digital/analog converter and at least one comparator, the magnetic induction module, the low pass filter module, and the amplifier are sequentially connected, and an output end of the amplifier is connected to a forward input end of the comparator, the digital/analog The output of the converter is coupled to the inverting input of the comparator, which is a dual-ended input single-ended output amplifier.

Further, the above device may further have the following features, including a magnetic induction module, a low pass filter module, an amplifier, two digital/analog converters, and two comparators, the magnetic induction module, the low pass filter module, and the amplifier Connected once, the output ends of the amplifiers are respectively connected to the forward inputs of the two comparators, and the two digital/analog converters and the two comparators form two paths, each of which is digital/analog The output of the converter is connected to the inverting input of the comparator, and each pair of the upper and lower channels form a pair, a pair.

Further, the above device may also have the following features, including a magnetic induction module, a low a pass filter module, an amplifier, six digital/analog converters, and six comparators, the outputs of which are respectively connected to the forward inputs of the six comparators, the six digital/analog converters The six comparators are combined with the six comparators, and the output of each of the digital/analog converters is connected to the inverting input of the comparator, and each pair of upper and lower channels is paired, and three pairs are provided.

Further, the above device may further have the following features: the magnetic induction module is a magnetic induction coil, a Hall device or a giant magnetoresistive device.

Further, the above device may further have the following features: the magnetic induction module is a magnetic induction coil, and the two output ends of the magnetic induction coil are directly connected to the two input ends of the low-pass filter module.

Further, the above device may further have the following feature, the magnetic induction module is a Hall device, and two output ends of the Hall device are connected to two input ends of the low-pass filter module through a DC blocking capacitor; or One output of the Hall device is connected to one input of the low pass filter module through a DC blocking capacitor, and the other output of the Hall device is directly connected to another input of the low pass filter module; or the Hall The two outputs of the device are directly connected to the two inputs of the low pass filter module.

Further, the above device may further have the following feature, the magnetic induction module is a giant magnetoresistive device, and two output ends of the giant magnetoresistive device are connected to two input ends of the low-pass filter module through a DC blocking capacitor; Or an output end of the giant magnetoresistive device is connected to one input end of the low pass filter module through a DC blocking capacitor, and the other output end of the giant magnetoresistive device is directly connected to the low pass filter module. One input is connected; or the two outputs of the giant magnetoresistive device are directly connected to the two inputs of the low pass filter module.

Further, the above device may further have the following features: the amplifier is a single-stage amplifier or a multi-stage cascade amplifier connected to a resistor negative feedback network.

Further, the above device may further have the following features, the amplifier is a four-stage cascade amplifier, and the composition of the four-stage cascade amplifier is:

The first stage comprises a first double-ended input single-ended output amplifier, and a resistor R _al resistors R _bl; resistance R _al One end is connected to the signal input port IN, and the other end is connected to the inverting input end of the first double-ended input single-ended output amplifier, and the resistor R _{bl is} connected to the inverting input terminal of the first double-ended input single-ended output amplifier and Between the outputs, the common input voltage of the same input terminal of the first double-ended input single-ended output amplifier

VCM;

The second stage includes a second double-ended input single-ended output amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _cl , and a resistor R. ₂ , capacitor and capacitor C ₂ ; resistor R _a2 and resistor R _b2 are connected in series between the common mode voltage VCM and the output of the second double-ended input single-ended output amplifier, the contact of the resistor R _a2 and the resistor R _b2 Connected to the inverting input terminal of the second double-ended input single-ended output amplifier, the resistor and the capacitor are sequentially connected in series between the output of the first double-ended input single-ended output amplifier and the ground GND, the capacitor C ₂ and the resistor R. _{2 is} connected in series between the junction of the resistor and the capacitor d and the common mode voltage VCM, the capacitor C ₂ and the resistor R. a contact of ₂ is connected to the same input terminal of the second double-ended input single-ended output amplifier;

The third stage includes a third double-ended input single-ended output amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _c3 , and a resistor R. _4, the capacitor capacitance C ₃ and C _4; and R _a3 resistance resistor ₁ ¾3 sequentially connected in series between the output terminal of said common mode voltage VCM and a third double-ended input single-ended output amplifier, a resistor R _a3 and R _b3 resistance The contact is connected to the inverting input of the third double-ended input single-ended output amplifier, and the resistor R and the capacitor C ₃ are sequentially connected in series between the output of the second double-ended input single-ended output amplifier and the ground GND. The capacitor C ₄ and the resistor are sequentially connected in series between the junction of the resistor Rc ₃ and the capacitor C _{3 and} the common mode voltage VCM, the capacitor C ₄ and the resistor R. a contact of ₄ is connected to the same input end of the third double-ended input single-ended output amplifier;

The fourth stage includes a fourth amplifier, a capacitor C ₅ and a resistor R _e5 ; a capacitor C ₅ and a resistor ₅ are sequentially connected in series between the output of the third double-ended input single-ended output amplifier and the common mode voltage VCM, and the capacitor C The junction of ₅ and the resistor R _e5 is connected to the non-inverting input terminal of the fourth amplifier, and the inverting input terminal of the fourth amplifier is connected to the output terminal.

The first stage comprises a first double-ended input single-ended output amplifier, a resistor R _al, capacitors and resistors R _bl D; A resistor 1 _{31 is} connected between the signal input terminal IN and the inverting input terminal of the first double-ended input single-ended output amplifier, and the resistor R _bl and the capacitor are connected in parallel in the reverse direction of the first double-ended input single-ended output amplifier Between the input end and the output end, the first double-ended input single-ended output amplifier is connected to the common mode voltage VCM;

The second stage includes a second double-ended input single-ended output amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _c2 , a capacitor C _{2 ,} and a capacitor C ₃ ; the resistor R _{a2 is} connected to the common mode voltage VCM and the second double end Between the inverting input terminals of the input single-ended output amplifier, the resistor R _b2 and the capacitor C ₃ are connected in parallel between the inverting input terminal and the output terminal of the second double-ended input single-ended output amplifier, the capacitor C ₂ and the resistor R _{C2 is} sequentially connected in series between the output of the first double-ended input single-ended output amplifier and the common mode voltage VCM, and the contact of the capacitor C ₂ and the resistor R _c2 is connected to the second double-ended input single-ended output amplifier To the input;

The third stage includes a third double-ended input single-ended output amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _{c4 ,} and a capacitor C ₄ ; the resistor R _a3 and the resistor R _b32 are sequentially connected in series at the common mode voltage VCM and the third Between the outputs of the double-ended input single-ended output amplifier, the junction of the resistor R _a3 and the resistor R _b32 is connected to the inverting input terminal of the third double-ended input single-ended output amplifier, the capacitor C ₄ and the resistor R. _{4 is} sequentially connected in series between the output of the second double-ended input single-ended output amplifier and the common mode voltage VCM, and the contact of the capacitor C ₄ and the resistor R _c4 is connected to the third double-ended input single-ended output amplifier To the input;

The fourth stage includes a fourth amplifier, a resistor R _e5 and a capacitor C ₅ ; a capacitor C ₅ and a resistor ₅ are sequentially connected in series between the output of the third double-ended input single-ended output amplifier and the common mode voltage VCM, and the capacitor C The junction of ₅ and the resistor R _e5 is connected to the non-inverting input terminal of the fourth amplifier, and the inverting input terminal of the fourth amplifier is connected to the output terminal.

The first stage comprises a first amplifier, a resistor R _al, resistors R _bl, R _all resistors and the resistor R _bll; resistor and the resistor R _al ₁ ¾1 sequentially forward signal in series at the output of the first input terminal INP and amplifier between the resistors R _bl and the resistor R _al contacts connected to the inverting input terminal of the first amplifier, a resistor ₁₃₁₁ and The resistor R _{b11 is} sequentially connected in series between the inverted signal input terminal I and the ground GND, and the contact of the resistor R _all and the resistor R _b11 is connected to the same input terminal of the first amplifier;

The second stage includes a second double-ended input single-ended output amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _cl , and a resistor R. ₂ , the capacitor and the capacitor C ₂ ; the resistor R _a2 and the resistor R _b2 are sequentially connected in series between the common mode voltage VCM and the output end of the second double-ended input single-ended output amplifier, and the contact of the resistor R _a2 and the resistor R _b2 Connected to the inverting input terminal of the second double-ended input single-ended output amplifier, the resistor R _cl and the capacitor are sequentially connected in series between the output end of the first amplifier and the ground GND, and the capacitor C ₂ and the resistor R _c2 are sequentially Connected in series between the resistor R _el , the junction of the capacitor and the common mode voltage VCM , the capacitor C ₂ and the resistor R. a contact of ₂ is connected to the same input terminal of the second double-ended input single-ended output amplifier;

The third stage includes a third double-ended input single-ended output amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _c3 , and a resistor R. ₄ , capacitor C ₃ and capacitor C ₄ ; resistor R _a3 and resistor 1 _3⁄43 are connected in series between the common mode voltage VCM and the output of the third double-ended input single-ended output amplifier, the resistor R _a3 and the resistor contact The inverting input terminal of the third double-ended input single-ended output amplifier, the resistor R and the capacitor C ₃ are sequentially connected in series between the output end of the second double-ended input single-ended output amplifier and the ground GND, and the capacitor C ₄ And the resistor Rc4 is sequentially connected in series between the junction of the resistor Rc ₃ and the capacitor C _{3 and} the common mode voltage VCM, and the junction of the capacitor C ₄ and the resistor R _C 4 is connected to the same input terminal of the third double-ended input single-ended output amplifier ;

Further, the above device may further have the following features: the digital/analog converter is a current mode R2R structure, and the output range of the digital/analog converter is at most one-half of the power supply ground voltage.

Further, the above device may further have the following features, the digital/analog converter is a current mode R2R structure, and the output range of the digital/analog converter is not limited to one-half power supply ground voltage, and the common mode level adjustable. Further, the above device may also have the following features, the digital/analog converter is a voltage mode R2R structure, and the output range of the digital/analog converter is not limited to one-half power supply ground voltage.

Further, the above device may further have the following features, the digital/analog converter is an R2R network structure, and the output range of the digital/analog converter is as large as the power supply ground voltage.

Further, the above device may further have the following features: the comparator for comparing the high level includes three 匪OS tubes MnO, Mnl, Mn2 and two PMOS tubes Mpl, Mp2, and an inverter, PM0S tube Mpl and The gate of the PM0S tube Mp2 is connected, the source is connected to the power supply Vcc, the drain of the PM0S tube Mpl is connected to the drain of the LV1, and the source of the MN1 and the Mn2 is connected to the MNO. The drain, the drain of the NMOS transistor Mn2 is connected to the drain of the PM0S transistor Mp2, the source of the MOS transistor MnO is grounded to GND, the gate is connected to the bias voltage Vbn, and the input terminal of the inverter is connected to the drain of the PM0S transistor Mp2. The gate of the MN2 transistor Mn2 is the positive input terminal Vin+ of the comparator, the gate of the MN OS Mn1 is the inverting input terminal Vin- of the comparator, and the output terminal of the inverter is the output terminal Vo of the comparator.

Further, the above device may further have the following features: the comparator for comparing the low level includes three PM0 tubes MpO, Mp3, Mp4 and two NM0S tubes Mn3, Mn4 and an inverter, the source of the PM0S tube MpO Connected to the power supply Vcc, the gate is connected to the bias voltage Vbp, the drain is connected to the source of the PM0S transistor Mp3 and the PM0S transistor Mp4, the drain of the PM0S transistor Mp 3 is connected to the drain and gate of the OS transistor Mn3, and the MN OS Mn3 and The source of the MN4 transistor Mn4 is grounded to GND, the drain of the MN4 transistor Mn4 is connected to the drain of the PM0S transistor Mp4, the input terminal of the inverter is connected to the drain of the NMOS transistor Mn4, and the gate of the PM0S transistor Mp4 is the positive of the comparator. To the input terminal Vin+, the gate of the PM0S transistor Mp3 is the inverting input terminal Vin_ of the comparator, and the output of the inverter is the output terminal Vo of the comparator.

Further, the above apparatus may further have the following feature, the bias voltage generating circuit of the amplifier comprises a 2-stage low-dropout linear regulator.

In order to solve the above technical problem, the present invention also provides a low frequency signal detecting method, based on the above analog front end device for a low frequency signal detecting and transmitting system, comprising: Step a, through experiment, measuring the voltage amplitude of the induced voltage of the magnetic induction module and the card reader transmitting the low frequency magnetic field at different distance points, and determining the corresponding relationship between the voltage amplitude and the distance, and establishing the voltage amplitude and Correspondence table of distances;

Step b, according to the need of decoding the low-frequency signal to transmit data and control the swipe distance, combined with the signal-to-noise ratio requirement, the hysteresis decision voltage threshold is formed by the two-level threshold outputted by one or more pairs of digital-to-analog converters to determine the analog signal, The code stream information transmitted by the low-frequency magnetic field, or the single-level threshold outputted by one or more digital-to-analog converters forms a decision voltage threshold to determine the analog signal, and obtains the code stream information transmitted by the low-frequency magnetic field; The bi-level threshold of the digital-to-analog converter output forms a non-hysteresis decision voltage threshold to determine the analog signal, obtains the distance characteristic information transmitted by the low-frequency magnetic field, or forms a single-level threshold through one or more digital-to-analog converter outputs. The non-hysteresis decision voltage threshold determines the analog signal, and obtains the distance characteristic information transmitted by the low frequency magnetic field;

Step c, sampling the signal after the non-hysteresis decision condition, obtaining a 0, 1 code stream sequence, setting a signal proportional threshold, and counting the code stream sequence within a set time window length, when the 1 signal is occupied by the code When the flow sequence ratio reaches the preset proportional threshold, it is considered to enter the preset distance range, otherwise it is considered that the distance range is not entered; the signal sequence after the decision of the hysteresis decision condition is decoded, the code stream information of the low frequency magnetic field is extracted, and the low frequency magnetic field signal is completed. One-way communication.

Further, the above method may further have the following features. In the step b, according to the correspondence table of the voltage amplitude and the distance in the step a, combined with the decoding distance, the distance control requirement, and the proportional threshold of the set 1 signal, the digital mode is set. The level at which the converter outputs to the comparator.

Further, the above method may further have the following feature: the level of the pair of digital-to-analog converters outputted to the comparator is a non-hysteresis decision condition, and the setting method is: setting the distance of the desired control to D1, finding the voltage amplitude and The correspondence table of the distance obtains the signal variation range corresponding to the distance D1 from +A1 to -A1, and the proportional threshold of the set 1 signal is R1. According to A1 and R1, the levels L1 and L2 output to the comparator are set to satisfy one cycle. Inside, when the amplitude of the output signal of the analog front-end device is greater than L1 or less than L2 The percentage between them is equal to R1, that is, if it is greater than R1, it enters the range of the required distance D1, otherwise it does not enter the range of the required control distance D1.

Further, the above method may further have the following feature: the level of the pair of digital-to-analog converters outputted to the comparator is a hysteresis decision condition, and the setting method is: setting the distance to be decoded to be D2, finding the voltage amplitude and The correspondence table of the distance obtains the change range of the signal corresponding to the distance D2 from +A2 to -A2, and the amplitude of most noise is measured as A3, and the level L 3, L4 output to the comparator is set such that L 3 is greater than +A3 And less than +A2; L4 is less than -A3 and greater than -A2, that is, decoding is allowed when the distance is less than D2, otherwise decoding is not allowed.

Further, the above method may further have the following feature. In the step b, the two comparator output signals input to the non-hysteresis decision condition comparison level are logically ORed to obtain a digital signal for extracting the distance information.

Further, the above method may further have the following feature. In the step b, the two comparator outputs whose input is the hysteresis decision condition comparison level are subjected to hysteresis processing to obtain a digital signal for extracting the magnetic field code stream information.

Further, the above method may further have the following feature. In the step c, the digital glitch filter is set to perform burr filtering on the input digital signal, and the low frequency magnetic field data stream is decoded from the signal for filtering the glitch.

Further, the above method may further have the following feature. In the step b, a single digital-to-analog converter is used to output a single comparison level to extract magnetic field distance information and code stream information.

Further, the above method may further have the following feature: using a single comparator output comparison level to extract the magnetic field code stream information, and the level of the digital-to-analog converter output to the comparator is set to the amplifier input reference level.

Further, the above method may also have the following features: decoding using a single comparator or a digital signal output by a pair of comparators.

Further, the above method may also have the following features, using a single comparator or a pair of comparators to lose The digital signal is judged by a single distance; the digital signals output by the plurality of single comparators are used to determine a plurality of distances, or the plurality of pairs of comparators are used to determine a plurality of distances and a plurality of distance intervals; The digital signal output by the single comparator performs a plurality of distance determinations, or uses a plurality of paired comparators to determine a plurality of distances and a plurality of distance intervals.

Further, the above method may further have the following feature: the plurality of single comparators and the digital signals output by the paired comparators are mixed to determine the plurality of distances and the plurality of distance intervals.

The invention can reduce the interference of the circuit noise and the environmental noise on the low frequency signal received and the low frequency signal received in the transmission system, thereby improving the accuracy of the low frequency alternating magnetic field distance detection and control. DRAWINGS

1 is a structural diagram of an analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention;

2 is another structural diagram of an analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention;

3 is still another structural diagram of an analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention;

4 is a structural diagram of a programmable gain amplifier according to an embodiment of the present invention;

FIG. 5 is a structural diagram of another programmable gain amplifier according to an embodiment of the present invention; FIG.

6 is a structural diagram of still another programmable gain amplifier according to an embodiment of the present invention;

Figure 7 is a structural diagram of a digital/analog converter in an embodiment of the present invention;

Figure 7. 2 is a structural diagram of another digital/analog converter in the embodiment of the present invention;

Figure 7.3 is a structural diagram of still another digital/analog converter in the embodiment of the present invention;

Figure 7.4 is a structural diagram of another digital/analog converter according to an embodiment of the present invention;

FIG. 8 is a structural diagram of a comparator according to an embodiment of the present invention; FIG.

FIG. 9 is a structural diagram of another comparator according to an embodiment of the present invention; FIG. 10 is a structural diagram of a bias voltage generating circuit of a programmable gain amplifier according to an embodiment of the present invention;

Figure 11.1 is a structural diagram of a first magnetic induction module according to an embodiment of the present invention;

Figure 11.2 is a structural diagram of a second magnetic induction module according to an embodiment of the present invention;

Figure 11.3 is a structural diagram of a third magnetic induction module in the embodiment of the present invention;

Figure 11.4 is a structural diagram of a fourth magnetic induction module according to an embodiment of the present invention;

Figure 11.5 is a structural diagram of a fifth magnetic induction module according to an embodiment of the present invention;

Figure 11.6 is a structural diagram of a sixth magnetic induction module according to an embodiment of the present invention;

Figure 11.7 is a structural diagram of a seventh magnetic induction module according to an embodiment of the present invention;

12 is a flowchart of a method for detecting a low frequency signal according to an embodiment of the present invention;

FIG. 13 is a schematic diagram showing the correspondence between the distance and the amplitude value of the low frequency sensing signal by the magnetic induction module being placed into different mobile communication terminals according to an embodiment of the present invention;

14 is a schematic diagram of decoding processing using a pair of comparators using a magnetic field data low frequency signal detection method according to an embodiment of the present invention;

15 is a schematic diagram of a distance control process using a pair of comparators using a low frequency signal detection method according to an embodiment of the present invention;

16 is a schematic diagram of decoding processing using a single comparator using a magnetic field data low frequency signal detecting method according to an embodiment of the present invention;

Figure 17 is a schematic diagram of a distance control process using a single comparator using a low frequency signal detection method in accordance with an embodiment of the present invention. Detailed ways

The main idea of the present invention is to add an analog front end device to the low frequency signal detection and transmission system to reduce the interference of circuit noise and environmental noise on low frequency signals, thereby improving the accuracy of low frequency alternating magnetic field distance detection and control. The principles and features of the present invention are described below in conjunction with the accompanying drawings and embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing an analog front end apparatus for a low frequency signal detecting and transmitting system according to an embodiment of the present invention. As shown in FIG. 1, the analog front end device of the low frequency signal detection and transmission system of the present invention comprises a magnetic induction module 100, a low pass filter module 104, an amplifier 101, a digital/analog converter 102 and a comparator 103, a magnetic induction module 100, The low pass filter module 104, the amplifier 01 is connected in sequence, the output of the amplifier 101 is connected to the forward input of the comparator 103, and the output of the digital/analog converter 102 is connected to the inverting input of the comparator 103. In the present invention, the amplifier 101 is a double-ended input single-ended output amplifier. The amplifier 101 pre-amplifies the input weak signal, and the digital/analog converter 102 converts the digital signal output by the digital controller into an analog signal, and then compares the two signals by the comparator 103 to obtain a desired digital signal, which is transmitted to Processing in the digital controller. The digital controller mentioned here belongs to the low frequency detection and transmission system, but it is not an analog front end. Its function is to control the comparator and digital/analog converter on/off mode according to the comparator output.

2 is another structural diagram of an analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention. As shown in FIG. 2, in this embodiment, the analog front end device of the low frequency signal detection and transmission system includes a magnetic induction module 100, a low pass filtering module 104, and an amplifier.

The digital/analog converter 102, the digital/analog converter 105 and the comparator 103, the comparator 106, the magnetic induction module 100, the low-pass filter module 104, and the amplifier 101 are sequentially connected, and the output of the amplifier 101 and the comparator 103 are respectively connected. , the forward input of the comparator 106 is connected, the digital / analog converter

102. The digital/analog converter 105 is combined with the comparator 103 and the comparator 106. The output of the digital/analog converter in each path is connected to the inverting input of the comparator, and each pair of the upper and lower channels form a pair. A total of one pair.

FIG. 3 is still another structural diagram of an analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention. As shown in FIG. 3, in this embodiment, the simulation of the low frequency signal detection and transmission system The front end device includes a magnetic induction module 100, a low pass filtering module 104, an amplifier 201, six digital/analog converters 202, 203, 204 and six comparators 205, 206, 207, and the outputs of the amplifier 201 are respectively The forward inputs of the six comparators 205, 206, 207 are connected, and the six digital/analog converters 202, 203, 204 and the six comparisons 205, 206, 207 form six paths, each of which is a digital/analog converter. The output end is connected to the opposite input end of the comparator, and each pair of upper and lower channels form a pair, a total of three pairs.

In the present invention, the amplifier may be a single-stage amplifier or a multi-stage cascade amplifier connected to a resistor negative feedback network. Here, we give examples of several cascaded amplifiers.

4 is a structural diagram of a programmable gain amplifier in accordance with an embodiment of the present invention. 4, the embodiment of the present invention, the amplifier is a four cascaded amplifiers, the composition of the cascode amplifier is four: a first stage comprising a first double-ended input single-ended output amplifier 301, a resistor and the resistor R _al R _bl ; one end of the resistor 1 ₃₁ is connected to the signal input port IN, and the other end is connected to the inverting input terminal of the first double-ended input single-ended output amplifier 301, and the resistor R _{bl is} connected to the opposite of the first double-ended input single-ended output amplifier 301 Between the input terminal and the output terminal, the common input voltage of the first double-ended input single-ended output amplifier 301 is connected to the common mode voltage VCM; the second stage includes a second double-ended input single-ended output amplifier 302, a resistor R _a2 , and a resistor R _b2 , resistor R _cl , and resistor R. ₂ , capacitor and capacitor C ₂ ; resistor R _a2 and resistor R _b2 are connected in series between the common mode voltage VCM and the output of the second double-ended input single-ended output amplifier 302, the junction of the resistor R _a2 and the resistor R _b2 The inverting input of the second double-ended input single-ended output amplifier 302, the resistor and the capacitor are sequentially connected in series between the output of the first double-ended input single-ended output amplifier 301 and the ground GND, and the capacitor C ₂ and the resistor Rc _{2 are} compliant. The second series is connected between the junction of the resistor R _el and the capacitor d and the common mode voltage VCM, and the junction of the capacitor C ₂ and the resistor R _e2 is connected to the same input terminal of the second double-ended input single-ended output amplifier 302; the third stage includes the third Double-ended input single-ended output amplifier 303, resistor R _a3 , resistor R _b3 , and resistor R. _3. Resistor capacitor C ₃ and capacitor C ₄ ; resistor R _a3 and resistor 1 _3⁄43 are sequentially connected in series between the common mode voltage VCM and the output of the third double-ended input single-ended output amplifier 303, resistor R _a3 and resistor R _b3 The contact is connected to the inverting input of the third double-ended input single-ended output amplifier 303, resistor R. ₃ and capacitor C ₃ are connected in series in the second Between the output of the double-ended input single-ended output amplifier 302 and the ground GND, the capacitor C ₄ and the resistor R _c4 are sequentially connected in series between the junction of the resistor Rc ₃ and the capacitor C _{3 and} the common mode voltage VCM, the capacitor C ₄ and the resistor R The junction of _c4 is connected to the non-inverting input terminal of the third double-ended input single-ended output amplifier 303; the fourth stage includes a fourth amplifier 304, a capacitor C ₅ and a resistor R. ₅ ; Capacitor C ₅ and resistor ₅ are sequentially connected in series between the output of the third double-ended input single-ended output amplifier 303 and the common mode voltage VCM, and the contacts of the capacitor C ₅ and the resistor R _c5 are connected to the same direction of the fourth amplifier 304 At the input end, the inverting input of the fourth amplifier 304 is connected to the output.

The amplifier shown in Figure 4 is a programmable gain amplifier with low-pass and high-pass filtering. It is divided into four levels. The circuit in each block is one level, IN is the signal input port, and VCM is common. Mode voltage input port, Vout signal output port. The operational amplifier 301 (ie, the first double-ended input single-ended output amplifier) is connected to a resistive negative feedback structure, the closed-loop gain is determined by the ratio of 1 _3⁄41 and 1 ₃₁ , and the ratio of R _bl and R _al is adjustable. d , C ₂ , Rc ₂ constitute a first-order low-pass and high-pass filter; C ₂ has a blocking function, and the offset voltage of the first-stage circuit is blocked from being transmitted to the second stage; the operational amplifier 302 (ie, the second double-ended input list) output amplifier) connected to a negative feedback resistor structure, which closed-loop gain determined by the ratio of R _b2 and R _a2, R _a2 and R _b2 ratio adjustable. R. ₃ , C ₃ , C ₄ , R _e4 constitute a first-order pass and high-pass filter; C ₄ has a blocking function, and the offset voltage of the circuit blocking the second stage is transmitted to the third stage; the operational amplifier 303 (ie, the third double-ended input single-ended output amplifier) connected to a negative feedback resistor structure, which closed-loop gain determined by the ratio of R _a3 and R _b3, R _a3 and R _b3 ratio adjustable. C ₅ and ₅ constitute a first-order high-pass filter; at the same time, the offset voltage of the previous circuit is blocked to the last stage; the operational amplifier 304 (ie, the fourth amplifier) is connected to a buffer structure of unity gain. The offset voltage of the entire PGA is only the offset voltage of the operational amplifier 304 connected to the unity gain buffer structure. The low frequency cutoff frequency of this programmable gain amplifier is! ^ and ^, R. ₃ and C ₃ jointly determine that the high frequency cutoff frequency is jointly determined by C ₂ and R < ₂ , C ₄ and ₄ , C ₅ and R _C5 .

In this embodiment, if the two-stage amplification can meet the requirements, the third stage can be removed to form a three-level structure. To ensure that the frequency response constitutes a low-pass, 1^ and _ei , R _e3 and C ₃ can be reserved or partially retained to form a Qualcomm. (^ and !^, ( ₄ and ₄ , ( ₅ and ₅ can be reserved or partially reserved. If the first-stage amplification can meet the requirements, the second and third levels can be removed, forming a two-level structure, to ensure that the frequency response constitutes a low pass. 1^ and

Re ₃ and C ₃ may be retained or partially retained, and C ₂ and R _C2 , C ₄ and R _C4 , C ₅ and R _C5 constituting the high pass may be retained or partially retained.

FIG. 5 is a structural diagram of another programmable gain amplifier according to an embodiment of the present invention. 5, the embodiment of the present invention, the amplifier is a four cascaded amplifiers, the composition of the cascode amplifier is four: a first stage comprising a first double-ended input single-ended output amplifier 301, a resistor R _al, resistance R _bl and capacitor d; a resistor 1 is connected between the signal input terminal IN and the inverting input terminal of the first double-ended input single-ended output amplifier 301, and the resistor R _bl and the capacitor are connected in parallel to the first double-ended input single-ended output amplifier Between the inverting input terminal and the output terminal of the 301, the non-inverting input terminal of the first double-ended input single-ended output amplifier 301 is connected to the common mode voltage VCM; the second stage includes a second double-ended input single-ended output amplifier 302, and a resistor R _A2 , resistor R _b2 , resistor Re ₂ , capacitor C ₂ and capacitor C ₃ ; resistor R _{a2 is} connected between the common mode voltage VCM and the inverting input of the second double-ended input single-ended output amplifier 302, the resistor R _b2 and The capacitor C _{3 is} connected in parallel between the inverting input terminal and the output terminal of the second double-ended input single-ended output amplifier 302, and the capacitor C ₂ and the resistor R _c2 are sequentially connected in series at the output end of the first double-ended input single-ended output amplifier 301. Between the common mode voltage VCM, the capacitor C ₂ and the resistor R. The contact of ₂ is connected to the non-inverting input of the second double-ended input single-ended output amplifier 302; the third stage includes a third double-ended input single-ended output amplifier 303, a resistor R _a3 , a resistor R _b3 , a resistor R _c4 and a capacitor C ₄ The resistor R _a3 and the resistor R _b32 are sequentially connected in series between the common mode voltage VCM and the output of the third double-ended input single-ended output amplifier 303, and the contact of the resistor R _a3 and the resistor R _b32 is connected to the third double-ended input single-ended terminal inverting input of the output amplifier 303, a capacitor C ₄ and a resistor R. _{4 is} connected in series between the output of the second double-ended input single-ended output amplifier 302 and the common mode voltage VCM, and the contact of the capacitor C ₄ and the resistor I ^ is connected to the same input of the third double-ended input single-ended output amplifier 303 The fourth stage includes a fourth amplifier 304, a resistor Rc ₅ and a capacitor C ₅ ; the capacitor C ₅ and the resistor ₅ are sequentially connected in series between the output of the third double-ended input single-ended output amplifier 303 and the common mode voltage VCM, The junction of the capacitor C ₅ and the resistor R _c5 is connected to the non-inverting input terminal of the fourth amplifier 304, and the inverting input terminal and the output terminal phase of the fourth amplifier 304 Even.

The amplifier shown in Figure 5 is also a programmable gain amplifier, the only difference from the structure in Figure 4 is the low-pass cutoff frequency! ^ and ^, R _b2 and C _{2 are} jointly determined.

FIG. 6 is a structural diagram of still another programmable gain amplifier according to an embodiment of the present invention. 6, the embodiment of the present invention, the amplifier is a four cascaded amplifiers, the composition of the cascode amplifier is four: a first stage comprising a first amplifier 301, a resistor R _al, resistors R _bl, R _all resistance and a resistor R _bll; resistor and the resistor R _al ₁ ¾1 sequentially connected in series between the positive output terminal of the first signal input terminal INP and the amplifier 301, the resistor R _al resistors R _bl and contacts the first reverse amplifier 301 is connected The input terminal, the resistor R _all and the resistor R _b11 are sequentially connected in series between the reverse signal input terminal I and the ground GND, and the contacts of the resistor R _all and the resistor R _b11 are connected to the same input terminal of the first amplifier 301; The second double-ended input single-ended output amplifier 302, the resistor R _a2 , the resistor R _b2 , the resistor R _el , and the resistor R are included. ₂ , the capacitor and the capacitor C ₂ ; the resistor R _a2 and the resistor R _b2 are sequentially connected in series between the common mode voltage VCM and the output end of the second double-ended input single-ended output amplifier 302, and the contacts of the resistor R _a2 and the resistor R _b2 are connected The second double-ended input is connected to the inverting input terminal of the single-ended output amplifier 302. The resistor R _cl and the capacitor are sequentially connected in series between the output terminal of the first amplifier 301 and the ground GND. The capacitor C ₂ and the resistor Rc ₂ are sequentially connected in series in the resistor. R _el , the junction of the capacitor and the common mode voltage VCM, the capacitor C ₂ and the resistor R. The contact of ₂ is connected to the non-inverting input terminal of the second double-ended input single-ended output amplifier 302; the third stage includes a third double-ended input single-ended output amplifier 303, a resistor R _a3 , a resistor R _b3 , and a resistor R. ₃ , the resistance R. ₄ , capacitor C ₃ and capacitor C ₄ ; resistor R _a3 and resistor 1 _3⁄43 are sequentially connected in series between the common mode voltage VCM and the output of the third double-ended input single-ended output amplifier 303, the resistor R _a3 and the resistor contact are connected The inverting input of the three-terminal input single-ended output amplifier 303, the resistor Rc ₃ and the capacitor C ₃ are sequentially connected in series between the output of the second double-ended input single-ended output amplifier 302 and the ground GND, the capacitor C ₄ and the resistor R. _{4 is} connected in series to the resistor R. ₃ , the junction of the capacitor C _{3 and} the common mode voltage VCM, the junction of the capacitor C ₄ and the resistor R _e4 is connected to the same input terminal of the third double-ended input single-ended output amplifier 303; the fourth stage includes the fourth amplifier 304, the resistor Rc ₅ and capacitor C ₅ ; capacitor C ₅ and resistor ₅ are connected in series between the output of the third double-ended input single-ended output amplifier 303 and the common mode voltage VCM, capacitor C ₅ and electricity The junction of the resistor R _e5 is connected to the non-inverting input terminal of the fourth amplifier 304, and the inverting input terminal of the fourth amplifier 304 is connected to the output terminal.

The amplifier shown in Figure 6 is also a programmable gain amplifier, the only difference from the structure of Figure 4 is the need to input a differential signal. Where Rall = Ral and Rbll = Rbl, the gain of the first stage is the ratio of R _bl and R _al , and the gain is adjustable.

Here, we give several examples of digital/analog converters.

Figure 7.1 is a structural diagram of a digital/analog converter in an embodiment of the present invention. As shown in Figure 7.1, in this embodiment, the digital/analog converter uses a current mode R2R DAC to convert digital to analog, and the output range is up to one-half of the power supply ground voltage. In accordance with the reference level requirements of the present invention, a corresponding high and low potential reference level can be generated using a corresponding connection.

Figure 7.2 is a structural diagram of another digital/analog converter in the embodiment of the present invention. As shown in Figure 7.2, in this embodiment, the digital/analog converter uses the current mode R2R DAC to achieve digital to analog conversion. The difference from the DAC shown in Figure 7.1 is that the output range is not limited to two-division. A power supply ground voltage, and the common mode level is adjustable, as determined by the Vcom voltage value. The use of such a DAC in accordance with the present invention can reduce the design complexity of the reference level generating circuit.

Figure 7.3 is a structural diagram of still another digital/analog converter in the embodiment of the present invention. As shown in Figure 7.3, in this embodiment, the digital/analog converter uses a voltage mode R2R DAC to achieve digital to analog conversion, and its output range is not limited to one-half of the power supply ground voltage. The use of such a DAC in accordance with the present invention can reduce the design complexity of the reference level generating circuit.

Figure 7.4 is a structural diagram of still another digital/analog converter in the embodiment of the present invention. As shown in Figure 7. 4, in this embodiment, the digital/analog converter uses the R2R network to implement digital-to-analog conversion. The output range is 2 times Vref, and the maximum can be the power supply ground voltage. According to the present invention, since such an electric circuit is reduced, the design complexity and power consumption of the reference level generating circuit can be reduced by reducing one amplifier.

Here, we also give examples of several comparators.

FIG. 8 is a structural diagram of a comparator according to an embodiment of the present invention. As shown in FIG. 8, in this embodiment, The comparator comprises three MNOS tubes MnO, Mnl, Mn2 and two PM0S tubes Mp Mp2, and an inverter, the PM0S tube Mpl is connected to the gate of the PM0S tube Mp2, and the source is connected to the power supply Vcc, the PM0S tube Mpl The drain of the drain MOS transistor Mn1, the source of the NMOS transistor Mn 1 and the NMOS transistor Mn2 are connected to the drain of the MOS transistor of the OS transistor MnO, and the drain of the MOS transistor Mn2 is connected to the drain of the PM0 transistor Mp2. The source of the OS tube MnO is grounded to GND, the gate is connected to the bias voltage Vbn, the input of the inverter is connected to the drain of the PM0S transistor Mp2, and the gate of the MOS transistor Mn2 is the forward input of the comparator V in+, 匪OS The gate of the tube Mn1 is the inverting input Vin- of the comparator, and the output of the inverter is the output Vo of the comparator. The comparator shown in Figure 8 is used for the comparison of the high levels in the three pairs of comparators in Figure 2, namely the comparison of VG1 + , VG2+ and VM+. Since the Li OS is used as an input tube, it is possible to implement a high level comparison function.

FIG. 9 is a structural diagram of another comparator in the embodiment of the present invention. As shown in FIG. 9, in this embodiment, the comparator includes three PMOS transistors MpO, Mp3, Mp4 and two NMOS transistors Mn3, Mn4 and an inverter. The source of the PM0S transistor MpO is connected to the power supply Vcc, and the gate. Connected to the bias voltage Vbp, the drain is connected to the source of the PM0S transistor Mp3 and the PM0S transistor Mp4, the drain of the PM0S transistor Mp3 is connected to the drain and the gate of the NM0S transistor Mn3, and the source of the MOS transistor Mn3 and the MOS transistor Mn4 is grounded. GND, the drain of the MN4 transistor Mn4 is connected to the drain of the PM0S transistor Mp4, the input of the inverter is connected to the drain of the MN4 transistor Mn4, and the gate of the PM0S transistor Mp4 is the positive input terminal of the comparator Vin+, the PM0S transistor Mp3 The gate of the comparator is the inverting input Vin- of the comparator, and the output of the inverter is the output of the comparator Vo. The comparator shown in Figure 9 is used for the comparison of low levels in the three pairs of comparators in Figure 2, namely VG1_, VG2 - and VM -. Since PM0S is used as an input tube, it is possible to implement a low level comparison function.

Figure 10 is a block diagram showing a bias voltage generating circuit of a programmable gain amplifier in accordance with an embodiment of the present invention. As shown in FIG. 10, the power supply voltage VIN is generated by a 2-stage LD0 (Low Dropout regula tor) 901 and 902 to generate a bias voltage VCM of the programmable gain amplifier (that is, the aforementioned common mode voltage). Greatly improve the power supply rejection ratio of the bias voltage of the programmable gain amplifier.

FIG. 1 is a structural diagram of a first magnetic induction module according to an embodiment of the present invention. Figure 11.1, magnetic The sensing module is a magnetic induction coil. The two output terminals of the magnetic induction coil can be directly connected to the two input terminals of the low-pass filter module.

Figure 11.2 is a structural diagram of a second magnetic induction module in the embodiment of the present invention. In Figure 11.2, the magnetic sensing module is a Hall device, and the two outputs of the Hall device are connected to the two input terminals of the low-pass filter module through a DC blocking capacitor.

Figure 11.3 is a structural diagram of a third magnetic induction module in the embodiment of the present invention. In Figure 11.3, the magnetic sensing module is a Hall device. One output of the Hall device is connected to one input of the low-pass filter module through a DC blocking capacitor, and the other output of the Hall device is directly connected to the low-pass filter module. One input is connected.

Figure 11.4 is a structural diagram of a fourth magnetic induction module in the embodiment of the present invention. In Figure 11.4, the magnetic sensing module is a Hall device, and the two outputs of the Hall device are directly connected to the two inputs of the low-pass filter module.

Figure 11.5 is a structural diagram of a fifth magnetic induction module in the embodiment of the present invention. In Figure 11.5, the magnetic induction module is a giant magnetoresistive device. The two output terminals of the giant magnetoresistive device are connected to the two input terminals of the low-pass filter module through a DC blocking capacitor.

Figure 11.6 is a structural diagram of a sixth magnetic induction module in the embodiment of the present invention. In Fig. 11.6, the magnetic induction module is a giant magnetoresistive device, and an output end of the giant magnetoresistive device is connected to one input end of the low-pass filter module through a DC blocking capacitor, and the other output terminal of the giant magnetoresistive device directly The other input of the low pass filter module is connected.

Figure 11.7 is a structural diagram of a seventh magnetic induction module in the embodiment of the present invention. In Figure 11.7, the magnetic induction module is a giant magnetoresistive device. The two output terminals of the giant magnetoresistive device are directly connected to the two input terminals of the low-pass filter module.

The analog front-end device for low-frequency signal detection and transmission system provided by the invention can reduce the interference of circuit noise and environmental noise on the low-frequency signal detected and transmitted in the low-frequency signal, thereby improving the low-frequency alternating magnetic field distance detection. And the precision of the control. Based on the aforementioned analog front end device for low frequency signal detection and transmission system, the present invention also proposes a low frequency signal detection method. 12 is a flowchart of a low frequency signal detecting method according to an embodiment of the present invention. As shown in FIG. 12, in the embodiment, the low frequency signal detecting method includes the following steps: Step 1201: measuring an amplitude value of the induced voltage after being amplified at different distances;

Through experimental means, the amplitude values of the induced voltage of the magnetic induction module and the magnetic field-transmitting card reader at different distances are amplified by the amplifier on different mobile phone terminals, and corresponding records are made. FIG. 1 is a schematic diagram showing the correspondence between the distance and the amplitude of the low frequency sensing signal by the magnetic induction module being placed into different mobile communication terminals according to an embodiment of the present invention.

Step 1202: Establish a correspondence table between the voltage amplitude and the distance;

The measurement data of multiple terminals is processed to obtain a correspondence table of voltage amplitude and distance, as shown in Table 1.

Correspondence table between amplitude value and distance of low frequency induced signal

Distance between mobile communication terminal and card reader (cm) Induced signal amplitude (dBmV)

1 cm 52

2cm 47

3cm 40

4cm 36

5 cm 30

6cm 26

7cm 21 8cm 17

9cm 11

10cm 8

14cm 5 Step 1203, enter the low frequency magnetic field data decoding process;

Step 1205, setting a digital-to-analog converter output level;

If the distance to be decoded is D2, look up the correspondence table between the amplitude value and the distance, and obtain the variation range of the signal corresponding to D2 from +A2 to -A2. The amplitude of most noise is measured as A3, and the power output to the comparator is set. Flat L3, L4, such that L3 should be greater than +A3, and less than +A2; L4 is less than -A3, and greater than -A2, that is, when the distance is less than D2, decoding is allowed, otherwise decoding is not allowed.

Step 1207, the comparator output signal is delayed;

Step 1209, decoding the processed signal;

The decoder decodes the logically processed signal according to the encoding format to obtain low frequency magnetic field data stream information. The decoder sets the digital glitch filter to perform glitch filtering on the input digital signal.

Step 1211, completing one-way communication of the low frequency magnetic field signal;

The decoded data is correlated and applied to complete the one-way communication function of the low frequency magnetic field signal. Step 1204, entering a distance control process;

Step 1206, setting a digital-to-analog converter output level;

If the distance to be controlled is D1, find the correspondence table between the amplitude value and the distance, and the signal change amplitude corresponding to D1 is +A1 to -A1, and the proportional threshold of the set 1 signal is R1. According to A1 and R1, the output is set to the comparator. The levels L1, L2 satisfy the period in which the output signal amplitude of the front-end device is greater than L1 or the percentage of time less than L2 is equal to R1, that is, if it is greater than R1, it enters the distance D1 of the required control, otherwise it does not enter the range. It is required to control the distance D1.

Step 1208, the comparator output signal logic or processing; When a paired comparator is used to obtain a digital signal for judging the distance between the card reader and the card, the pair of digital signals are operated as follows: Comparing the output signal of the input high comparison level comparator with the low After the output signal of the level comparator is inverted, the signal is ORed to obtain a digital signal for distance determination.

Step 1210, sampling the logically processed signal to obtain a 0, 1 data stream;

Step 1212: Perform statistics on 0 and 1 data by using a preset time window.

The length of the time window is preset, and the 0 and 1 data in the time window are counted, and the ratio of 1 is calculated.

In step 1214 and step 1216, the statistical result is compared with the set signal threshold of the set 1 to complete the distance judgment and realize the distance control.

Figure 14 is a schematic diagram showing the decoding process using a pair of comparators using a magnetic field data low frequency signal detection method in an embodiment of the present invention. As shown in Figure 14, AO is the output signal of the amplifier. Input Comparator High Comparison Level VG+, Low Comparison Level VG-Set according to the decoding distance and by looking up the correspondence table of amplitude value and distance. D02 is the output signal of the comparator that inputs the high compare level, and D03 is the inverted signal of the output of the comparator that inputs the low compare level. After the hysteresis processing, the digital signal is a hysteretic logic processed signal of the output signals D02 and DO3 of the comparator. A digital glitch filter can be set to glitch the input signal. The low-frequency magnetic field data stream information can be obtained by decoding the hysteresis-processed signal according to the encoding format.

FIG. 15 is a schematic diagram of a distance control process using a pair of comparators using a low frequency signal detection method according to an embodiment of the present invention. As shown in Figure 14, AO is the output signal of the amplifier. The amplitude varies from -A1 to +A1, and the corresponding distance is assumed to require the distance L to be controlled. First, the correspondence table of the amplitude value and the distance is searched for, and the signal amplitude value at the distance is obtained. Set the proportional threshold of the 1 signal to R1. According to R1, the setting of the high comparison level VG+ and the low comparison level VG- satisfies that the percentage of time that the front-end device output signal amplitude is greater than VG+ or less than VG- is equal to R1 in one cycle. Performing or processing the output signals D02, D03 of the paired comparators to obtain a signal D04, The signal is sampled to obtain a sampled 0, 1 data stream. In the figure, the dotted line box on the 0 and 1 data streams represents the preset time window. The length of the time window is set to be equal to one signal period. The 0 and 1 signals in the time window are counted, and the ratio of the 1 signal is obtained. The proportional threshold of the signal is compared. If it is greater than the proportional threshold, the sensing module is considered to be within the distance L; otherwise, the distance is not considered to be entered.

Figure 16 is a diagram showing the decoding process using a single comparator using a magnetic field data low frequency signal detection method in accordance with an embodiment of the present invention. As shown in Figure 15, AO is the output signal of the amplifier. The comparison level of the input comparator VG is set to the amplifier input reference level. The output signal of the comparator is used directly as the decoded signal. A digital glitch filter can be set to glitch the input signal. The signal is decoded according to the encoding format to obtain low frequency magnetic field data stream information.

Figure 17 is a schematic diagram of a distance control process using a single comparator using a low frequency signal detection method in accordance with an embodiment of the present invention. As shown in Figure 16, AO is the output signal of the amplifier. The amplitude varies from -A1 to +A1, and the corresponding distance is assumed to require the distance L to be controlled. First, the correspondence table between the amplitude value and the distance is searched to obtain the signal amplitude value at the distance. Set the proportional threshold of the 1 signal to R1. According to R1, the setting of the comparison level VG satisfies that in a period, the percentage of time that the front-end device output signal amplitude is greater than VG is equal to R1. The output signal of the comparator is sampled to obtain the sampled 0, 1 data stream. In the figure, the dotted line box on the 0 and 1 data streams represents the preset time window. The length of the time window is set equal to one signal period. The 0 and 1 signals in the time window are counted, and the ratio of the 1 signal is obtained. The proportional threshold of the signal is compared. If it is greater than the proportional threshold, the sensing module is considered to be within the distance L; otherwise, the distance is not considered to be entered.

The six comparators in Fig. 3 can be configured to be used in three pairs, and simultaneously perform decoding, determination of multiple distances, distance intervals, and control. It can also be used independently as six separate comparators, and performs decoding, multiple distances, and distance interval judgment and control. Some of the comparators may also be used in pairs to perform decoding or distance, distance interval judgment and control; some of the comparators are used independently for decoding, distance, distance interval judgment and control. In fact, the front-end device can configure one or more comparators as needed for distance determination and control of multiple distances, multiple distance intervals, and low-frequency magnetic field signal decoding.

The low frequency signal detecting method provided by the invention can reduce the interference of the circuit noise and the environmental noise on the low frequency signal detected and the low frequency signal received in the transmission system, thereby improving the accuracy of the low frequency alternating magnetic field distance detection and control.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.

Claims

Claim

An analog front end device for a low frequency signal detection and transmission system for use in a short range communication system, comprising at least one magnetic induction module, at least one low pass filtering module, at least one amplifier, at least one digital/analog a converter and at least one comparator, wherein the magnetic induction module, the low pass filter module, and the amplifier are sequentially connected, an output of the amplifier is connected to a forward input end of the comparator, and an output of the digital/analog converter The terminal is coupled to the inverting input of the comparator, which is a dual-ended input single-ended output amplifier.

2. The analog front end device for low frequency signal detection and transmission system according to claim 1, comprising a magnetic induction module, a low pass filtering module, an amplifier, two digital/analog converters and two a comparator, the magnetic induction module, the low-pass filter module, and the amplifier are sequentially connected, and the output ends of the amplifiers are respectively connected to the forward inputs of the two comparators, and the two digital/analog converters and the The two comparators form two channels, and the output of the digital/analog converter in each path is connected to the inverting input of the comparator, and each pair of upper and lower channels is formed into a pair.

3. The analog front end device for low frequency signal detection and transmission system according to claim 1, comprising a magnetic induction module, a low pass filtering module, an amplifier, six digital/analog converters and six a comparator, an output of the amplifier is respectively connected to a forward input of the six comparators, and the six digital/analog converters and the six comparators form a six-way, digital/analog conversion in each path The output of the device is connected to the inverting input of the comparator, and each pair of the upper and lower channels form a pair, a total of three pairs.

4. The analog front end device for low frequency signal detection and transmission system according to claim 1, wherein the magnetic induction module is a magnetic induction coil, a Hall device or a giant magnetoresistive device.

The analog front end device for low frequency signal detection and transmission system according to claim 4, wherein the magnetic induction module is a magnetic induction coil, and two outputs of the magnetic induction coil The terminal is directly connected to the two inputs of the low pass filter module.

6. The analog front end device for a low frequency signal detection and transmission system according to claim 4, wherein the magnetic induction module is a Hall device, and the two output ends of the Hall device pass through a DC blocking capacitor and The two low-pass filter modules are connected to each other; or one output of the Hall device is connected to one input of the low-pass filter module through a DC blocking capacitor, and the other output of the Hall device is directly connected The other input of the low pass filter module is connected; or the two outputs of the Hall device are directly connected to the two inputs of the low pass filter module.

The analog front end device for low frequency signal detection and transmission system according to claim 4, wherein the magnetic induction module is a giant magnetoresistive device, and the two output ends of the giant magnetoresistive device are separated by straight a capacitor is connected to the two input ends of the low pass filter module; or an output end of the giant magnetoresistive device is connected to an input end of the low pass filter module through a DC blocking capacitor, and the giant magnetoresistive device The other output is directly connected to the other input of the low pass filter module; or the two outputs of the giant magnetoresistive device are directly connected to the two inputs of the low pass filter module.

8. The analog front end device for a low frequency signal detection and transmission system according to claim 1, wherein the amplifier is a single stage amplifier or a multistage cascade amplifier connected to a resistor negative feedback network.

9. The analog front end device for a low frequency signal detection and transmission system according to claim 3, wherein the amplifier is a four-stage cascade amplifier, and the four-stage cascade amplifier has the following composition:

The first stage comprises a first double-ended input single-ended output amplifier, and a resistor R _al resistors R _bl; terminating resistor R _al is a signal input port IN, the other end of the first double-reverse input terminal of the single-ended output amplifier The input end, the resistor R _{bl is} connected between the inverting input end and the output end of the first double-ended input single-ended output amplifier, and the common-mode input terminal of the first double-ended input single-ended output amplifier is connected to the common mode voltage VCM; The second stage includes a second double-ended input single-ended output amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _cl , and a resistor R. ₂ , capacitor and capacitor C ₂ ; resistor R _a2 and resistor R _b2 are connected in series between the common mode voltage VCM and the output of the second double-ended input single-ended output amplifier, the contact of the resistor R _a2 and the resistor R _b2 Connected to the inverting input terminal of the second double-ended input single-ended output amplifier, the resistor and the capacitor are sequentially connected in series between the output of the first double-ended input single-ended output amplifier and the ground GND, and the capacitor C ₂ ₂ and the resistor Rc of sequentially connected in series between the capacitor and the contact resistance R _el d of the common-mode voltage VCM, and a resistor R. the capacitor C ₂ is connected to the second contact ₂ double-ended input single-ended output amplifier with the input terminal ;

The third stage includes a third double-ended input single-ended output amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _c3 , and a resistor R. _4, the capacitor capacitance C ₃ and C _4; and R _a3 resistance resistor ₁ ¾3 sequentially connected in series between the output terminal of said common mode voltage VCM and a third double-ended input single-ended output amplifier, a resistor R _a3 and R _b3 resistance The contact is connected to the inverting input of the third double-ended input single-ended output amplifier, and the resistor R and the capacitor C ₃ are sequentially connected in series between the output of the second double-ended input single-ended output amplifier and the ground GND. Capacitor C ₄ and resistor R. _{4 is} connected in series to the resistor R. ₃ and the junction of capacitor C ₃ and common mode voltage VCM, capacitor C ₄ and resistor R. a contact of ₄ is connected to the same input end of the third double-ended input single-ended output amplifier;

10. The analog front end device for a low frequency signal detection and transmission system according to claim 3, wherein said amplifier is a four-stage cascade amplifier, and the four-stage cascade amplifier has the following composition:

The first stage comprises a first double-ended input single-ended output amplifier, a resistor R _al, capacitors and resistors R _bl D; 1 ^ a resistor connected to the signal input terminal IN and the first double-ended input single-ended output amplifier inverting input Between the terminals, a resistor R _bl and a capacitor are connected in parallel between the inverting input terminal and the output terminal of the first double-ended input single-ended output amplifier, and the first double-ended input single-ended output amplifier is connected in the same direction Total Mode voltage VCM;

11. The analog front end device for a low frequency signal detection and transmission system according to claim 3, wherein said amplifier is a four-stage cascade amplifier, and said four-stage cascade amplifier has the following composition:

The first stage comprises a first amplifier, a resistor R _al, resistors R _bl, R _all resistors and the resistor R _bll; resistor and the resistor R _al ₁ ¾1 sequentially forward signal in series at the output of the first input terminal INP and amplifier between the _Al resistor R and the resistor R connected to the contacts _BL inverting input terminal of the first amplifier, a resistor ₁₃₁₁ and a resistor R connected in series between _BLL sequentially inverted I signal input to the GND and significantly, the resistance R The contact of _all and the resistor R _b11 is connected to the same input end of the first amplifier; The second stage includes a second double-ended input single-ended output amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _cl , and a resistor R. ₂ , the capacitor and the capacitor C ₂ ; the resistor R _a2 and the resistor R _b2 are sequentially connected in series between the common mode voltage VCM and the output end of the second double-ended input single-ended output amplifier, and the contact of the resistor R _a2 and the resistor R _b2 Connected to the inverting input terminal of the second double-ended input single-ended output amplifier, the resistor ε _ε1 , the capacitor (^ is sequentially connected in series between the output end of the first amplifier and the ground GND, the capacitor C ₂ and the resistor are sequentially Connected in series between the resistor R _el , the junction of the capacitor and the common mode voltage VCM , the junction of the capacitor C ₂ and the resistor R. ₂ is connected to the same input terminal of the second double-ended input single-ended output amplifier;

The third stage includes a third double-ended input single-ended output amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _c3 , and a resistor R. ₄ , capacitor C ₃ and capacitor C ₄ ; resistor R _a3 and resistor 1 _3⁄43 are connected in series between the common mode voltage VCM and the output of the third double-ended input single-ended output amplifier, the resistor R _a3 and the resistor contact The inverting input terminal of the third double-ended input single-ended output amplifier, the resistor R and the capacitor C ₃ are sequentially connected in series between the output end of the second double-ended input single-ended output amplifier and the ground GND, and the capacitor C ₄ And the resistor R _C 4 is connected in series in the resistor R. ₃ , the junction of the capacitor C _{3 and} the common mode voltage VCM, the junction of the capacitor C ₄ and the resistor Rc4 is connected to the same input end of the third double-ended input single-ended output amplifier;

12. The analog front end device for a low frequency signal detection and transmission system according to claim 1, wherein said digital/analog converter is a current mode R2R structure, said digital/analog converter having a maximum output range It is the voltage of one-half of the power supply.

The analog front end device for low frequency signal detection and transmission system according to claim 1, wherein the digital/analog converter is a current mode R2R structure, and an output range of the digital/analog converter It is not limited to one-half of the power supply ground voltage, and the common mode level can be adjusted.

14. The analog front end mounting for a low frequency signal detection and transmission system according to claim The digital/analog converter is a voltage mode R2R structure, and an output range of the digital/analog converter is not limited to a voltage of one-half power supply.

The analog front end device for low frequency signal detection and transmission system according to claim 1, wherein the digital/analog converter is an R2R network structure, and the output range of the digital/analog converter is as large as Power ground voltage.

16. The analog front end apparatus for low frequency signal detection and transmission system according to claim 1, wherein the comparator for comparing the high level comprises three MN transistors MnO, Mnl, Mn2 and two PMOS The tubes Mpl, Mp2, and an inverter are connected to the gate of the PMOS transistor Mpl and the PMOS transistor Mp2, the source is connected to the power supply Vcc, the drain of the PMOS transistor Mpl is connected to the drain of the MOS transistor Mn1, and the LV transistor Mn 1 The source of the MN2 tube Mn2 is connected to the drain of the MOS transistor MnO, the drain of the MOS transistor Mn2 is connected to the drain of the PMOS transistor Mp2, the source of the MOS transistor MnO is grounded to GND, and the gate is connected to the bias voltage Vbn. The input end of the inverter is connected to the drain of the PMOS transistor Mp2, the gate of the MN2 transistor Mn2 is the positive input terminal Vin+ of the comparator, and the gate of the MN OS Mn1 is the reverse input terminal Vin_ of the comparator, the inverter The output is the output of the comparator Vo.

17. The analog front end device for a low frequency signal detection and transmission system according to claim 1, wherein the comparator for comparing the low level comprises three PMOS transistors MpO, Mp3, Mp4 and two MNs. Tube Mn3, Mn4 and an inverter, the source of the PMOS transistor MpO is connected to the power source Vcc, the gate is connected to the bias voltage Vbp, the drain is connected to the source of the PMOS transistor Mp 3 and the PMOS transistor Mp4, and the drain of the PMOS transistor Mp3 is connected. The drain and gate of MN OS Mn3, the source of MN OS Mn3 and MN OS Mn4 are grounded to GND, the drain of MN OS Mn4 is connected to the drain of PMOS transistor Mp4, and the input of inverter is connected to OS The drain of the transistor Mn4, the gate of the PMOS transistor Mp4 is the forward input terminal Vin+ of the comparator, the gate of the PMOS transistor Mp3 is the inverting input terminal Vin- of the comparator, and the output terminal of the inverter is the output terminal of the comparator Vo .

18. The analog front end apparatus for low frequency signal detection and transmission system according to claim 1, wherein the bias voltage generating circuit of the amplifier comprises a two-stage low dropout linear regulator.

A low-frequency signal detecting method, the analog front-end device for a low-frequency signal detecting and transmitting system according to any one of claims 1 to 18, comprising:

Step a, through experiment, measuring the voltage amplitude of the induced voltage of the magnetic induction module and the card reader transmitting the low frequency magnetic field at different distance points, and determining the corresponding relationship between the voltage amplitude and the distance, and establishing the voltage amplitude and Correspondence table of distances;

Step b, according to the requirement of decoding the low-frequency signal transmission data and controlling the swipe distance, combined with the signal-to-noise ratio requirement, the hysteresis decision voltage threshold is formed by the bi-level threshold outputted by one or more pairs of digital-to-analog converters to determine the analog signal, The code stream information transmitted by the low-frequency magnetic field, or the single-level threshold outputted by one or more digital-to-analog converters forms a decision voltage threshold to determine the analog signal, and obtains the code stream information transmitted by the low-frequency magnetic field; The bi-level threshold of the digital-to-analog converter output forms a non-hysteresis decision voltage threshold to determine the analog signal, obtains the distance characteristic information transmitted by the low-frequency magnetic field, or forms a single-level threshold through one or more digital-to-analog converter outputs. The non-hysteresis decision voltage threshold determines the analog signal, and obtains the distance characteristic information transmitted by the low frequency magnetic field;

The low-frequency signal detecting method according to claim 19, wherein in the step b, according to the correspondence table of the voltage amplitude and the distance in the step a, the decoding distance, the distance control requirement, and the setting 1 are combined. The proportional threshold of the signal sets the level at which the digital-to-analog converter outputs to the comparator.

The low-frequency signal detecting method according to claim 20, wherein the level of the pair of digital-to-analog converters outputted to the comparator is a non-hysteresis decision condition, and the setting method is: setting the distance of the desired control to D1, find the correspondence table of the voltage amplitude and the distance, and obtain the signal corresponding to the distance D1. The range of change is +A1 to -A1, and the proportional threshold of the set 1 signal is R1. According to A1 and R1, the levels L1 and L2 output to the comparator are set to satisfy the amplitude of the output signal of the analog front-end device greater than L1 or in one cycle. The percentage of time less than L2 is equal to R1, that is, if it is greater than R1, it enters the range of distance D1 required for control, otherwise it does not enter the range of required control distance D1.

The low-frequency signal detecting method according to claim 20, wherein the level of the pair of digital-to-analog converters outputted to the comparator is a hysteresis decision condition, and the setting method is: setting the distance at which decoding is desired to be D2, find the correspondence table of voltage amplitude and distance, and obtain the change range of the signal corresponding to the distance D2 from +A2 to -A2. The amplitude of most noise is measured as A3, and the level of output to the comparator is set to L3, L4. Let L3 be greater than +A3 and less than +A2; L4 is less than -A3 and greater than _A2, ie, decoding is allowed when the distance is less than D2, otherwise decoding is not allowed.

The low frequency signal detecting method according to claim 19, wherein in the step b, the two comparator output signals input to the Y hysteresis decision condition comparison level are logically ORed to obtain an extraction method. The digital signal of the distance information.

The low frequency signal detecting method according to claim 19, wherein in the step b, the two comparator outputs whose input is the hysteresis decision condition comparison level are subjected to hysteresis processing to obtain a magnetic field code stream. Digital signal of information.

The low frequency signal detecting method according to claim 19, wherein in the step c, the digital glitch filter is set to perform burr filtering on the input digital signal, and the low frequency magnetic field is decoded from the signal for filtering the glitch. data flow.

The low frequency signal detecting method according to claim 19, wherein in the step b, the magnetic field distance information and the code stream information are extracted using a single comparison level output from a single digital to analog converter.

The low frequency signal detecting method according to claim 26, wherein the comparison level is used to extract the magnetic field code stream information using a single comparator, and the level of the digital-to-analog converter output to the comparator is set to an amplifier input reference level. .

The low frequency signal detecting method according to claim 19, wherein a single ratio is used The digital signal output by the comparator or the paired comparator is decoded.

The low frequency signal detecting method according to claim 19, wherein a single distance is judged using a single comparator or a digital signal output from the pair of comparators; and the plurality of single comparator outputs are used to perform a plurality of signals Judgment of distance, or use multiple pairs of comparators to determine multiple distances and multiple distance intervals; use multiple digital comparator output digital signals to determine multiple distances, or use multiple pairs of comparators Judgment of multiple distances and multiple distance intervals.

The low-frequency signal detecting method according to claim 19, wherein the plurality of single comparators and the digital signals output from the paired comparators are mixed to determine a plurality of distances and a plurality of distance intervals.