WO2011135644A1

WO2011135644A1 - Input/output circuit, semiconductor control system, and control method for input/output circuit

Info

Publication number: WO2011135644A1
Application number: PCT/JP2010/007177
Authority: WO
Inventors: 平田貴士; 大塚英文; 橋本剛
Original assignee: パナソニック株式会社
Priority date: 2010-04-27
Filing date: 2010-12-09
Publication date: 2011-11-03
Also published as: JP2011234085A

Abstract

An output buffer (21) is equipped with transistors (TP1, TN1) that are connected between a power supply and ground and a resistive element (R1) that is connected between a node (n1) and an input/output terminal (23), and an output buffer (22) is equipped with transistors (TP2, TN2) that are connected between the power supply and the ground and a resistive element (R2) that is connected between a node (n2) and the input/output terminal (23). In signal input mode, the output buffers (21, 22) form a single termination circuit. For example, the transistors (TP1, TN2) are turned on, the transistors (TN1, TP2) are turned off, and a current path passing through the resistive elements (R1, R2) is formed.

Description

Input / output circuit, semiconductor control system, and input / output circuit control method

The present invention relates to an input / output circuit for transmitting and receiving digital signals at high speed, which is mounted on video equipment, communication equipment, and the like.

Recent video equipment such as PCs (Personal Computers), digital televisions, Blu-ray recorders, etc. have a processor that performs image processing and numerical computation processing, and a DRAM (Dynamic Random Access Memory) that buffers image data and computation data. It is used. Along with the improvement in processor performance, the amount of data transmitted to and from the DRAM has been increasing year by year, and the speed of data transmission and the increase in the number of bits are progressing.

In general, a DDR (Double Data Rate) standard defined by JEDEC (Joint Electron Device Engineering Engineering Council) is used for a DRAM interface for transmitting and receiving data between a processor and a DRAM. In this DDR standard, a push-pull off-chip driver (OCD) is used on the transmitting side as an IO circuit, and a Thevenin-type on-die termination (to suppress signal reflection on the receiving side) ODT) is used.

FIG. 7 shows an example of the configuration of a conventional input / output circuit, where 101 is an OCD circuit, 102 is an ODT circuit, and 103 is a control circuit for the OCD circuit 101. In the DDR standard, a resistance value is defined for both transmission and reception. For example, in the DDR3 standard, the resistance value of OCD is determined to be 30 to 68Ω, and the resistance value of ODT is determined to be 80 to 240Ω. For this reason, when signals are transmitted and received, currents IH and IL of around 10 mA always flow to the transmission side and the reception side. Further, regarding the resistance values of OCD and ODT, IV characteristics are also specified in detail, and therefore, a configuration in which a transistor and a resistance element are connected in series is generally used as an OCD circuit or an ODT circuit. In the configuration of FIG. 7, in the OCD circuit 101, a transistor TP01, resistance elements Rp1 and Rn1, and a transistor TN01 are connected in series between the power supply and the ground. In the ODT circuit 102, the transistor TP02, the resistance elements Rp2 and Rn2, and the transistor TN02 are connected in series between the power supply and the ground.

JP 2003-133944 A

With the recent miniaturization of LSI manufacturing processes, for example, the internal logic circuit of LSI has been considerably reduced in area. However, in the case of a drive circuit such as an OCD circuit and a termination circuit such as an ODT circuit, as described above, it is necessary to constantly pass a current of, for example, about 10 mA. Therefore, the area has not been reduced. This hinders cost reduction of LSI.

Furthermore, the amount of current that can flow per unit wiring width is reduced from the viewpoint of EM (Electro Migration) due to the progress of thinning of the wiring layer accompanying the miniaturization of the process. This is also a big problem in reducing the area of the drive circuit and the termination circuit.

An object of the present invention is to realize an input / output circuit for transmitting and receiving a digital signal at a high speed with a small circuit area while maintaining EM resistance.

In one aspect of the present invention, the input / output circuit includes a first output buffer, a second output buffer, and an input / output terminal to which the first and second output buffers are connected in common. The first output buffer includes a first transistor connected between a power source and a first node, a second transistor connected between the first node and the ground, and the first transistor. A first resistance element connected between a node and the input / output terminal, and the second output buffer includes a third transistor connected between a power supply and a second node; A fourth transistor connected between the second node and the ground, and a second resistance element connected between the second node and the input / output terminal.

Then, a signal output mode for outputting a signal via the first and second output buffers and a signal input mode for setting the first and second output buffers as termination circuits are switched. Further, in the signal input mode, the first state where the first and fourth transistors are turned on and the second and third transistors are turned off, or the second and third transistors are turned on. And controlling to set the first and fourth transistors to the second state to turn them off.

According to this aspect, in the first output buffer, the first resistance element is shared between the power supply side and the ground side. Similarly, in the second output buffer, the second resistance element is connected to the power supply side and the ground side. And shared with. Thereby, a resistive element can be reduced. In the signal output mode, a current flows through the first and second resistance elements in opposite directions when the signal “H” is output and when the signal “L” is output. For this reason, since EM degradation of a resistance element is suppressed, it becomes possible to suppress the width | variety of a resistance element small. Further, in the signal input mode, the termination circuit is configured by combining the first and second output buffers. At this time, a current path passing through the first and second resistance elements is formed from the power supply to the ground. . Therefore, an input / output circuit that functions as both a driver circuit and a termination circuit can be realized with a small circuit area while maintaining EM resistance.

In the signal input mode, it is preferable to switch between the first state and the second state at a predetermined timing.

According to this, since the direction of the current flowing through the first and second resistance elements is switched in the signal input mode, it is possible to improve the EM resistance of the resistance element and the wiring and via connected thereto. In addition, since the transistors to be activated are also switched, the average amount of current flowing through each transistor and its wiring is reduced, thereby suppressing EM deterioration of the transistor wiring. Therefore, the width of the resistance element, the width of the transistor wiring, and the like can be reduced, and the circuit area can be reduced.

According to the present invention, an input / output circuit that functions as both a driver circuit and a termination circuit can be realized with a small circuit area and low power consumption while maintaining EM resistance. As a result, it is possible to achieve both reliability and cost reduction of LSI mounted on video equipment, communication equipment, and the like.

1 is an example of a semiconductor control system in which an input / output circuit according to an embodiment is mounted. It is a figure which shows the structure of the input / output circuit which concerns on embodiment, and the operation | movement in signal output mode. It is a figure which shows the structure of the input / output circuit which concerns on embodiment, and the operation | movement in signal input mode. It is a figure which shows the structure of the input / output circuit which concerns on embodiment, and the operation | movement in signal input mode. It is an equivalent circuit diagram of the input / output circuit which concerns on embodiment, (a) is at the time of signal output, (b) is at the time of signal input. It is an example of a configuration in which an output buffer is divided and arranged in a plurality of units. It is a block diagram of the conventional input / output circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an example of a semiconductor control system in which the input / output circuit according to the embodiment is mounted. In FIG. 1, 1 is a processor that performs image processing, arithmetic processing, and the like, 2 is a DRAM (Dynamic Random Access Memory), and 3 is a PROM (Programmable Read Only Memory) that stores an OS (Operating System) and a control program. The processor 1 has a CPU 11 and performs image processing, arithmetic processing, and the like in accordance with instructions of the OS and control program stored in the PROM 3. The DRAM 2 is used as a buffer for exchanging control programs, calculation data, image data, and the like with the processor 1 at high speed. The processor 1 has a DRAM interface 12 for transmitting and receiving a large amount of data between the CPU 11 and the DRAM 2 at high speed.

The input / output circuit according to the present embodiment is provided, for example, in the DRAM interface 12 of FIG. For example, in a recent standard PC (Personal Computer), the processor 1 and the DRAM 2 are connected by 100 or more signal lines, and data transfer is performed at a speed of several hundred Mbps or more. For this purpose, the DRAM interface 12 is equipped with 100 or more input / output circuits for each signal line.

Note that the input / output circuit according to the present embodiment is also used in, for example, an LSI that performs image processing and numerical calculation, and a device that communicates digital signals at high speed.

2 to 4 are diagrams showing the configuration and operation of the input / output circuit according to this embodiment. 2 to 4, 20 is a buffer unit, and 30 is an input / output control circuit. Reference numeral 40 denotes an input / output counterpart circuit unit.

The buffer unit 20 includes a first output buffer 21, a second output buffer 22, an input / output terminal 23 to which the first and

second output buffers

21 and 22 are connected in common, and an input buffer 24. The first output buffer 21 includes a transistor TP1 as a first transistor connected between the power supply and the first node n1, and a second transistor connected between the first node n1 and the ground. A transistor TN1 and a resistance element R1 as a first resistance element connected between the first node n1 and the input / output terminal 23 are provided. The second output buffer 22 includes a transistor TP2 as a third transistor connected between the power supply and the second node n2, and a fourth transistor connected between the second node n2 and the ground. A transistor TN2 and a resistance element R2 as a second resistance element connected between the second node n2 and the input / output terminal 23 are provided.

The input / output control circuit 30 includes a signal generator 31, a changeover switch 32, and an inverter 33. The gates of the transistors TP1 and TN1 of the first output buffer 21 and the transistors TP2 and TN2 of the second output buffer 22 are provided. To output a signal. Then, a signal output mode for outputting a signal via the first and second output buffers 21 and 22 and a signal input mode for setting the first and second output buffers 21 and 22 as termination circuits are switched. FIG. 2 shows the operation in the signal output mode, and FIGS. 3 and 4 show the operation in the signal input mode.

The operation in the signal output mode will be described with reference to FIG. As shown in FIG. 2, in the signal output mode, the changeover switch 32 is set to the upper side, and the input / output control circuit 30 supplies the same signal to the first and second output buffers 21 and 22, that is, from the signal generator 31. Output the output signal. When the signal generator 31 outputs the signal “L (Low)”, the transistors TP1 and TP2 are turned on and the transistors TN1 and TN2 are turned off. Therefore, the signal “H (High)” is output from the first and second output buffers 21 and 22 to the input / output terminal 23. On the other hand, when the signal generator 31 outputs the signal “H”, the transistors TP1 and TP2 are turned off and the transistors TN1 and TN2 are turned on. Therefore, the signal “L” is output from the first and second output buffers 21 and 22 to the input / output terminal 23.

Here, in the input / output circuit according to this embodiment, in the output buffers 21 and 22, the resistance elements R1 and R2 are shared between the power supply side and the ground side. For example, in the first output buffer 21, when the signal “H” is output, the transistor TP1 and the resistor element R1 form an output resistor, and when the signal “L” is output, the transistor TN1 and the resistor element R1. Constitutes the output resistance (in FIG. 2, the direction of the current is indicated by a white arrow). By sharing the resistance elements R1 and R2 in this way, the resistance elements can be reduced compared to the conventional configuration in which the resistance elements are provided on both the power supply side and the ground side as shown in FIG. Thereby, a layout area can be made smaller than before.

Furthermore, in the conventional configuration as shown in FIG. 7, a current always flows through the resistance element in a certain direction. For this reason, in order to ensure the EM resistance, it is necessary to secure a sufficiently large width of the resistance element, and there is a problem that the layout area is further increased. On the other hand, in the input / output circuit of this embodiment, current flows through the resistance elements R1 and R2 in opposite directions when the signal “H” is output and when the signal “L” is output. For this reason, the EM deterioration of the resistance element is suppressed as compared with the conventional case, and therefore the width of the resistance element can be suppressed to be small.

The operation in the signal input mode will be described with reference to FIG. 3 and FIG. In the signal input mode, the first and second output buffers 21 and 22 are set as termination circuits.

Here, for example, in the conventional configuration as shown in FIG. 7, a circuit configuration similar to that of the Thevenin type termination circuit 102 can be realized by simultaneously turning on the transistors TP1 and TN1 of the output buffer 101. That is, the output buffer 101 can also be used as a termination circuit at the time of signal input. However, in the input / output circuit according to the present embodiment, for example, when the transistors TP1 and TN1 of the first output buffer 21 are simultaneously turned on, the resistance component between the power supply and the ground becomes only the ON resistance of the transistors TP1 and TN1. End up. For this reason, although the first output buffer 21 can be set as a termination circuit, there arises a problem that the operating current is significantly increased as compared with the conventional one.

Therefore, in this embodiment, in order to solve this problem, the termination circuit is realized by combining the first output buffer 21 and the second output buffer 22. That is, as shown in FIGS. 3 and 4, in the signal input mode, the changeover switch 32 is set to the lower side, and the input / output control circuit 30 has the polarities of the first and second output buffers 21 and 22 opposite to each other. The signal is output. That is, the output signal of the signal generator 31 is supplied to the first output buffer 21 as it is, and the inverted signal of the output signal of the signal generator 31 is supplied to the second output buffer 22.

In FIG. 3, the signal generator 31 outputs a signal “L”, and the signal “L” is given to the first output buffer 21, while the signal “H” is given to the second output buffer 22. It is done. At this time, in the first output buffer 21, the transistor TP1 is turned on and the transistor TN1 is turned off. In the second output buffer 22, the transistor TP2 is turned off and the transistor TN2 is turned on. As a result, a current path is formed from the power supply to the ground through the transistor TP1, the resistor element R1, the resistor element R2, and the transistor TN2. That is, the termination circuit is configured by the transistors TP1 and TN2 and the resistance elements R1 and R2. In this case, the input resistance value is a parallel resistance value of the ON resistance of the transistor TP1 and the series resistance of the resistance element R1, and the ON resistance of the transistor TN2 and the series resistance of the resistance element R2. Therefore, it is possible to operate as a termination circuit with an operating current comparable to that of the prior art.

In FIG. 4, the signal generator 31 outputs a signal “H”, the signal “H” is given to the first output buffer 21, while the signal “L” is given to the second output buffer 22. Given. At this time, in the first output buffer 21, the transistor TP1 is turned off and the transistor TN1 is turned on. In the second output buffer 22, the transistor TP2 is turned on and the transistor TN2 is turned off. As a result, a current path is formed from the power supply to the ground through the transistor TP2, the resistor element R2, the resistor element R1, and the transistor TN1. That is, a termination circuit is configured by the transistors TP2 and TN1 and the resistance elements R1 and R2. In this case, the input resistance value is a parallel resistance value of the ON resistance of the transistor TP2 and the series resistance of the resistance element R2, and the ON resistance of the transistor TN1 and the series resistance of the resistance element R1. Therefore, it is possible to operate as a termination circuit with an operating current comparable to that of the prior art.

In the signal input mode, the state shown in FIG. 3 or the state shown in FIG. 4 may be used. Or you may make it switch the state of FIG. 3 and the state of FIG. 4 at a predetermined | prescribed timing suitably. For example, the state of FIG. 3 and the state of FIG. 4 may be switched at a predetermined time period, or the state of FIG. 3 and the state of FIG. 4 may be switched each time the signal input mode is entered.

3 and FIG. 4, the directions of the currents flowing through the resistance elements R1 and R2 are reversed. Therefore, by switching between the state of FIG. 3 and the state of FIG. 4, the direction of the current flowing through the resistance elements R1 and R2 can be changed, thereby suppressing deterioration of the resistance elements R1 and R2 due to EM. Is possible. 3 and FIG. 4, the transistor to be activated is also switched. Therefore, by switching between the state of FIG. 3 and the state of FIG. 4, the average amount of current flowing through each transistor and its wiring can be reduced. Thereby, EM deterioration with respect to transistor wiring can be suppressed. Therefore, it is possible to reduce the width of the resistance element, the width of the transistor wiring, and the like necessary for satisfying the specified value of the EM resistance, and the layout area can be reduced.

Normally, the specified value of the output resistance at the time of signal output is less than or equal to the specified value of the input resistance at the time of signal input, so even if one termination circuit is configured by two output buffers, there is a particular problem. Does not occur.

FIG. 5 is a simplified diagram of an equivalent circuit of the input / output circuit according to the present embodiment, where (a) is an equivalent circuit at the time of signal output, and (b) is an equivalent circuit at the time of signal input. As shown in FIG. 5A, when two

output buffers

21 and 22 are used in parallel at the time of signal output, the output resistance Rout is:
Rout = (RTP1 + R1) // (RTP2 + R2)
It becomes. On the other hand, when a signal is input, as shown in FIG. 5B, when the termination circuit is configured using two

output buffers

21 and 22, the input resistance Rin is
Rin = (RTP1 + R1) // (RTN2 + R2)
It becomes. However, RTP1, RTP2, and RTN2 are ON resistance values of the transistors TP1, TP2, and TN2, respectively. If the ON resistance values of the transistors are equal to each other, the output resistance Rout and the input resistance Rin are equal. For example, when the output resistance Rout = 50Ω and the input resistance Rin = 50Ω are realized, the output resistance Rout = 50Ω can be realized when the output resistance of each of the output buffers 21 and 22 is 100Ω. Further, when the signal is input, the input resistance Rin viewed from the external terminal becomes a parallel resistance of 100Ω and 100Ω, that is, 50Ω, as shown in FIG. 5B.

If it is desired to set the output resistance and input resistance values individually, the output buffer is divided into a plurality of units (10 units 601 to 610 in FIG. 6) and used as shown in FIG. What is necessary is just to select the number of units suitably. For example, in the configuration of FIG. 6, when the resistance value of one unit is R, the output resistance at the time of signal output can be set in 10 steps from R, R / 2, R / 3,. . Further, the input resistance at the time of signal input can be set in five stages of R / 2, R / 4, R / 6, R / 8, and R / 10.

Further, by using a plurality of units and switching the unit to be activated, the average current flowing through the transistor wiring can be reduced in the same manner as described above, so that EM degradation can be suppressed.

In the above-described embodiment, the input / output control circuit 30 has been described by taking a simple configuration as an example. However, the present invention is not limited to this.

In the semiconductor control system shown in FIG. 1, the CPU 11 instructs the input / output circuit included in the DRAM interface 12 to switch between the signal input mode and the signal output mode in accordance with the program stored in the PROM 3. And Furthermore, the CPU 11 may also switch the transistors that are in the ON state in the signal input mode. For example, the state shown in FIG. 3 and the state shown in FIG. 4 may be switched by software. When the output buffer is divided into a plurality of units, the number of units to be used may be appropriately selected by software. Thereby, in the signal input mode, the switching timing of the transistors in the ON state and the number of units used can be optimized. Of course, switching of transistors in the ON state and selection of the number of units may be performed by an internal circuit.

Also, the termination circuit realization method using two output buffers shown in this embodiment can be applied to a conventional output buffer configuration as shown in FIG. 7 or an output buffer not using a resistance device. Is possible.

In the present invention, an input / output circuit that functions as both a driver circuit and a termination circuit is realized with a small circuit area and low power consumption while maintaining EM resistance. This is useful for ensuring the reliability and cost reduction of the interface LSI to be transmitted.

21 first output buffer 22 second output buffer 23 input / output terminal 30 input / output control circuit TP1 first transistor TN1 second transistor TP2 third transistor TN2 fourth transistor R1 first resistor element R2 second Resistive element n1 first node n2 second node

Claims

A first output buffer;
A second output buffer;
An input / output terminal to which the first and second output buffers are connected in common;
An input / output control circuit that switches between a signal output mode for performing signal output via the first and second output buffers and a signal input mode for setting the first and second output buffers as termination circuits;
The first output buffer comprises:
A first transistor connected between the power supply and the first node;
A second transistor connected between the first node and ground;
A first resistance element connected between the first node and the input / output terminal;
The second output buffer comprises:
A third transistor connected between the power supply and the second node;
A fourth transistor connected between the second node and ground;
A second resistance element connected between the second node and the input / output terminal;
In the signal input mode, the input / output control circuit turns on the first and fourth transistors and turns off the second and third transistors, or turns off the second and third transistors. 3. An input / output circuit that performs control to turn on the third transistor and set the second transistor in the second state to turn off the first and fourth transistors.
The input / output circuit according to claim 1.
The input / output control circuit switches the first state and the second state at a predetermined timing in the signal input mode.
An input / output circuit according to claim 1;
A semiconductor control system comprising: means for instructing the input / output circuit to switch between the signal input mode and the signal output mode.
An input / output circuit control method comprising: a first output buffer; a second output buffer; and an input / output terminal to which the first and second output buffers are connected in common.
The first output buffer comprises:
A first transistor connected between the power supply and the first node;
A second transistor connected between the first node and ground;
A first resistance element connected between the first node and the input / output terminal;
The second output buffer comprises:
A third transistor connected between the power supply and the second node;
A fourth transistor connected between the second node and ground;
A second resistance element connected between the second node and the input / output terminal;
In the signal output mode, control is performed to output signals through the first and second output buffers, while in the signal input mode, control is performed to set the first and second output buffers as termination circuits. And
In the signal input mode, the first and fourth transistors are turned on, the second and third transistors are turned off, or the second and third transistors are turned on. A control method for an input / output circuit, wherein control is performed to set the first and fourth transistors to a second state for turning them off.
In the input / output circuit control method according to claim 4,
A control method for an input / output circuit, wherein the first state and the second state are switched at a predetermined timing in the signal input mode.