WO2011125251A1 - Method and apparatus for manufacturing thin film silicon solar cell - Google Patents

Method and apparatus for manufacturing thin film silicon solar cell Download PDF

Info

Publication number
WO2011125251A1
WO2011125251A1 PCT/JP2010/069518 JP2010069518W WO2011125251A1 WO 2011125251 A1 WO2011125251 A1 WO 2011125251A1 JP 2010069518 W JP2010069518 W JP 2010069518W WO 2011125251 A1 WO2011125251 A1 WO 2011125251A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
substrate
microcrystalline silicon
crystallization rate
forming
Prior art date
Application number
PCT/JP2010/069518
Other languages
French (fr)
Japanese (ja)
Inventor
賢治 新谷
幹雄 山向
晋作 山口
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2012509273A priority Critical patent/JP5220239B2/en
Publication of WO2011125251A1 publication Critical patent/WO2011125251A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
    • H01L31/076—Multiple junction or tandem solar cells
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H01L31/1812—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table including only AIVBIV alloys, e.g. SiGe
    • H01L31/1816—Special manufacturing methods for microcrystalline layers, e.g. uc-SiGe, uc-SiC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • microcrystalline silicon cells it is known that the crystallinity of the type I (intrinsic) microcrystalline silicon layer that serves as the power generation layer (ratio of the crystalline component to the amorphous component of the film) has a significant effect on the cell characteristics. . For this reason, in a plasma CVD apparatus for forming a microcrystalline silicon layer, it is necessary to manage the crystallization rate in addition to the control of film thickness and conductivity performed by a normal CVD apparatus.
  • the management of the crystallization rate of a microcrystalline silicon film was made by preparing a sample in which a microcrystalline silicon film was formed on a glass substrate, and transferring the sample to a crystallization rate evaluation apparatus to measure and manage the crystallization rate.
  • a crystallization rate evaluation apparatus to measure and manage the crystallization rate.
  • the transfer robot transfers the product substrate between the transfer chamber 30, the load lock chamber 20, and the film forming chambers A, B, and C.
  • the crystallization rate measuring means 40 a microscopic laser Raman spectroscopic device using Raman spectroscopy can be used, and the crystallization rate measurement result measured by the crystallization rate measuring means 40 indicates the film forming conditions of each film forming chamber. It is sent to the film forming condition control means 50 to be controlled.
  • the load lock chamber 20 is a space for carrying the product substrate into and out of the transfer chamber 30.
  • the load lock chamber 20 is connected to the transfer chamber 30 via the gate valve 60.
  • FIG. 4 is a flowchart for explaining the transport procedure of the product substrate in the plasma CVD apparatus 100 according to the present embodiment.
  • the procedure for conveying the product substrate will be described together with the procedure shown in FIG.
  • the gate valve 60 between the load lock chamber 20 and the transfer chamber 30 is opened.
  • the product substrate in the load lock chamber 20 is loaded on the arm of a transfer robot in the transfer chamber 30 and is vacuum transferred from the load lock chamber 20 to the film forming chamber A through the transfer chamber 30.
  • the crystallization rate of the N-type microcrystalline silicon film 5 of the amorphous silicon cell 6 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30 (step) S22).
  • the measurement result of the crystallization rate is sent to the film forming condition control means 50 (step S41).
  • step S42 the film-forming condition control means 50 determines the film-forming conditions for the P-type microcrystalline silicon film 7 on the product substrate, and the film-forming conditions for the P-type microcrystalline silicon film 7 are plasma CVD.
  • Step S23 (FIG. 2, step S7).
  • the film forming conditions of the P-type microcrystalline silicon film 7 are controlled according to the result of the crystallization rate measurement of the N-type microcrystalline silicon film 5 of the amorphous silicon cell 6 by the crystallization rate measuring means 40.
  • the film forming condition control means 50 selects a film forming condition that causes the crystallization rate to be higher than usual so that the crystallization rate of the P-type microcrystalline silicon film 7 formed on the product substrate is substantially constant. It becomes possible to keep it.
  • the product substrate on which the P-type microcrystalline silicon film 7 is formed is loaded on the arm of the transfer robot in the transfer chamber 30 and is vacuum transferred from the film forming chamber A to the film forming chamber B through the transfer chamber 30.
  • the crystallization rate of the P-type microcrystalline silicon film 7 of the microcrystalline silicon cell 10 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30 ( Step S24).
  • the measurement result of the crystallization rate is sent to the film forming condition control means 50 (step S43).
  • step S44 the film formation condition control means 50 determines the film formation conditions for the I-type microcrystalline silicon film 8 on the product substrate, and the film formation of the I-type microcrystalline silicon film 8 is performed by plasma CVD under the film formation conditions.
  • Step S25 (FIG. 2, step S8).
  • the film forming conditions of the I-type microcrystalline silicon film 8 are controlled according to the result of the crystallization rate measurement of the P-type microcrystalline silicon film 7 of the microcrystalline silicon cell 10 by the crystallization rate measuring means 40.
  • step S46 the film-forming condition control means 50 determines the film-forming conditions for the N-type microcrystalline silicon film 9 on the product substrate, and the film-forming conditions for the N-type microcrystalline silicon film 9 are plasma CVD.
  • Step S27 (FIG. 2, step S9).
  • the film forming conditions of the N-type microcrystalline silicon film 9 are controlled according to the result of the crystallization rate measurement of the I-type microcrystalline silicon film 8 of the microcrystalline silicon cell 10 by the crystallization rate measuring means 40.
  • FIG. 1 The cross-sectional structure of a two-layer tandem-type thin-film silicon solar cell using amorphous silicon and microcrystalline silicon manufactured by the method and apparatus for manufacturing a thin-film silicon solar cell according to Embodiment 2 of the present invention as the power generation layer is the same as in FIG. It is. Moreover, the flowchart explaining the procedure which manufactures the 2 layer tandem-type thin film silicon solar cell with the manufacturing method of the thin film silicon solar cell which concerns on this Embodiment is also the same as that of FIG.
  • the film forming chamber A is a film forming chamber for forming the P-type microcrystalline silicon film 7.
  • the film forming chamber B is a film forming chamber for forming the I-type microcrystalline silicon film 8.
  • the film forming chamber C is a film forming chamber for forming the N-type microcrystalline silicon film 9.
  • the film forming chambers A, B, and C are each connected to a transfer chamber via a gate valve.
  • the transfer chamber 30 is a space for transferring a substrate between the load lock chamber 20 and the film forming chambers A, B, and C.
  • the transfer chamber 30 includes a transfer robot (not shown) operable in vacuum, a crystallization rate measuring means 40 for measuring the crystallization rate of the microcrystalline silicon film on the product substrate, and the substrate temperature of the product substrate.
  • Substrate temperature measuring means 41 for measuring is provided.
  • the substrate temperature measuring means 41 may be provided in the transfer robot in the transfer chamber 30.
  • the gate valve 60 between the load lock chamber 20 and the transfer chamber 30 is opened.
  • the product substrate in the load lock chamber 20 is loaded on the arm of a transfer robot in the transfer chamber 30 and is vacuum transferred from the load lock chamber 20 to the film forming chamber A through the transfer chamber 30.
  • the crystallization rate of the N-type microcrystalline silicon film 5 of the amorphous silicon cell 6 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30.
  • the substrate temperature is measured by the substrate temperature measuring means 41 provided in the transfer robot in the transfer chamber 30 (step S52).
  • the measurement results of the crystallization rate and the substrate temperature are sent to the film forming conditions and the substrate heating time control means 51 (step S61).
  • step S62 the film forming conditions and the substrate temperature raising time control means 51 determine the substrate temperature raising time and the film forming conditions of the P type microcrystalline silicon film 7 performed before the formation of the P type microcrystalline silicon film 7.
  • the substrate heating time after the substrate is heated, the P-type microcrystalline silicon film 7 is formed by plasma CVD under the film forming conditions (step S53) (FIG. 2, step S7).
  • the film forming conditions for the P-type microcrystalline silicon film 7 are determined by the same method as in the first embodiment, and the substrate heating time before forming the P-type microcrystalline silicon film 7 is the film forming chamber by the substrate temperature measuring means 41. Control is performed according to the result of the substrate temperature measurement immediately before being transferred to A.
  • the substrate temperature rise before the P-type microcrystalline silicon film 7 is formed is longer than the normal temperature raising time. It is expected to reach a predetermined temperature in a short time.
  • the film formation conditions and the substrate temperature increase time control means 51 can shorten the substrate temperature increase time before the formation of the P-type microcrystalline silicon film 7 by setting the substrate temperature increase time shorter than usual. It is possible to improve.
  • the product substrate on which the P-type microcrystalline silicon film 7 is formed is loaded on the arm of the transfer robot in the transfer chamber 30 and is vacuum transferred from the film forming chamber A to the film forming chamber B through the transfer chamber 30.
  • the crystallization rate of the P-type microcrystalline silicon film 7 of the microcrystalline silicon cell 10 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30.
  • the substrate temperature is measured by the substrate temperature measuring means 41 provided in the transfer robot in the transfer chamber 30 (step S54).
  • the measurement results of the crystallization rate and the substrate temperature are sent to the film forming conditions and the substrate heating time control means 51 (step S63).
  • the substrate temperature rise before the I-type microcrystalline silicon film 8 is formed is longer than the normal temperature raising time. It is expected to reach a predetermined temperature in a short time.
  • the film formation conditions and the substrate temperature increase time control means 51 can shorten the substrate temperature increase time before the formation of the I-type microcrystalline silicon film 8 by setting the substrate temperature increase time shorter than usual. It is possible to improve.
  • the product substrate on which the I-type microcrystalline silicon film 8 is formed according to the film forming conditions and the film forming conditions determined by the substrate heating time control means 51 is loaded on the arm of the transfer robot in the transfer chamber 30 and the film forming chamber B Is transferred to the film forming chamber C through the transfer chamber 30.
  • the crystallization rate of the I-type microcrystalline silicon film 8 of the microcrystalline silicon cell 10 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30.
  • the substrate temperature is measured by the substrate temperature measuring means 41 provided in the transfer robot in the transfer chamber 30 (step S56).
  • the measurement results of the crystallization rate and the substrate temperature are sent to the film forming conditions and the substrate heating time control means 51 (step S65).
  • FIG. 9 is a diagram schematically showing the relationship between the substrate heating time and the temperature of the substrate loaded on the stage heater.
  • the temperature of the substrate loaded on the stage heater rises with time and saturates at the stage heater temperature.
  • the substrate temperature rise time T until the substrate temperature reaches the stage heater temperature becomes longer as the substrate temperature (initial substrate temperature Ts) before introduction of the film forming chamber is lower than the stage heater temperature.
  • a long substrate heating time T (here, T1) is set based on the lowest assumed initial substrate temperature Ts (for example, Ts1).
  • the plasma CVD apparatus is described as an example of the CVD apparatus for forming the microcrystalline silicon film.
  • the CVD method is not limited to this, and other methods such as hot wire CVD are used. The same effect can be obtained even by the CVD method.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Sustainable Development (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Sustainable Energy (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Photovoltaic Devices (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Disclosed is a method for manufacturing a thin film silicon solar cell, which includes: measuring steps (S22, 24, 26) wherein a crystallization rate of a film to be a base film is measured, said film being formed on a substrate by CVD and containing a fine crystalline silicon component; steps (S42, 44, 46) wherein, on the basis of previously obtained relationships among the crystallization rate of the base film, conditions of forming the film on the base film, and the crystallization rate of the film formed on the base film by the CVD under the conditions, film-forming conditions are determined on the basis of the crystallization rate measured in the measuring steps, and a desired crystallization rate of the film, which is formed on the base film and contains the fine crystalline silicon component; and steps (S23, 25, 27) wherein the film containing the fine crystalline silicon component is formed by the CVD on the base film under the determined film-forming conditions, in a second film-forming chamber, which is different from the first film-forming chamber wherein the base film is formed, and which can have the substrate vacuum-transferred thereto from the first film-forming chamber.

Description

薄膜シリコン太陽電池の製造方法および製造装置Thin-film silicon solar cell manufacturing method and manufacturing apparatus
　本発明は、絶縁性基板上に作製した微結晶シリコン層を含む薄膜シリコン太陽電池の製造方法および製造装置に関する。 The present invention relates to a method and an apparatus for manufacturing a thin film silicon solar cell including a microcrystalline silicon layer manufactured on an insulating substrate.
　太陽光発電は、化石燃料による火力発電の代替エネルギーとして期待されており、太陽光発電システムの生産量は年々増加している。このために、シリコン基板を原材料に用いるバルク型太陽電池ではシリコンウエハが不足するという事態が発生し、シリコン基板の価格高騰により製造コストの増大が懸念されている。このため、シリコン基板の供給量に製造コストが左右されない薄膜シリコン太陽電池が注目されている。 Solar power generation is expected as an alternative to thermal power generation using fossil fuels, and the production of solar power generation systems is increasing year by year. For this reason, in a bulk solar cell using a silicon substrate as a raw material, there is a situation in which a silicon wafer is insufficient, and there is a concern about an increase in manufacturing cost due to a rise in the price of the silicon substrate. For this reason, a thin-film silicon solar cell whose manufacturing cost does not depend on the supply amount of the silicon substrate has attracted attention.
　薄膜シリコン太陽電池の一例として、ガラス基板上に複数の発電層を積層したタンデム型薄膜シリコン太陽電池がある。アモルファスシリコンを発電層に用いたセルを光入射側に作製し、この上に、微結晶シリコンを発電層に用いたセルを作製した２層タンデム型薄膜シリコン太陽電池の場合、短波長域に分光感度を有するアモルファスシリコンセルと長波長域に分光感度を有する微結晶シリコンセルを積層することで、幅広い波長域において分光感度を有する高効率な薄膜シリコン太陽電池を実現できる。 An example of a thin film silicon solar cell is a tandem thin film silicon solar cell in which a plurality of power generation layers are stacked on a glass substrate. In the case of a two-layer tandem-type thin-film silicon solar cell in which a cell using amorphous silicon as a power generation layer is formed on the light incident side and a cell using microcrystalline silicon as a power generation layer is formed on the cell, the spectrum is analyzed in the short wavelength region. By stacking an amorphous silicon cell having sensitivity and a microcrystalline silicon cell having spectral sensitivity in a long wavelength region, a highly efficient thin-film silicon solar cell having spectral sensitivity in a wide wavelength region can be realized.
　また、アモルファスシリコンセルと微結晶シリコンセルとの間に中間層として微結晶シリコン酸化膜を挿入した２層タンデム型薄膜シリコン太陽電池も提唱されている（特許文献１参照）。この構造は、アモルファスシリコンセルで吸収しきれなかった入射光を微結晶シリコン酸化膜により再度アモルファスシリコンセル側に反射させることでアモルファスシリコンセルの高効率化を図ることができる。 Also, a two-layer tandem thin film silicon solar cell in which a microcrystalline silicon oxide film is inserted as an intermediate layer between an amorphous silicon cell and a microcrystalline silicon cell has been proposed (see Patent Document 1). In this structure, the efficiency of the amorphous silicon cell can be improved by reflecting incident light that could not be absorbed by the amorphous silicon cell to the amorphous silicon cell side again by the microcrystalline silicon oxide film.
　通常、アモルファスシリコンセルおよび微結晶シリコンセルは製膜条件が大きく異なるために、それぞれ異なるプラズマＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ：化学気相成長）装置で形成される。また、アモルファスシリコンセルおよび微結晶シリコンセルのＰ／Ｉ／Ｎ型の各層は、クロスコンタミネーションによるセル特性の劣化を抑制するために、プラズマＣＶＤ装置の異なる製膜室にて形成される。また、ＣＶＤ装置の各製膜室間における基板の搬送は、大気暴露によるシリコン表面の酸化を防止するため真空中で行われる。 Usually, the amorphous silicon cell and the microcrystalline silicon cell are formed by different plasma CVD (Chemical Vapor Deposition) apparatuses because the film forming conditions are greatly different. In addition, the P / I / N type layers of the amorphous silicon cell and the microcrystalline silicon cell are formed in different film forming chambers of the plasma CVD apparatus in order to suppress deterioration of cell characteristics due to cross contamination. The substrate is transferred between the film forming chambers of the CVD apparatus in a vacuum in order to prevent oxidation of the silicon surface due to atmospheric exposure.
特許第４２８４５８２号公報Japanese Patent No. 4284582
　微結晶シリコンセルでは、発電層となるＩ型（Ｉｎｔｒｉｎｓｉｃ：真性）微結晶シリコン層の結晶化率（膜の結晶成分とアモルファス成分の比）がセル特性に大きな影響を与えることが知られている。このため、微結晶シリコン層を形成するプラズマＣＶＤ装置では、通常のＣＶＤ装置で行なわれる膜厚や導電率の管理に加えて結晶化率を管理する必要がある。 In microcrystalline silicon cells, it is known that the crystallinity of the type I (intrinsic) microcrystalline silicon layer that serves as the power generation layer (ratio of the crystalline component to the amorphous component of the film) has a significant effect on the cell characteristics. . For this reason, in a plasma CVD apparatus for forming a microcrystalline silicon layer, it is necessary to manage the crystallization rate in addition to the control of film thickness and conductivity performed by a normal CVD apparatus.
　従来、微結晶シリコン膜の結晶化率の管理は、ガラス基板上に微結晶シリコン膜を形成したサンプルを作製し、結晶化率評価装置にサンプルを移して結晶化率を測定・管理していた（例えば、特開２００４－３３５８２４号公報参照）。しかし、上述の方法では、結晶化率評価の際に製品の処理を一時的に停止してサンプルを作製する必要があるため、製造工程のスループット低下が問題となっていた。 Conventionally, the management of the crystallization rate of a microcrystalline silicon film was made by preparing a sample in which a microcrystalline silicon film was formed on a glass substrate, and transferring the sample to a crystallization rate evaluation apparatus to measure and manage the crystallization rate. (For example, refer to JP 2004-335824 A). However, in the above-described method, it is necessary to temporarily stop the processing of the product at the time of evaluating the crystallization rate to produce a sample.
　また、２層タンデム型薄膜シリコン太陽電池を作成する場合、微結晶シリコンセルのＰ型微結晶シリコン膜の製膜はアモルファスシリコンセルのＮ型微結晶シリコン膜上に製膜が行なわれるため、アモルファスシリコンセルのＮ型微結晶シリコン膜の結晶化率が変動した場合、この上に製膜するＰ型微結晶シリコン膜の結晶化率が変化するという問題点がある。 When a two-layer tandem-type thin film silicon solar cell is formed, since the P-type microcrystalline silicon film of the microcrystalline silicon cell is formed on the N-type microcrystalline silicon film of the amorphous silicon cell, it is amorphous. When the crystallization rate of the N-type microcrystalline silicon film of the silicon cell varies, there is a problem that the crystallization rate of the P-type microcrystalline silicon film formed thereon changes.
　例えば、アモルファスシリコンセルのＮ型微結晶シリコン膜の結晶化率が高くなった場合には、Ｎ型微結晶シリコン膜表面に形成された多量の結晶が核となり、この上に製膜するＰ型微結晶シリコン膜の結晶成長が促進されることでＰ型微結晶シリコン膜の結晶化率が高くなる。この結果、引き続き製膜される微結晶シリコンセルの発電層であるＩ型微結晶シリコン層の結晶化率が通常よりも高くなり、最終的に２層タンデム型薄膜シリコン太陽電池のセル特性が劣化し、製品の歩留まりが低下するという問題点があった。 For example, when the crystallization rate of an N-type microcrystalline silicon film in an amorphous silicon cell increases, a large amount of crystals formed on the surface of the N-type microcrystalline silicon film serve as nuclei, and a P-type film is formed thereon. By promoting the crystal growth of the microcrystalline silicon film, the crystallization rate of the P-type microcrystalline silicon film is increased. As a result, the crystallization rate of the I-type microcrystalline silicon layer, which is the power generation layer of the subsequently formed microcrystalline silicon cell, becomes higher than usual, and eventually the cell characteristics of the two-layer tandem thin-film silicon solar cell deteriorate. However, there is a problem that the yield of the product is lowered.
　また、特開平４－３５４３２６号公報では、ロール・ツー・ロール法で作製される薄膜シリコン太陽電池において、Ｐ／Ｉ／Ｎ層の各製膜室内に赤外線ビームを照射し、フーリエ変換赤外吸収分光法により膜中の結合水素をモニターする方法が開示されている。しかし、この方法では、長尺基板の進行方向の膜特性は連続的に取得できるものの、長尺基板の短辺方向の膜特性を評価できないため、製膜中にプラズマに分布が生じ、短辺方向に膜特性の異常が発生した場合に検知できないという問題がある。 In Japanese Patent Laid-Open No. 4-354326, in a thin film silicon solar cell manufactured by a roll-to-roll method, an infrared beam is irradiated into each film forming chamber of the P / I / N layer, and Fourier transform infrared absorption is performed. A method for monitoring bound hydrogen in a film by spectroscopy is disclosed. However, in this method, although the film characteristics in the traveling direction of the long substrate can be obtained continuously, the film characteristics in the short side direction of the long substrate cannot be evaluated, so that distribution occurs in the plasma during film formation, and the short side There is a problem that it cannot be detected when an abnormality in the film characteristics occurs in the direction.
　更に、微結晶シリコン膜の結晶化率は、微結晶シリコン製膜時の基板温度によって変化することが知られている。図１０は、Ｉ型微結晶シリコン層の結晶化率の基板温度依存性を示した図である。図１０に示すように、製膜時の基板温度に依存してＩ型微結晶シリコン層の結晶化率が変化することがわかる。このため、通常は、製膜室内のステージヒータ上にガラス基板を設置し、製膜ガスを導入した状態で基板をステージヒータの温度にまで昇温させ、基板温度が安定した状態で製膜を開始する。これにより、処理毎の基板温度のばらつきを抑制して微結晶シリコン膜の結晶化率の安定化を図っている。この場合、基板昇温前の基板温度にバラつきが生じたとしても基板を所望の温度にまで確実に昇温できるように基板昇温時間を長く設定しており、このことがスループットの低下を引き起こしていた。 Furthermore, it is known that the crystallization rate of the microcrystalline silicon film varies depending on the substrate temperature when the microcrystalline silicon film is formed. FIG. 10 is a diagram showing the substrate temperature dependence of the crystallization rate of the I-type microcrystalline silicon layer. As shown in FIG. 10, it can be seen that the crystallization rate of the I-type microcrystalline silicon layer changes depending on the substrate temperature during film formation. For this reason, usually, a glass substrate is installed on the stage heater in the deposition chamber, and the substrate is heated to the temperature of the stage heater with the deposition gas introduced, and the deposition is performed with the substrate temperature being stable. Start. Thereby, the variation in the substrate temperature for each process is suppressed, and the crystallization rate of the microcrystalline silicon film is stabilized. In this case, even if the substrate temperature before the substrate temperature rises, the substrate temperature rise time is set long so that the substrate temperature can be surely raised to the desired temperature, which causes a decrease in throughput. It was.
　本発明は、上記に鑑みてなされたものであって、製造スループット及び歩留まりを向上させた薄膜シリコン太陽電池の製造方法および製造装置を得ることを目的とする。 The present invention has been made in view of the above, and an object of the present invention is to obtain a method and an apparatus for manufacturing a thin-film silicon solar cell with improved manufacturing throughput and yield.
　上述した課題を解決し、目的を達成するために、本発明は、基板の上にＣＶＤによって製膜された下地膜となる微結晶シリコン成分を含む膜の結晶化率を測定する測定工程と、前記下地膜の結晶化率と当該下地膜の上に製膜する条件と当該条件のもと当該下地膜の上にＣＶＤにより製膜された微結晶シリコン成分を含む膜の結晶化率との予め求めておいた関係に基づいて、前記測定工程で測定された結晶化率と前記下地膜の上に製膜する微結晶シリコン成分を含む膜の所望の結晶化率とに基づいて製膜条件を決定する工程と、前記下地膜が製膜された第１の製膜室とは別の製膜室であって、第１の製膜室から前記基板を真空搬送することが可能な第２の製膜室において、決定された前記製膜条件のもと、当該下地膜の上に微結晶シリコン成分を含む膜をＣＶＤにより製膜する工程とを含むことを特徴とする。 In order to solve the above-described problems and achieve the object, the present invention includes a measuring step of measuring a crystallization rate of a film containing a microcrystalline silicon component which is a base film formed on a substrate by CVD, The crystallization rate of the base film, the conditions for forming the film on the base film, and the crystallization rate of a film containing a microcrystalline silicon component formed by CVD on the base film under the conditions are previously set. Based on the relationship obtained, the film formation conditions are determined based on the crystallization rate measured in the measurement step and the desired crystallization rate of the film containing the microcrystalline silicon component formed on the base film. And a second film forming chamber that is different from the first film forming chamber on which the base film is formed, and is capable of vacuum transporting the substrate from the first film forming chamber. In the film forming chamber, microcrystalline silicon is formed on the base film under the determined film forming conditions. Characterized in that it comprises a step of forming a film by CVD of films containing.
　また、本発明は、前記製膜する工程の前に、前記下地膜が製膜された前記基板の温度を測定する工程と、測定された前記基板の温度に基づいて、前記製膜する工程の前の前記基板の前記第２の製膜室における昇温時間を決定する工程と、前記製膜する工程の前に、前記第２の製膜室において前記基板を前記昇温時間で昇温する工程とをさらに含むことを特徴とする。 Further, the present invention includes a step of measuring the temperature of the substrate on which the base film has been formed and a step of forming the film based on the measured temperature of the substrate before the step of forming the film. Prior to the step of determining the temperature rising time of the previous substrate in the second film forming chamber and the step of forming the film, the substrate is heated in the second film forming chamber for the temperature rising time. And further comprising a step.
　本発明によれば、薄膜シリコン太陽電池製造のスループットを向上させ、かつ歩留まりを向上させるという効果を奏する。 According to the present invention, there are the effects of improving the throughput of manufacturing a thin film silicon solar cell and improving the yield.
図１は、本発明の実施の形態１および２にかかるタンデム型薄膜シリコン太陽電池の構造を説明するための断面模式図である。FIG. 1 is a schematic cross-sectional view for explaining the structure of a tandem-type thin film silicon solar cell according to first and second embodiments of the present invention. 図２は、タンデム型薄膜シリコン太陽電池を製造する手順を説明するフローチャートである。FIG. 2 is a flowchart illustrating a procedure for manufacturing a tandem-type thin film silicon solar cell. 図３は、本発明の実施の形態１に係る薄膜シリコン太陽電池の微結晶シリコンセル製膜用のプラズマＣＶＤ装置の構成を示すブロック図である。FIG. 3 is a block diagram showing a configuration of a plasma CVD apparatus for forming a microcrystalline silicon cell of the thin-film silicon solar battery according to Embodiment 1 of the present invention. 図４は、本発明の実施の形態１に係る微結晶シリコンセル製造用のプラズマＣＶＤ装置における製品処理手順を説明するフロー図である。FIG. 4 is a flowchart for explaining a product processing procedure in the plasma CVD apparatus for manufacturing a microcrystalline silicon cell according to the first embodiment of the present invention. 図５は、下地膜の結晶化率に応じて、所望の結晶化率の微結晶シリコンの製膜条件を選択する方法を説明するための図である。FIG. 5 is a diagram for explaining a method of selecting a film formation condition of microcrystalline silicon having a desired crystallization rate in accordance with the crystallization rate of the base film. 図６は、他の構造のタンデム型薄膜シリコン太陽電池の構造を説明するための断面模式図である。FIG. 6 is a schematic cross-sectional view for explaining the structure of a tandem-type thin film silicon solar cell having another structure. 図７は、本発明の実施の形態２に係る薄膜シリコン太陽電池の微結晶シリコンセル製膜用のプラズマＣＶＤ装置の構成を示すブロック図である。FIG. 7 is a block diagram showing a configuration of a plasma CVD apparatus for forming a microcrystalline silicon cell of a thin film silicon solar battery according to Embodiment 2 of the present invention. 図８は、本発明の実施の形態２に係る微結晶シリコンセル製造用のプラズマＣＶＤ装置における製品処理手順を説明するフロー図である。FIG. 8 is a flowchart for explaining a product processing procedure in the plasma CVD apparatus for manufacturing a microcrystalline silicon cell according to the second embodiment of the present invention. 図９は、製膜前の基板温度に応じて、所望の基板昇温時間を決定する方法を説明するための図である。FIG. 9 is a diagram for explaining a method of determining a desired substrate heating time according to the substrate temperature before film formation. 図１０は、基板温度に応じてＩ型微結晶シリコン層の結晶化率が変化することを説明するための図である。FIG. 10 is a diagram for explaining that the crystallization rate of the I-type microcrystalline silicon layer changes according to the substrate temperature.
　以下に、本発明にかかる薄膜シリコン太陽電池の製造方法および製造装置の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。 Embodiments of a method for manufacturing a thin-film silicon solar cell and a manufacturing apparatus according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.
実施の形態１．
　図１は、本発明の実施の形態１にかかる薄膜シリコン太陽電池の製造方法および製造装置で製造するアモルファスシリコンと微結晶シリコンを発電層に用いた２層タンデム型薄膜シリコン太陽電池の断面構造を示す。 Embodiment 1 FIG.
FIG. 1 shows a cross-sectional structure of a two-layer tandem-type thin film silicon solar cell using amorphous silicon and microcrystalline silicon manufactured by a method and an apparatus for manufacturing a thin film silicon solar cell according to a first embodiment of the present invention as a power generation layer. Show.
　ガラス基板１上には、透明導電膜２が形成され、この透明導電膜２の表面には、入射光を効率的に散乱させるための凹凸形状（図示せず）が形成されている。この上に、Ｐ型アモルファスシリコン膜３、Ｉ型アモルファスシリコン膜４、Ｎ型微結晶シリコン膜５から成るアモルファスシリコンセル６が形成されており、このアモルファスシリコンセル６上に、Ｐ型微結晶シリコン膜７、Ｉ型微結晶シリコン膜８、Ｎ型微結晶シリコン膜９から成る微結晶シリコンセル１０が形成されている。微結晶シリコンセル１０上には、光閉じ込め層となる第２の透明導電膜１１および金属電極膜１２が形成されている。 A transparent conductive film 2 is formed on the glass substrate 1, and an uneven shape (not shown) for efficiently scattering incident light is formed on the surface of the transparent conductive film 2. An amorphous silicon cell 6 comprising a P-type amorphous silicon film 3, an I-type amorphous silicon film 4 and an N-type microcrystalline silicon film 5 is formed on the amorphous silicon cell 6. A microcrystalline silicon cell 10 composed of the film 7, the I-type microcrystalline silicon film 8, and the N-type microcrystalline silicon film 9 is formed. On the microcrystalline silicon cell 10, a second transparent conductive film 11 and a metal electrode film 12 are formed as a light confinement layer.
　図２は、本発明の実施の形態１に係る薄膜シリコン太陽電池の製造方法により２層タンデム型薄膜シリコン太陽電池を製造する手順を説明するフローチャートである。 FIG. 2 is a flowchart illustrating a procedure for manufacturing a two-layer tandem-type thin film silicon solar cell by the method for manufacturing a thin film silicon solar cell according to Embodiment 1 of the present invention.
　ステップＳ１では、製品基板であるガラス基板１を用意し、ガラス基板１を洗浄する。ステップＳ２ではガラス基板１に透明導電膜２を製膜する。ここで得られる透明導電膜２は、下部電極層を構成する。ステップＳ３では、レーザースクライブにより、透明導電膜２をセル状にパターニングする。 In step S1, a glass substrate 1 which is a product substrate is prepared, and the glass substrate 1 is cleaned. In step S2, a transparent conductive film 2 is formed on the glass substrate 1. The transparent conductive film 2 obtained here constitutes a lower electrode layer. In step S3, the transparent conductive film 2 is patterned into a cell shape by laser scribing.
　ステップＳ４、Ｓ５、Ｓ６では、それぞれボロン（Ｂ）をドープしたＰ型アモルファスシリコン膜３、ノンドープのＩ型アモルファスシリコン膜４、リン（Ｐ）をドープしたＮ型微結晶シリコン膜５を順次製膜し、アモルファスシリコンセル６を形成する。ここで、アモルファスシリコンセル６のＮ層としてＮ型微結晶シリコン膜５を製膜するのは、アモルファスシリコンセル６と微結晶シリコンセル１０の接合性を高めるためである。 In steps S4, S5, and S6, a P-type amorphous silicon film 3 doped with boron (B), an undoped I-type amorphous silicon film 4, and an N-type microcrystalline silicon film 5 doped with phosphorus (P) are sequentially formed. Then, an amorphous silicon cell 6 is formed. Here, the reason why the N-type microcrystalline silicon film 5 is formed as the N layer of the amorphous silicon cell 6 is to improve the bondability between the amorphous silicon cell 6 and the microcrystalline silicon cell 10.
　ステップＳ７、Ｓ８、Ｓ９では、それぞれリン（Ｐ）をドープしたＰ型微結晶シリコン膜７、ノンドープのＩ型微結晶シリコン膜８、ボロン（Ｂ）をドープしたＮ型微結晶シリコン膜９を順次製膜し微結晶シリコンセル１０を形成する。 In steps S7, S8, and S9, a P-type microcrystalline silicon film 7 doped with phosphorus (P), an undoped I-type microcrystalline silicon film 8, and an N-type microcrystalline silicon film 9 doped with boron (B) are sequentially formed. A microcrystalline silicon cell 10 is formed by film formation.
　ステップＳ１０では、レーザースクライブにより、積層されたアモルファスシリコンセル６および微結晶シリコンセル１０をセル状にパターニングする。 In step S10, the laminated amorphous silicon cell 6 and microcrystalline silicon cell 10 are patterned into cells by laser scribing.
　ステップＳ１１では、第２の透明導電膜１１を製膜する。ここで得られる第２の透明導電膜１１は、光閉じ込め層を構成する。ステップＳ１２では、金属電極膜１２を製膜する。ここで得られる金属電極膜１２は、上部電極層を構成する。 In step S11, the second transparent conductive film 11 is formed. The second transparent conductive film 11 obtained here constitutes an optical confinement layer. In step S12, the metal electrode film 12 is formed. The metal electrode film 12 obtained here constitutes an upper electrode layer.
　ステップＳ１３では、レーザースクライブにより、積層されたアモルファスシリコンセル６、微結晶シリコンセル１０、第２の透明導電膜１１および金属電極膜１２をセル状にパターニングする。 In step S13, the laminated amorphous silicon cell 6, microcrystalline silicon cell 10, second transparent conductive film 11 and metal electrode film 12 are patterned into cells by laser scribing.
　以上の製造工程によって、隣接するセル間で下部電極層と上部電極層とが直列に接続された構造を形成する。その後、基板洗浄（ステップＳ１４）、太陽電池特性検査（ステップＳ１５）を経て、実装工程へ移行する。 Through the above manufacturing process, a structure in which the lower electrode layer and the upper electrode layer are connected in series between adjacent cells is formed. Thereafter, the substrate cleaning (step S14) and the solar cell characteristic inspection (step S15) are performed, and then the mounting process is started.
　図３は、本実施の形態に係る微結晶シリコンセル製膜用のプラズマＣＶＤ装置１００の概略構成を示すブロック図である。プラズマＣＶＤ装置１００において、図２のステップＳ７、Ｓ８、Ｓ９が実行される。本実施の形態で使用するプラズマＣＶＤ装置１００は、マルチチャンバ方式を採用するプラズマＣＶＤ装置である。本プラズマＣＶＤ装置は、ロードロック室２０、搬送室３０および三つの製膜室Ａ、Ｂ、Ｃを備える。ロードロック室２０および製膜室Ａ、Ｂ、Ｃは、搬送室３０の周囲に設けられている。 FIG. 3 is a block diagram showing a schematic configuration of a plasma CVD apparatus 100 for forming a microcrystalline silicon cell according to the present embodiment. In the plasma CVD apparatus 100, steps S7, S8, and S9 in FIG. 2 are executed. The plasma CVD apparatus 100 used in this embodiment is a plasma CVD apparatus that employs a multi-chamber system. This plasma CVD apparatus includes a load lock chamber 20, a transfer chamber 30, and three film forming chambers A, B, and C. The load lock chamber 20 and the film forming chambers A, B, and C are provided around the transfer chamber 30.
　製膜室Ａは、Ｐ型微結晶シリコン膜７の製膜のための製膜室である。製膜室Ｂは、Ｉ型微結晶シリコン膜８の製膜のための製膜室である。製膜室Ｃは、Ｎ型微結晶シリコン膜９の製膜のための製膜室である。製膜室Ａ、Ｂ、Ｃは、それぞれゲートバルブを介して搬送室に接続されている。 The film forming chamber A is a film forming chamber for forming the P-type microcrystalline silicon film 7. The film forming chamber B is a film forming chamber for forming the I-type microcrystalline silicon film 8. The film forming chamber C is a film forming chamber for forming the N-type microcrystalline silicon film 9. The film forming chambers A, B, and C are each connected to a transfer chamber via a gate valve.
　搬送室３０は、ロードロック室２０、製膜室Ａ、Ｂ、Ｃの間で基板を搬送するためのスペースである。搬送室３０には、真空中で動作可能な搬送ロボット（図示せず）と製品基板上の微結晶シリコン膜の結晶化率を測定するための結晶化率測定手段４０が設けられている。 The transfer chamber 30 is a space for transferring a substrate between the load lock chamber 20 and the film forming chambers A, B, and C. The transfer chamber 30 is provided with a transfer robot (not shown) operable in vacuum and a crystallization rate measuring means 40 for measuring the crystallization rate of the microcrystalline silicon film on the product substrate.
　搬送ロボットは、搬送室３０とロードロック室２０、製膜室Ａ、Ｂ、Ｃとの間で製品基板を搬送する。結晶化率測定手段４０は、ラマン分光法を用いた顕微レーザーラマン分光装置を用いることができ、結晶化率測定手段４０で測定した結晶化率測定結果は、各製膜室の製膜条件を制御する製膜条件制御手段５０に送られる。ロードロック室２０は、搬送室３０への製品基板の搬入および取り出しのためのスペースである。ロードロック室２０は、ゲートバルブ６０を介して搬送室３０に接続されている。 The transfer robot transfers the product substrate between the transfer chamber 30, the load lock chamber 20, and the film forming chambers A, B, and C. As the crystallization rate measuring means 40, a microscopic laser Raman spectroscopic device using Raman spectroscopy can be used, and the crystallization rate measurement result measured by the crystallization rate measuring means 40 indicates the film forming conditions of each film forming chamber. It is sent to the film forming condition control means 50 to be controlled. The load lock chamber 20 is a space for carrying the product substrate into and out of the transfer chamber 30. The load lock chamber 20 is connected to the transfer chamber 30 via the gate valve 60.
　図４は、本実施の形態に係るプラズマＣＶＤ装置１００における製品基板の搬送手順を説明するフロー図である。ここでは、図２に示す手順とともに、製品基板の搬送手順を説明する。 FIG. 4 is a flowchart for explaining the transport procedure of the product substrate in the plasma CVD apparatus 100 according to the present embodiment. Here, the procedure for conveying the product substrate will be described together with the procedure shown in FIG.
　透明導電膜２が製膜され（図２、ステップＳ２）、レーザースクライブ（ステップＳ３）、アモルファスシリコンセル６の形成工程（ステップＳ４～Ｓ６）を経た製品基板は、ロードロック室２０内に設置される（図４、ステップＳ２１）。ロードロック室２０内に製品基板が設置されると、ロードロック室２０内を真空排気する。 The transparent conductive film 2 is formed (FIG. 2, step S2), the laser scribe (step S3), and the product substrate that has undergone the process of forming the amorphous silicon cell 6 (steps S4 to S6) is placed in the load lock chamber 20. (FIG. 4, step S21). When the product substrate is installed in the load lock chamber 20, the load lock chamber 20 is evacuated.
　ロードロック室２０を真空排気した後、ロードロック室２０と搬送室３０間のゲートバルブ６０が開かれる。ロードロック室２０内の製品基板は、搬送室３０内の搬送ロボットのアームに積載され、ロードロック室２０から搬送室３０を経て、製膜室Ａに真空搬送される。この際に、搬送室３０に設けられた結晶化率測定手段４０により、製品基板の最表面に形成されたアモルファスシリコンセル６のＮ型微結晶シリコン膜５の結晶化率が測定される（ステップＳ２２）。この結晶化率の測定結果は、製膜条件制御手段５０に送られる（ステップＳ４１）。 After the load lock chamber 20 is evacuated, the gate valve 60 between the load lock chamber 20 and the transfer chamber 30 is opened. The product substrate in the load lock chamber 20 is loaded on the arm of a transfer robot in the transfer chamber 30 and is vacuum transferred from the load lock chamber 20 to the film forming chamber A through the transfer chamber 30. At this time, the crystallization rate of the N-type microcrystalline silicon film 5 of the amorphous silicon cell 6 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30 (step) S22). The measurement result of the crystallization rate is sent to the film forming condition control means 50 (step S41).
　製膜条件制御手段５０は、ステップＳ４２において、製品基板のＰ型微結晶シリコン膜７の製膜条件を決定し、この製膜条件のもとＰ型微結晶シリコン膜７の製膜がプラズマＣＶＤにより行なわれる（ステップＳ２３）（図２、ステップＳ７）。Ｐ型微結晶シリコン膜７の製膜条件は、結晶化率測定手段４０によるアモルファスシリコンセル６のＮ型微結晶シリコン膜５の結晶化率測定の結果に応じて制御される。 In step S42, the film-forming condition control means 50 determines the film-forming conditions for the P-type microcrystalline silicon film 7 on the product substrate, and the film-forming conditions for the P-type microcrystalline silicon film 7 are plasma CVD. (Step S23) (FIG. 2, step S7). The film forming conditions of the P-type microcrystalline silicon film 7 are controlled according to the result of the crystallization rate measurement of the N-type microcrystalline silicon film 5 of the amorphous silicon cell 6 by the crystallization rate measuring means 40.
　例えば、アモルファスシリコンセル６のＮ型微結晶シリコン膜５の結晶化率が通常よりも低いことが検知された場合は、この上に製膜するＰ型微結晶シリコン膜７の結晶化率が低下することが予想される。この場合、製膜条件制御手段５０は、通常よりも結晶化率が高くなる製膜条件を選択することにより、製品基板に製膜されるＰ型微結晶シリコン膜７の結晶化率をほぼ一定に保つことが可能となる。 For example, when it is detected that the crystallization rate of the N-type microcrystalline silicon film 5 of the amorphous silicon cell 6 is lower than usual, the crystallization rate of the P-type microcrystalline silicon film 7 formed thereon is lowered. Is expected to. In this case, the film forming condition control means 50 selects a film forming condition that causes the crystallization rate to be higher than usual so that the crystallization rate of the P-type microcrystalline silicon film 7 formed on the product substrate is substantially constant. It becomes possible to keep it.
　アモルファスシリコンセル６のＮ型微結晶シリコン膜５の結晶化率測定結果を基にして調整されるＰ型微結晶シリコン膜７の製膜パラメータとして、ＳｉＨ４流量、Ｈ２流量、製膜圧力および基板-電極間距離などがある。 As the deposition parameters of the P-type microcrystalline silicon film 7 adjusted based on the crystallization rate measurement result of the N-type microcrystalline silicon film 5 of the amorphous silicon cell 6, the SiH 4 flow rate, the H 2 flow rate, the deposition pressure, and There is a distance between the substrate and the electrode.
　Ｐ型微結晶シリコン膜７が形成された製品基板は、搬送室３０内の搬送ロボットのアームに積載され、製膜室Ａから搬送室３０を経て製膜室Ｂに真空搬送される。この際に、搬送室３０に設けられた結晶化率測定手段４０により、製品基板の最表面に形成された微結晶シリコンセル１０のＰ型微結晶シリコン膜７の結晶化率が測定される（ステップＳ２４）。この結晶化率の測定結果は、製膜条件制御手段５０に送られる（ステップＳ４３）。 The product substrate on which the P-type microcrystalline silicon film 7 is formed is loaded on the arm of the transfer robot in the transfer chamber 30 and is vacuum transferred from the film forming chamber A to the film forming chamber B through the transfer chamber 30. At this time, the crystallization rate of the P-type microcrystalline silicon film 7 of the microcrystalline silicon cell 10 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30 ( Step S24). The measurement result of the crystallization rate is sent to the film forming condition control means 50 (step S43).
　製膜条件制御手段５０は、ステップＳ４４において、製品基板のＩ型微結晶シリコン膜８の製膜条件を決定し、この製膜条件のもとＩ型微結晶シリコン膜８の製膜がプラズマＣＶＤにより行なわれる（ステップＳ２５）（図２、ステップＳ８）。Ｉ型微結晶シリコン膜８の製膜条件は、結晶化率測定手段４０による微結晶シリコンセル１０のＰ型微結晶シリコン膜７の結晶化率測定の結果に応じて制御される。 In step S44, the film formation condition control means 50 determines the film formation conditions for the I-type microcrystalline silicon film 8 on the product substrate, and the film formation of the I-type microcrystalline silicon film 8 is performed by plasma CVD under the film formation conditions. (Step S25) (FIG. 2, step S8). The film forming conditions of the I-type microcrystalline silicon film 8 are controlled according to the result of the crystallization rate measurement of the P-type microcrystalline silicon film 7 of the microcrystalline silicon cell 10 by the crystallization rate measuring means 40.
　例えば、微結晶シリコンセル１０のＰ型微結晶シリコン膜７の結晶化率が通常より低いことが検知された場合は、この上に製膜するＩ型微結晶シリコン膜８の結晶化率が低下することが予想される。この場合、製膜条件制御手段５０は、通常よりも結晶化率が高くなる製膜条件を選択することにより、製品基板に製膜されるＩ型微結晶シリコン膜８の結晶化率をほぼ一定に保つことが可能となる。 For example, when it is detected that the crystallization rate of the P-type microcrystalline silicon film 7 of the microcrystalline silicon cell 10 is lower than usual, the crystallization rate of the I-type microcrystalline silicon film 8 formed thereon is lowered. Is expected to. In this case, the film forming condition control means 50 selects a film forming condition that causes the crystallization rate to be higher than usual so that the crystallization rate of the I-type microcrystalline silicon film 8 formed on the product substrate is substantially constant. It becomes possible to keep it.
　微結晶シリコンセル１０のＰ型微結晶シリコン膜７の結晶化率測定結果を基にして調整されるＩ型微結晶シリコン膜８の製膜パラメータとして、ＳｉＨ４流量、Ｈ２流量、製膜圧力および基板-電極間距離などがある。 The deposition parameters of the I-type microcrystalline silicon film 8 adjusted based on the crystallization rate measurement result of the P-type microcrystalline silicon film 7 of the microcrystalline silicon cell 10 are SiH 4 flow rate, H 2 flow rate, and deposition pressure. And substrate-electrode distance.
　製膜条件制御手段５０により決定された製膜条件によりＩ型微結晶シリコン膜８が形成された製品基板は、搬送室３０内の搬送ロボットのアームに積載され、製膜室Ｂから搬送室３０を経て、製膜室Ｃに真空搬送される。この際に、搬送室３０に設けられた結晶化率測定手段４０により、製品基板の最表面に形成された微結晶シリコンセル１０のＩ型微結晶シリコン膜８の結晶化率が測定される（ステップＳ２６）。この結晶化率の測定結果は、製膜条件制御手段５０に送られる（ステップＳ４５）。 The product substrate on which the I-type microcrystalline silicon film 8 is formed according to the film forming conditions determined by the film forming condition control means 50 is loaded on the arm of the transfer robot in the transfer chamber 30 and is transferred from the film forming chamber B to the transfer chamber 30. Then, the film is transferred to the film forming chamber C by vacuum. At this time, the crystallization rate of the I-type microcrystalline silicon film 8 of the microcrystalline silicon cell 10 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30 ( Step S26). The measurement result of the crystallization rate is sent to the film forming condition control means 50 (step S45).
　製膜条件制御手段５０は、ステップＳ４６において、製品基板のＮ型微結晶シリコン膜９の製膜条件を決定し、この製膜条件のもとＮ型微結晶シリコン膜９の製膜がプラズマＣＶＤにより行なわれる（ステップＳ２７）（図２、ステップＳ９）。Ｎ型微結晶シリコン膜９の製膜条件は、結晶化率測定手段４０による微結晶シリコンセル１０のＩ型微結晶シリコン膜８の結晶化率測定の結果に応じて制御される。 In step S46, the film-forming condition control means 50 determines the film-forming conditions for the N-type microcrystalline silicon film 9 on the product substrate, and the film-forming conditions for the N-type microcrystalline silicon film 9 are plasma CVD. (Step S27) (FIG. 2, step S9). The film forming conditions of the N-type microcrystalline silicon film 9 are controlled according to the result of the crystallization rate measurement of the I-type microcrystalline silicon film 8 of the microcrystalline silicon cell 10 by the crystallization rate measuring means 40.
　例えば、微結晶シリコンセル１０のＩ型微結晶シリコン膜８の結晶化率が通常より低いことが検知された場合は、この上に製膜するＮ型微結晶シリコン膜９の結晶化率が低下することが予想される。この場合、製膜条件制御手段５０は、通常よりも結晶化率が高くなる製膜条件を選択することにより、製品基板に製膜されるＮ型微結晶シリコン膜９の結晶化率をほぼ一定に保つことが可能となる。 For example, when it is detected that the crystallization rate of the I-type microcrystalline silicon film 8 of the microcrystalline silicon cell 10 is lower than usual, the crystallization rate of the N-type microcrystalline silicon film 9 formed thereon is lowered. Is expected to. In this case, the film forming condition control means 50 selects a film forming condition that causes the crystallization rate to be higher than usual so that the crystallization rate of the N-type microcrystalline silicon film 9 formed on the product substrate is substantially constant. It becomes possible to keep it.
　微結晶シリコンセル１０のＩ型微結晶シリコン膜８の結晶化率測定結果を基にして調整されるＮ型微結晶シリコン膜９の製膜パラメータとして、ＳｉＨ４流量、Ｈ２流量、製膜圧力および基板-電極間距離などがある。 The deposition parameters of the N-type microcrystalline silicon film 9 adjusted based on the crystallization rate measurement result of the I-type microcrystalline silicon film 8 of the microcrystalline silicon cell 10 are SiH 4 flow rate, H 2 flow rate, and deposition pressure. And substrate-electrode distance.
　製膜条件制御手段５０により決定された製膜条件によりＮ型微結晶シリコン膜９が形成された製品基板は、搬送室３０内の搬送ロボットのアームに積載され、製膜室Ｃから搬送室３０を経て（ステップＳ２８）、ロードロック室２０へ真空搬送される（ステップＳ２９）。製品基板がロードロック室２０に設置されると、搬送室３０との間のゲートバルブ６０が閉じ、ロードロック室２０内を大気開放する。このようにして微結晶シリコンセル１０が形成された製品基板は、ロードロック室２０から取り出され、図２のステップＳ１０以降の手順へ移行する。 The product substrate on which the N-type microcrystalline silicon film 9 is formed according to the film forming condition determined by the film forming condition control means 50 is loaded on the arm of the transfer robot in the transfer chamber 30 and is transferred from the film forming chamber C to the transfer chamber 30. (Step S28), and is vacuum-transferred to the load lock chamber 20 (Step S29). When the product substrate is installed in the load lock chamber 20, the gate valve 60 between the product lock chamber 20 and the transfer chamber 30 is closed, and the inside of the load lock chamber 20 is opened to the atmosphere. The product substrate on which the microcrystalline silicon cell 10 is formed in this way is taken out from the load lock chamber 20, and the process proceeds to the procedure after step S10 in FIG.
　このように、プラズマＣＶＤ装置１００内において、新たに微結晶シリコン膜を形成する直前に、その製膜の下地となる微結晶シリコン膜の結晶化率を結晶化率測定手段４０が測定する。そして、測定結果である下地膜の結晶化率に応じて、その上に製膜を行なう微結晶シリコン膜の結晶化率が一定となるように製膜条件制御手段５０が製膜条件を決定する。これにより、製膜を行なう微結晶シリコン膜の結晶化率を一定に保つことが可能となる。 Thus, in the plasma CVD apparatus 100, immediately before a new microcrystalline silicon film is formed, the crystallization rate measuring means 40 measures the crystallization rate of the microcrystalline silicon film that is the base of the film formation. Then, according to the crystallization rate of the base film, which is the measurement result, the film forming condition control means 50 determines the film forming conditions so that the crystallization rate of the microcrystalline silicon film to be formed thereon is constant. . As a result, the crystallization rate of the microcrystalline silicon film to be formed can be kept constant.
　さらに、上記プラズマＣＶＤの装置構成により、下地膜および製膜後の微結晶シリコン膜の結晶化率を測定する際に、製品基板をＣＶＤ装置から取り出す必要が無いため、製造スループットの向上が図れる。 Furthermore, with the plasma CVD apparatus configuration, it is not necessary to take out the product substrate from the CVD apparatus when measuring the crystallization rate of the base film and the microcrystalline silicon film after film formation, so that the manufacturing throughput can be improved.
　ここで、下地となる微結晶シリコン膜の結晶化率測定結果に応じて、その上に製膜を行なう微結晶シリコン膜の結晶化率が一定となるよう製膜条件を決定する方法の一例について説明する。 Here, an example of a method for determining the film-forming conditions so that the crystallization rate of the microcrystalline silicon film to be deposited thereon is constant according to the crystallization rate measurement result of the underlying microcrystalline silicon film explain.
　図５は、微結晶シリコン製膜時のＳｉＨ４流量をパラメータとして、下地の微結晶シリコン層の結晶化率と、この下地膜上にプラズマＣＶＤにより製膜した微結晶シリコン層の結晶化率の関係を模式的に示した図である。結晶化率の測定には顕微ラマン分光測定装置を用い、アモルファスシリコンのラマンシフト・ピークであるＩａ：４８０cm-1と結晶シリコンのラマンシフト・ピークであるＩｃ：５２０cm-1のピーク強度比（Ｉｃ/Ｉａ）を結晶化率と定義した。 FIG. 5 shows the crystallization rate of the underlying microcrystalline silicon layer and the crystallization rate of the microcrystalline silicon layer deposited by plasma CVD on the underlying film, using the SiH 4 flow rate during the microcrystalline silicon deposition as a parameter. It is the figure which showed the relationship typically. The crystallinity ratio was measured using a microscopic Raman spectroscopic measurement device, and the peak intensity ratio (Ic: 480 cm −1 of Raman shift peak of amorphous silicon and Ic: 520 cm −1 of Raman shift peak of crystalline silicon (Ic). / Ia) was defined as the crystallization rate.
　通常、下地膜の結晶化率はＩｃ/Ｉａ＝３程度であり、この上に微結晶シリコン膜を標準条件（ＳｉＨ４流量：５sccm（Standard　Cubic　Centimeter　per　Minute））で製膜した場合の結晶化率はＩｃ/Ｉａ＝５程度となる。しかし、下地膜の結晶化率が低い場合、この上に微結晶シリコン膜を標準条件（ＳｉＨ４流量：５sccm）で製膜すると結晶化率は低下する。このため、下地膜の結晶化率が通常よりも低いＩｃ/Ｉａ＝２であった場合、ＳｉＨ４流量を３sccmに減じた製膜条件を選択して微結晶シリコン膜を形成することで、製膜した微結晶シリコン膜の結晶化率を通常通り（Ｉｃ/Ｉａ～５）に保つことができる。 Usually, the crystallization rate of the underlying film is about Ic / Ia = 3, and a crystallization is performed when a microcrystalline silicon film is formed on this under standard conditions (SiH 4 flow rate: 5 sccm (Standard Cubic Centimeter per Minute)). The rate is about Ic / Ia = 5. However, in the case where the crystallization rate of the base film is low, the crystallization rate is lowered if a microcrystalline silicon film is formed thereon under standard conditions (SiH 4 flow rate: 5 sccm). For this reason, when the crystallization rate of the base film is Ic / Ia = 2, which is lower than usual, a film forming condition with the SiH 4 flow rate reduced to 3 sccm is selected to form a microcrystalline silicon film. The crystallinity of the formed microcrystalline silicon film can be maintained as usual (Ic / Ia˜5).
　一方、下地膜の結晶化率が高い場合、この上に微結晶シリコン膜を標準条件（ＳｉＨ４流量：５sccm）で製膜すると結晶化率は増加する。このため、下地膜の結晶化率が通常よりも高いＩｃ/Ｉａ＝４であった場合、ＳｉＨ４流量を７sccmに増加させた製膜条件を選択して微結晶シリコン膜を形成することで、製膜した微結晶シリコン膜の結晶化率を通常通り（Ｉｃ/Ｉａ～５）に保つことができる。 On the other hand, when the crystallization rate of the base film is high, the crystallization rate increases when a microcrystalline silicon film is formed thereon under standard conditions (SiH 4 flow rate: 5 sccm). For this reason, when the crystallization rate of the base film is Ic / Ia = 4, which is higher than usual, by selecting the film forming conditions in which the SiH 4 flow rate is increased to 7 sccm, the microcrystalline silicon film is formed. The crystallization rate of the formed microcrystalline silicon film can be maintained as usual (Ic / Ia˜5).
　以上説明したように、図５の関係を予めもとめた上で、製膜の下地となる微結晶シリコン層の結晶化率の測定結果に基づき、その上に製膜する微結晶シリコン膜の製膜条件を決定することで、製膜する微結晶シリコン膜の結晶化率を一定に保つことができる。言い換えると、製膜する微結晶シリコン膜に所望の結晶化率を与えるための製膜条件を決定することができる。これにより、薄膜シリコン太陽電池の製造の歩留まりを向上させることができる。 As described above, based on the measurement result of the crystallization rate of the microcrystalline silicon layer which is the base of the film formation, after obtaining the relationship of FIG. 5 in advance, the film formation of the microcrystalline silicon film to be formed thereon is performed. By determining the conditions, the crystallization rate of the microcrystalline silicon film to be formed can be kept constant. In other words, film forming conditions for giving a desired crystallization rate to the microcrystalline silicon film to be formed can be determined. Thereby, the manufacturing yield of the thin film silicon solar cell can be improved.
　なお、微結晶シリコン製膜時の結晶化率を制御する製膜パラメータとしてはＳｉＨ４流量に限らず、製膜圧力、ＲＦ電力、Ｈ２流量、基板-電極間距離などがあり、これらの製膜パラメータそれぞれを、またはこれらを複数組み合わせて制御しても構わない。 The deposition parameters for controlling the crystallization rate during the microcrystalline silicon deposition are not limited to the SiH 4 flow rate, but include the deposition pressure, RF power, H 2 flow rate, substrate-electrode distance, and the like. You may control each film | membrane parameter or combining these two or more.
　微結晶シリコン膜の結晶化率測定においては、製品基板が搬送室３０の搬送ロボットのアーム上に積載された状態で、搬送ロボットを移動させながら結晶化率の測定を行なうことで、結晶化率の基板面内分布を測定することができる。 In the measurement of the crystallization rate of the microcrystalline silicon film, the crystallization rate is measured by moving the transfer robot while the product substrate is loaded on the arm of the transfer robot in the transfer chamber 30. Can be measured.
　上記実施の形態においては、Ｐ型、Ｉ型、Ｎ型微結晶シリコン膜それぞれの製膜前に下地膜の結晶化率を測定する場合について説明したが、必ずしも全ての微結晶シリコン膜の製膜前に結晶化率測定を行なう必要はない。少なくとも、微結晶シリコンセルの特性に大きな影響を及ぼすＩ型微結晶シリコン膜８の製膜前に行なうことが望ましい。 In the above embodiment, the case where the crystallization rate of the base film is measured before the deposition of each of the P-type, I-type, and N-type microcrystalline silicon films has been described. However, the deposition of all the microcrystalline silicon films is not necessarily performed. There is no need to measure the crystallization rate in advance. It is desirable to carry out at least before forming the I-type microcrystalline silicon film 8 which has a great influence on the characteristics of the microcrystalline silicon cell.
　また上記実施の形態においては、微結晶シリコンセル１０の製造方法を例に説明したが、これに限定されるものではない。例えば、微結晶シリコン酸化膜セル、微結晶シリコンカーバイドセル、微結晶シリコンゲルマニュウムセルなど、微結晶シリコン成分を含む膜をプラズマＣＶＤ法により形成する場合においても、上記実施の形態と同様な製造方法により同様の効果を得ることができる。 In the above embodiment, the method for manufacturing the microcrystalline silicon cell 10 has been described as an example, but the present invention is not limited to this. For example, even when a film containing a microcrystalline silicon component, such as a microcrystalline silicon oxide film cell, a microcrystalline silicon carbide cell, or a microcrystalline silicon germanium cell, is formed by a plasma CVD method, the manufacturing method similar to the above embodiment is used. Similar effects can be obtained.
　本実施の形態においては、図１に示した薄膜シリコン太陽電池の製造方法を例に説明したが、図６に示したアモルファスシリコンセル上に中間層として微結晶シリコン酸化膜を形成したタンデム型薄膜シリコン太陽電池などのセル構造でも同様の効果を得ることができる。 In the present embodiment, the method for manufacturing the thin film silicon solar cell shown in FIG. 1 has been described as an example. However, a tandem thin film in which a microcrystalline silicon oxide film is formed as an intermediate layer on the amorphous silicon cell shown in FIG. Similar effects can be obtained with a cell structure such as a silicon solar cell.
　図６の２層タンデム型薄膜シリコン太陽電池においては、アモルファスシリコンセル６と微結晶シリコンセル１０との間に中間層として微結晶シリコン酸化膜１３が挿入されている。この構造は、アモルファスシリコンセル６で吸収しきれなかった入射光を微結晶シリコン酸化膜１３により再度アモルファスシリコンセル６側に反射させることでアモルファスシリコンセル６の高効率化を図っている。 6, a microcrystalline silicon oxide film 13 is inserted as an intermediate layer between the amorphous silicon cell 6 and the microcrystalline silicon cell 10 in the two-layer tandem thin film silicon solar cell. In this structure, incident light that could not be absorbed by the amorphous silicon cell 6 is reflected again to the amorphous silicon cell 6 side by the microcrystalline silicon oxide film 13, thereby improving the efficiency of the amorphous silicon cell 6.
　本実施の形態においては、結晶化率測定手段４０を搬送室３０に設置した場合について述べたが、ロードロック室２０に設置しても良い。この場合、ロードロック室２０を真空引きや大気開放する際に、並行して結晶化率を測定することができるため、薄膜シリコン太陽電池の製造スループットを向上させることができる。 In the present embodiment, the case where the crystallization rate measuring means 40 is installed in the transfer chamber 30 has been described, but it may be installed in the load lock chamber 20. In this case, since the crystallization rate can be measured in parallel when the load lock chamber 20 is evacuated or opened to the atmosphere, the manufacturing throughput of the thin-film silicon solar cell can be improved.
実施の形態２．
　本発明の実施の形態２にかかる薄膜シリコン太陽電池の製造方法および製造装置で製造するアモルファスシリコンと微結晶シリコンを発電層に用いた２層タンデム型薄膜シリコン太陽電池の断面構造も図１と同様である。また、本実施の形態に係る薄膜シリコン太陽電池の製造方法により２層タンデム型薄膜シリコン太陽電池を製造する手順を説明するフローチャートも図２と同様である。 Embodiment 2. FIG.
The cross-sectional structure of a two-layer tandem-type thin-film silicon solar cell using amorphous silicon and microcrystalline silicon manufactured by the method and apparatus for manufacturing a thin-film silicon solar cell according to Embodiment 2 of the present invention as the power generation layer is the same as in FIG. It is. Moreover, the flowchart explaining the procedure which manufactures the 2 layer tandem-type thin film silicon solar cell with the manufacturing method of the thin film silicon solar cell which concerns on this Embodiment is also the same as that of FIG.
　図７は、本実施の形態に係る微結晶シリコンセル製膜用のプラズマＣＶＤ装置２００の概略構成を示すブロック図である。プラズマＣＶＤ装置２００において、図２のステップＳ７、Ｓ８、Ｓ９が実行される。本実施の形態で使用するプラズマＣＶＤ装置２００は、マルチチャンバ方式を採用するプラズマＣＶＤ装置である。本プラズマＣＶＤ装置は、ロードロック室２０、搬送室３０および三つの製膜室Ａ、Ｂ、Ｃを備える。ロードロック室２０および製膜室Ａ、Ｂ、Ｃは、搬送室３０の周囲に設けられている。 FIG. 7 is a block diagram showing a schematic configuration of a plasma CVD apparatus 200 for forming a microcrystalline silicon cell according to the present embodiment. In the plasma CVD apparatus 200, steps S7, S8, and S9 in FIG. 2 are executed. The plasma CVD apparatus 200 used in this embodiment is a plasma CVD apparatus that employs a multi-chamber system. This plasma CVD apparatus includes a load lock chamber 20, a transfer chamber 30, and three film forming chambers A, B, and C. The load lock chamber 20 and the film forming chambers A, B, and C are provided around the transfer chamber 30.
　製膜室Ａは、Ｐ型微結晶シリコン膜７の製膜のための製膜室である。製膜室Ｂは、Ｉ型微結晶シリコン膜８の製膜のための製膜室である。製膜室Ｃは、Ｎ型微結晶シリコン膜９の製膜のための製膜室である。製膜室Ａ、Ｂ、Ｃは、それぞれゲートバルブを介して搬送室に接続されている。 The film forming chamber A is a film forming chamber for forming the P-type microcrystalline silicon film 7. The film forming chamber B is a film forming chamber for forming the I-type microcrystalline silicon film 8. The film forming chamber C is a film forming chamber for forming the N-type microcrystalline silicon film 9. The film forming chambers A, B, and C are each connected to a transfer chamber via a gate valve.
　搬送室３０は、ロードロック室２０、製膜室Ａ、Ｂ、Ｃの間で基板を搬送するためのスペースである。搬送室３０には、真空中で動作可能な搬送ロボット（図示せず）と製品基板上の微結晶シリコン膜の結晶化率を測定するための結晶化率測定手段４０および製品基板の基板温度を測定するための基板温度測定手段４１が設けられている。基板温度測定手段４１は搬送室３０の搬送ロボットに設けられていてもよい。 The transfer chamber 30 is a space for transferring a substrate between the load lock chamber 20 and the film forming chambers A, B, and C. The transfer chamber 30 includes a transfer robot (not shown) operable in vacuum, a crystallization rate measuring means 40 for measuring the crystallization rate of the microcrystalline silicon film on the product substrate, and the substrate temperature of the product substrate. Substrate temperature measuring means 41 for measuring is provided. The substrate temperature measuring means 41 may be provided in the transfer robot in the transfer chamber 30.
　搬送ロボットは、搬送室３０とロードロック室２０、製膜室Ａ、Ｂ、Ｃとの間で製品基板を搬送する。結晶化率測定手段４０は、ラマン分光法を用いた顕微レーザーラマン分光装置を用いることができ、基板温度測定手段４１は、熱電対による温度測定手段を用いることができる。結晶化率測定手段４０および基板温度測定手段４１で測定した結晶化率測定結果および温度測定結果は、各製膜室の製膜条件および基板昇温時間を制御する製膜条件および基板昇温時間制御手段５１に送られる。ロードロック室２０は、搬送室３０への製品基板の搬入および取り出しのためのスペースである。ロードロック室２０は、ゲートバルブ６０を介して搬送室３０に接続されている。 The transfer robot transfers the product substrate between the transfer chamber 30, the load lock chamber 20, and the film forming chambers A, B, and C. As the crystallization rate measuring means 40, a microscopic laser Raman spectroscopic apparatus using Raman spectroscopy can be used, and as the substrate temperature measuring means 41, a temperature measuring means using a thermocouple can be used. The crystallization rate measurement result and the temperature measurement result measured by the crystallization rate measuring means 40 and the substrate temperature measuring means 41 are the film forming conditions and substrate heating time for controlling the film forming conditions and the substrate heating time in each film forming chamber. It is sent to the control means 51. The load lock chamber 20 is a space for carrying the product substrate into and out of the transfer chamber 30. The load lock chamber 20 is connected to the transfer chamber 30 via the gate valve 60.
　図８は、本実施の形態に係るプラズマＣＶＤ装置２００における製品基板の搬送手順を説明するフロー図である。以下、図２に示す手順とともに、製品基板の搬送手順を説明する。 FIG. 8 is a flowchart for explaining the transport procedure of the product substrate in the plasma CVD apparatus 200 according to the present embodiment. Hereinafter, the procedure for conveying the product substrate will be described together with the procedure shown in FIG.
　透明導電膜２が製膜され（図２、ステップＳ２）、レーザースクライブ（ステップＳ３）、アモルファスシリコンセル６の形成工程（ステップＳ４～Ｓ６）を経た製品基板は、ロードロック室２０内に設置される（図８、ステップＳ５１）。ロードロック室２０内に製品基板が設置されると、ロードロック室２０内を真空排気する。 The transparent conductive film 2 is formed (FIG. 2, step S2), the laser scribe (step S3), and the product substrate that has undergone the process of forming the amorphous silicon cell 6 (steps S4 to S6) is placed in the load lock chamber 20. (FIG. 8, step S51). When the product substrate is installed in the load lock chamber 20, the load lock chamber 20 is evacuated.
　ロードロック室２０を真空排気した後、ロードロック室２０と搬送室３０間のゲートバルブ６０が開かれる。ロードロック室２０内の製品基板は、搬送室３０内の搬送ロボットのアームに積載され、ロードロック室２０から搬送室３０を経て、製膜室Ａに真空搬送される。この際に、搬送室３０に設けられた結晶化率測定手段４０により、製品基板の最表面に形成されたアモルファスシリコンセル６のＮ型微結晶シリコン膜５の結晶化率が測定され、さらに、搬送室３０の搬送ロボットに設けられた基板温度測定手段４１により基板温度が測定される（ステップＳ５２）。この結晶化率と基板温度の測定結果は、製膜条件および基板昇温時間制御手段５１に送られる（ステップＳ６１）。 After the load lock chamber 20 is evacuated, the gate valve 60 between the load lock chamber 20 and the transfer chamber 30 is opened. The product substrate in the load lock chamber 20 is loaded on the arm of a transfer robot in the transfer chamber 30 and is vacuum transferred from the load lock chamber 20 to the film forming chamber A through the transfer chamber 30. At this time, the crystallization rate of the N-type microcrystalline silicon film 5 of the amorphous silicon cell 6 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30. The substrate temperature is measured by the substrate temperature measuring means 41 provided in the transfer robot in the transfer chamber 30 (step S52). The measurement results of the crystallization rate and the substrate temperature are sent to the film forming conditions and the substrate heating time control means 51 (step S61).
　製膜条件および基板昇温時間制御手段５１は、ステップＳ６２において、Ｐ型微結晶シリコン膜７の製膜前に行なわれる基板昇温時間およびＰ型微結晶シリコン膜７の製膜条件を決定し、この基板昇温時間の間、基板を加熱した後にこの製膜条件のもとＰ型微結晶シリコン膜７の製膜がプラズマＣＶＤにより行なわれる（ステップＳ５３）（図２、ステップＳ７）。Ｐ型微結晶シリコン膜７の製膜条件は実施の形態１と同様な方法で決定され、Ｐ型微結晶シリコン膜７製膜前の基板昇温時間は、基板温度測定手段４１による製膜室Ａに搬送される直前の基板温度測定の結果に応じて制御される。 In step S62, the film forming conditions and the substrate temperature raising time control means 51 determine the substrate temperature raising time and the film forming conditions of the P type microcrystalline silicon film 7 performed before the formation of the P type microcrystalline silicon film 7. During the substrate heating time, after the substrate is heated, the P-type microcrystalline silicon film 7 is formed by plasma CVD under the film forming conditions (step S53) (FIG. 2, step S7). The film forming conditions for the P-type microcrystalline silicon film 7 are determined by the same method as in the first embodiment, and the substrate heating time before forming the P-type microcrystalline silicon film 7 is the film forming chamber by the substrate temperature measuring means 41. Control is performed according to the result of the substrate temperature measurement immediately before being transferred to A.
　例えば、製膜室Ａに搬送される直前の基板温度が通常よりも高いことが検知された場合は、Ｐ型微結晶シリコン膜７製膜前の基板昇温は、通常の昇温時間よりも短時間で所定の温度に達することが予想される。この場合、製膜条件および基板昇温時間制御手段５１は、通常よりも基板昇温時間を短く設定することにより、Ｐ型微結晶シリコン膜７製膜前の基板昇温時間を短縮できスループットの向上を図ることが可能となる。 For example, when it is detected that the substrate temperature immediately before being transferred to the film forming chamber A is higher than usual, the substrate temperature rise before the P-type microcrystalline silicon film 7 is formed is longer than the normal temperature raising time. It is expected to reach a predetermined temperature in a short time. In this case, the film formation conditions and the substrate temperature increase time control means 51 can shorten the substrate temperature increase time before the formation of the P-type microcrystalline silicon film 7 by setting the substrate temperature increase time shorter than usual. It is possible to improve.
　一方、製膜室Ａに搬送される直前の基板温度が通常よりも低いことが検知された場合は、Ｐ型微結晶シリコン膜７製膜前の基板昇温は、通常の昇温時間では基板が十分に昇温されないことが予想される。この場合、製膜条件および基板昇温時間制御手段５１は、通常よりも基板昇温時間を長く設定することにより、Ｐ型微結晶シリコン膜７製膜前の基板温度を所望の温度に昇温することができ、Ｐ型微結晶シリコン膜７の結晶化率のばらつきを抑制することが可能となる。 On the other hand, when it is detected that the substrate temperature immediately before being transferred to the film forming chamber A is lower than usual, the substrate temperature rise before the P-type microcrystalline silicon film 7 is formed is the substrate during the normal temperature raising time. Is not expected to rise sufficiently. In this case, the film formation conditions and the substrate temperature increase time control means 51 increase the substrate temperature before forming the P-type microcrystalline silicon film 7 to a desired temperature by setting the substrate temperature increase time longer than usual. It is possible to suppress variation in the crystallization rate of the P-type microcrystalline silicon film 7.
　Ｐ型微結晶シリコン膜７が形成された製品基板は、搬送室３０内の搬送ロボットのアームに積載され、製膜室Ａから搬送室３０を経て製膜室Ｂに真空搬送される。この際に、搬送室３０に設けられた結晶化率測定手段４０により、製品基板の最表面に形成された微結晶シリコンセル１０のＰ型微結晶シリコン膜７の結晶化率が測定され、さらに、搬送室３０の搬送ロボットに設けられた基板温度測定手段４１により基板温度が測定される（ステップＳ５４）。この結晶化率と基板温度の測定結果は、製膜条件および基板昇温時間制御手段５１に送られる（ステップＳ６３）。 The product substrate on which the P-type microcrystalline silicon film 7 is formed is loaded on the arm of the transfer robot in the transfer chamber 30 and is vacuum transferred from the film forming chamber A to the film forming chamber B through the transfer chamber 30. At this time, the crystallization rate of the P-type microcrystalline silicon film 7 of the microcrystalline silicon cell 10 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30. The substrate temperature is measured by the substrate temperature measuring means 41 provided in the transfer robot in the transfer chamber 30 (step S54). The measurement results of the crystallization rate and the substrate temperature are sent to the film forming conditions and the substrate heating time control means 51 (step S63).
　製膜条件および基板昇温時間制御手段５１は、ステップＳ６４において、Ｉ型微結晶シリコン膜８の製膜前に行なわれる基板昇温時間およびＩ型微結晶シリコン膜８の製膜条件を決定する。この基板昇温時間の間、基板は加熱され、その後にこの製膜条件のもとＩ型微結晶シリコン膜８の製膜がプラズマＣＶＤにより行なわれる（ステップＳ５５）（図２、ステップＳ８）。Ｉ型微結晶シリコン膜８の製膜条件は実施の形態１と同様な方法で決定され、Ｉ型微結晶シリコン膜８製膜前の基板昇温時間は、基板温度測定手段４１による製膜室Ｂに搬送される直前の基板温度測定の結果に応じて制御される。 The film forming conditions and substrate heating time control means 51 determine the substrate heating time and the film forming conditions for the I-type microcrystalline silicon film 8 that are performed before forming the I-type microcrystalline silicon film 8 in step S64. . During this substrate heating time, the substrate is heated, and then the I-type microcrystalline silicon film 8 is formed by plasma CVD under the film forming conditions (step S55) (FIG. 2, step S8). The film forming conditions of the I-type microcrystalline silicon film 8 are determined by the same method as in the first embodiment, and the substrate heating time before forming the I-type microcrystalline silicon film 8 is the film forming chamber by the substrate temperature measuring means 41. Control is performed according to the result of the substrate temperature measurement immediately before being transferred to B.
　例えば、製膜室Ｂに搬送される直前の基板温度が通常よりも高いことが検知された場合は、Ｉ型微結晶シリコン膜８製膜前の基板昇温は、通常の昇温時間よりも短時間で所定の温度に達することが予想される。この場合、製膜条件および基板昇温時間制御手段５１は、通常よりも基板昇温時間を短く設定することにより、Ｉ型微結晶シリコン膜８製膜前の基板昇温時間を短縮できスループットの向上を図ることが可能となる。 For example, when it is detected that the substrate temperature immediately before being transferred to the film forming chamber B is higher than usual, the substrate temperature rise before the I-type microcrystalline silicon film 8 is formed is longer than the normal temperature raising time. It is expected to reach a predetermined temperature in a short time. In this case, the film formation conditions and the substrate temperature increase time control means 51 can shorten the substrate temperature increase time before the formation of the I-type microcrystalline silicon film 8 by setting the substrate temperature increase time shorter than usual. It is possible to improve.
　一方、製膜室Ｂに搬送される直前の基板温度が通常よりも低いことが検知された場合は、Ｉ型微結晶シリコン膜８製膜前の基板昇温は、通常の昇温時間では基板が十分に昇温されないことが予想される。この場合、製膜条件および基板昇温時間制御手段５１は、通常よりも基板昇温時間を長く設定することにより、Ｉ型微結晶シリコン膜８製膜前の基板温度を所望の温度に昇温することができ、Ｉ型微結晶シリコン膜８の結晶化率のばらつきを抑制することが可能となる。 On the other hand, when it is detected that the substrate temperature immediately before being transferred to the film forming chamber B is lower than usual, the substrate temperature rise before the formation of the I-type microcrystalline silicon film 8 is the substrate during the normal temperature rising time. Is not expected to rise sufficiently. In this case, the film formation conditions and the substrate temperature increase time control means 51 increase the substrate temperature before forming the I-type microcrystalline silicon film 8 to a desired temperature by setting the substrate temperature increase time longer than usual. Therefore, it is possible to suppress variation in the crystallization rate of the I-type microcrystalline silicon film 8.
　製膜条件および基板昇温時間制御手段５１が決定した製膜条件によりＩ型微結晶シリコン膜８が形成された製品基板は、搬送室３０内の搬送ロボットのアームに積載され、製膜室Ｂから搬送室３０を経て製膜室Ｃに真空搬送される。この際に、搬送室３０に設けられた結晶化率測定手段４０により、製品基板の最表面に形成された微結晶シリコンセル１０のＩ型微結晶シリコン膜８の結晶化率が測定され、さらに、搬送室３０の搬送ロボットに設けられた基板温度測定手段４１により、基板温度が測定される（ステップＳ５６）。この結晶化率と基板温度の測定結果は、製膜条件および基板昇温時間制御手段５１に送られる（ステップＳ６５）。 The product substrate on which the I-type microcrystalline silicon film 8 is formed according to the film forming conditions and the film forming conditions determined by the substrate heating time control means 51 is loaded on the arm of the transfer robot in the transfer chamber 30 and the film forming chamber B Is transferred to the film forming chamber C through the transfer chamber 30. At this time, the crystallization rate of the I-type microcrystalline silicon film 8 of the microcrystalline silicon cell 10 formed on the outermost surface of the product substrate is measured by the crystallization rate measuring means 40 provided in the transfer chamber 30. The substrate temperature is measured by the substrate temperature measuring means 41 provided in the transfer robot in the transfer chamber 30 (step S56). The measurement results of the crystallization rate and the substrate temperature are sent to the film forming conditions and the substrate heating time control means 51 (step S65).
　製膜条件および基板昇温時間制御手段５１は、ステップＳ６６において、Ｎ型微結晶シリコン膜９の製膜前に行なわれる基板昇温時間およびＮ型微結晶シリコン膜９の製膜条件を決定する。この基板昇温時間の間、基板は加熱され、その後にこの製膜条件のもとＮ型微結晶シリコン膜９の製膜がプラズマＣＶＤにより行なわれる（ステップＳ５７）（図２、ステップＳ９）。Ｎ型微結晶シリコン膜９の製膜条件は実施の形態１と同様な方法で決定され、Ｎ型微結晶シリコン膜９製膜前の基板昇温時間は、基板温度測定手段４１による製膜室Ｃに搬送される直前の基板温度測定の結果に応じて制御される。 The film forming conditions and substrate heating time control means 51 determine the substrate heating time and the film forming conditions for the N-type microcrystalline silicon film 9 that are performed before forming the N-type microcrystalline silicon film 9 in step S66. . During this substrate heating time, the substrate is heated, and thereafter the N-type microcrystalline silicon film 9 is formed by plasma CVD under the film forming conditions (step S57) (FIG. 2, step S9). The film forming conditions for the N-type microcrystalline silicon film 9 are determined by the same method as in the first embodiment, and the substrate heating time before forming the N-type microcrystalline silicon film 9 is the film forming chamber by the substrate temperature measuring means 41. It is controlled according to the result of the substrate temperature measurement immediately before being transferred to C.
　例えば、製膜室Ｃに搬送される直前の基板温度が通常よりも高いことが検知された場合は、Ｎ型微結晶シリコン膜９製膜前の基板昇温は、通常の昇温時間よりも短時間で所定の温度に達することが予想される。この場合、製膜条件および基板昇温時間制御手段５１は、通常よりも基板昇温時間を短く設定することにより、Ｎ型微結晶シリコン膜９製膜前の基板昇温時間を短縮できスループットの向上を図ることが可能となる。 For example, when it is detected that the substrate temperature immediately before being transferred to the film forming chamber C is higher than usual, the substrate temperature rise before the N-type microcrystalline silicon film 9 is formed is longer than the normal temperature raising time. It is expected to reach a predetermined temperature in a short time. In this case, the film formation conditions and the substrate temperature increase time control means 51 can shorten the substrate temperature increase time before forming the N-type microcrystalline silicon film 9 by setting the substrate temperature increase time shorter than usual. It is possible to improve.
　一方、製膜室Ｃに搬送される直前の基板温度が通常よりも低いことが検知された場合は、Ｎ型微結晶シリコン膜９製膜前の基板昇温は、通常の昇温時間では基板が十分に昇温されないことが予想される。この場合、製膜条件および基板昇温時間制御手段５１は、通常よりも基板昇温時間を長く設定することにより、Ｎ型微結晶シリコン膜９製膜前の基板温度を所望の温度に昇温することができ、Ｎ型微結晶シリコン膜９の結晶化率のばらつきを抑制することが可能となる。 On the other hand, when it is detected that the substrate temperature immediately before being transferred to the film forming chamber C is lower than usual, the substrate temperature rise before the N-type microcrystalline silicon film 9 is formed is the substrate during the normal temperature raising time. Is not expected to rise sufficiently. In this case, the film formation conditions and the substrate temperature increase time control means 51 increase the substrate temperature before forming the N-type microcrystalline silicon film 9 to a desired temperature by setting the substrate temperature increase time longer than usual. Thus, variation in the crystallization rate of the N-type microcrystalline silicon film 9 can be suppressed.
　製膜条件および基板昇温時間制御手段５１が決定した製膜条件によりＮ型微結晶シリコン膜９が形成された製品基板は、搬送室３０内の搬送ロボットのアームに積載され、製膜室Ｃから搬送室３０を経て（ステップＳ５８）、ロードロック室２０へ真空搬送される（ステップＳ５９）。製品基板がロードロック室２０に設置されると、搬送室３０との間のゲートバルブ６０が閉じ、ロードロック室２０内を大気開放する。このようにして微結晶シリコンセル１０が形成された製品基板は、ロードロック室２０から取り出され、図２のステップＳ１０以降の手順へ移行する。 The product substrate on which the N-type microcrystalline silicon film 9 is formed according to the film forming conditions and the film forming conditions determined by the substrate heating time control means 51 is loaded on the arm of the transfer robot in the transfer chamber 30 and is formed into the film forming chamber C. Then, through the transfer chamber 30 (step S58), it is vacuum transferred to the load lock chamber 20 (step S59). When the product substrate is installed in the load lock chamber 20, the gate valve 60 between the product lock chamber 20 and the transfer chamber 30 is closed, and the inside of the load lock chamber 20 is opened to the atmosphere. The product substrate on which the microcrystalline silicon cell 10 is formed in this way is taken out from the load lock chamber 20, and the process proceeds to the procedure after step S10 in FIG.
　このように、プラズマＣＶＤ装置２００内において、新たに微結晶シリコン膜を形成する前に、その製膜の下地となる微結晶シリコン膜の結晶化率を結晶化率測定手段４０が測定すると共に、基板の温度を基板温度測定手段４１が測定する。また、測定結果である基板温度に応じて、その上に別の微結晶シリコン膜を形成する前に行なう基板昇温ステップにおける基板昇温時間を決定すると共に、測定結果である下地膜の結晶化率に応じて、その上に製膜を行なう別の微結晶シリコン膜の結晶化率が一定となるように製膜条件を決定する。これにより、基板の昇温が必要最低限に抑えられると共に、製膜を行う微結晶シリコン膜の結晶化率を一定に保つことが可能となる。 As described above, in the plasma CVD apparatus 200, before forming a new microcrystalline silicon film, the crystallization rate measuring means 40 measures the crystallization rate of the microcrystalline silicon film that is the base of the film formation, The substrate temperature measuring means 41 measures the temperature of the substrate. Further, according to the substrate temperature as a measurement result, the substrate heating time in the substrate heating step to be performed before forming another microcrystalline silicon film on the substrate is determined, and crystallization of the base film as the measurement result is performed. Depending on the rate, the film forming conditions are determined so that the crystallization rate of another microcrystalline silicon film to be formed thereon is constant. Accordingly, the temperature rise of the substrate can be suppressed to the minimum necessary, and the crystallization rate of the microcrystalline silicon film to be formed can be kept constant.
　ここで、製膜前の基板温度測定結果に応じて、その上に微結晶シリコンの製膜を行なう前の基板昇温時間を決定する方法の一例について説明する。 Here, an example of a method for determining the substrate heating time before forming the microcrystalline silicon film thereon according to the substrate temperature measurement result before forming the film will be described.
　図９は、基板昇温時間とステージヒータ上に積載した基板温度との関係を模式的に示した図である。ステージヒータ上に積載した基板の温度は、時間と共に上昇してステージヒータ温度で飽和する。図９に示されるように、製膜室導入前の基板温度（初期基板温度Ｔｓ）がステージヒータ温度より低いほど、基板温度がステージヒータ温度に到達するまでの基板昇温時間Ｔが長くなることがわかる。通常は、想定される最も低い初期基板温度Ｔｓ（例えばＴｓ１）を基に長い基板昇温時間Ｔ（ここではＴ１）を設定していた。 FIG. 9 is a diagram schematically showing the relationship between the substrate heating time and the temperature of the substrate loaded on the stage heater. The temperature of the substrate loaded on the stage heater rises with time and saturates at the stage heater temperature. As shown in FIG. 9, the substrate temperature rise time T until the substrate temperature reaches the stage heater temperature becomes longer as the substrate temperature (initial substrate temperature Ts) before introduction of the film forming chamber is lower than the stage heater temperature. I understand. Usually, a long substrate heating time T (here, T1) is set based on the lowest assumed initial substrate temperature Ts (for example, Ts1).
　しかし上記実施の形態に示した基板昇温ステップの方法を用いることで、製膜室導入前の初期基板温度Ｔｓを測定して初期基板温度が（Ｔｓ１より高い）Ｔｓ２であった場合は基板昇温時間をＴ２へと短縮でき、初期基板温度が（Ｔｓ２より高い）Ｔｓ３であった場合は基板昇温時間をＴ３へとさらに短縮することができる。これにより、製膜時の基板温度を一定に保ちつつ基板昇温時間を短縮することができるので、スループットの向上を図ることができる。 However, by using the substrate heating step method described in the above embodiment, the initial substrate temperature Ts before introduction of the film forming chamber is measured, and if the initial substrate temperature is Ts2 (higher than Ts1), the substrate temperature rises. The warming time can be shortened to T2, and when the initial substrate temperature is Ts3 (which is higher than Ts2), the substrate warming time can be further shortened to T3. Thereby, since the substrate heating time can be shortened while keeping the substrate temperature during film formation constant, the throughput can be improved.
　なお、製膜前の基板温度測定手段４１としては、搬送ロボットに熱電対など接触式の温度計を設置することにより実現可能である。これにより簡便に基板温度を測定することができる。また、この他に、放射型温度計などの非接触式の基板温度測定手段４１を用いても良い。この場合、非接触式の温度測定手段を搬送室に固定し、製品基板が搬送室３０の搬送ロボットのアーム上に積載された状態で、搬送ロボットを移動させながら基板温度の測定を行なうことで、基板温度の基板面内分布を測定することができる。また、これらの基板温度測定手段４１は搬送室３０に限ることなく、ロードロック室２０に設けることも可能である。 The substrate temperature measuring means 41 before film formation can be realized by installing a contact-type thermometer such as a thermocouple in the transfer robot. Thereby, the substrate temperature can be easily measured. In addition, non-contact type substrate temperature measuring means 41 such as a radiation thermometer may be used. In this case, a non-contact temperature measuring means is fixed to the transfer chamber, and the substrate temperature is measured while moving the transfer robot while the product substrate is loaded on the arm of the transfer robot in the transfer chamber 30. The substrate in-plane distribution of the substrate temperature can be measured. Further, the substrate temperature measuring means 41 is not limited to the transfer chamber 30 and can be provided in the load lock chamber 20.
　また、上記実施の形態１および２では、微結晶シリコン膜を形成するＣＶＤ装置としてはプラズマＣＶＤ装置を例に説明したが、ＣＶＤの方式としてはこれに限定されず、ホットワイヤーＣＶＤ等の他の方式のＣＶＤでも同様の効果を得ることができる。 In the first and second embodiments, the plasma CVD apparatus is described as an example of the CVD apparatus for forming the microcrystalline silicon film. However, the CVD method is not limited to this, and other methods such as hot wire CVD are used. The same effect can be obtained even by the CVD method.
　さらに、本願発明は上記実施の形態に限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で種々に変形することが可能である。また、上記実施の形態には種々の段階の発明が含まれており、開示される複数の構成要件における適宜な組み合わせにより種々の発明が抽出されうる。例えば、実施の形態に示される全構成要件からいくつかの構成要件が削除されても、発明が解決しようとする課題の欄で述べた課題が解決でき、発明の効果の欄で述べられている効果が得られる場合には、この構成要件が削除された構成が発明として抽出されうる。更に、異なる実施の形態にわたる構成要素を適宜組み合わせてもよい。 Furthermore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent requirements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When an effect is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention. Furthermore, the constituent elements over different embodiments may be appropriately combined.
　以上のように、本発明にかかる薄膜シリコン太陽電池の製造方法および製造装置は、微結晶シリコン成分を含む層をプラズマＣＶＤ法により形成する場合に有用であり、特に、微結晶シリコン膜の結晶化率の制御による製造スループット及び歩留まりの向上に適している。 As described above, the method and apparatus for manufacturing a thin-film silicon solar cell according to the present invention are useful when a layer containing a microcrystalline silicon component is formed by a plasma CVD method, and in particular, crystallization of a microcrystalline silicon film. It is suitable for improving the production throughput and yield by controlling the rate.
　１　ガラス基板
　２　透明導電膜
　３　Ｐ型アモルファスシリコン膜
　４　Ｉ型アモルファスシリコン膜
　５　Ｎ型微結晶シリコン膜
　６　アモルファスシリコンセル
　７　Ｐ型微結晶シリコン膜
　８　Ｉ型微結晶シリコン膜
　９　Ｎ型微結晶シリコン膜
　１０　微結晶シリコンセル
　１１　第２の透明導電膜（光閉じ込め層）
　１２　金属電極膜
　１３　微結晶シリコン酸化膜（中間層）
　２０　ロードロック室
　３０　搬送室
　４０　結晶化率測定手段
　４１　基板温度測定手段
　５０　製膜条件制御手段
　５１　製膜条件および基板昇温時間制御手段
　６０　ゲートバルブ
　１００、２００　プラズマＣＶＤ装置
　Ｓ１～Ｓ１５、Ｓ２１～Ｓ２９、Ｓ４１～Ｓ４６、Ｓ５１～Ｓ５９、Ｓ６１～Ｓ６６　ステップ 1 Glass substrate 2 Transparent conductive film 3 P-type amorphous silicon film 4 I-type amorphous silicon film 5 N-type microcrystalline silicon film 6 Amorphous silicon cell 7 P-type microcrystalline silicon film 8 I-type microcrystalline silicon film 9 N-type microcrystalline silicon Film 10 Microcrystalline silicon cell 11 Second transparent conductive film (light confinement layer)
12 Metal electrode film 13 Microcrystalline silicon oxide film (intermediate layer)
20 Load lock chamber 30 Transfer chamber 40 Crystallization rate measuring means 41 Substrate temperature measuring means 50 Film forming condition control means 51 Film forming conditions and substrate heating time control means 60 Gate valve 100, 200 Plasma CVD apparatus S1 to S15, S21 to Steps S29, S41 to S46, S51 to S59, S61 to S66

Claims (14)

  1. 　基板の上にＣＶＤによって製膜された下地膜となる微結晶シリコン成分を含む膜の結晶化率を測定する測定工程と、
    　前記下地膜の結晶化率と当該下地膜の上に製膜する条件と当該条件のもと当該下地膜の上にＣＶＤにより製膜された微結晶シリコン成分を含む膜の結晶化率との予め求めておいた関係に基づいて、前記測定工程で測定された結晶化率と前記下地膜の上に製膜する微結晶シリコン成分を含む膜の所望の結晶化率とに基づいて製膜条件を決定する工程と、
    　前記下地膜が製膜された第１の製膜室とは別の製膜室であって、第１の製膜室から前記基板を真空搬送することが可能な第２の製膜室において、決定された前記製膜条件のもと、当該下地膜の上に微結晶シリコン成分を含む膜をＣＶＤにより製膜する工程とを
    　含むことを特徴とする薄膜シリコン太陽電池の製造方法。     A measurement step of measuring the crystallization rate of a film containing a microcrystalline silicon component which becomes a base film formed by CVD on a substrate;
    The crystallization rate of the base film, the conditions for forming the film on the base film, and the crystallization rate of a film containing a microcrystalline silicon component formed by CVD on the base film under the conditions are previously set. Based on the relationship obtained, the film formation conditions are determined based on the crystallization rate measured in the measurement step and the desired crystallization rate of the film containing the microcrystalline silicon component formed on the base film. A step of determining;
    In a second film-forming chamber that is different from the first film-forming chamber on which the base film is formed, and in which the substrate can be vacuum-transferred from the first film-forming chamber, Forming a film containing a microcrystalline silicon component on the base film by CVD under the film forming conditions determined. The method for manufacturing a thin-film silicon solar cell, comprising:
  2. 　前記製膜する工程において製膜する膜は、Ｉ型微結晶シリコン膜である
    　ことを特徴とする請求項１に記載の薄膜シリコン太陽電池の製造方法。     The method for producing a thin-film silicon solar cell according to claim 1, wherein the film to be formed in the film-forming step is an I-type microcrystalline silicon film.
  3. 　前記測定は、顕微ラマン分光測定である
    　ことを特徴とする請求項１または２に記載の薄膜シリコン太陽電池の製造方法。     The method of manufacturing a thin-film silicon solar cell according to claim 1, wherein the measurement is microscopic Raman spectroscopy.
  4. 　前記製膜条件は、ＳｉＨ４流量、製膜圧力、ＲＦ電力、Ｈ２流量、若しくは基板-電極間距離、またはこれらを複数組み合わせたものである
    　ことを特徴とする請求項１、２または３に記載の薄膜シリコン太陽電池の製造方法。     The film forming conditions are SiH 4 flow rate, film forming pressure, RF power, H 2 flow rate, or substrate-electrode distance, or a combination thereof. The manufacturing method of the thin film silicon solar cell of description.
  5. 　前記製膜する工程の前に、前記下地膜が製膜された前記基板の温度を測定する工程と、
    　測定された前記基板の温度に基づいて、前記製膜する工程の前の前記基板の前記第２の製膜室における昇温時間を決定する工程と、
    　前記製膜する工程の前に、前記第２の製膜室において前記基板を前記昇温時間で昇温する工程と
    　をさらに含むことを特徴とする請求項１～４のいずれか１つに記載の薄膜シリコン太陽電池の製造方法。     Measuring the temperature of the substrate on which the base film has been formed before the step of forming the film;
    Determining a temperature rising time in the second film forming chamber of the substrate before the film forming step based on the measured temperature of the substrate;
    The method of any one of claims 1 to 4, further comprising a step of raising the temperature of the substrate in the second film-forming chamber before the film-forming step. Manufacturing method of thin film silicon solar cell.
  6. 　前記ＣＶＤはプラズマＣＶＤ法である
    　ことを特徴とする請求項１～５のいずれか１つに記載の薄膜シリコン太陽電池の製造方法。     The method of manufacturing a thin-film silicon solar cell according to any one of claims 1 to 5, wherein the CVD is a plasma CVD method.
  7. 　基板の上にＣＶＤにより微結晶シリコン成分を含む膜を製膜する複数の製膜室と、
    　複数の前記製膜室の間で前記基板を真空搬送するための搬送室と、
    　大気圧からの真空排気が可能であり前記基板を外部から搬入及び外部へ搬出するためのロードロック室と、
    　前記搬送室または前記ロードロック室のいずれかに配置され、前記基板上に形成された微結晶シリコン成分を含む膜の結晶化率を測定する結晶化率測定手段と、
    　前記結晶化率測定手段によって測定された前記結晶化率に基づいて前記製膜室における製膜条件を制御する製膜条件制御手段と
    　を備えたことを特徴とする薄膜シリコン太陽電池の製造装置。     A plurality of film forming chambers for forming a film containing a microcrystalline silicon component by CVD on a substrate;
    A transfer chamber for vacuum transfer of the substrate between the plurality of film forming chambers;
    A load-lock chamber that can be evacuated from atmospheric pressure and is used to carry in and out the substrate from the outside;
    A crystallization rate measuring means that is disposed in either the transfer chamber or the load lock chamber and measures the crystallization rate of a film containing a microcrystalline silicon component formed on the substrate;
    An apparatus for manufacturing a thin-film silicon solar cell, comprising: a film-forming condition control unit that controls a film-forming condition in the film-forming chamber based on the crystallization rate measured by the crystallization rate measuring unit.
  8. 　前記製膜条件制御手段によって製膜条件が制御される前記製膜室において、Ｉ型微結晶シリコン膜が製膜される
    　ことを特徴とする請求項７に記載の薄膜シリコン太陽電池の製造装置。     The apparatus for manufacturing a thin film silicon solar cell according to claim 7, wherein an I-type microcrystalline silicon film is formed in the film forming chamber in which the film forming conditions are controlled by the film forming condition control means.
  9. 　前記結晶化率測定手段は、顕微ラマン分光測定装置である
    　ことを特徴とする請求項７または８に記載の薄膜シリコン太陽電池の製造装置。     The apparatus for producing a thin-film silicon solar cell according to claim 7 or 8, wherein the crystallization rate measuring means is a microscopic Raman spectroscopic measuring device.
  10. 　前記製膜条件制御手段によって制御される製膜条件は、ＳｉＨ４流量、製膜圧力、ＲＦ電力、Ｈ２流量、若しくは基板-電極間距離、またはこれらを複数組み合わせたものである
    　ことを特徴とする請求項７、８または９に記載の薄膜シリコン太陽電池の製造装置。     The film forming condition controlled by the film forming condition control means is characterized in that the SiH 4 flow rate, the film forming pressure, the RF power, the H 2 flow rate, the substrate-electrode distance, or a combination of these is used. The apparatus for manufacturing a thin-film silicon solar cell according to claim 7, 8 or 9.
  11. 　前記結晶化率測定手段による結晶化率の測定を、前記基板を搬送ロボットによって移動させながら行なうことで前記基板面内の結晶化率の分布を測定する
    　ことを特徴とする請求項７～１０のいずれか１つに記載の薄膜シリコン太陽電池の製造装置。     11. The distribution of the crystallization rate in the substrate surface is measured by measuring the crystallization rate by the crystallization rate measuring means while moving the substrate by a transfer robot. The manufacturing apparatus of the thin film silicon solar cell as described in any one.
  12. 　前記搬送室または前記ロードロック室のいずれかに配置され、前記基板の温度を測定する基板温度測定手段と、
    　前記基板温度測定手段によって測定された前記基板の温度に基づいて前記製膜室における製膜前の前記基板の昇温時間を制御する基板昇温時間制御手段と
    　をさらに備えたことを特徴とする請求項７～１１のいずれか１つに記載の薄膜シリコン太陽電池の製造装置。     A substrate temperature measuring means disposed in either the transfer chamber or the load lock chamber and measuring the temperature of the substrate;
    Substrate temperature rising time control means for controlling the temperature rising time of the substrate before film formation in the film forming chamber based on the temperature of the substrate measured by the substrate temperature measuring means. The thin-film silicon solar cell manufacturing apparatus according to any one of claims 7 to 11.
  13. 　前記基板温度測定手段は、放射温度計、もしくは前記基板を搬送する搬送ロボットに設けられた接触式温度計である
    　ことを特徴とする請求項７～１２のいずれか１つに記載の薄膜シリコン太陽電池の製造装置。     The thin-film silicon solar cell according to any one of claims 7 to 12, wherein the substrate temperature measuring means is a radiation thermometer or a contact-type thermometer provided in a transfer robot that transfers the substrate. Battery manufacturing equipment.
  14. 　前記製膜室はプラズマＣＶＤ装置である
    　ことを特徴とする請求項７～１３のいずれか１つに記載の薄膜シリコン太陽電池の製造装置。     The thin film silicon solar cell manufacturing apparatus according to any one of claims 7 to 13, wherein the film forming chamber is a plasma CVD apparatus.
PCT/JP2010/069518 2010-04-09 2010-11-02 Method and apparatus for manufacturing thin film silicon solar cell WO2011125251A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012509273A JP5220239B2 (en) 2010-04-09 2010-11-02 Thin-film silicon solar cell manufacturing method and manufacturing apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-090730 2010-04-09
JP2010090730 2010-04-09

Publications (1)

Publication Number Publication Date
WO2011125251A1 true WO2011125251A1 (en) 2011-10-13

Family

ID=44762226

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/069518 WO2011125251A1 (en) 2010-04-09 2010-11-02 Method and apparatus for manufacturing thin film silicon solar cell

Country Status (2)

Country Link
JP (1) JP5220239B2 (en)
WO (1) WO2011125251A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003073515A1 (en) * 2002-02-28 2003-09-04 National Institute Of Advanced Industrial Science And Technology Thin-film solar cell and its production method
JP2004363577A (en) * 2003-05-13 2004-12-24 Kyocera Corp Semiconductor thin film, photoelectric converter employing it, and photovoltaic generator device
JP2005244071A (en) * 2004-02-27 2005-09-08 Sharp Corp Solar cell and its manufacturing method
JP2006032800A (en) * 2004-07-20 2006-02-02 Mitsubishi Heavy Ind Ltd Plasma treatment device, solar cell and manufacturing method of solar cell
JP2006073878A (en) * 2004-09-03 2006-03-16 Sharp Corp Photoelectric converter and manufacturing method therefor
WO2008078471A1 (en) * 2006-12-25 2008-07-03 Sharp Kabushiki Kaisha Photoelectric converter and method for fabricating the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003073515A1 (en) * 2002-02-28 2003-09-04 National Institute Of Advanced Industrial Science And Technology Thin-film solar cell and its production method
JP2004363577A (en) * 2003-05-13 2004-12-24 Kyocera Corp Semiconductor thin film, photoelectric converter employing it, and photovoltaic generator device
JP2005244071A (en) * 2004-02-27 2005-09-08 Sharp Corp Solar cell and its manufacturing method
JP2006032800A (en) * 2004-07-20 2006-02-02 Mitsubishi Heavy Ind Ltd Plasma treatment device, solar cell and manufacturing method of solar cell
JP2006073878A (en) * 2004-09-03 2006-03-16 Sharp Corp Photoelectric converter and manufacturing method therefor
WO2008078471A1 (en) * 2006-12-25 2008-07-03 Sharp Kabushiki Kaisha Photoelectric converter and method for fabricating the same

Also Published As

Publication number Publication date
JPWO2011125251A1 (en) 2013-07-08
JP5220239B2 (en) 2013-06-26

Similar Documents

Publication Publication Date Title
US6858087B2 (en) Vacuum-processing method using a movable cooling plate during processing
Arguirov et al. Residual stress in Si nanocrystals embedded in a SiO2 matrix
JP5379801B2 (en) Thin film photoelectric conversion device and manufacturing method thereof
US9112088B2 (en) Method for manufacturing a thin-film solar cell using a plasma between parallel electrodes
Chen et al. Van Der Waals hybrid perovskite of high optical quality by chemical vapor deposition
Tong et al. 2D Derivative Phase Induced Growth of 3D all inorganic perovskite micro–nanowire array based photodetectors
CN107924825A (en) Manufacture method, lining processor and the program of semiconductor devices
US20140083505A1 (en) Varying cadmium telluride growth temperature during deposition to increase solar cell reliability
Wen et al. Ultrasensitive photodetectors promoted by interfacial charge transfer from layered perovskites to chemical vapor deposition‐grown MoS2
Neimash et al. Nanocrystals growth control during laser annealing of Sn:(α-Si) composites
Feng et al. Intact Vertical 3D–0D–2D Carbon‐Based p–n Junctions for Use in High‐Performance Photodetectors
Van den Donker et al. Deposition of highly efficient microcrystalline silicon solar cells under conditions of low H2 dilution: the role of the transient depletion induced incubation layer
Rau et al. Development of a rapid thermal annealing process for polycrystalline silicon thin-film solar cells on glass
Yatskiv et al. Electrical and optical properties of rectifying ZnO homojunctions fabricated by wet chemistry methods
JP5220239B2 (en) Thin-film silicon solar cell manufacturing method and manufacturing apparatus
Heilbronn et al. Fast growth of thin multi‐crystalline silicon ribbons by the RST method
Tsukamoto et al. Evaluation of crystallinity of lattice-matched Ge/GeSiSn heterostructure by Raman spectroscopy
US7687300B2 (en) Method of dynamic temperature control during microcrystalline SI growth
Chaudhary et al. Effect of pressure on bonding environment and carrier transport of a-Si: H thin films deposited using 27.12 MHz assisted PECVD process
KR20210030775A (en) Method for forming transition metal dichalcogenide film and method of manufacturing an electric device including the same
JP5084784B2 (en) Microcrystalline silicon film manufacturing apparatus and microcrystalline silicon film manufacturing method
Hashemi Amiri et al. High‐Quality Indium Phosphide Films and Nano‐Network Grown Using Low‐Cost Metal‐Catalyzed Vapor–Liquid–Solid Method for Photovoltaic Applications
Smith et al. Control of thick single crystal erbium oxide growth on (1 1 1) silicon
Schönau et al. Photoluminescence study of polycrystalline silicon thin films prepared by liquid and solid phase crystallization
JP5493421B2 (en) Semiconductor device manufacturing method and semiconductor manufacturing apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10849491

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2012509273

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10849491

Country of ref document: EP

Kind code of ref document: A1