WO2011122739A1

WO2011122739A1 - Wafer and single crystal ingot manufacturing method for manufacturing the same

Info

Publication number: WO2011122739A1
Application number: PCT/KR2010/004780
Authority: WO
Inventors: Yo-Han Jung; Se-Hun Kim; Bok-Cheol Sim; Yun-Seon Jang; Hong-Woo Lee
Original assignee: Lg Siltron Inc.
Priority date: 2010-03-30
Filing date: 2010-07-21
Publication date: 2011-10-06
Also published as: KR20110108876A; TW201139765A

Abstract

Provided are a wafer and a single crystal ingot manufacturing method for manufacturing the same. In a wafer including an interstitial region (region Pi) and a vacancy region (region Pv), the region Pv does not exceed about 50 % of an upper surface of the wafer.

Description

WAFER AND SINGLE CRYSTAL INGOT MANUFACTURING METHOD FOR MANUFACTURING THE SAME

The present disclosure relates to a wafer and a single crystal ingot manufacturing method for manufacturing the same.

With the fining of a design rule in a semiconductor process, a degree of completion of a silicon wafer is also being required. Wafers used in semiconductor require a structure that does not exert a bad influence on a structure, which is formed at a surface, by maintaining the surface in a zero-defect state and simultaneously can increase the yield of a device, which is molded at a surface, by gathering a metal in a bulk within a certain distance from the surface.

Accordingly, wafer development pursues a zero defect, and technology development is fundamentally being made on a Denuded Zone (DZ) and a Bulk Micro Defect (BMD). The surfaces of wafers pursue a defect neutral state by controlling a void defect due to a vacancy and an interstitial defect due to interstitial, and pursue the increase of a BMD for enhancing a gathering effect in a bulk within a certain distance from a surface. For implementing these, various subsequent thermal processes such as a Rapid Thermal Process (RTP) and an annealing process exist.

In some Silicon On Insulator (SOI) processes, since one wafer is repeatedly used several times, products are required in which a defect does not exist to a bulk.

Generally, an SOI wafer manufacturing process repeatedly uses the surface of a silicon wafer through a SmartCut process, and processes such as thermal oxidation and Chemical Mechanical Planarization (CMP) are applied for enhancing the forming of an oxide layer and a degree of planarization each time a new surface is formed.

In the SOI wafer manufacturing process, a defect is grown by repetitive thermal treatment when oxygen and a crystal defect exist inside a silicon wafer. Even when any defect is not detected from a surface in the initial state of a silicon wafer, a defect occurs which may affect a device yield in a surface and a bulk by a defect that is grown through repetitive thermal treatment. Accordingly, a silicon wafer for an SOI wafer requires a much lower oxygen concentration and a much lower point defect concentration than the existing products.

Embodiments provide a wafer and a single crystal ingot manufacturing method for manufacturing the same, which do not decrease a device yield due to the occurrence of a crystal defect and oxygen precipitation in a surface even when thermal treatment and a polishing process are performed several times like an SOI wafer manufacturing process.

In one embodiment, a wafer including an interstitial region (region Pi) and a vacancy region (region Pv) is characterized in that the region Pv does not exceed about 50 % of an upper surface of the wafer.

In another embodiment, a method for manufacturing a silicon single crystal ingot with a heater and a crucible includes: applying a magnetic field to a silicon melt which is contained in the crucible, controlling a melt level between the melt and the heater, and controlling a rotation speed of the crucible containing the melt to manufacture the silicon single crystal ingot, wherein a wafer where the single crystal ingot is cut comprises an interstitial region (region Pi) and a vacancy region (region Pv), and the region Pv does not exceed about 50 % of an upper surface of the wafer.

The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

According to embodiments, provided can be a wafer that does not decrease a device yield due to the occurrence of a crystal defect and oxygen precipitation in a surface even when thermal treatment and a polishing process are performed several times for a zero-defect wafer where the crystal defect of a surface exists to less than a detection limit, like an SOI wafer manufacturing process.

Fig. 1 is a view exemplarily illustrating a crystal defect region of a single crystal ingot.

Figs. 2 and 3 are views exemplarily illustrating a shape where a defect is formed only in a region Pv with respect to before and after thermal treatment is performed in the same oxygen concentration.

Figs. 4 and 5 are views exemplarily illustrating a shape where a defect is formed based on a critical oxygen concentration in a wafer according to an embodiment.

Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.

In the description of embodiments, it will be understood that when a layer (or film), region, pattern or structure is referred to as being ‘on’ another layer (or film), region, pad or pattern, the terminology of ‘on’ and ‘under’ includes both the meanings of ‘directly’ and ‘indirectly’. Further, the reference about ‘on’ and ‘under’ each layer will be made on the basis of drawings.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience in description and clarity. Also, the size of each element does not entirely reflect an actual size.

(Embodiment)

A single crystal, which is produced as a semiconductor class product, may include a vacancy region Pv and an interstitial region Pi, and may include some P-band regions.

A crystal defect in a bulk is generated and grown by the combining of oxygen and a vacancy, and the control of a defect concentration in the bulk is linked to the control of a vacancy concentration and the control of an oxygen concentration.

In a product having the crystal defect of a bulk controlled, largely, a method may be performed which entirely decreases a vacancy concentration by shifting a point defect concentration from a vacancy region to an interstitial region and thereby suppresses the occurrence of a defect, and a method may be performed which suppresses the generation and growth of a crystal.

A crystal defect region of a single crystal may be illustrated like in Fig. 1. A wafer grown in a region 10 shows a void crystal defect such as a Flow Pattern Defect (FPD), and a defect by an interstitial loop is detected from a region 50. A region 20 has a vacancy point defect, but does not affect a device because it does not exist as a Three-Dimensional (3D) defect. An interstitial point defect also exists in a region 40.

A zero-defect wafer is grown in the

regions

20, 30 and 40. In Fig. 1, the setting of the regions 10 to 50 are divided into several stages, but they may substantially be divided into the difference of a continuous defect concentration instead of discrete stages.

A point defect (vacancy or interstitial) existing in fine atom units grows as a 3D defect according to the thermal history of a corresponding single crystal, and the growth of the defect is closely related with the oxygen concentration of a single crystal. Particularly, a vacancy and oxygen have very close relationships.

In this way, when a vacancy and oxygen coexist with each other, there is very much possibility that they may evolve into a crystal defect.

Accordingly, a thermodynamic environment is made which may suppress the generation of a defect when decreasing an oxygen concentration or a vacancy concentration.

A wafer according to an embodiment enables it to be produced in the region 40 of Fig. 1 by controlling the thermal history of a single crystal in the growing of a crystal, and considerably decreases the concentration of a residual vacancy by forming the region Pi, i.e., an interstitial region. Simultaneously, the wafer may low control the oxygen concentration of a single crystal and thus suppress a void defect and a defect by oxygen precipitation.

In an embodiment, a wafer is produced in various conditions, and a crystal defect is precipitated by performing thermal treatment by the point defect region and oxygen concentration of a single crystal. Through such a result, a critical point defect region and an oxygen concentration are checked.

Figs. 2 and 3 are views exemplarily illustrating a shape where a defect D is formed only in a region Pv with respect to before and after thermal treatment is performed in the same oxygen concentration.

An experiment has been made which measures the crystal defect concentration of a surface before and after thermal treatment is performed on the wafer of a region Pi and the wafer of a region Pv for a long time in the same oxygen concentration. As the experimented result, the concentration of a crystal defect has not been increased according to whether to perform thermal treatment in the wafer of the region Pi, but a plurality of new crystal defects have been generated in the wafer of the region Pv. Accordingly, this denotes that a vacancy and oxygen have grown into a defect according to thermal treatment performed for a long time and is detected as a new defect D.

In a wafer according to an embodiment, by dividing the region Pi and the region Pv in a method such as copper decoration, a defect existing to less than a detection limit does not grow into a new defect when the region Pv does not exceed about 50 % of an entire wafer region.

According to an embodiment, by dividing the region Pi and the region Pv, a defect existing to less than a detection limit does not grow into a new defect when the region Pv has a range of about 30 to 50 % of the upper surface of a wafer as an upper limit.

According to an embodiment, moreover, by dividing the region Pi and the region Pv, a defect existing to less than a detection limit does not grow into a new defect when the region Pv is in a range equal to or less than one-third of a wafer radius.

Figs. 4 and 5 are views illustrating a shape where a defect D is formed based on a critical oxygen concentration in a wafer according to an embodiment.

According to an embodiment, in a case that experiments the wafer of the same crystal defect region per various oxygen concentrations such as Pi, Pv or mixture, an additional crystal defect by thermal treatment has not been grown in an oxygen concentration equal to or less than about 10.4 ppma, but a crystal defect D has been generated in an oxygen concentration higher than about 10.4 ppma. For example, in the case of a wafer according to an embodiment, an additional crystal defect by thermal treatment has not been grown in an oxygen concentration of about 5 ppma to 10.4 ppma.

As an example, an additional crystal defect by thermal treatment has not been grown in a sample 1 (8.5 ppma) and a sample 2 (10.0 ppma), but a crystal defect D has been generated in a sample 3 (10.5 ppma).

According to an embodiment, when the region Pv has a range of about 30 to 50 % of the upper surface of a wafer as an upper limit or the oxygen concentration of the wafer has 10.4 ppma, a defect existing to less than a detection limit does not grow into a new defect. Naturally, when satisfying all the two conditions, it can efficiently be prevented that a defect existing to less than a detection limit does not grow into a new defect.

According to an embodiment, provided can be a wafer and a single crystal ingot manufacturing method for the same, which do not decrease a device yield due to the occurrence of a crystal defect and oxygen precipitation in a surface even when thermal treatment and a polishing process are performed several times for a zero-defect wafer where the crystal defect of a surface exists to less than a detection limit, like an SOI wafer manufacturing process.

Hereinafter, the following description will be made on a single crystal ingot manufacturing method for manufacturing a zero-defect wafer according to an embodiment.

In a zero-defect single crystal by the Czochralski manufacturing method, the control of an oxygen concentration is one of difficult processes. A quarts crucible containing a silicon melt solution is formed of silicon oxide (SiO2), and thus it serves as a source region of oxygen that allows the oxygen to flow into a melt when contacting the melt.

In an embodiment, a method may be applied which varies the convection change of a melt and the rotation speed of a single crystal to control an oxygen concentration that flows in the single crystal, and a method may also be applied which controls an oxygen concentration with a magnetic field.

As the strength of a magnetic field increases, the flow speed of a melt decreases rapidly. This changes the solubility of a quartz crucible and the volatility of oxygen to decrease the oxygen concentration of a single crystal.

However, the strength of a magnetic field leads to the temperature change of a melt, which affects the point defect distribution of a single crystal. Accordingly, it is important to find a condition suitable for the control of a point defect and the decrease of an oxygen concentration.

In an exemplary embodiment, an oxygen concentration may considerably decrease through the change of a Melt Level (ML) other than a magnetic field. The ML denotes the position of the surface of a silicon melt with respect to a heater and is a representative index that indicates the relative position of a melt with respect to an entire hot zone.

As the ML becomes lower, the lower portion of a quartz crucible is not heated but the heating of the side wall of the quartz crucible is induced. Though this, a melt convection speed and an oxygen solubility speed may easily be reduced.

Simultaneously with this, an oxygen concentration may additionally be reduced when using a strong magnetic field. Moreover, a relative convection speed between a melt and a quartz crucible can decrease by lowering the rotation speed of a quartz crucible, and thus the oxygen concentration can additionally be reduced.

In an exemplary embodiment, the lowering of the ML, the use of a strong magnetic field and the decrease of the rotation speed of a quartz crucible are required when producing a low oxygen zero-defect wafer compared to the existing method for manufacturing a zero-defect wafer.

For example, in the ML according to an exemplary embodiment, a distance from the uppermost end of a heater to the surface of a melt may have a range from +100 mm (where the melt is higher than the heater) to -300 mm (where the melt is lower than the heater), and an oxygen concentration decreases as the ML becomes lower.

In an exemplary embodiment, moreover, the strength of a magnetic field may have a range from about 1000 gauss to 5000 gauss, and an oxygen concentration decreases as the magnetic field becomes stronger.

In an exemplary embodiment, the rotation speed of a crucible may have a range of about 0.1 to 5 rpm, and an oxygen concentration decreases as a rotation speed becomes lower.

According to embodiments, provided can be a wafer and a single crystal ingot manufacturing method for manufacturing the same, which do not decrease a device yield due to the occurrence of a crystal defect and oxygen precipitation in a surface even when thermal treatment and a polishing process are performed several times for a zero-defect wafer where the crystal defect of a surface exists to less than a detection limit, like an SOI wafer manufacturing process.

The features, structures and effects of the above-described embodiments are included in at least one embodiment, and are not necessarily limited only to one embodiment. Furthermore, the features, structures and effects that have be exemplified above in each embodiment may also be combined or modified on other embodiments and embodied by those skilled in the art. Accordingly, contents associated with the combination and modification should be construed as being included the scope of embodiments.

Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various modifications and applications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to modifications and applications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art. For example, each element that has been described above in embodiments may be modified and embodied. Furthermore, all differences related to the modifications and applications will be construed as being included in the scope of each embodiment that will be defined in claims.

Claims

A wafer including an interstitial region (region Pi) and a vacancy region (region Pv), characterized in that the region Pv does not exceed about 50 % of an upper surface of the wafer.
The wafer according to claim 1, wherein the region Pv does not exceed about 30 to 50 % of the upper surface of the wafer.
The wafer according to claim 1, wherein the region Pv is in a range equal to or less than one-third of a wafer radius (R).
The wafer according to claim 2, wherein the region Pv is in a range equal to or less than one-third of a wafer radius (R).
The wafer according to any one of claims 1 to 4, wherein an oxygen concentration of the wafer is equal to or less than about 10.4 ppma.
The wafer according to claim 5, wherein the wafer comprises an oxygen concentration of about 5 ppma to 10.4 ppma.
A method for manufacturing a silicon single crystal ingot with a heater and a crucible, the method comprising:

applying a magnetic field to a silicon melt which is contained in the crucible, controlling a melt level between the melt and the heater, and controlling a rotation speed of the crucible containing the melt to manufacture the silicon single crystal ingot,

wherein a wafer where the single crystal ingot is cut comprises an interstitial region (region Pi) and a vacancy region (region Pv), and the region Pv does not exceed about 50 % of an upper surface of the wafer.
The method according to claim 7, wherein in the controlling of a melt level, the melt level denotes a distance from an uppermost end of the heater to a surface, and the melt level has a range of about +100 to -300 mm.
The method according to claim 7, wherein a strength of magnetic field has a range of about 1000 gauss to 5000 gauss.
The method according to claim 7, wherein a rotation speed of the crucible has a range of about 0.1 rpm to 5 rpm.
The method according to claim 7, wherein the region Pv does not exceed about 30 to 50 % of the upper surface of the wafer.
The method according to claim 7, wherein the region Pv is in a range equal to or less than one-third of a wafer radius (R).
The method according to claim 7, wherein an oxygen concentration of the ingot is equal to or less than about 10.4 ppma.