503463 A7 ____B7_ 五、發明說明（1 ) 本發明係關於一種由柴克勞斯基法-CZ法（Czochralski method)製取之矽晶錠切出之半導體積體電路用矽晶圓及 其製造方法。 近年來在製造半導體積體電路之製程中，被認為使產 率（yield)下降之原因有，例如構成氧化誘發堆疊缺陷（ Oxidationlnduced Stacking Fault, K下簡稱為 0SF) 之核之氧析出物之微小缺陷、起因於结晶之粒子（Crystal Originated Particle K下簡稱為COP)、或侵入型轉位（ Interstitial-type Large Dislocation, K下簡稱為 L/D )之存在。0SF係在结晶成長時引進成為其核之微小缺陷 ，製造半導體裝置時之氧化製程等時顯現化，成為所製作 裝置之漏洩電流增加等之不良原因。在氨與過氧化氫之混 合疲洗淨鏡面研磨後之矽晶圓時，晶圓表面形成坑洞，K 顆粒計算器測量此晶圓時，坑洞也隨本來之顆粒一起被當 作顆粒檢出。上逑坑洞係起因於结晶者，為了與本來之顆 粒區別，稱作C0P。此晶圓表面之坑洞之C0P成為使電氣 特性，例如氧化膜之經長時間後之絕緣破壞特性（Time Dependent dielectric Breakdown，TDDB)、氧化膜酎歷 特性（Time Zero Dielectric Breakdown TZDB)等劣化之 原因。同時，若COP存在於晶圓表面則在裝置之配線製程 形成台階差，此台階差成為斷線之原因，使製品之製成率 降低。而且，L/D也被稱作轉位簇，或因將產生缺陷之矽 晶圓浸泡在K氟酸為主成分之選擇蝕刻疲時會產生坑洞而 被稱作轉位坑洞。此L/D也成為使電氣特性，例如漏洩特 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公Μ ) 請 先 閱 讀 背 面 之 注 •意 事 項 再 填 寫 本 頁 f 訂 線 503463 經濟部智慧財產局員工消費合作社印製 A7 ___B7____五、發明說明（2 ) 性、絕緣特性等劣化之原因。 從K上各點可K瞭解，從製造半導體積體電路時使用 之矽晶圓減少OSF、C0P及L/D十分重要。 K往揭示有一種減少此0SF及C0P之方法，係使用能 夠快速加熱•快速冷郤之裝置，在100X氫氣環境或氫氣與 氬氣之混合環境下，κΐ2〇ου〜矽之融點以下之溫度範圍 ，將矽晶圓熱處理1〜60秒鐘之方法（日本國特開平10-326 790)。依據本方法時，可以將每片直徑8时之晶圓之〇·12 ymM上之COP數減少到50個Κ下，且可提高氧化膜耐壓 之良品率。 但上逑傳統之方法，因為是使用在熱處理前之狀態時 ，8时晶圓整個表面之〇.12μ mK上之C0P數有300個Μ 上之矽晶圓，因此要使晶圓整個表面之C 0 Ρ數降到〇個是 極度困難，不僅如此，因為是在還元性環境下進行超過 1250¾之高溫熱處理，因此有晶圓容易被Fe等污染之缺點 。同時，使用可K快速加熱•快速冷卻之裝置，進行1150 ti之熱處理時，又很容易引起结晶缺陷之滑移。而且*快 速加熱在拉上時作出之氧元素析出核受到抑制，在裝置製 程此核不會充分析出》無法期待除氣效果，因此有對金屬 污染，其污染雜質之去除能力變弱之缺點。 本發明之第1目的在提供，無0SF(0SF free)且可K 使〇·12^5ϊΚ上之COP數實質上等於G個（以下稱作無COP •COP free)，幾乎沒有]^等之污染或幾乎不會發生滑移之 矽晶圓及其製造方法。 ί—-----.—— (請先閱讀背面之注意事項再填寫本頁) 訂_————線j -·1 n emf I n 1 ' I I Γ- n n n I n ϋ 1 I ! I . 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 503463 A7 ____B7___ 五、發明說明（3 ) 本發明之第2目的在提供，無〇SF或無COP*幾乎沒有 Pe等之污染或幾乎不會發生滑移之矽晶圓及其製造方法。 (請先閱讀背面之注意事項再填寫本頁) 本發明之第3目的在提供，在半導體裝置製造過程實 施熱處理時，氧元素析出核從晶圓之中心商周緣均一出現 ，發揮IG效果之矽晶圓。 本發明之第1個觀點，係在氧氣環境下，KlOOOt! 士 30°C之溫度範圍進行2〜5小時之熱處理，再繼續Μ1130Ό ±3〇υ之溫度範圍進行1〜16小時之熱處理時，不會發生 氧化誘導堆叠缺陷（〇 S F )，起因於晶圓表面之未滿0 · 1 2 μ沮 之结晶之顆粒（COP)數在3〜10個/ cm2之範圍內，且起因 於晶圓表面之〇 · 12 ^ aK上之结晶之顆粒（C0P)數在0 · 5涸 /cih2K下，為其特徵之矽晶圓。 本發明之第2個観點，係從矽融液拉上矽單结晶晶錠 ，切削上逑晶錠K製造矽晶圓之方法，其特徵在於* K拉 上速度VUm/分）拉上上逑晶錠，在矽融點至13Q ου之溫度 範圍内*分別使上逑晶錠之中心之軸方向之溫度坡度為G a (t： /hub)，上逑晶錠之周緣之軸方向之溫度坡度為Gb(°C/ 值磁）時，V/Ga及V/Gb分別為0·23〜0·50ιιπ2/分· 10。 本發明之實施形態 本發明之實施形態之矽晶圓係藉CZ毕，Κ依據Voronkov 理論之一定之拉上速度輪廓，従熱區（hot zone)爐内之 矽融液拉上晶錠，切削此晶錠而製成。 一般藉C Z法從熱區爐內之矽融液拉上矽單结晶之晶錠 時，矽單结晶會發生之缺陷有，點缺陷（point defect) -6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 503463 A7 ___B7___ 五、發明說明（4 ) 及凝集體（agglomerates:三度空間缺陷）。點缺陷有空孔 型點缺陷及格子間矽型點缺陷之兩種一般之彩態。空孔型 點缺陷係一涸矽原子脫離矽结晶格子之正常位置者。這種 空孔成為空孔型點缺陷。另一方面，若原子在矽结晶之非 格子地點（interstitial cite)被發現，便是格子間矽型 點缺陷。 一般來講，點缺陷係形成在矽融液（溶融矽）與晶錠（ 固狀矽）之間之接觸面。惟，若繼續拉上晶錠，接觸面之 部分會隨著被拉上而開始泠郤。在冷卻期間*空孔型點缺 陷及格子間矽型點缺陷各自之擴散將缺陷合併，而形成空 孔型點缺陷之凝集體（vacancy agglomerates)或格子間矽 型點缺陷之凝集體（interstitial agglomerates)。換言 之，凝集體係因點缺陷之合併而發生之三度空間構造。 空孔型點缺陷之凝集體除了上逑之COP K外，另包含 叫著 LSTD(Laster Scattering Tomograph Defects)或 FPD (Flow Pattern Defects)之缺陷，格子間砂型點缺陷之凝 集體則包含上逑叫著L/D之缺陷。所謂FPD係指，將切削晶 錠而製成之矽晶圓K無攪拌之狀態下進行30分鐘之無水蝕 刻（Secco etching，Μ K2 Cr 2 0 ? · 5 0 % H F ：純水= 44g·· 2 0 0 0 cc: lOOQcc之混合液蝕刻）時出現之呈現特異流動模式之 痕跡之源。而LSTD係指，向矽單结晶照射紅外線時，具有 與矽不同之折射率，發出散亂光之源。503463 A7 ____B7_ 5. Description of the invention (1) The present invention relates to a silicon wafer for semiconductor integrated circuits cut out of a silicon ingot prepared by the Czochralski method and a method for manufacturing the same. . In recent years, in the process of manufacturing semiconductor integrated circuits, it is considered that the reason for the decrease in yield is, for example, the tiny amount of oxygen precipitates in the nucleus constituting the Oxidation Induced Stacking Fault (hereinafter referred to as 0SF). The existence of defects, crystalline-derived particles (hereinafter referred to as COP), or invasive translocation (Interstitial-type Large Dislocation (hereinafter referred to as L / D)). 0SF is caused by the introduction of tiny defects that become its core during crystal growth, and is manifested during the oxidation process and the like during the manufacture of semiconductor devices, which has caused the increase in leakage current of the manufactured devices. When the mirror-polished silicon wafer was washed with a mixture of ammonia and hydrogen peroxide, a pit was formed on the wafer surface. When the K particle calculator measured the wafer, the pit was also used as a particle inspection along with the original particles. Out. The upper pit is caused by the crystallizer, and it is called COP to distinguish it from the original particles. The COP of the pits on the surface of the wafer deteriorates the electrical characteristics, such as the time-dependent dielectric breakdown (TDDB) of the oxide film, and the time zero dielectric breakdown (TZDB) of the oxide film. the reason. At the same time, if the COP exists on the surface of the wafer, a step difference will be formed in the device's wiring process. This step difference will cause disconnection and reduce the production rate of the product. In addition, L / D is also called an indexing cluster, or it is called an indexing pit because a silicon wafer that produces defects is immersed in K-fluoric acid as the main component and will pit when it is etched. This L / D also makes the electrical characteristics, such as leaked special paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 gM) Please read the notes and notices on the back before filling in this page. F Line 503463 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau A7 _B7____ V. Invention Description (2) Reasons for deterioration of properties, insulation properties, etc. It can be understood from various points on K that it is important to reduce OSF, C0P, and L / D from the silicon wafers used in manufacturing semiconductor integrated circuits. K revealed that there is a method to reduce this 0SF and C0P, which uses a device capable of rapid heating and rapid cooling, in a 100X hydrogen environment or a mixed environment of hydrogen and argon, κΐ2〇ου ~ temperature below the melting point of silicon Range, a method for heat-treating a silicon wafer for 1 to 60 seconds (Japanese Patent Application Laid-Open No. 10-326 790). According to this method, the number of COPs on each wafer at 8 · 12 ymM can be reduced to less than 50 K, and the yield of the oxide film withstand voltage can be improved. However, the conventional method is used, because when the state before the heat treatment is used, the number of COPs on the entire surface of the wafer at 8:00 on the 12th μmK is 300 silicon wafers, so the entire surface of the wafer must be It is extremely difficult to reduce the number of C 0 P to zero, and not only that, because it is subjected to high temperature heat treatment in excess of 1,250 ¾ under the original environment, there is a disadvantage that the wafer is easily contaminated by Fe and the like. At the same time, using a device capable of K rapid heating and rapid cooling, when performing a heat treatment of 1150 ti, it is easy to cause slippage of crystal defects. Moreover, the nucleus of oxygen element precipitation made by the rapid heating during the pull-up is inhibited, and this nucleus will not be fully analyzed in the process of the device. “The degassing effect cannot be expected. Therefore, it has the disadvantage of contaminating metals and weakening their ability to remove contaminating impurities. The first object of the present invention is to provide that there is no 0SF (0SF free) and K can make the number of COPs on 〇12 ^ 5ϊK substantially equal to G (hereinafter referred to as COP-free • COP free), and there is almost no] ^ etc. Silicon wafers that contaminate or hardly slip and methods of making them. ί —-----.—— (Please read the notes on the back before filling in this page) Order _———— line j-· 1 n emf I n 1 'II Γ- nnn I n ϋ 1 I! I. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 503463 A7 ____B7___ V. Description of the invention (3) The second purpose of the invention is to provide, no 〇SF or no COP * almost no Pe Silicon wafers that are contaminated or scarcely slipped, and methods of making the same. (Please read the precautions on the back before filling this page.) The third object of the present invention is to provide silicon that, during the heat treatment of the semiconductor device manufacturing process, the oxygen element precipitation nuclei appear uniformly from the periphery of the center of the wafer and exert the IG effect. Wafer. The first aspect of the present invention is that when the heat treatment is performed at a temperature range of KlOOt! ± 30 ° C for 2 to 5 hours under an oxygen environment, and then the heat treatment is continued at a temperature range of M1130Ό ± 3〇υ for 1 to 16 hours, No oxidation-induced stacking defects (〇SF) will occur, and the number of crystalline particles (COP) due to less than 0 · 1 2 μ on the wafer surface is in the range of 3 to 10 / cm2, and it is caused by the wafer The number of crystalline particles (C0P) on the surface of 0.12 ^ aK is a characteristic silicon wafer at 0 · 5 涸 / cih2K. The second point of the present invention is a method for drawing a silicon single crystal ingot from a silicon melt, and cutting the silicon ingot K to produce a silicon wafer, which is characterized by * K drawing speed (VUm / min) drawing on Ingot crystals, in the temperature range from the melting point of silicon to 13Q ου * make the temperature gradient in the axial direction of the center of the upper ingot crystal be G a (t: / hub), and the axial direction of the peripheral edge of the ingot crystal ingot. When the temperature gradient is Gb (° C / value magnetism), V / Ga and V / Gb are 0 · 23 ~ 0.550mπ2 / min · 10, respectively. Embodiment of the invention The silicon wafer of the embodiment of the present invention is borrowed from CZ, and K is drawn at a certain speed profile according to Voronkov theory. The silicon melt in the hot zone furnace is drawn on the ingot and cut. This ingot is made. Generally, when the silicon single crystal ingot is pulled up from the silicon melt in the hot zone furnace by the CZ method, the defects of the silicon single crystal are: point defect -6-This paper size applies to Chinese national standards (CNS ) A4 specification (210 X 297 mm) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 503463 A7 ___B7___ V. Description of the invention (4) and agglomerates: third-degree space defects. Point defects have two general color states: hole type point defects and inter-lattice silicon type point defects. Hollow point defects are those in which a single atom of silicon leaves the normal position of a silicon crystal lattice. Such voids become void-type point defects. On the other hand, if the atom is found at an interstitial cite of silicon crystal, it is an inter-lattice silicon-type point defect. Generally speaking, point defects are formed at the contact surface between a silicon melt (fused silicon) and an ingot (solid silicon). However, if you continue to pull the ingot, the part of the contact surface will start to sag as it is pulled up. During the cooling period * the respective diffusion of void point defects and inter-lattice silicon point defects merge the defects to form vacancy agglomerates or interstitial agglomerates of silicon point defects. ). In other words, the three-dimensional spatial structure of the agglutination system due to the merger of point defects. In addition to the COP K of the upper point defect, the aggregate of void point defects also includes defects called LSTD (Laster Scattering Tomograph Defects) or FPD (Flow Pattern Defects). L / D defects. The so-called FPD refers to a 30-minute waterless etching (Secco etching, M K2 Cr 2 0? · 50% HF: pure water = 44g ··) of a silicon wafer K produced by cutting an ingot without stirring. 2 0 0 0 cc: lOOQcc mixed liquid etching) source that shows traces of specific flow patterns. LSTD means that when silicon single crystal is irradiated with infrared rays, it has a refractive index different from that of silicon and emits scattered light.
Voronkov之理論係指，為了成長缺陷數少高純度之晶 錠，以晶錠之拉上速度為VUm/分），熱區構造而晶錠與矽 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） . · ^裝--------tr------— (請先閱讀背面之注意事項再填寫本頁) 503463 A7 ____B7 ___ 五、發明說明（5 ) (請先閱讀背面之注意事項再填寫本頁) 融液之接觸面之溫度坡度為G (Ό /mm)時，控制V/G (mm2/¾ •分）。本理論係如第1圖所示，K V/G為橫軸，以空孔型 點缺陷濃度及格子間矽型點缺陷濃度同為縱軸，K圖式方 式表示V/G與點缺陷濃度之關係*說明空孔領域與格子間 矽領域之境界由V/G決定。詳逑之，V/G比在臨界點K上 時，形成空孔型點缺陷濃度優勢之晶錠，反面，V/G比在 臨界點以下時，則形成格子間矽型點缺陷濃度優勢之晶錠。 本發明之實施形態之一定之拉上速度輪廓係決定成， 晶錠從熱區爐内之矽溶融物拉上時，對溫度坡度之拉上速 度之比（V/G)大幅度超越，限制於晶錠中央之空孔型點缺 陷成支配性存在之領域内之第1臨界比（（V/Gh)。此項拉 上速度輪廓係Μ實驗方式將基準晶錠軸方商切削，或以實 驗方式將基準晶錠切削成晶圓，或者組合這些技術，而藉 模擬，依據上逑Voronkov理論決定之。亦即，此項決定係 在模擬後，確認晶錠之軸方向切削或切削成之晶圓》再返 覆進行模擬而為之。為了模擬而在一定之範圍決定多種拉 ,上速度，成長多數基準晶錠。如第2圖所示，模擬用之拉 上速度之輪廓係由1 . 2aia/分之高拉上速度（a)調蝥到0 · 5 rani/分之低拉上速度（c)再調整到高拉上逮度（d)。上逑低 拉上逮度也可Μ是d. 4 aa/分或K下之速度，拉上速度（b) 及（d)之變化最好是成線形者。 K不同速度拉上之多數涸基準晶錠個別沿軸方法切削 。最合適之V/G由軸方向之切削，晶圓之確認及模擬之结 果之栢關關係而決定，接著決定最合適之拉上速度輪酈， -8- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 503463 • A7 B7 五、發明說明（6 ) 藉由該輪廓製造晶錠。實際之拉上速度輪靡不受包括所希 望之晶錠之直徑，使用之特定之熱區爐及矽溶融物之品質 等之限制*依存於很多變數。 若描繪慢慢降低拉上速度使V/G連續降低時之晶錠之 截面圖，便可K瞭解第3圖所示之事實。在第3圖，[V] 表示晶內之空孔型點缺陷成支配ft，存在有空孔型_點缺 陷之凝集體之領域，[I]表示晶錠内之格子間矽型點缺陷 成支配性*存在有格子間矽型點缺陷之凝集體之領域* [P] 表示不存在空孔型點缺陷之凝集體及格子間矽型點缺陷之 凝集體之完整領域。 再者，COP或L/D等點缺陷之之凝集體因不同之檢测 方法，有時會表示檢測靈敏度，檢測下限值不同之值。因 此，在本說明書，「不存在有點缺陷之凝集體J之意思是 ，對經過鏡面加工之矽軍结晶施加無攪拌無水蝕刻後，用 光學顯微鏡，K觀察面積與蝕刻部分之積作為檢査體積進 行觀察時，對流動模式（空孔型點缺陷）及轉位簇（格子間 ，矽型點缺陷）之各凝集體為lxi(T3cm3之撿査體積，檢出1 個缺陷時作為檢測下限值（IX 1〇3個/ cm3)，而點缺陷之凝 集體之數目在上逑檢測下限值K下。 如第3鼸所示，晶錠之軸方向位置PQ之所有領域為空 孔型點缺陷成支配性之領域。位置Pi包含中央有空孔型點 缺陷成支配性之領域。位置h包含格子間矽型點缺陷成支 配性之環及中央之完蝥領域。而位置P3則全為完整領域。 從第3圖可K明瞭，對應位置PQ之晶圓，其所有領 -9 - 本纸張尺度適角中國國家標準（CNS)A4規格（210 X 297公釐） III!IIJlIi>--· I I (請先閱讀背面之注意事項再填寫本頁) 訂-· -丨線- 503463 A7 ___Β7__— —— 五、發明說明（7 ) (請先閱讀背面之注意事項再填寫本頁) 域均為空孔型點缺陷成支配性之領域。對應位置 Wt包含中央有格子間矽型點缺陷成支配性之領域。對應位 置P4之晶圓W4包含格子間矽型點缺陷成支配性之瓌及+央 之完整領域。而對應位置p3之晶圓w3則全為完整領域° 晶圓Wi在氧氣環境下，Μΐοοου 土 3〇υ之溫度範圍進 行2〜5小時之熱處理，再繼續K 113 (TC 士 3(TC之潙度範圍 進行1〜16小時之熱處理時，便如第4圖所示，在晶圓之 半徑之1/2附近發生0SF環。從對應位置Pi之晶圓Wi愈向 對應位置PQ之晶圓WQ，0SF環之直徑愈大，如第5圖所示 ，對應位置Pq之晶圓Wa時便超過晶錠之直徑，經過上逑熱 處理也不會發生0SF環。 本發明之實施形態之晶圓係對應位置Pd之晶圓^ ° 一 般來講，對應位置Ρ α之晶圓Wa，從晶圓之周緣愈向晶圓之 中心，愈有出現大形之COP之傾向。第1實施彤態之拉上 方法，係在晶錠之全長育成對應位置PQ之領域之方法。具 體上是，晶錠之中心之軸方向之溫度坡度為Ga *晶錠之周 緣之軸方向之溫度坡度為Sb時，拉上晶錠時使V/Ga及V/Gb 分別為0.23〜0.5011112/分之拉上方法。此拉上方法相當於 申請專利範圍第6項。如此拉上時，在晶圓中心之0.12 am Μ上之COP之數目也在0·5個/ cra2K下，在晶圓表面之，未滿 0.12IKBI之C0P之數目則被抑制在3〜10個/cm2之範圍。V/ Ga及V/Gb未滿0·23ιηιπ2/分時會發生0SF，超過0·50ΐϋΐη2/分 ，則矽單结晶晶錠之育成會不穩定。 0·12αιηΚ上之C0P用上逑一定之顆粒計數器來测量 -10- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） " ~ 503463 _ B7_；__ 五、發明說明（8 ) 。未滿0.12ym之COP中，O.lOiuraK上之C0P用上述一定 之顆粒計數器來測量。或者，未滿〇·12// ΐη之C0P藉計算 FPD來測量，或依據日本專利第2520316號之「矽晶圓之 微小坑洞之撿測方法J來測量。此檢測方法，係使用氨糸 洗淨液在一定條件下洗淨矽晶圓表面，直到可K用顆粒計 數器測量矽晶圓表面之坑洞數為止，而使用此顆粒計數器 測量洗淨後之晶表面之坑洞數，再Μ同一條件洗淨此晶圓 表面，使用此顆粒計數器測量再度洗淨後之晶表面之坑洞 數，依據此等測量值之差及到可测量時之洗淨次數，檢出 洗淨一次後之晶圓表面之微小坑洞之大小及其數目之方法。 再者，C0P之尺寸會因顆粒計數器之不同製造商，不 同型式而顯示不同值，因此本說明書所稱之「0.12// si之 C0PJ係指使用垂直射入型之KLA-Tencor公司製之SFS6200 糸列、ADE公司製之CR80系列或日立電子工程公司製之 LS6000糸列之各顆粒計數器時顯示〇.12em之值之C0P。 而K上逑各顆粒計數器測量之值係聚苯乙烯膠乳粒子之換 算值，不是原子間力顯微鏡（AFM)之實測值。 本發明之實施形態之晶圓係進一步控制晶内之氧元素 濃度。在CZ法，係藉改變供給熱區爐内之氨氣之流量、儲 •存矽溶融物之石英坩鍋之轉動速度、熱區爐內之壓力等* 來控制晶圓中之氧元素濃度。 半導體裝置製造商需要可發揮IG效果之矽晶圓時，使 晶圓内部之氧元素濃度為1.2X 1018atoms/cm3〜1.6X 1018 atonis/cffl3 (舊ASTM)，使氧原子分布在蝥個晶圓。亦即， 驗1 1 - 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Voronkov's theory is that in order to grow high-purity crystal ingots with few defects, the pulling speed of the crystal ingot is VUm / min), the structure of the hot zone, and the ingot and silicon paper dimensions are applicable to the Chinese National Standard (CNS) A4 specification. (210 X 297 mm). ^ Equipment -------- tr -------- (Please read the notes on the back before filling in this page) 503463 A7 ____B7 ___ 5. Description of the invention (5 ) (Please read the precautions on the back before filling this page) When the temperature gradient of the contact surface of the melt is G (Ό / mm), control V / G (mm2 / ¾ • minutes). This theory is shown in Figure 1. KV / G is the horizontal axis, and the hole-type point defect concentration and the inter-lattice silicon-type point defect concentration are the same as the vertical axis. The K diagrammatically shows the V / G and the point defect concentration. Relations * shows that the realm of the void area and the inter-lattice silicon area is determined by V / G. In detail, when the V / G ratio is above the critical point K, a crystal ingot with an advantage of the void type point defect concentration is formed. On the other hand, when the V / G ratio is below the critical point, an inter-lattice silicon type point defect concentration advantage is formed. Crystal ingot. A certain drawing speed profile of the embodiment of the present invention is determined. When the ingot is drawn from the silicon melt in the hot zone furnace, the ratio of the drawing speed (V / G) to the temperature gradient is greatly exceeded, which limits The first critical ratio ((V / Gh) in the field where the hole-type point defect in the center of the ingot is dominant. This pull-up speed profile is based on the M experimental method of cutting the reference ingot shaft quotient, or The reference ingot is cut into wafers experimentally, or these technologies are combined, and the simulation is used to determine it based on the above Voronkov theory. That is, after the simulation, the decision is to confirm that the ingot is cut or cut in the axial direction. "Wafer" and then repeat the simulation for this purpose. For simulation, determine a variety of pull and pull speeds, and grow most of the reference ingots. As shown in Figure 2, the contour of the pull speed for simulation is changed from 1. 2aia / minute high pull-up speed (a) adjusted to 0 · 5 rani / minute low pull-up speed (c) and then adjusted to high pull-up speed (d). Low pull-up speed can also be adjusted. Μ is the speed at d. 4 aa / min or K, and the change of pull-up speed (b) and (d) is preferably linear Most of the 涸 benchmark ingots pulled at different speeds are individually cut along the axis method. The most suitable V / G is determined by the relationship between the cutting in the axial direction, the confirmation of the wafer, and the simulation result, and then the most suitable Pull up the speed wheel, -8- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 503463 • A7 B7 V. Description of Invention (6 ) Manufacture ingots with this profile. The actual pull-in speed is not limited by the diameter of the desired ingot, the quality of the specific hot zone furnace and the quality of the silicon melt, etc. * depends on many variables. By drawing the cross-sectional view of the ingot when slowly lowering the pull-up speed to continuously reduce V / G, K can understand the fact shown in Fig. 3. In Fig. 3, [V] represents a hole-type point defect in the crystal. Dominated by ft, there is a field with void type _ point defects in the aggregate, [I] indicates that the inter-lattice silicon-type point defects in the ingot dominate * area where there are inter-lattice silicon-type point defects in the aggregate * [P] Represents aggregates and cells without void point defects The complete field of aggregates of type point defects. In addition, the aggregates of point defects such as COP or L / D sometimes have different detection sensitivity and lower detection limit values due to different detection methods. Therefore, in In this specification, "the absence of the agglomerated aggregate J means that when the silicon army crystals that have been mirror-finished are subjected to non-stirring and anhydrous etching, the optical microscope, the product of the observation area of K and the etched part is used as the inspection volume. For the aggregates of the flow pattern (void-type point defects) and the transposition clusters (inter-lattice, silicon-type point defects), the inspection volume is lxi (T3cm3). When 1 defect is detected, it is used as the detection lower limit (IX 1 (0 / cm3), and the number of aggregates of point defects is below the upper limit K of detection. As shown in Fig. 3 (a), all the fields of the axial position PQ of the ingot are dominated by the hole-type point defects. The position Pi includes a field in which a hole-type point defect in the center becomes dominant. Position h contains the dominating ring of silicon-type point defects between lattices and the central complete area. The position P3 is all the complete field. As can be seen from Figure 3, the corresponding position of the wafer at PQ, all of its collars are -9-this paper is in the right angle Chinese National Standard (CNS) A4 specification (210 X 297 mm) III! IIJlIi >-II (Please read the notes on the back before filling this page) Order-·-丨 line- 503463 A7 ___ Β7 __—— —— V. Description of the invention (7) (Please read the notes on the back before filling this page) The fields are blank Pore point defects become the dominant field. Corresponding position Wt includes an area in which a central silicon-type point defect is dominant in the center. The wafer W4 corresponding to the position P4 includes a complete area where the inter-lattice silicon-type point defects become dominant and the + center. The wafer w3 at the corresponding position p3 is all in a complete area. Wafer Wi In an oxygen environment, the temperature range of Μΐοοου soil 3〇υ is heat-treated for 2 to 5 hours, and then K 113 (TC 士 3 (TC 之 沩) is continued. When the heat treatment is performed within a range of 1 to 16 hours, as shown in Fig. 4, a 0SF ring occurs near 1/2 of the wafer radius. From the wafer Wi at the corresponding position Pi to the wafer WQ at the corresponding position PQ The larger the diameter of the 0SF ring, as shown in Figure 5, the wafer Wa at the corresponding position Pq exceeds the diameter of the ingot, and the 0SF ring will not occur after the heat treatment of the wafer. The wafer system according to the embodiment of the present invention The wafer corresponding to the position Pd ^ ° Generally speaking, the wafer Wa corresponding to the position P α tends to show a large-scale COP from the periphery of the wafer to the center of the wafer. The above method is a method of cultivating the corresponding position PQ over the entire length of the ingot. Specifically, when the temperature gradient in the axial direction of the center of the ingot is Ga * When the temperature gradient in the axial direction of the circumference of the ingot is Sb, pull How to pull V / Ga and V / Gb to 0.23 ~ 0.5011112 / min when ingots are crystallized. This pull-up The method is equivalent to item 6 of the scope of patent application. When this is pulled up, the number of COPs on the wafer center of 0.12 am Μ is also 0.5 / cra2K, and on the wafer surface, less than 0.12 IKBI C0P The number is suppressed to be in the range of 3 to 10 pieces / cm2. When V / Ga and V / Gb are less than 0 · 23ιηιπ2 / minute, 0SF will occur, and if it exceeds 0 · 50ΐϋΐη2 / minute, the silicon single crystal ingot breeding society Unstable. The C0P on 0 · 12αιηΚ is measured with a certain particle counter. -10- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) " ~ 503463 _ B7_; __ 5 Explanation of the invention (8). In the COP less than 0.12ym, the COP on 0.1OiuraK is measured using the above-mentioned certain particle counter. Or, the COP that is less than 0.1 · // ΐη is measured by calculating FPD, or according to Japanese Patent No. 2520316 "Measurement method for micro-pits of silicon wafers J". This test method uses ammonia cleaning solution to clean the surface of silicon wafers under certain conditions until a particle counter can be used. Measure the number of pits on the surface of the silicon wafer, and use this particle counter to measure the crystals after cleaning Number of pits on the surface, and then clean the wafer surface under the same conditions. Use this particle counter to measure the number of pits on the crystal surface after re-cleaning. Based on the difference between these measured values and the number of cleaning times when it can be measured Method for detecting the size and number of tiny pits on the wafer surface after cleaning once. Furthermore, the size of C0P will show different values due to different manufacturers and different types of particle counters. `` 0.12 // C0PJ of Si '' means each particle counter displayed when using the vertical injection type KLA-Tencor's SFS6200 queue, CRADE ADE's CR80 series, or Hitachi Electronics Engineering's LS6000 queue. C0P with a value of 12em. The value measured by each particle counter on K is the converted value of polystyrene latex particles, not the actual value measured by the atomic force microscope (AFM). The wafer according to the embodiment of the present invention further controls the oxygen element concentration in the crystal. In the CZ method, the concentration of oxygen in the wafer is controlled by changing the flow of ammonia gas supplied to the furnace in the hot zone, the rotation speed of the quartz crucible that stores the silicon melt, and the pressure in the furnace in the hot zone. When a semiconductor device manufacturer needs a silicon wafer that can exert the IG effect, the oxygen element concentration in the wafer is 1.2X 1018 atoms / cm3 to 1.6X 1018 atonis / cffl3 (former ASTM), so that oxygen atoms are distributed on one wafer. . That is, Examination 1 1-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
MM9 VHMM MV 503463 A7 ________B7_ 五、發明說明（9 ) (請先閱讀背面之注意事項再填寫本頁) 此半導體裝置製造商在半導體裝置製造過程熱處理此晶圓 時，會在晶圓之中心至周緣均出現氧元素析出物而發揮IG 效果。為了要使其成為此氧元素濃度，而例如控制氩氣之 流量為60〜110公升/分、儲存矽溶融物之石英坩鍋之轉 動速度為4〜12rpni、熱區爐內之壓力為20〜60Torr。 .半導體裝置製造商不需要可發揮IG效果之矽晶圓時， 使晶圓內部之氧元素濃度為未滿1.2X 1018atoias/ein3 (舊 AST Μ)之低氧濃度。要使其成為此氧元素濃度，則例如控 制氩氣之流量為80〜150公升/分、儲存矽溶融物之石英坩 鍋之轉動速度為4〜9γρβι、熱區爐内之壓力為15〜6QTorr。 切削Μ上逑條件拉上之晶錠而製成之矽晶圓在遷元性 環境下，Κ1050〜1220 °C之溫度範圍進行30〜150分鐘之 熱處理後，縱使起因於矽單结晶中之氧原子而形成之未滿 0.12am之C0P之數目在3〜10個/ cm2之範圍時，若0.12以诅 K上之COP之數目也在〇·5個/cm2K下，特別是在0個/ cbi2 ，便會消失。此熱處理時之昇溫速度要在1 5 °C /分K下。 未滿上逑溫度及時間之下限值時C0P不會完全消失，超過 上限值時晶圓有可能被Fe等污染。其结果，整個晶片表面 之C0P之數目成為0個（無C0P)，獲得幾乎沒有Fe等之污 染或幾乎不會發生滑移之晶圓。遷元性環境為100%氫氣環 境，或氫氣與氩氣之混合環境，或者是氫氣與氮氣之混合 環境。 而切削以上述條件拉上之晶錠製成之矽晶圓在遷元性 環境下熱處理時，不但C0P會消失，同時晶圓内部，尤其 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 503463 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（l〇 ) 是從晶圓表面至至少深度G · 2 ^ m之範圍內之空孔型點缺陷 之凝集體也會消失。 【實施例】 其次將本發明之實施例與比較例一起說明如下。 〈實施例1> 將晶錠拉上，使其在晶錠之全長育成對懕第3圖·所示 位置Ρα之領域，旦K晶錠中心之軸方1¾之溫度坡度為Ga， K晶錠周緣之軸方商之溫度坡度為Gb時，V/Ga及V/Gb分 別成為約0.2 7 m ffl2/分· t。這時為了抑制晶錠中之氧元素 濃度，將氬氣之流量維持在約no公升/分*將儲存矽溶融 物之石英坩鍋之轉速維持在約5〜lGrpni，將熱區爐内之壓 力維持在約6 G T 〇 r r。 從如此拉上之晶錠切削之矽晶圓經研磨使邊緣成§1形 後*再鏡面研磨，準備直徑8时，厚度740^15之矽晶圓。 將準備之5片矽晶圓作為COP數之測量用，別的5片作為 晶圓中之氧濃度之測量用。 .〈實施例2> 將與實施例1同樣之方式獲得之矽晶圓用作檢査0SF 是否會顯現化。別的5片矽晶圓則在lflOX氫氣環境下， 以1130它之溫度熱處理90分鐘。 使用雷射顆粒計數器（KLA-Tencor公司製，SFS 6 2 0 0 ) 撿査實施例1之5片矽晶圓之表面之直徑200πιιπ之圓内 〇·12^πϊΚ上之C0P數。使用同一雷射顆粒計數器，根據 上述專利第2 5 2 0 3 1 6號之「矽晶圓之微小坑洞之撿出方法 -13- ， 本紙張尺度適闬中國國家標準（CNS)A4規格（210 X 297公釐） _ J --------tr--------- (請先閱讀背面之注意事項再填寫本頁) 503463 A7 - _B7_______五、發明說明（11 ) 」測量同一之5 H矽晶圓之表面之直徑200 mm圓内之〇· 12 ν 上之C0P數。 為了比較，使用同一雷射顆粒計數器測量時之大小未 滿0·12μβι之C0P數有5個/ cm2，上之C0P數有 1個/cm2之矽晶圓作為比較例1。將此比較例1之矽晶圓 與實施例2同一條件熱處埋，作為比較例2之矽晶圓。 使用二次離子質量分析（SIMS)測量簧施例1及比較 例1之另外5片矽晶圓之表面下5/i μ深度之氧元素濃度。 其平均值示於表1。 Κ高溫氧化之方法將實施例1及比較例2之各矽晶圓 Κ 1 0 (3 0 °C熱處理2小時，接著Κ 11 0 0 t：熱處 '理1 2小時，檢 査0SF是否會顯現化。再使用雷射顆粒計數器（KLA-Tencor 公司製，SFS6200)撿査剩下之5片矽晶圓之表面直徑200 mm之圓內（K12winK上之C0P數。使用同一雷射顆粒計數 器，根據上逑專利第2520316號之「矽晶圓之徼小坑洞之 撿出方法J測量同一之5片矽晶圓之表面直徑200 mm圓內 之0·12αΒΐΚ上之C0P數。此等之各平均值示於表1。 --------^---------線 < (請先閱讀背面之注意事項再填寫本頁) -J· I I J -MM9 VHMM MV 503463 A7 ________B7_ V. Description of the Invention (9) (Please read the precautions on the back before filling this page) This semiconductor device manufacturer will heat-treat the wafer during the semiconductor device manufacturing process, and will center the wafer to the periphery. All of the oxygen precipitates appeared and exerted the IG effect. In order to make this oxygen element concentration, for example, the flow rate of argon gas is controlled to 60 to 110 liters / minute, the rotation speed of a quartz crucible storing silicon melt is 4 to 12 rpni, and the pressure in the hot zone furnace is 20 to 60Torr. When a semiconductor device manufacturer does not need a silicon wafer that can exhibit the IG effect, the oxygen element concentration inside the wafer is made to be a low oxygen concentration of less than 1.2X 1018atoias / ein3 (old AST M). To make this oxygen concentration, for example, the flow rate of argon gas is controlled to 80 to 150 liters / minute, the rotation speed of the quartz crucible storing the silicon melt is 4 to 9 γρβι, and the pressure in the hot zone furnace is 15 to 6 QTorr . The silicon wafer produced by cutting the crystal ingot pulled on the upper surface of M is heat-treated at a temperature range of K1050 ~ 1220 ° C for 30 ~ 150 minutes under a migrating environment, even if the oxygen is caused by silicon single crystal. When the number of COPs under 0.12am formed by atoms is in the range of 3 to 10 pieces / cm2, if the number of COPs on 0.12 to curse K is also 0.5 pieces / cm2K, especially at 0 pieces / cbi2 , It will disappear. The temperature increase rate during this heat treatment should be at 15 ° C / minK. C0P will not completely disappear when the upper temperature and lower time limits are not exceeded, and the wafer may be contaminated with Fe or the like when the upper limit is exceeded. As a result, the number of COPs on the entire wafer surface becomes zero (no COP), and a wafer with little contamination of Fe or the like or almost no slippage is obtained. The migration environment is a 100% hydrogen environment, or a mixed environment of hydrogen and argon, or a mixed environment of hydrogen and nitrogen. When silicon wafers made by cutting ingots drawn under the above conditions are heat-treated in a migrating environment, not only will the C0P disappear, but also the inside of the wafer, especially -12- This paper size applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) 503463 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (10) is a hole type point within the range from the surface of the wafer to a depth of at least G · 2 ^ m Defects will disappear. [Examples] Next, examples of the present invention and comparative examples will be described below. <Example 1> The crystal ingot was pulled up so as to form a pair of regions in the position Pα shown in Fig. 3 over the entire length of the crystal ingot. The temperature gradient of the axis 1¾ of the center of the K crystal ingot was Ga, K crystal ingot. When the temperature gradient of the axial quotient of the periphery is Gb, V / Ga and V / Gb become about 0.2 7 m ffl2 / min · t, respectively. At this time, in order to suppress the oxygen element concentration in the ingot, the flow rate of argon gas is maintained at about no liters / minute. * The speed of the quartz crucible storing the silicon melt is maintained at about 5 to 1 Grpni, and the pressure in the hot zone furnace is maintained At about 6 GT 〇rr. The silicon wafer cut from the ingot thus pulled up is ground to a §1 shape after grinding * and then mirror-polished. A silicon wafer with a thickness of 740 ^ 15 when a diameter of 8 is prepared. The five silicon wafers prepared were used for measuring the COP number, and the other five wafers were used for measuring the oxygen concentration in the wafer. <Example 2> A silicon wafer obtained in the same manner as in Example 1 was used to check whether 0SF was visualized. The other 5 silicon wafers were heat-treated at 1130 for 90 minutes under the lflOX hydrogen environment. A laser particle counter (KLA-Tencor Corporation, SFS 6 2 0 0) was used to check the number of COP on the surface of the 5 silicon wafers of Example 1 within a circle of 200 μm in diameter and a diameter of 0. 12 ^ πϊK. Using the same laser particle counter, according to the above-mentioned patent No. 2520 0 16 16 "Method for picking up tiny pits in silicon wafers-13-", the paper size is in accordance with the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) _ J -------- tr --------- (Please read the notes on the back before filling this page) 503463 A7-_B7_______ V. Description of the invention (11 ) ”Measure the number of COP on a 12 mm circle within a circle of 200 mm in diameter on the same 5 H silicon wafer. For comparison, a silicon wafer having a size of less than 0 · 12μβι when measured by the same laser particle counter was 5 silicon wafers / cm2, and a silicon wafer having a C0P number of 1 / cm2 was used as Comparative Example 1. The silicon wafer of Comparative Example 1 was buried under the same conditions as in Example 2 and used as a silicon wafer of Comparative Example 2. The secondary ion mass analysis (SIMS) was used to measure the oxygen concentration at a depth of 5 / i μ below the surface of the other 5 silicon wafers of Spring Example 1 and Comparative Example 1. The average value is shown in Table 1. Κ High-temperature oxidation method The silicon wafers of Example 1 and Comparative Example 2 were heat-treated at κ 1 0 (3 0 ° C for 2 hours, followed by κ 11 0 0 t: heat treatment for 1 hour, and it was checked whether 0SF appeared. Then use a laser particle counter (KLA-Tencor, SFS6200) to check the remaining 5 silicon wafers with a diameter of 200 mm within the circle (C0P number on K12winK. Use the same laser particle counter, according to The method for picking up small pits in silicon wafers No. 2520316 of the above patent J measures the number of COPs on 0 · 12αΒΐΚ in a circle of 200 mm diameter of the same 5 silicon wafers. These averages The values are shown in Table 1. -------- ^ --------- line < (Please read the precautions on the back before filling this page) -J · IIJ-
J t .14. 本紙張尺度適兩中國國家標準（CNS)A4規格（210 X 297公釐） 503463 A7 B7 五、發明說明（12 ) 【表1】 C0P之數目（涸/cm2) 氧元素濃度 X ίο19 (atoffls/cm3) (舊 ASTM) 有無 0SF 氫氧熱處理前 氫氧熱處理後 <0.12/i μ ^0.12/ti m <0.12 jU hi ^QAZum 實施例1 6· 5 0.35 — — 1.32 — 實施例2 -- 一 0 0 . 一 迦 *\\\ 比較例1 5 1 -- 一 1.34 一一 比較例2 -- —— 2 0.5 有 P ------------------ (請先閱讀背面之注意事項再填寫本頁) 訂 線 從表1可K看清楚，未滿0.12/iffi之COP之數目，比 較例1之矽晶圓是5個/era2但實施例1之矽晶圓是平均 6·5個/ cm2。而〇·12“ιηΜ上之COP之數目，比較例1之 矽晶圓是1個/cm2»但實施例1之矽晶圓則是平均Q.35個 /cm2。實施例1及比較例1之氧元素濃度均是約1.3X10" atoms/cffl3，很適合IG用晶圓。 而比較例2之矽晶圓之0 S F顯現化，且此晶圓之未滿 0 . 12 μ COP之數目為平均2個/ cm2，0·12^ιηΚ上之COP 之數目為平均0.5個/ cm2，對此，實施例2之矽晶圓之〇SF 未顯現，且此晶圓之未滿0.12/i a之COP未被檢出，〇· 12 “ fflM上之C0P也未被檢出。 亦即，比較例1之晶圓所存在之未滿0. 12 y a之C0P ’ 在經氫氣環境下之熱處理之比較例2之晶圓並未消失。此 -15· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 503463 A7 __B7__ 五、發明說明（13) 現象應該是，比較例1之晶圓之COP較實施例1之晶圓之 COP大，1130 °C左右之溫度不會完全消失之故。 〈實施例3> 將與實施例1同樣之方式獲得之矽晶圓，在1 Q 0 X氫 氣之環境下，分別 Μΐ〇5〇υ、ιιοου、ii5〇°c、ΐ2〇ου 及 1220 υ之溫度熱處理90分鐘。而對此等經過熱處理之矽晶 圓進行氧化膜耐壓（TZDB)之測量。此項測量係在晶圓之 表面形成厚度9Π1Π之氧化膜，在其上面形成電極，施加10 ΜV/CIS之電壓應力，而檢查各晶圓之良品率。其结果示於 第6圖。 〈比較例3> 將與實施例1同樣之方式獲得之5片矽晶圓，在100% 氳氣之環境下，分別 K 1 〇 5 0 °C、11 0 (TC、11 5 0 °C、1 2 0 0 t! 及1220t!之溫度熱處理90分鐘。而對此等經過熱處理之矽 晶圓進行與實施例3 —樣之氧化膜耐壓（TZDB)測量，檢 査各晶圓之良品率。其结果示於第6圖。 從第6圖可K明白，比較例3是在1 1 5 0 υ良品率才到 達90% Κ上，對此實施例3之良品率從1050¾到1220”差 不都在100%。 〈實施例4> 將與簧施例1同樣之方式獲得之5片矽晶圓，分別在 100¾氫氣之環境下，Κ113〇υ之溫度熱處理90分鐘。模仿 半導體装置製程之熱處理，在此晶圓表面形成厚度500nm 之氧化膜。然後K氟酸去除此氧化膜後，在去除此氧化膜 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -l·. 裝J t .14. This paper is suitable for two Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 503463 A7 B7 V. Description of the invention (12) [Table 1] Number of C0P (涸 / cm2) Oxygen concentration X ίο19 (atoffls / cm3) (formerly ASTM) Presence or absence of 0SF before and after oxyhydrogen heat treatment After oxyhydrogen heat treatment <0.12 / i μ ^ 0.12 / ti m < 0.12 jU hi ^ QAZum Example 1 6 · 5 0.35 — — 1.32 — Example 2-One 0 0. One Gia * \\\ Comparative Example 1 5 1-One 1.34 One Comparative Example 2----- 2 0.5 With P ------------- ----- (Please read the precautions on the back before filling in this page) The order line can be seen clearly from Table K. The number of COPs less than 0.12 / iffi, the silicon wafer of Comparative Example 1 is 5 / era2 However, the silicon wafers of Example 1 had an average of 6.5 pieces / cm2. In contrast, the number of COPs on 〇.12 "m, the silicon wafer of Comparative Example 1 is 1 piece / cm2», but the silicon wafer of Example 1 is an average Q.35 pieces / cm2. Example 1 and Comparative Example 1 The oxygen element concentration is about 1.3 × 10 " atoms / cffl3, which is very suitable for IG wafers. The 0 SF of the silicon wafer of Comparative Example 2 was visualized, and the number of wafers less than 0. 12 μ COP was The average number of COPs on 2 / cm2 and 0 · 12 ^ ιηκ is 0.5 / cm2. In this regard, the 0SF of the silicon wafer of Example 2 does not appear, and the wafer is less than 0.12 / ia. The COP was not detected, and the COP on fflM was not detected. That is, the wafer of Comparative Example 1 which has a COP 'of less than 0.12 y a under the heat treatment in a hydrogen atmosphere does not disappear. This -15 · This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 503463 A7 __B7__ V. Description of the invention (13) The phenomenon should be that the COP of the wafer of Comparative Example 1 is larger than that of Example 1 The COP of the wafer is large, and the temperature around 1130 ° C will not completely disappear. <Example 3> The silicon wafer obtained in the same manner as in Example 1 was subjected to a 1 Q 0 X hydrogen atmosphere, respectively, Μΐ〇〇〇〇, ιιοου, ii50〇 ° C, ΐ2〇ου, and 1220 υ Heat treatment for 90 minutes. For these heat-treated silicon wafers, the oxide film withstand voltage (TZDB) was measured. This measurement is to form an oxide film with a thickness of 9Π1Π on the surface of the wafer, form an electrode on it, and apply a voltage stress of 10 MV / CIS to check the yield of each wafer. The results are shown in Fig. 6. <Comparative Example 3> Five silicon wafers obtained in the same manner as in Example 1 were respectively K 1 0 5 0 ° C, 11 0 (TC, 11 5 0 ° C, Heat treatment was performed at a temperature of 1 2 0 0 t! And 1220 t! For 90 minutes. The silicon wafers subjected to the heat treatment were subjected to the same measurement of the oxide film withstand voltage (TZDB) as in Example 3 to check the yield of each wafer. The results are shown in Fig. 6. As can be understood from Fig. 6, it can be seen from Comparative Example 3 that the yield rate of Comparative Example 3 reached 90% κ at 1 1 50 0. The yield rate of Example 3 from 1050¾ to 1220 "is almost the same. All of them are 100%. <Example 4> Five silicon wafers obtained in the same manner as in Example 1 were heat-treated in a 100¾ hydrogen atmosphere at a temperature of κ113〇υ for 90 minutes. A heat treatment that mimics the semiconductor device process An oxide film with a thickness of 500 nm is formed on the surface of this wafer. After removing the oxide film by K-fluoric acid, the paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (please first Read the notes on the back and fill out this page) -l ·.
503463 A7 __ B7__ 五、發明說明（l4 ) 之晶圓表面再度形成厚度9nm之氧化膜，進行與實施例3 一樣之氧化膜耐壓（TZDB)測量，檢査各晶圓之良品率。 其结果示於第7圖。 〈比較例4 > 將與實施例1同樣之方式獲得之5片矽晶圓，分別與 實施例4相同之條件進行熱處理、形成氧化膜、去除氧化 膜、及氧化膜之再形成，進行與實施例3 —漾之氧化膜耐 壓（TZDB)測量，檢査各晶圓之良品率。其结果示於第7 圖。 從第7圖可K看出，比較例4之良品率在60¾前後， 對此，實旅例4之良品率差不多在ιοο%。從這一事實可以 知道，實施例4之經氫氣熱處理後之晶圓至少從表面至深 度a完全不存在有空孔點缺陷之凝集體。 〈實施例5> 經齊郎1 曰慧时轰¾員X.消費合阼fi印製 (請先閱讀背面之注意事項再填寫本頁) 將與實施例1同樣之方式獲得之矽晶圓，在100%氫 氣之環境下，M113Q°C之溫度熱處理90分鐘。KSC-1洗 淨液（NHsOH: H2〇2: H2〇=l: 1: 5)返覆洗淨此晶圓，而 従晶圓表面向深度方向KO.liU ffi、0.2m ffl、〇.3以in、0.4 /im、G.5w in分階段蝕刻。各階段均Κ雷射顆粒計數器（ KLA-Tencor公司製，SFS6200)測量晶圓表面之COP數。 其结果不於第8圖0 〈比較例5 > 將與比較例1同樣之方式獲得矽晶圓，與實施例5相 同之條件進行熱處理後，返覆K S C - 1洗淨液洗淨，而分 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐） 503463 A7 B7 五、發明說明（IS ) P皆段刻。κ跟實施例5栢同之雷射顆粒計數器測量晶圓 之C0P數。其结果示於第8圖。 從第8圖可K明白，從晶圓表面之深度愈大，比較例 5之矽晶圓之C 0 P數愈增多，但實施例5之矽晶圓則維持 無c〇P之狀態。 圖式之簡軍說明 第1圖係表示本發明之實施形態之依據Bornkov之理 論之V/G比與空孔型點缺陷濃度或格子間矽型點缺陷濃度 之關係之圖。 第2圖係表示決定所希望之拉上速度輪廓之拉上速度 之變化之特性圖。 第3圖係表示本發明之實施形態之基準晶錠之空孔型 點缺陷佔優勢之領域，格子間矽型點缺陷佔優勢之領域及 完整領域之X線斷層照相之概略圖。 第4圖係表示在對應第3圖之位置Pi之矽晶Wi出現0SF .之狀況之圖。 遂齊Sri曰¾讨轰笱員1.消費^阼^印^ (請先閱讀背面之注意事項再填寫本頁) 第5圖係表示在對應第3圖之位置PB之本發明之實施 形態之矽晶Wa不出現0SF之狀況之圖。 第6圖係表示實施例3與比較例3之氫氣環境下之熱 處理溫度與氧化膜耐壓（T Z D B )之關係之圖。 第7圖係表示實_例4與比較例4之氧化膜再肜成後 之氧化膜耐壓（TZDB)之關係之圖。 第8圖係表示因實施例5與比較例5之返覆SC-1洗 本紙張尺度適闬中國ϋ家標準（CNS)A4規格（210 x 297公爱） 503463 A7 B7 五、發明說明（I6 )淨，出現在晶圓表面之c 〇 p之變化狀況之圖。 符號說明Wl〜------晶圓 (請先閱讀背面之注意事項再填寫本頁) ---11---訂------I ---遠 %, 經濟部智慧財產局員工消費合作社印製 一 19- 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公爱）503463 A7 __ B7__ 5. In the description of the invention (l4), an oxide film with a thickness of 9 nm was formed on the surface of the wafer again. The oxide film withstand voltage (TZDB) measurement was performed as in Example 3 to check the yield of each wafer. The results are shown in FIG. 7. <Comparative Example 4> Five silicon wafers obtained in the same manner as in Example 1 were respectively heat-treated under the same conditions as in Example 4 to form an oxide film, remove the oxide film, and reform the oxide film. Example 3—Measurement of TZDB's withstand voltage (TZDB), check the yield of each wafer. The results are shown in Figure 7. It can be seen from FIG. 7 that the yield of the comparative example 4 is around 60¾, and the yield of the actual travel example 4 is almost ιοο%. From this fact, it can be known that the wafer subjected to the hydrogen heat treatment in Example 4 does not have aggregates having void hole defects at least from the surface to the depth a at least. <Example 5> Printed by Qi Lang1, Hui Shihong ¾ member X. Consumption combined with fi (Please read the precautions on the back before filling this page) The silicon wafer obtained in the same way as in Example 1, Under the environment of 100% hydrogen, heat treatment at M113Q ° C for 90 minutes. KSC-1 cleaning solution (NHsOH: H2〇2: H2〇 = 1: 1: 5) repeatedly cleaned the wafer, and the surface of the wafer in the depth direction KO.liU ffi, 0.2m ffl, 0.3 Etching at in, 0.4 / im, G.5w in stages. A laser particle counter (KLA-Tencor, SFS6200, manufactured by KLA-Tencor) measures the COP number on the wafer surface at each stage. The result is not as shown in FIG. 8 (Comparative Example 5). A silicon wafer was obtained in the same manner as in Comparative Example 1, and after the heat treatment was performed under the same conditions as in Example 5, the KSC-1 washing liquid was returned and washed. The paper size applies the Chinese national standard (CNS> A4 specification (210 X 297 mm) 503463 A7 B7 V. The description of the invention (IS) P is a period of time. Κ is the same as the laser particle counter used in Example 5 for measuring wafers The C0P number is shown in Fig. 8. As can be understood from Fig. 8, the larger the depth of the wafer surface, the more the C 0 P number of the silicon wafer of Comparative Example 5, but the silicon of Example 5 The wafers remain in the state of no cOP. Brief description of the drawings The first figure shows the V / G ratio and the void-type point defect concentration or inter-lattice silicon-type points according to Bornkov's theory according to the embodiment of the present invention. A graph showing the relationship between the defect concentrations. Fig. 2 is a characteristic diagram showing a change in the drawing speed that determines a desired drawing speed profile. Fig. 3 is a hole type point defect showing a reference crystal ingot according to an embodiment of the present invention. Dominant fields, inter-lattice silicon point defects, and X-rays of complete fields The schematic diagram of the layer photography. Fig. 4 is a diagram showing the situation where 0SF. Appears in the silicon crystal Wi of the position Pi corresponding to Fig. 3. Sui Qi Sri said ¾ to discuss the members 1. Consumption ^ 阼 ^ 印 ^ (Please (Read the precautions on the back before filling in this page.) Figure 5 shows the situation where the silicon wafer Wa of 0SF does not appear in the embodiment of the present invention corresponding to the position PB in Figure 3. Figure 6 shows Example 3. A graph showing the relationship between the heat treatment temperature and the oxide film withstand voltage (TZDB) in the hydrogen environment of Comparative Example 3. Fig. 7 shows the oxide film withstand voltage after the oxide films of Example 4 and Comparative Example 4 were re-formed ( TZDB). Figure 8 shows the SC-1 wash paper size for the response of Example 5 and Comparative Example 5. The paper is suitable for the Chinese Standard (CNS) A4 (210 x 297 public love) 503463 A7 B7 V. The description of the invention (I6) is a graph showing the change of c 〇p appearing on the wafer surface. Symbol description Wl ~ ------ Wafer (Please read the precautions on the back before filling this page) --- 11 --- Order ------ I --- Far%, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 19- This paper size applies to Chinese National Standard (CNS) A 4 specifications (210 X 297 public love)