WO2011105283A1 - Spherical compound semiconductor cell, solar cell module, and methods for manufacturing the spherical compound semiconductor cell and the solar cell module - Google Patents
Spherical compound semiconductor cell, solar cell module, and methods for manufacturing the spherical compound semiconductor cell and the solar cell module Download PDFInfo
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- WO2011105283A1 WO2011105283A1 PCT/JP2011/053407 JP2011053407W WO2011105283A1 WO 2011105283 A1 WO2011105283 A1 WO 2011105283A1 JP 2011053407 W JP2011053407 W JP 2011053407W WO 2011105283 A1 WO2011105283 A1 WO 2011105283A1
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- DVRDHUBQLOKMHZ-UHFFFAOYSA-N chalcopyrite Chemical group [S-2].[S-2].[Fe+2].[Cu+2] DVRDHUBQLOKMHZ-UHFFFAOYSA-N 0.000 claims abstract description 20
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- 229910052725 zinc Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/03529—Shape of the potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
- H01L31/03923—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including AIBIIICVI compound materials, e.g. CIS, CIGS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
- H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
- H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
- H01L31/0465—PV modules composed of a plurality of thin film solar cells deposited on the same substrate comprising particular structures for the electrical interconnection of adjacent PV cells in the module
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0749—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/541—CuInSe2 material PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a method for manufacturing a spherical solar battery cell and a modularization technique, and more particularly to a method for manufacturing a spherical compound semiconductor cell using a compound semiconductor with high energy conversion efficiency and a modularization technique.
- a chalcopyrite compound semiconductor used as an absorption layer of a solar cell has been conventionally produced, for example, using a two-stage process as shown in FIGS. 9 (a) and 9 (b). That is, an electrode 22 made of Mo or the like is formed on the substrate 21, and a Cu thin film 23 and an In thin film 24 are stacked on the electrode 22 so that the film thickness ratio thereof is about 1: 2.2 to 2.4. Then, the substrate is heat-treated in a chalcogen atmosphere such as Se or S, or in a gas containing chalcogen, such as H 2 Se or H 2 S , to form a CuInS 2 , CuInSe 2 or CuInTe 2 thin film as the chalcopyrite type compound thin film 25. ing.
- a chalcogen atmosphere such as Se or S
- a gas containing chalcogen such as H 2 Se or H 2 S
- a chalcogenite thin film 27 of CuInS 2 , CuInSe 2, or CuInTe 2 is formed by depositing a chalcogen thin film 26 of S, Se, Te or the like, performing a heat treatment, and performing a solid phase reaction.
- an increase in the specific surface area of the absorption layer can be cited as one of methods for increasing the photoelectric conversion efficiency of the solar cell and improving the performance.
- a process of forming a texture structure or a concavo-convex structure on the surface of the photoelectric conversion layer, a specific surface area with respect to the projected area, and a spherical structure capable of absorbing incident light in all directions There are solar cells.
- spherical solar cells when spherical solar cells are modularized, they can be installed on curved surfaces, increase efficiency by increasing the specific surface area with respect to the projected area, and have little dependency on incident light angle, resulting in extreme power generation efficiency with respect to changes in incident light angle. Expectations are high, such as the effect of suppressing performance degradation.
- Patent Documents 1 to 3 as prior art relating to spherical solar cells.
- JP 2001-177121 A Japanese Patent Laid-Open No. 2004-203652 JP 2004-104138 A
- the spherical solar cells currently on the market are products mainly using silicon-based materials, and the spherical solar cells using the above compound semiconductors have not been studied.
- spherical silicon solar cells have many problems, such as the absence of the application of an antireflection coating that compensates for the high refractive index of the silicon material and the texture structure that achieves the effect of increasing the specific surface area that has been implemented in conventional silicon solar cells.
- spherical crystal silicon is generally produced by a melt dropping method to form a spherical electrode, it is not suitable for mass production, and it is difficult to obtain guidelines for future production cost reduction.
- An object of the present invention is to provide a spherical compound semiconductor cell using a compound semiconductor film capable of suppressing recombination and leakage leakage current.
- a spherical compound semiconductor cell includes a spherical electrode having at least a surface as a conductor, a compound semiconductor layer having a chalcopyrite structure formed on the surface of the spherical electrode, and the compound semiconductor layer. And a transparent electrode layer formed on the surface of the buffer layer.
- the solar cell module of the present invention includes a spherical electrode having at least a surface as a conductor, a compound semiconductor layer having a chalcopyrite structure formed on the surface of the spherical electrode, and a buffer layer formed on the surface of the compound semiconductor layer
- a spherical compound semiconductor cell having a transparent electrode layer formed on the surface of the buffer layer and having a surface on which the conductor of the spherical electrode is exposed; and a through-hole having a predetermined pattern on the surface of the conductive support substrate
- a plurality of the spherical compound semiconductor cells disposed in the through-hole portion of the insulating layer, and the conductor of the spherical electrode and the conductive support substrate are electrically connected to each other. Characterized by the structure.
- mechanical milling is performed by mixing at least a spherical electrode whose surface is a conductor and a powder of a single element material or compound element material containing a group Ib element, a group IIIb element and a group VIb element. And a step of forming a compound semiconductor layer having a chalcopyrite structure on the surface of the spherical electrode.
- FIG. 1 shows a configuration of an example of an embodiment of the present invention, and shows a double-sided connection module diagram, where (a) is a symmetrical arrangement of spherical cells, and (b) is an alternating arrangement. is there.
- (A) to (c) show different wiring electrode patterns on the insulating substrate, and series-parallel connection can be realized at the time of cell arrangement.
- (A) and (b) are photographs respectively showing before and after the formation of the compound semiconductor film on the spherical electrode by the method of the embodiment of the present invention.
- (A) and (b) are photographs respectively showing before and after the reaction of the compound semiconductor film by the heat treatment of the embodiment of the present invention. It is a figure which shows the X-ray-diffraction result of a compound semiconductor film.
- the manufacturing process of the conventional chalcopyrite type compound thin film is shown, (a) is a figure which shows the process of laminating
- the manufacturing process of the conventional chalcopyrite type compound thin film is shown, (a) is a figure which shows the process of laminating
- FIG. 1 shows an example of a device cross-sectional view in which spherical compound semiconductor cells according to an embodiment of the present invention are arranged and modularized.
- the spherical compound semiconductor cell of this embodiment includes at least one compound semiconductor layer 2 on at least the entire surface or a part of the surface of the spherical electrode 1 whose surface (layer) 1b is a conductor, and the compound semiconductor layer 2
- the buffer layer 3 deposited on the buffer layer 4, the buffer layer 4 deposited on the buffer layer 3, and the transparent electrode layer 5 deposited on the buffer layer 4.
- the layer 6 is provided.
- the spherical compound semiconductor cell may have a configuration in which the buffer layer 4 and the antireflection layer 6 are omitted.
- FIG. 1 (a) As a solar cell module in which spherical compound semiconductor cells are arranged and modularized, an example of a parallel connection module is shown in FIG. 1 (a), and an example of a series connection module is shown in FIG. 1 (b).
- an insulating layer 8 (insulating substrate, substrate) is formed on the surface of the conductive support substrate 10, and the insulating layer 8 is formed in FIGS. 5A and 5C. As shown in FIG. 5, the through holes are formed in a predetermined pattern.
- An electrode lead line 7 connected to the conductive support substrate 10 is formed in the through hole of the insulating layer 8.
- a wiring electrode 9 (hereinafter also referred to as “wiring electrode layer”) is formed on the surface of the insulating layer 8 in a predetermined pattern.
- a spherical compound semiconductor cell is disposed in the through hole portion of the insulating layer 8 to constitute a solar cell module.
- the spherical compound semiconductor cell is processed so that the spherical electrode 1 is exposed at a part of the surface.
- the exposed spherical electrode 1 and the electrode lead wire 7 are electrically connected, the transparent electrode layer 5 and the wiring electrode layer are electrically connected, and the spherical electrode 1 and the transparent electrode layer 5 are insulated by the insulating layer 8 It has become.
- the spherical electrodes 1 of the plurality of spherical compound semiconductor cells are electrically connected by the electrode lead wire 7 and the conductive support substrate 10, and the transparent electrode layers 5 are electrically connected by the wiring electrode 9. It has a connected structure.
- the insulating layer 8 and the wiring electrode 9 are formed on the surface of the conductive support substrate 10 in a predetermined pattern as shown in FIG. 5B.
- the insulating layer 8 has through holes formed in a predetermined pattern as shown in FIG. In the through hole of the insulating layer 8, an electrode lead line 7 connected to the conductive support substrate 10 is formed.
- a spherical compound semiconductor cell is disposed in the through hole portion of the insulating layer 8 to constitute a solar cell module. At this time, the spherical compound semiconductor cell is processed so that the spherical electrode 1 is exposed at a part of the surface.
- the exposed spherical electrode 1 and the electrode lead wire 7 are electrically connected, and the transparent electrode layer 5 and the wiring electrode layer are electrically connected.
- the series connection module has a structure in which the spherical electrode 1 and the transparent electrode layer 5 of the adjacent spherical compound semiconductor cell are electrically connected by the electrode lead wire 7, the conductive support substrate 10, and the wiring electrode 9.
- An insulating layer 8 is formed on the conductive support substrate 10 so that the spherical electrode 1 and the transparent electrode layer 5 of one spherical compound semiconductor cell are not short-circuited.
- a structure in which the compound semiconductor layer 2, the buffer layer 3, and the buffer layer 4 are formed in this order on the surface 1b of the spherical electrode 1 is formed.
- the structure is arranged in the through hole portion of the insulating layer 8 having the through hole.
- each layer within the range that fits in the through hole in the lower bottom portion of the structure is removed to the surface 1b of the spherical electrode 1, and a conductive material such as a conductive adhesive is used for the spherical electrode 1 in the through hole.
- An electrode lead line 7 is formed.
- the electrode lead wire 7 is connected to one side or both sides of the conductive support substrate 10.
- a semiconductor module is obtained by forming the transparent electrode layer 5 and the antireflection layer 6 on the buffer layer 4.
- a semiconductor module is obtained by forming the transparent electrode layer 5 and the antireflection layer 6 on the buffer layer 4.
- the spherical compound semiconductor cells are regularly arranged in the through-hole portions of the insulating layer 8 having through-holes, and an electrode is obtained through the through-holes to ensure electrical insulation from the transparent electrode on the cell surface, and spherical A compound semiconductor cell can be arranged finely and a high performance solar cell module can be provided.
- At least the surface 1 b is a conductor, forms an electrical junction such as an ohmic junction with the compound semiconductor layer 2, and has excellent chemical or physical junction.
- Materials with no are preferred.
- a metal material such as Mo, Al, Ni, Ti, Cu, Mg, Li, and Fe corresponds to this, but is not limited thereto, and may be a highly conductive organic compound conductive material or inorganic compound material.
- the core 1a of the spherical electrode 1 is preferably made of a material having high thermal stability during the process and having as low a moisture and oxygen permeability and absorption rate as possible. If flexibility is not required, it may be an inorganic material such as zirconia stabilized yttrium (YSZ) or glass, or a metal plate or ceramic plate such as zinc, aluminum, stainless steel, chromium, tin, nickel, iron or nickel copper. .
- YSZ zirconia stabilized yttrium
- metal plate or ceramic plate such as zinc, aluminum, stainless steel, chromium, tin, nickel, iron or nickel copper.
- polyesters such as polyethylene terephthalate, polybutylene phthalate, polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycycloolefin, norbornene resin, poly (chlorotrifluoroethylene) ) And other organic materials.
- An opaque plastic substrate may also be used.
- the spherical electrode 1 has a diameter of 100 ⁇ m to 10 cm.
- the diameter is smaller than 100 ⁇ m, powder synthesis and a heterogeneous reaction mixture are formed in the step of forming the compound semiconductor layer 2 on the surface 1b of the spherical electrode 1, and Ib-VIb-VIb It may become an impurity in the compound phase. Further, it has been experimentally found that when the diameter is larger than 10 cm, it is difficult to form the compound semiconductor layer 2 on the spherical electrode 1.
- a hemispherical shape, an ellipsoidal shape, or a divided shape of those spheres can also be used.
- the compound semiconductor layer 2 is prepared by mixing a spherical electrode 1 whose surface 1b is a conductor and a powder of a single element material or a compound element material containing a group Ib element, a group IIIb element and a group VIb element, and subjecting it to a mechanical milling process.
- the compound semiconductor layer 2 can be formed on the surface 1b of the spherical electrode 1.
- a powder of a single element material or a compound element material containing a group Ib element, a group IIIb element and a group VIb element a single element material of a group Ib element, a group IIIb element and a group VIb element, or an Ib-VIb compound and a group IIIb-VIb compound
- plural kinds of powders of compound element materials such as a VIb group element compound or an Ib-VIb-VIb compound can be used.
- a ball mill, sand mill, bead mill, or the like can be applied.
- the compound semiconductor layer 2 constitutes a concavo-convex film in which crystal grains having a length in a one-dimensional direction of 5 nm to 100 ⁇ m are connected.
- the a-axis: 0.5 nm and the c-axis: 1.1 nm are common, and the crystal grain size is a minimum of 5 nm if 10 layers are laminated in the a-axis direction.
- the diameter of the spherical electrode 1 is 10 mm
- the thin film surface has a concavo-convex structure having steps and periods of 5 nm to 100 ⁇ m.
- the increase rate of the surface area of the compound semiconductor film with respect to the surface area of the spherical electrode 1 is 1.001 times to 20000 times.
- the compound semiconductor layer 2 has a material-specific band gap of 0.1 to 5 eV, and the compound semiconductor layer 2 has an absorption coefficient of 1 ⁇ 10 3 to 1 ⁇ 10 10 cm ⁇ 1 at a wavelength of 450 nm to 500 nm.
- the film thickness is deposited to 5 nm to 500 ⁇ m.
- the film thickness of the compound semiconductor layer 2 is determined in consideration of the light absorption coefficient of the compound semiconductor material. As the light absorption coefficient of the material is higher, the film thickness can be reduced and the resistance component of the material is not affected.
- the film thickness is increased, the insulating element is increased and the electrical performance is decreased.
- the solar spectrum in the wavelength region of 450 nm to 500 nm has a very high energy density.
- the compound semiconductor layer 2 has a film thickness of 100 nm and an absorption coefficient of 1 ⁇ 10 3 cm. When it is smaller than -1 , energy is hardly absorbed. Further, when it is assumed that all light is absorbed at a film thickness of 100 nm, the absorption coefficient is approximately 1 ⁇ 10 10 cm ⁇ 1 . Ideally, if the absorption coefficient of the compound semiconductor layer 2 having a wavelength of 450 nm to 500 nm is 1 ⁇ 10 5 cm ⁇ 1 , a film thickness of about 3 ⁇ m to 10 ⁇ m is sufficient.
- Examples of the formation method of the buffer layer 3 include a vacuum vapor deposition method, a sputtering method, an ion plating method, a physical vapor deposition method such as an MBE method, or a CVD method such as plasma polymerization.
- a coating method such as a cast method, a spin coating method, a dipping method, an LB method, a chemical solution deposition method, a sol-gel method, or the like can be used.
- a printing method such as ink jet printing or screen printing, or a transfer method such as thermal transfer or laser transfer may be used. Patterning may be performed by chemical etching such as photolithography, physical etching using ultraviolet rays or lasers, or by vacuum deposition or sputtering with a mask overlapped, or lift-off. Method, printing method, transfer method may be used.
- the role of the buffer layer 3 is mainly to form a reaction product with the compound semiconductor layer 2 at the interface with the compound semiconductor layer 2 and to form a pn junction between the reaction product and the compound semiconductor layer 2. Photoelectric conversion is performed by the pn junction.
- the buffer layer 3 may have a function of forming a reaction product with the material constituting the buffer layer 4 at the interface with the buffer layer 4.
- a metal oxide, a metal sulfide, and a metal nitride can be used as such a buffer layer 3.
- metal oxide As the metal oxide, ZnO, MgTiO 3 , BaTiO 3 , TiO, MgO, SrO, ZrO, CdO, TiZrO 2 , metal sulfides include ZnS, TiS 2 , ZrS, MgS, MgTiS 3 , CdS, and metal nitrides include Zn 3 N 2 , TiN, Mg 3 N 2 .
- Examples of the method for forming the buffer layer 4 include a vacuum vapor deposition method, a sputtering method, an ion plating method, a physical vapor deposition method such as an MBE method, or a CVD method such as plasma polymerization.
- a coating method such as a cast method, a spin coating method, a dipping method, an LB method, a chemical solution deposition method, a sol-gel method, or the like can be used.
- a printing method such as ink jet printing or screen printing, or a transfer method such as thermal transfer or laser transfer may be used. Patterning may be performed by chemical etching such as photolithography, physical etching using ultraviolet rays or lasers, or by vacuum deposition or sputtering with a mask overlapped, or lift-off. Method, printing method, transfer method may be used.
- the role of the buffer layer 4 is to match the energy levels of the transparent electrode layer 5 and the buffer layer 3. By matching the energy levels in this way, it is possible to prevent carriers that have undergone charge separation between the compound semiconductor layer 2 and the reaction product from recombining between the buffer layer 3 and the transparent electrode layer 5. Further, this can suppress the leakage current. Further, when all of the buffer layer 3 forms a reaction product with the compound semiconductor layer 2, it is difficult to match the energy level of the reaction product and the transparent electrode layer 5, and recombination is likely to occur at the interface between the two. By providing the buffer layer 4, recombination and leakage leakage current can be suppressed by matching the energy ranking of the reaction product of the buffer layer 3 and the compound semiconductor layer 2 and the transparent electrode layer 5.
- a metal oxide can be used, and examples of the metal oxide include ZnO, MgTiO 3 , BaTiO 3 , TiO, MgO, SrO, ZrO, CdO, and TiZrO 2 . It is preferable that a reaction product of the constituent material of the buffer layer 3 and the constituent material of the buffer layer 4 is formed in the vicinity of the interface between the buffer layer 3 and the buffer layer 4. In addition, a reaction product of the constituent material of the buffer layer 4 and the constituent material of the transparent electrode layer 5 is preferably formed in the vicinity of the interface between the buffer layer 4 and the transparent electrode layer 5. If the buffer layer 3 has the function of the buffer layer 4, the buffer layer 4 can be omitted.
- the transparent electrode layer 5 is a visible light transmissive conductive film deposited by a thin film forming method such as sputtering, CVD, sol-gel, or coating pyrolysis, and includes indium tin oxide (ITO), zinc oxide (ZnO), Tin (SnO 2 ) or the like, and poly (3,4-ethylenedioxythiophene) -poly- (styrenesulfonate) (PEDOT: PSS) can be used as the organic material, but this is not restrictive.
- ITO indium tin oxide
- ZnO zinc oxide
- Tin Tin
- PEDOT poly (3,4-ethylenedioxythiophene) -poly- (styrenesulfonate)
- the antireflection layer 6 can be realized by a technique of forming an antireflection film as a method for reducing the surface reflection of light. This is to form a transparent film having a refractive index intermediate between that of the compound semiconductor absorption layer and air on the outermost surface, thereby suppressing the reflectance by utilizing the light interference effect.
- the antireflection film there is a single-layer structure of a titanium oxide (TiO 2 ) film or a silicon nitride (SiN) film formed by a chemical vapor deposition (CVD) method or the like.
- CVD chemical vapor deposition
- the electrode lead wire 7 is electrically and physically bonded to the conductive material on the surface of the spherical electrode 1 and has a structure excellent in adhesion and conductivity. Although it can be formed with a silver paste material or a conductive adhesive material, it is not limited thereto.
- the insulating layer 8 may have flexibility as well as a solid substrate that does not allow bending.
- the through-hole structure has a columnar structure, a cone structure, or a three-dimensional figure structure of a truncated cone, and is characterized by holding a spherical compound semiconductor cell. That is, it is necessary that the pores are smaller than the diameter of the spherical compound semiconductor cell. Further, gaps generated after being held can be compensated with an insulating material. For example, an insulating resin material corresponds to this.
- the wiring electrode 9 uses a conductive material, and can be formed in various pattern shapes on the conductive support substrate 10 on which the insulating layer is formed, as shown in FIGS. As a result, cell series-parallel can be realized.
- the conductor, the spherical compound layer, and the buffer layer 3 on the surface 1b of the spherical electrode 1 of the spherical compound semiconductor cell are physically and electrically insulated and are physically and electrically joined to the transparent electrode layer 5. .
- the conductive support substrate 10 may be flexible as well as a solid substrate that does not allow bending, and the entire surface of the substrate or the contact point with the electrode lead wire 7 from the spherical conductor may be a conductive material.
- a metal material such as Mo, Al, Ni, Ti, Cu, Mg, Li, Fe, Au, or Ag corresponds to this, but is not limited thereto, and may be a highly conductive organic compound conductive material or inorganic compound material.
- Alkali metal single element or a compound thereof, or alkaline earth is present in any or all of the core 1a of the spherical electrode 1 or the layer between the core 1a and the conductor on the surface 1b, or between the conductor on the surface 1b and the compound semiconductor layer 2. It is preferable that an alkaline element such as a single metal element or a compound thereof is present. In addition, it is preferable that an alkaline element is also present in the compound semiconductor layer 2.
- Example 1 Cu powder, In powder, and sulfur powder were prepared as 0.05 mol, 0.05 mol, and 0.1 mol, respectively, and a spherical Mo ball having a diameter of 3 mm was prepared as the spherical electrode 1. These powders and balls were charged into a planetary ball mill container and milled for 1 hour with a planetary ball mill to form a compound semiconductor having a chalcopyrite structure of CuInS 2 on the spherical Mo surface.
- FIG. 6 shows a spherical ball photograph and a spherical compound semiconductor cell photograph before and after milling. Further, an electron micrograph of the compound semiconductor layer 2 deposited on the surface is shown in FIG.
- the spherical Mo substrate is not limited to this as long as Mo is deposited on at least the surface.
- the method is not limited to the planetary ball mill, and other methods such as a sand mill and a bead mill may be used.
- the compound semiconductor layer 2 having a large crystal grain size was obtained as shown in FIG.
- the surface unevenness is maintained, and the specific surface area is larger than the surface area of the spherical electrode 1.
- the heat treatment temperature is not limited to this, and heating may be performed at a temperature corresponding to the target crystal grain size and crystallinity.
- a 50 nm-thick CdS film was deposited on the surface of the compound semiconductor layer 2 by a chemical solution deposition method to form a buffer layer 3 (first buffer layer).
- the chemical solution deposition method was performed by immersing in a chemical solution having a constant temperature of 40 ° C. or higher with the compound semiconductor layer 2 deposited on the spherical electrode 1.
- the film thickness may be 50 nm to 100 nm, and the film formation is not limited to this method, and a sol-gel method, a vapor deposition method, a sputtering method, or the like may be used.
- a solution of non-doped ZnO was applied by a sol-gel method, followed by drying at 100 ° C.
- the film formation of the buffer layer and the transparent electrode layer 5 may be a solution coating method, a vacuum deposition method, a sputtering method, or the like.
- Example 2 In the spherical compound semiconductor cell of Example 1, a titanium oxide (TiO 2 ) film was formed as the antireflection layer 6 on the surface of the transparent electrode layer 5 by a chemical vapor deposition (CVD) method.
- CVD chemical vapor deposition
- Example 3 In Example 1, the spherical electrode 1 in which the core of the spherical Mo was made of an alkali compound material made of silicate glass was used. Otherwise, a spherical compound semiconductor cell was produced in the same manner as in Example 1.
- Example 4 Etching with a spherical compound cell in a state where the top view has the conductive wiring of FIG. 5A or 5C and the buffer layer of Example 1 is formed in the insulating layer 8 having a through hole. Immerse in solvent. At this time, the etching process is performed until only the lower bottom portion of the spherical electrode 1 is immersed until the conductor on the surface 1b of the spherical electrode 1 appears. After the drying treatment, a conductive adhesive such as silver paste was filled in the through hole, and the conductor on the surface 1b of the spherical electrode 1 and one side of the Al plate as the conductive support substrate 10 were adhered.
- a conductive adhesive such as silver paste was filled in the through hole, and the conductor on the surface 1b of the spherical electrode 1 and one side of the Al plate as the conductive support substrate 10 were adhered.
- FIG. 3 is an example in which the cross-sectional shape of the wiring electrode 9 is different from that in FIG. is there.
- Example 5 The top view has the conductive wiring of FIG. 5 (b) and is immersed in the etching solvent in a state where the spherical compound cell in the state where the buffer layer of Example 1 is formed is disposed on the insulating layer 8 having the through hole. To do. At this time, the etching process is performed until only the lower bottom portion of the spherical electrode 1 is immersed until the conductor on the surface 1b of the spherical electrode 1 appears. After the drying treatment, a conductive adhesive such as silver paste was filled in the through hole, and the conductor on the surface 1b of the spherical electrode 1 and one side of the Al plate as the conductive support substrate 10 were adhered.
- a conductive adhesive such as silver paste was filled in the through hole, and the conductor on the surface 1b of the spherical electrode 1 and one side of the Al plate as the conductive support substrate 10 were adhered.
- FIG. 5B shows a structure in which four columns are provided with a partition, and each column is connected in series, so that the parallel connection of the spherical compound cells 4 is one partition and four parallel 4 series connections are possible.
- the conductive wiring pattern is not limited to this, and other patterns may be used.
- Example 6 In the structure shown in FIG. 1B, in the insulating layer 8 having a through hole, the through hole is constituted by a hole and a wiring electrode 9, and the buffer layer of Example 1 was formed to the through hole of the hole part. In a state where the spherical compound cell in the state is arranged, it is immersed in an etching solvent. At this time, an etching process is performed until the conductor on the surface 1b of the spherical electrode 1 appears so that only the lower bottom portion of the spherical electrode 1 is immersed.
- a conductive adhesive such as silver paste is filled in the through hole of the hole portion, and the conductor on the surface 1b of the spherical electrode 1 and one side of the Al plate as the conductive support substrate 10 are combined. Glued. Thereafter, a transparent electrode layer ZnO: Al was deposited by sputtering so as to be deposited on the spherical compound surface side. At this time, the wiring electrode 9 filled in the through hole is electrically joined. After the heat drying treatment, an antireflection layer 6 was formed by the method of Example 2 to obtain a module structure. This structure is a structure that realizes series connection of spherical compound cells using a substrate.
- Example 7 The top view has the conductive wiring of FIG. 5 (a) or (c), and in the insulating layer 8 having a through hole, the spherical compound cell in a state where the buffer layer of Example 1 is formed is cut in half, The cut surface is arranged on the through hole side. Thereafter, a conductive adhesive such as a silver paste was filled in the through hole, and the conductor on the surface 1 b of the spherical electrode 1 was bonded to one side of the Al plate as the conductive support substrate 10. Thereafter, a transparent electrode layer ZnO: Al was deposited by sputtering so as to be deposited on the spherical surface side. After the heat treatment, an antireflection layer 6 was formed by the method of Example 4 to obtain a module structure shown in FIG.
- a conductive adhesive such as a silver paste
- FIG. 4A shows a structure in which the structure described in Example 4 is installed on both sides.
- a spherical compound cell in a state where the top view has the conductive wiring of FIG. 5A or 5C and the buffer layer of Example 1 is formed in the insulating layer 8 having a through hole is arranged.
- it is immersed in an etching solvent.
- an etching process is performed until the conductor on the surface 1b of the spherical electrode 1 appears so that only the lower bottom portion of the spherical electrode 1 is immersed.
- a conductive adhesive such as silver paste was filled in the through hole, and the conductor on the surface 1b of the spherical electrode 1 and both surfaces of the Al plate as the conductive support substrate 10 were adhered. Thereafter, a transparent electrode layer ZnO: Al was deposited by sputtering so as to be deposited on the spherical surface side. After the heat treatment, an antireflection layer 6 was formed by the method of Example 2 to obtain a module structure shown in FIG. This structure is an all parallel connection structure of spherical compound cells.
- FIGS. 5A and 5C are examples of the all-parallel connection pattern. The manufacturing method and structure are not limited to this, and there are structures such as FIG.
- a spherical solar battery cell that can increase the projected area of the light absorption layer and can significantly reduce the amount of material used can be made of a compound semiconductor. Further, recombination of cells and suppression of leakage leakage current can be achieved. Note that the present invention can also be applied to a light emitting element.
Abstract
Disclosed is a spherical compound semiconductor cell wherein a compound semiconductor film that can suppress recombination and a leak current is sued. The spherical compound semiconductor cell is provided with: a spherical electrode (1), having at least the surface thereof formed of a conductor; a compound semiconductor layer (2), which is formed on the surface of the spherical electrode (1), and which has a chalcopyrite structure; buffer layers (3, 4) formed on the surface of the compound semiconductor layer (2); and a transparent electrode layer (5) formed on the surfaces of the buffer layers (3, 4). In the spherical compound semiconductor cell, recombination and a leak current are suppressed, and photoelectric conversion efficiency is increased by having the cell structure provided with the buffer layers (3, 4).
Description
本発明は、球状太陽電池セルの製造方法及びモジュール化技術に係り、特にエネルギー変換効率の高い化合物半導体を用いた球状化合物半導体セルの製造方法及びモジュール化技術に関する。
The present invention relates to a method for manufacturing a spherical solar battery cell and a modularization technique, and more particularly to a method for manufacturing a spherical compound semiconductor cell using a compound semiconductor with high energy conversion efficiency and a modularization technique.
太陽電池の吸収層として用いられるカルコパイライト化合物半導体は、例えば、従来、図９（ａ），（ｂ）で示したように２段階プロセスを用いて作製されている。すなわち、基板２１上にＭｏ等の電極２２を形成し、その電極２２上にＣｕ薄膜２３とＩｎ薄膜２４とを両者の膜厚比が１：２.２～２.４程度となるように積層し、その基板を例えばＳｅやＳ等のカルコゲン雰囲気中、あるいはカルコゲンを含むガス、例えばＨ２ＳｅやＨ２Ｓ中で熱処理を行い、カルコパイライト型化合物薄膜２５としてＣｕＩｎＳ2，ＣｕＩｎＳｅ2やＣｕＩｎＴｅ2薄膜を形成している。
A chalcopyrite compound semiconductor used as an absorption layer of a solar cell has been conventionally produced, for example, using a two-stage process as shown in FIGS. 9 (a) and 9 (b). That is, an electrode 22 made of Mo or the like is formed on the substrate 21, and a Cu thin film 23 and an In thin film 24 are stacked on the electrode 22 so that the film thickness ratio thereof is about 1: 2.2 to 2.4. Then, the substrate is heat-treated in a chalcogen atmosphere such as Se or S, or in a gas containing chalcogen, such as H 2 Se or H 2 S , to form a CuInS 2 , CuInSe 2 or CuInTe 2 thin film as the chalcopyrite type compound thin film 25. ing.
また、図１０（ａ），（ｂ）に示すように、図９と同様に、基板２１の電極２２上にＣｕ薄膜２３とＩｎ薄膜２４の積層膜を形成した後、前記薄膜上にさらに例えばＳ，ＳｅやＴｅ等のカルコゲン薄膜２６を蒸着し、熱処理を行って固相反応によって、ＣｕＩｎＳ2，ＣｕＩｎＳｅ2やＣｕＩｎＴｅ2のカルコパイライト型化合物薄膜２７を形成している。
Further, as shown in FIGS. 10A and 10B, after forming a laminated film of a Cu thin film 23 and an In thin film 24 on the electrode 22 of the substrate 21 as in FIG. A chalcogenite thin film 27 of CuInS 2 , CuInSe 2, or CuInTe 2 is formed by depositing a chalcogen thin film 26 of S, Se, Te or the like, performing a heat treatment, and performing a solid phase reaction.
一方、太陽電池の光電変換効率を増大させ、性能を向上させる手法の一つに吸収層の比表面積増大が挙げられる。従来、本効果を最大限に得るために光電変換層表面にテクスチャ構造や凹凸構造を形成る工程や、投影面積に対して比表面積増大となり、全方位の入射光吸収を可能とする球状構造の太陽電池セルなどがある。特に球状太陽電池はモジュール化した際、曲面への設置も可能な対応性、投影面積に対する比表面積の増大による高効率化、及び入射光角度依存が少なく、入射光角度変化に対する発電効率の極端な性能低下を抑制する効果があるなど期待も大きい。
On the other hand, an increase in the specific surface area of the absorption layer can be cited as one of methods for increasing the photoelectric conversion efficiency of the solar cell and improving the performance. Conventionally, in order to obtain this effect to the maximum extent, a process of forming a texture structure or a concavo-convex structure on the surface of the photoelectric conversion layer, a specific surface area with respect to the projected area, and a spherical structure capable of absorbing incident light in all directions There are solar cells. In particular, when spherical solar cells are modularized, they can be installed on curved surfaces, increase efficiency by increasing the specific surface area with respect to the projected area, and have little dependency on incident light angle, resulting in extreme power generation efficiency with respect to changes in incident light angle. Expectations are high, such as the effect of suppressing performance degradation.
球状太陽電池に関する先行技術としては特許文献１～３等がある。
There are Patent Documents 1 to 3 as prior art relating to spherical solar cells.
しかしながら、現在、市場に出回っている球状太陽電池は、主にシリコン系材料を用いた製品であり、上記のような化合物半導体を用いた球状太陽電池については検討されていない。
However, the spherical solar cells currently on the market are products mainly using silicon-based materials, and the spherical solar cells using the above compound semiconductors have not been studied.
一方、球状シリコン太陽電池は、従来のシリコン太陽電池で実施済みの比表面積増大効果を得るテクスチャ構造やシリコン材料の高屈折率を補う反射防止膜コーティングの適用がないなど課題も多い。また、一般的に球状結晶シリコンを溶融滴下法により作製し球状電極としているため、量産には不向きで、今後の製造コスト低減の指針が得にくい。
On the other hand, spherical silicon solar cells have many problems, such as the absence of the application of an antireflection coating that compensates for the high refractive index of the silicon material and the texture structure that achieves the effect of increasing the specific surface area that has been implemented in conventional silicon solar cells. In addition, since spherical crystal silicon is generally produced by a melt dropping method to form a spherical electrode, it is not suitable for mass production, and it is difficult to obtain guidelines for future production cost reduction.
例えばカルコパイライト型化合物半導体を用いた球状太陽電池の作製において、Ｉｂ族元素の薄膜とIIIｂ族元素の薄膜との２層をカルコゲン共存下で加熱処理して化合物半導体を得る従来の製造方法において改善すべき課題としては、球状電極へのＣｕ薄膜２３やＩｎ薄膜２４の蒸着膜形成が非常に困難であり、複雑な装置や工数を必要とすること、蒸着法はチャンバ内への材料付着が顕著となり材料収率が低いこと、化合物半導体太陽電池において球状構造適用時の再結合及びリーク漏れ電流抑制が挙げられる。
For example, in the manufacture of spherical solar cells using chalcopyrite type compound semiconductors, improvements have been made in the conventional manufacturing method for obtaining compound semiconductors by heat-treating two layers of a thin film of group Ib and a thin film of group IIIb in the presence of chalcogen As problems to be solved, it is very difficult to form a Cu thin film 23 or an In thin film 24 on a spherical electrode, and it requires complicated equipment and man-hours. In the vapor deposition method, material deposition in the chamber is remarkable. Thus, the material yield is low, and recombination and leakage leakage current suppression when a spherical structure is applied in a compound semiconductor solar cell can be mentioned.
本発明は、再結合及びリーク漏れ電流を抑制できる化合物半導体膜を用いた球状の化合物半導体セルを提供することを目的とする。
An object of the present invention is to provide a spherical compound semiconductor cell using a compound semiconductor film capable of suppressing recombination and leakage leakage current.
上記の課題を解決するために、本発明の球状化合物半導体セルは、少なくとも表面が導電体である球状電極と、球状電極の表面に形成されたカルコパイライト構造の化合物半導体層と、前記化合物半導体層の表面に形成された緩衝層と、前記緩衝層の表面に形成された透明電極層を具備することを特徴とする。
In order to solve the above problems, a spherical compound semiconductor cell according to the present invention includes a spherical electrode having at least a surface as a conductor, a compound semiconductor layer having a chalcopyrite structure formed on the surface of the spherical electrode, and the compound semiconductor layer. And a transparent electrode layer formed on the surface of the buffer layer.
また、本発明の太陽電池モジュールは、少なくとも表面が導電体である球状電極と、球状電極の表面に形成されたカルコパイライト構造の化合物半導体層と、前記化合物半導体層の表面に形成された緩衝層と、前記緩衝層の表面に形成された透明電極層を具備し、前記球状電極の導電体が露出した面を有する球状化合物半導体セルと、導電性支持基板の表面に所定のパターンで貫通孔が形成され絶縁層を有する基板とを備え、複数個の前記球状化合物半導体セルが前記絶縁層の貫通孔部に配置され、前記球状電極の導電体と前記導電性支持基板とが電気的に接続された構造を特徴とする。
Further, the solar cell module of the present invention includes a spherical electrode having at least a surface as a conductor, a compound semiconductor layer having a chalcopyrite structure formed on the surface of the spherical electrode, and a buffer layer formed on the surface of the compound semiconductor layer A spherical compound semiconductor cell having a transparent electrode layer formed on the surface of the buffer layer and having a surface on which the conductor of the spherical electrode is exposed; and a through-hole having a predetermined pattern on the surface of the conductive support substrate A plurality of the spherical compound semiconductor cells disposed in the through-hole portion of the insulating layer, and the conductor of the spherical electrode and the conductive support substrate are electrically connected to each other. Characterized by the structure.
また、球状化合物半導体セルの製造方法において、少なくとも表面が導電体である球状電極と、Ｉｂ族元素、IIIｂ族元素及びVIｂ族元素を含む単元素材料または化合物元素材料の粉末を混合し、メカニカルミリング処理を施し、球状電極の表面にカルコパイライト構造の化合物半導体層を形成する工程を有することを特徴とする。
Also, in the method of manufacturing a spherical compound semiconductor cell, mechanical milling is performed by mixing at least a spherical electrode whose surface is a conductor and a powder of a single element material or compound element material containing a group Ib element, a group IIIb element and a group VIb element. And a step of forming a compound semiconductor layer having a chalcopyrite structure on the surface of the spherical electrode.
本発明により、化合物半導体膜を用いた球状の化合物半導体セルの再結合及びリーク漏れ電流の抑制を図ることができる。
According to the present invention, recombination of a spherical compound semiconductor cell using a compound semiconductor film and suppression of leakage leakage current can be achieved.
以下、本発明を実施するための最良の形態を説明する。
Hereinafter, the best mode for carrying out the present invention will be described.
図１は、本発明の実施形態に係わる球状化合物半導体セルを配列し、モジュール化した素子断面図の一例を示すものである。
FIG. 1 shows an example of a device cross-sectional view in which spherical compound semiconductor cells according to an embodiment of the present invention are arranged and modularized.
本実施形態の球状化合物半導体セルは、少なくとも表面（層）１ｂが導電体である球状電極１の全面又は一部の表面に、少なくとも１種以上の化合物半導体層２を具備し、化合物半導体層２上に堆積された緩衝層３と、緩衝層３上に堆積された緩衝層４と、緩衝層４上に堆積された透明電極層５を具備し、透明電極層５上に堆積された反射防止層６を具備した構成である。球状化合物半導体セルとしては、緩衝層４、反射防止層６を省略した構成とすることも可能である。このように緩衝層を具備したセル構造とすることで、再結合またはリーク漏れ電流を抑制し光電変換効率が増加する球状化合物半導体セルを提供できる。
The spherical compound semiconductor cell of this embodiment includes at least one compound semiconductor layer 2 on at least the entire surface or a part of the surface of the spherical electrode 1 whose surface (layer) 1b is a conductor, and the compound semiconductor layer 2 The buffer layer 3 deposited on the buffer layer 4, the buffer layer 4 deposited on the buffer layer 3, and the transparent electrode layer 5 deposited on the buffer layer 4. The layer 6 is provided. The spherical compound semiconductor cell may have a configuration in which the buffer layer 4 and the antireflection layer 6 are omitted. Thus, by using a cell structure having a buffer layer, a spherical compound semiconductor cell in which recombination or leakage leakage current is suppressed and photoelectric conversion efficiency is increased can be provided.
球状化合物半導体セルを配列してモジュール化した太陽電池モジュールとして、図１（ａ）に並列接続モジュール、図１（ｂ）に直列接続モジュールの例を示す。
As a solar cell module in which spherical compound semiconductor cells are arranged and modularized, an example of a parallel connection module is shown in FIG. 1 (a), and an example of a series connection module is shown in FIG. 1 (b).
図１（ａ）に示した並列接続モジュールでは、導電性支持基板１０の表面に絶縁層８（絶縁基板。基板）が形成されており、絶縁層８には図５（ａ），（ｃ）に示したように所定のパターンで貫通孔が形成されている。絶縁層８の貫通孔内に導電性支持基板１０と接続した電極引き出し線７が形成されている。また、絶縁層８の表面に所定のパターンで配線電極９（以下、「配線電極層」とも称する。）が形成されている。球状化合物半導体セルを絶縁層８の貫通孔部分に配置して太陽電池モジュールを構成している。この際、球状化合物半導体セルは表面の一部で球状電極１が露出するように加工が施されている。露出した球状電極１と電極引き出し線７が電気的に接続され、透明電極層５と配線電極層が電気的に接続され、球状電極１と透明電極層５とは絶縁層８により絶縁された構造となっている。また、並列接続モジュールでは、複数個の球状化合物半導体セルの球状電極１同士が電極引き出し線７、導電性支持基板１０により電気的に接続され、透明電極層５同士が配線電極９により電気的に接続された構造となっている。
In the parallel connection module shown in FIG. 1A, an insulating layer 8 (insulating substrate, substrate) is formed on the surface of the conductive support substrate 10, and the insulating layer 8 is formed in FIGS. 5A and 5C. As shown in FIG. 5, the through holes are formed in a predetermined pattern. An electrode lead line 7 connected to the conductive support substrate 10 is formed in the through hole of the insulating layer 8. A wiring electrode 9 (hereinafter also referred to as “wiring electrode layer”) is formed on the surface of the insulating layer 8 in a predetermined pattern. A spherical compound semiconductor cell is disposed in the through hole portion of the insulating layer 8 to constitute a solar cell module. At this time, the spherical compound semiconductor cell is processed so that the spherical electrode 1 is exposed at a part of the surface. The exposed spherical electrode 1 and the electrode lead wire 7 are electrically connected, the transparent electrode layer 5 and the wiring electrode layer are electrically connected, and the spherical electrode 1 and the transparent electrode layer 5 are insulated by the insulating layer 8 It has become. In the parallel connection module, the spherical electrodes 1 of the plurality of spherical compound semiconductor cells are electrically connected by the electrode lead wire 7 and the conductive support substrate 10, and the transparent electrode layers 5 are electrically connected by the wiring electrode 9. It has a connected structure.
図１（ｂ）に示した直列接続モジュールでは、導電性支持基板１０の表面には図５（ｂ）に示したように所定のパターンで絶縁層８と配線電極９が形成されている。また、絶縁層８には図５（ｂ）に示したように所定のパターンで貫通孔が形成されている。絶縁層８の貫通孔内には導電性支持基板１０と接続した電極引き出し線７が形成されている。球状化合物半導体セルを絶縁層８の貫通孔部分に配置して太陽電池モジュールを構成している。この際、球状化合物半導体セルは表面の一部で球状電極１が露出するように加工が施されている。露出した球状電極１と電極引き出し線７が電気的に接続され、透明電極層５と配線電極層が電気的に接続された構造となっている。直列接続モジュールでは、隣接する球状化合物半導体セルの球状電極１と透明電極層５が電極引き出し線７、導電性支持基板１０、配線電極９により電気的に接続された構造となっている。また、導電性支持基板１０には１つの球状化合物半導体セルの球状電極１と透明電極層５同士が短絡しないように絶縁層８が形成されている。
In the series connection module shown in FIG. 1B, the insulating layer 8 and the wiring electrode 9 are formed on the surface of the conductive support substrate 10 in a predetermined pattern as shown in FIG. 5B. The insulating layer 8 has through holes formed in a predetermined pattern as shown in FIG. In the through hole of the insulating layer 8, an electrode lead line 7 connected to the conductive support substrate 10 is formed. A spherical compound semiconductor cell is disposed in the through hole portion of the insulating layer 8 to constitute a solar cell module. At this time, the spherical compound semiconductor cell is processed so that the spherical electrode 1 is exposed at a part of the surface. The exposed spherical electrode 1 and the electrode lead wire 7 are electrically connected, and the transparent electrode layer 5 and the wiring electrode layer are electrically connected. The series connection module has a structure in which the spherical electrode 1 and the transparent electrode layer 5 of the adjacent spherical compound semiconductor cell are electrically connected by the electrode lead wire 7, the conductive support substrate 10, and the wiring electrode 9. An insulating layer 8 is formed on the conductive support substrate 10 so that the spherical electrode 1 and the transparent electrode layer 5 of one spherical compound semiconductor cell are not short-circuited.
本発明の実施形態に係わる半導体モジュールの製造方法の一実施形態を説明する。
An embodiment of a method for manufacturing a semiconductor module according to an embodiment of the present invention will be described.
まず、球状電極１の表面１ｂに化合物半導体層２、緩衝層３、緩衝層４を順に形成した構造体を形成する。次に、貫通孔を有する絶縁層８の貫通孔部分に上記構造体を配列する。次に、上記構造体の下底部のうち貫通孔におさまる範囲内の各層を球状電極１の表面１ｂまで除去し、貫通孔内部の球状電極１に導電性接着剤等の導電性材料を用いて電極引き出し線７を形成する。この電極引き出し線７を導電性支持基板１０の片面又は両面に接続する。緩衝層４上に透明電極層５、反射防止層６を形成することにより半導体モジュールが得られる。
First, a structure in which the compound semiconductor layer 2, the buffer layer 3, and the buffer layer 4 are formed in this order on the surface 1b of the spherical electrode 1 is formed. Next, the structure is arranged in the through hole portion of the insulating layer 8 having the through hole. Next, each layer within the range that fits in the through hole in the lower bottom portion of the structure is removed to the surface 1b of the spherical electrode 1, and a conductive material such as a conductive adhesive is used for the spherical electrode 1 in the through hole. An electrode lead line 7 is formed. The electrode lead wire 7 is connected to one side or both sides of the conductive support substrate 10. A semiconductor module is obtained by forming the transparent electrode layer 5 and the antireflection layer 6 on the buffer layer 4.
また、他の製造方法の実施形態を説明する。
Further, another embodiment of the manufacturing method will be described.
まず、球状電極１の表面１ｂの導電体が露出するように球状化合物半導体セルの一部を切断する。次に、規則的に設けられた貫通孔を有する絶縁層８の該貫通孔内に球状化合物半導体セルの切断面を向けて配列する。貫通孔内部の球状電極１に導電性接着剤等の導電性材料を用いて電極引き出し線７を形成する。この電極引き出し線７を導電性支持基板１０の片面又は両面に接続する。緩衝層４上に透明電極層５、反射防止層６を形成することにより半導体モジュールが得られる。
First, a part of the spherical compound semiconductor cell is cut so that the conductor on the surface 1b of the spherical electrode 1 is exposed. Next, the insulating layer 8 having regularly provided through holes is arranged in the through holes with the cut surface of the spherical compound semiconductor cell facing. An electrode lead wire 7 is formed on the spherical electrode 1 inside the through hole using a conductive material such as a conductive adhesive. The electrode lead wire 7 is connected to one side or both sides of the conductive support substrate 10. A semiconductor module is obtained by forming the transparent electrode layer 5 and the antireflection layer 6 on the buffer layer 4.
球状化合物半導体セルを規則的に貫通孔を有する絶縁層８の貫通孔部へ配列し、貫通孔を介して電極を得ることでセル表面の透明電極との電気的絶縁性を確保し、且つ球状化合物半導体セルを細密配列可能とし、高性能な太陽電池モジュールを提供できる。
The spherical compound semiconductor cells are regularly arranged in the through-hole portions of the insulating layer 8 having through-holes, and an electrode is obtained through the through-holes to ensure electrical insulation from the transparent electrode on the cell surface, and spherical A compound semiconductor cell can be arranged finely and a high performance solar cell module can be provided.
球状電極１において、少なくとも表面１ｂは導電体であり、化合物半導体層２とオーミック接合などの電気的な接合を形成し、且つ化学的又は物理的接合が優れており、化合物半導体層２の膜剥離がない材料が好ましい。例えばＭｏ，Ａｌ，Ｎｉ，Ｔｉ，Ｃｕ，Ｍｇ，Ｌｉ，Ｆｅなどなどの金属材料がこれにあたるがこの限りでなく、高導電性の有機化合物導電材料や無機化合物材料などでもよい。
In the spherical electrode 1, at least the surface 1 b is a conductor, forms an electrical junction such as an ohmic junction with the compound semiconductor layer 2, and has excellent chemical or physical junction. Materials with no are preferred. For example, a metal material such as Mo, Al, Ni, Ti, Cu, Mg, Li, and Fe corresponds to this, but is not limited thereto, and may be a highly conductive organic compound conductive material or inorganic compound material.
球状電極１の核１ａはプロセス中の熱安定性が高く、かつ可能な限り水分や酸素の透過率や吸収率の低い材料がよい。可撓性が必要でなければ、ジルコニア安定化イットリウム（ＹＳＺ）、ガラス等の無機材料、または、亜鉛、アルミニウム、ステンレス、クロム、スズ、ニッケル、鉄、ニッケル銅などの金属板やセラミック板でもよい。可撓性が必要な場合には、ポリエチレンテレフタレート、ポリブチレンフタレート、ポリエチレンナフタレート等のポリエステルやポリスチレン、ポリカーボネート、ポリエーテルスルホン、ポリアリレート、ポリイミド、ポリシクロオレフィン、ノルボルネン樹脂、ポリ（クロロトリフルオロエチレン）等の有機材料が挙げられる。また、不透明なプラスチック基板でもよい。特に、耐熱性、寸法安定性、耐溶剤性、電気絶縁性、及び加工性に優れていることが好ましい。また、表面１ｂを構成する材料と同材料でも良く、セレン化ナトリウム（Ｎａ2Ｓａ）やフッ化ナトリウム（ＮａＦ）、ケイ酸塩ガラス層などのアルカリ化合物材料を含む構成でもよい。
The core 1a of the spherical electrode 1 is preferably made of a material having high thermal stability during the process and having as low a moisture and oxygen permeability and absorption rate as possible. If flexibility is not required, it may be an inorganic material such as zirconia stabilized yttrium (YSZ) or glass, or a metal plate or ceramic plate such as zinc, aluminum, stainless steel, chromium, tin, nickel, iron or nickel copper. . When flexibility is required, polyesters such as polyethylene terephthalate, polybutylene phthalate, polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycycloolefin, norbornene resin, poly (chlorotrifluoroethylene) ) And other organic materials. An opaque plastic substrate may also be used. In particular, it is preferable to be excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, and workability. Also, may be a material constituting the surface 1b of the same material, sodium selenide (Na 2 Sa) and sodium fluoride (NaF), it may be configured to include an alkali compound material such as silicate glass layer.
球状電極１の直径は１００μｍ～１０ｃｍであり、１００μｍより小さい直径では、球状電極１の表面１ｂに化合物半導体層２を形成する工程で粉末合成と異種反応混合物質を形成し、Ｉｂ－VIｂ－VIｂ化合物相の不純物となる可能性がある。また、１０ｃｍより大きい直径では、球状電極１への化合物半導体層２の形成が困難であることが実験的に見出されている。化合物半導体セルを構成する球状電極１の形状としては球体状の他にも、半球体状、楕円体状、または、それらの球体の分割体形状を用いることもできる。
The spherical electrode 1 has a diameter of 100 μm to 10 cm. When the diameter is smaller than 100 μm, powder synthesis and a heterogeneous reaction mixture are formed in the step of forming the compound semiconductor layer 2 on the surface 1b of the spherical electrode 1, and Ib-VIb-VIb It may become an impurity in the compound phase. Further, it has been experimentally found that when the diameter is larger than 10 cm, it is difficult to form the compound semiconductor layer 2 on the spherical electrode 1. As the shape of the spherical electrode 1 constituting the compound semiconductor cell, in addition to the spherical shape, a hemispherical shape, an ellipsoidal shape, or a divided shape of those spheres can also be used.
化合物半導体層２は、少なくとも表面１ｂが導電体である球状電極１と、Ｉｂ族元素、IIIｂ族元素及びVIｂ族元素を含む単元素材料または化合物元素材料の粉末を混合し、メカニカルミリング処理を施すことにより、球状電極１の表面１ｂに化合物半導体層２を形成することができる。Ｉｂ族元素、IIIｂ族元素及びVIｂ族元素を含む単元素材料または化合物元素材料の粉末としては、Ｉｂ族元素とIIIｂ族元素とVIｂ族元素の単元素材料又はＩｂ－VIｂ化合物とIIIｂ－VIｂ化合物とVIｂ族元素化合物又はＩｂ－VIｂ－VIｂ化合物などの化合物元素材料の複数種の粉末を用いることができる。また、メカニカルミリング処理は、ボールミル、サンドミル、ビーズミルなど手法が適用できる。実際に球状電極１に堆積された化合物半導体層２のＸ線回折（ＸＲＤ）測定をしたところ、図８に示したように回折角２８°付近に（１１２）回折面をメインピークとしたＸＲＤ結果を得た。本結果より化合物半導体層２がカルコパイライト結晶構造を有することが分かった。
The compound semiconductor layer 2 is prepared by mixing a spherical electrode 1 whose surface 1b is a conductor and a powder of a single element material or a compound element material containing a group Ib element, a group IIIb element and a group VIb element, and subjecting it to a mechanical milling process. Thus, the compound semiconductor layer 2 can be formed on the surface 1b of the spherical electrode 1. As a powder of a single element material or a compound element material containing a group Ib element, a group IIIb element and a group VIb element, a single element material of a group Ib element, a group IIIb element and a group VIb element, or an Ib-VIb compound and a group IIIb-VIb compound And plural kinds of powders of compound element materials such as a VIb group element compound or an Ib-VIb-VIb compound can be used. For mechanical milling, a ball mill, sand mill, bead mill, or the like can be applied. When the X-ray diffraction (XRD) measurement of the compound semiconductor layer 2 actually deposited on the spherical electrode 1 was performed, the XRD result with the (112) diffraction surface as the main peak at a diffraction angle of about 28 ° as shown in FIG. Got. From this result, it was found that the compound semiconductor layer 2 has a chalcopyrite crystal structure.
化合物半導体層２は、ある１次元方向の長さが５ｎｍ～１００μｍである結晶粒径が連なり凹凸膜を構成する。カルコパイライトの結晶構造ではａ軸：０.５ｎｍ、ｃ軸：１.１ｎｍが一般的であり、ａ軸方向に１０層積層された粒であれば、その結晶粒径は最低５ｎｍとなる。例えば球状電極１の直径を１０ｍｍと仮定した場合、薄膜表面は５ｎｍ～１００μｍの段差や周期を有した凹凸構造となる。このとき、球状電極１の表面積に対する化合物半導体膜の表面積の増大率は１.００１倍～２００００倍となる。
The compound semiconductor layer 2 constitutes a concavo-convex film in which crystal grains having a length in a one-dimensional direction of 5 nm to 100 μm are connected. In the chalcopyrite crystal structure, the a-axis: 0.5 nm and the c-axis: 1.1 nm are common, and the crystal grain size is a minimum of 5 nm if 10 layers are laminated in the a-axis direction. For example, assuming that the diameter of the spherical electrode 1 is 10 mm, the thin film surface has a concavo-convex structure having steps and periods of 5 nm to 100 μm. At this time, the increase rate of the surface area of the compound semiconductor film with respect to the surface area of the spherical electrode 1 is 1.001 times to 20000 times.
化合物半導体層２は、材料固有のバンドギャップが０.１～５ｅＶであり、前記化合物半導体層２の波長４５０ｎｍ～５００ｎｍにおける吸収係数が１×１０3～１×１０10ｃｍ-1である。また、ある１次元方向の長さが５ｎｍ～１００μｍである結晶粒径が連なり凹凸膜を構成することから、その膜厚は５ｎｍ～５００μｍに膜堆積される。化合物半導体層２の膜厚は化合物半導体材料の光吸収係数との兼合いで決定される。材料の光吸収係数が高い程、膜厚を薄くすることができ材料の抵抗成分に影響をうけない。また、膜厚を厚くすると絶縁性要素が高くなり電気的性能が低くなる。一般に波長４５０ｎｍ～５００ｎｍの波長領域の太陽光スペクトルが有するエネルギー密度は非常に高いことは周知されており、この波長領域において、仮に化合物半導体層２の膜厚１００ｎｍで吸収係数が１×１０3ｃｍ-1よりも小さい場合、殆どエネルギー吸収はされない。また、膜厚１００ｎｍで全ての光を吸収すると仮定した場合、吸収係数はおよそ１×１０10ｃｍ-1となる。理想的に波長４５０ｎｍ～５００ｎｍの化合物半導体層２の吸収係数が１×１０5ｃｍ-1であれば、膜厚は３μｍ～１０μｍ程度で充分である。
The compound semiconductor layer 2 has a material-specific band gap of 0.1 to 5 eV, and the compound semiconductor layer 2 has an absorption coefficient of 1 × 10 3 to 1 × 10 10 cm −1 at a wavelength of 450 nm to 500 nm. In addition, since the crystal grain size having a length in a one-dimensional direction of 5 nm to 100 μm is connected to form an uneven film, the film thickness is deposited to 5 nm to 500 μm. The film thickness of the compound semiconductor layer 2 is determined in consideration of the light absorption coefficient of the compound semiconductor material. As the light absorption coefficient of the material is higher, the film thickness can be reduced and the resistance component of the material is not affected. Further, when the film thickness is increased, the insulating element is increased and the electrical performance is decreased. In general, it is well known that the solar spectrum in the wavelength region of 450 nm to 500 nm has a very high energy density. In this wavelength region, the compound semiconductor layer 2 has a film thickness of 100 nm and an absorption coefficient of 1 × 10 3 cm. When it is smaller than -1 , energy is hardly absorbed. Further, when it is assumed that all light is absorbed at a film thickness of 100 nm, the absorption coefficient is approximately 1 × 10 10 cm −1 . Ideally, if the absorption coefficient of the compound semiconductor layer 2 having a wavelength of 450 nm to 500 nm is 1 × 10 5 cm −1 , a film thickness of about 3 μm to 10 μm is sufficient.
緩衝層３の形成方法としては、真空蒸着法、スパッタリング法、イオンプレーティング法、ＭＢＥ法等の物理気相成長法あるいはプラズマ重合等のＣＶＤ法が挙げられる。湿式成膜法としては、キャスト法、スピンコート法、ディッピング法、ＬＢ法、化学溶液析出法、ゾルゲル法等の塗布法を用いることができる。また、インクジェット印刷やスクリーン印刷などの印刷法、熱転写やレーザー転写などの転写法を用いてもよい。パターニングは、フォトリソグラフィーなどによる化学的エッチングにより行ってもよいし、紫外線やレーザーなどによる物理的エッチングにより行ってもよく、マスクを重ねて真空蒸着やスパッタ等をして行ってもよいし、リフトオフ法、印刷法、転写法により行ってもよい。
Examples of the formation method of the buffer layer 3 include a vacuum vapor deposition method, a sputtering method, an ion plating method, a physical vapor deposition method such as an MBE method, or a CVD method such as plasma polymerization. As the wet film formation method, a coating method such as a cast method, a spin coating method, a dipping method, an LB method, a chemical solution deposition method, a sol-gel method, or the like can be used. Further, a printing method such as ink jet printing or screen printing, or a transfer method such as thermal transfer or laser transfer may be used. Patterning may be performed by chemical etching such as photolithography, physical etching using ultraviolet rays or lasers, or by vacuum deposition or sputtering with a mask overlapped, or lift-off. Method, printing method, transfer method may be used.
緩衝層３の役割は化合物半導体層２との界面に、化合物半導体層２との反応生成物を形成し、反応生成物と化合物半導体層２とでｐｎ接合を形成することを主目的としており、このｐｎ接合により光電変換される。また、緩衝層３は、緩衝層４との界面に緩衝層４を構成する材料との反応生成物を形成させる機能を有していてもよい。このような緩衝層３としては、金属酸化物、金属硫化物、金属窒化物を使用することができ、金属酸化物としてはＺｎＯ，ＭｇＴｉＯ3，ＢａＴｉＯ3，ＴｉＯ，ＭｇＯ，ＳｒＯ，ＺｒＯ，ＣｄＯ，ＴｉＺｒＯ2、金属硫化物としてはＺｎＳ，ＴｉＳ2，ＺｒＳ，ＭｇＳ，ＭｇＴｉＳ3，ＣｄＳ、金属窒化物としてはＺｎ3Ｎ2，ＴｉＮ，Ｍｇ3Ｎ2が挙げられる。
The role of the buffer layer 3 is mainly to form a reaction product with the compound semiconductor layer 2 at the interface with the compound semiconductor layer 2 and to form a pn junction between the reaction product and the compound semiconductor layer 2. Photoelectric conversion is performed by the pn junction. In addition, the buffer layer 3 may have a function of forming a reaction product with the material constituting the buffer layer 4 at the interface with the buffer layer 4. As such a buffer layer 3, a metal oxide, a metal sulfide, and a metal nitride can be used. As the metal oxide, ZnO, MgTiO 3 , BaTiO 3 , TiO, MgO, SrO, ZrO, CdO, TiZrO 2 , metal sulfides include ZnS, TiS 2 , ZrS, MgS, MgTiS 3 , CdS, and metal nitrides include Zn 3 N 2 , TiN, Mg 3 N 2 .
緩衝層４の形成方法としては、真空蒸着法、スパッタリング法、イオンプレーティング法、ＭＢＥ法等の物理気相成長法あるいはプラズマ重合等のＣＶＤ法が挙げられる。湿式成膜法としては、キャスト法、スピンコート法、ディッピング法、ＬＢ法、化学溶液析出法、ゾルゲル法等の塗布法を用いることができる。また、インクジェット印刷やスクリーン印刷などの印刷法、熱転写やレーザー転写などの転写法を用いてもよい。パターニングは、フォトリソグラフィーなどによる化学的エッチングにより行ってもよいし、紫外線やレーザーなどによる物理的エッチングにより行ってもよく、マスクを重ねて真空蒸着やスパッタ等をして行ってもよいし、リフトオフ法、印刷法、転写法により行ってもよい。
Examples of the method for forming the buffer layer 4 include a vacuum vapor deposition method, a sputtering method, an ion plating method, a physical vapor deposition method such as an MBE method, or a CVD method such as plasma polymerization. As the wet film formation method, a coating method such as a cast method, a spin coating method, a dipping method, an LB method, a chemical solution deposition method, a sol-gel method, or the like can be used. Further, a printing method such as ink jet printing or screen printing, or a transfer method such as thermal transfer or laser transfer may be used. Patterning may be performed by chemical etching such as photolithography, physical etching using ultraviolet rays or lasers, or by vacuum deposition or sputtering with a mask overlapped, or lift-off. Method, printing method, transfer method may be used.
緩衝層４の役割は、透明電極層５と緩衝層３のエネルギー準位整合をするためである。このようにエネルギー準位を整合させることで、化合物半導体層２と反応生成物との間で電荷分離したキャリアが緩衝層３と透明電極層５の間での再結合することを防止できる。また、これによってリーク漏れ電流を抑制することができる。また、緩衝層３のすべてが化合物半導体層２と反応生成物を形成した場合、反応生成物と透明電極層５のエネルギー順位の整合が困難であり、両者の界面で再結合を生じやすくなる。緩衝層４を設けることにより、緩衝層３と化合物半導体層２の反応生成物と透明電極層５のエネルギー順位を整合させることで再結合やリーク漏れ電流を抑制することができる。
The role of the buffer layer 4 is to match the energy levels of the transparent electrode layer 5 and the buffer layer 3. By matching the energy levels in this way, it is possible to prevent carriers that have undergone charge separation between the compound semiconductor layer 2 and the reaction product from recombining between the buffer layer 3 and the transparent electrode layer 5. Further, this can suppress the leakage current. Further, when all of the buffer layer 3 forms a reaction product with the compound semiconductor layer 2, it is difficult to match the energy level of the reaction product and the transparent electrode layer 5, and recombination is likely to occur at the interface between the two. By providing the buffer layer 4, recombination and leakage leakage current can be suppressed by matching the energy ranking of the reaction product of the buffer layer 3 and the compound semiconductor layer 2 and the transparent electrode layer 5.
このような緩衝層４としては金属酸化物を使用することができ、金属酸化物としてはＺｎＯ，ＭｇＴｉＯ3，ＢａＴｉＯ3，ＴｉＯ，ＭｇＯ，ＳｒＯ，ＺｒＯ，ＣｄＯ，ＴｉＺｒＯ2が挙げられる。緩衝層３と緩衝層４の界面近傍には緩衝層３の構成材料と緩衝層４の構成材料との反応生成物が形成されていることが好ましい。また、緩衝層４と透明電極層５の界面近傍に、緩衝層４の構成材料と透明電極層５の構成材料との反応生成物が形成されていることが好ましい。なお、緩衝層３が緩衝層４の機能を有する場合には、緩衝層４を省略することができる。
As the buffer layer 4, a metal oxide can be used, and examples of the metal oxide include ZnO, MgTiO 3 , BaTiO 3 , TiO, MgO, SrO, ZrO, CdO, and TiZrO 2 . It is preferable that a reaction product of the constituent material of the buffer layer 3 and the constituent material of the buffer layer 4 is formed in the vicinity of the interface between the buffer layer 3 and the buffer layer 4. In addition, a reaction product of the constituent material of the buffer layer 4 and the constituent material of the transparent electrode layer 5 is preferably formed in the vicinity of the interface between the buffer layer 4 and the transparent electrode layer 5. If the buffer layer 3 has the function of the buffer layer 4, the buffer layer 4 can be omitted.
透明電極層５はスパッタ法やＣＶＤ法、ゾルゲル法又は塗布熱分解法などの薄膜形成手法により堆積された可視光透過性導電膜であり、酸化インジウムスズ（ＩＴＯ）や、酸化亜鉛（ＺｎＯ）、酸化スズ（ＳｎＯ2）などや、有機材料としてはpoly（３，４－ethylenedioxythiophene）－poly－（styrenesulfonate）（ＰＥＤＯＴ：ＰＳＳ）が採用可能であるが、この限りではない。
The transparent electrode layer 5 is a visible light transmissive conductive film deposited by a thin film forming method such as sputtering, CVD, sol-gel, or coating pyrolysis, and includes indium tin oxide (ITO), zinc oxide (ZnO), Tin (SnO 2 ) or the like, and poly (3,4-ethylenedioxythiophene) -poly- (styrenesulfonate) (PEDOT: PSS) can be used as the organic material, but this is not restrictive.
反射防止層６は、光の表面反射を減らす方法として反射防止膜を形成する技術により実現できる。これは、化合物半導体吸収層と空気との中間の屈折率を有する透明な膜を最表面に形成することにより、光の干渉効果を利用して反射率を低く抑えるものである。反射防止膜としては、化学気相成長（ＣＶＤ：Chemical Vapor Deposition）法などで形成される酸化チタン（ＴｉＯ2）膜や窒化シリコン（ＳｉＮ）膜の単層構造のものがある。さらに、表面反射率を抑えるために、真空蒸着法を用いて２層構造にしたものもあるが、この限りではない。また、球状構造へ適用時の膜厚制御や材料制御による屈折率及び材料の光路長差を利用して入射光量を調整することも可能である。また、特に必要ない場合は、反射防止膜を形成しないことも可能である。
The antireflection layer 6 can be realized by a technique of forming an antireflection film as a method for reducing the surface reflection of light. This is to form a transparent film having a refractive index intermediate between that of the compound semiconductor absorption layer and air on the outermost surface, thereby suppressing the reflectance by utilizing the light interference effect. As the antireflection film, there is a single-layer structure of a titanium oxide (TiO 2 ) film or a silicon nitride (SiN) film formed by a chemical vapor deposition (CVD) method or the like. Furthermore, in order to suppress the surface reflectivity, there are some which have a two-layer structure using a vacuum deposition method, but this is not restrictive. It is also possible to adjust the amount of incident light by utilizing the refractive index and the optical path length difference of the material by controlling the film thickness and the material when applied to the spherical structure. Further, when not particularly necessary, it is possible not to form an antireflection film.
電極引き出し線７は、球状電極１の表面の導電性材料と電気的及び物理的に接合し、密着性及び導電性に優れる構造を有する。銀ペースト材料や導電性接着材料などで形成可能であるがこの限りでない。
The electrode lead wire 7 is electrically and physically bonded to the conductive material on the surface of the spherical electrode 1 and has a structure excellent in adhesion and conductivity. Although it can be formed with a silver paste material or a conductive adhesive material, it is not limited thereto.
絶縁層８は、湾曲を許容しない固体基板のみでなくフレキシブル性を有してもよい。貫通孔構造は、柱体構造または錐体構造または円錐台の立体図形構造を有しており、球状化合物半導体セルを保持することを特徴としている。すなわち、球状化合物半導体セル直径より小さい空孔である必要がある。また、保持された後に生じた隙間に関しては、絶縁性材料で補填することができる。たとえば絶縁性樹脂材料などがこれにあたる。
The insulating layer 8 may have flexibility as well as a solid substrate that does not allow bending. The through-hole structure has a columnar structure, a cone structure, or a three-dimensional figure structure of a truncated cone, and is characterized by holding a spherical compound semiconductor cell. That is, it is necessary that the pores are smaller than the diameter of the spherical compound semiconductor cell. Further, gaps generated after being held can be compensated with an insulating material. For example, an insulating resin material corresponds to this.
配線電極９は導電性材料を用いており、図５（ａ）～（ｃ）に示すように、絶縁層が形成された導電性支持基板１０上に様々なパターン形状で形成することができる。これによりセルの直並列を実現できる。ただし、球状化合物半導体セルの球状電極１の表面１ｂの導電体及び球状化合物層及び緩衝層３とは物理的及び電気的にも絶縁され、透明電極層５と物理的及び電気的に接合される。
The wiring electrode 9 uses a conductive material, and can be formed in various pattern shapes on the conductive support substrate 10 on which the insulating layer is formed, as shown in FIGS. As a result, cell series-parallel can be realized. However, the conductor, the spherical compound layer, and the buffer layer 3 on the surface 1b of the spherical electrode 1 of the spherical compound semiconductor cell are physically and electrically insulated and are physically and electrically joined to the transparent electrode layer 5. .
導電性支持基板１０は湾曲を許容しない固体基板のみでなくフレキシブル性を有してもよく、基板の全面又は、球状導電体からの電極引き出し線７との接点が、導電性材料であることが好ましい。Ｍｏ，Ａｌ，Ｎｉ，Ｔｉ，Ｃｕ，Ｍｇ，Ｌｉ，Ｆｅ，Ａｕ，Ａｇなどの金属材料がこれにあたるがこの限りでなく、高導電性の有機化合物導電材料や無機化合物材料などでもよい。
The conductive support substrate 10 may be flexible as well as a solid substrate that does not allow bending, and the entire surface of the substrate or the contact point with the electrode lead wire 7 from the spherical conductor may be a conductive material. preferable. A metal material such as Mo, Al, Ni, Ti, Cu, Mg, Li, Fe, Au, or Ag corresponds to this, but is not limited thereto, and may be a highly conductive organic compound conductive material or inorganic compound material.
球状電極１の核１ａ、又は核１ａと表面１ｂの導電体との層間、又は表面１ｂの導電体と化合物半導体層２の層間のいずれか又は全てにアルカリ金属単元素またはその化合物、又はアルカリ土類金属単元素またはその化合物などのアルカリ系元素が存在することが好ましい。また、化合物半導体層２中にもアルカリ系元素が存在することが好ましい。
Alkali metal single element or a compound thereof, or alkaline earth is present in any or all of the core 1a of the spherical electrode 1 or the layer between the core 1a and the conductor on the surface 1b, or between the conductor on the surface 1b and the compound semiconductor layer 2. It is preferable that an alkaline element such as a single metal element or a compound thereof is present. In addition, it is preferable that an alkaline element is also present in the compound semiconductor layer 2.
次に、実施例を挙げて本発明をより具体的に説明する。ただし、本発明はそれらの実施例のみに限定されるものではない。
Next, the present invention will be described more specifically with reference to examples. However, this invention is not limited only to those Examples.
（実施例１）
Ｃｕ粉末、Ｉｎ粉末、硫黄粉末をそれぞれ０.０５mol，０.０５mol，０.１mol用意し、球状電極１として直径３ｍｍの球状Ｍｏボールを用意した。それらの粉末及びボールを遊星ボールミル容器に仕込み、遊星ボールミルにて１時間ミリング処理を実施することで、球状Ｍｏ表面にＣｕＩｎＳ2のカルコパイライト構造の化合物半導体を形成した。図６にミリング実施前後の球状ボール写真図及び球状化合物半導体セル写真図を示す。また、表面に堆積された化合物半導体層２の電子顕微鏡写真を図７（ａ）に示すが、結晶粒径２μｍ～１０μｍが連なり球状膜を形成していることがわかる。また、図８に示すＸ線回折結果よりカルコパイライト構造を示すことがわかる。ここで、球状Ｍｏ基板は少なくとも表面にＭｏが堆積されていればよく、この限りではない。また、遊星ボールミルに限定せず、サンドミルやビーズミルなど他の手法でも良い。 Example 1
Cu powder, In powder, and sulfur powder were prepared as 0.05 mol, 0.05 mol, and 0.1 mol, respectively, and a spherical Mo ball having a diameter of 3 mm was prepared as thespherical electrode 1. These powders and balls were charged into a planetary ball mill container and milled for 1 hour with a planetary ball mill to form a compound semiconductor having a chalcopyrite structure of CuInS 2 on the spherical Mo surface. FIG. 6 shows a spherical ball photograph and a spherical compound semiconductor cell photograph before and after milling. Further, an electron micrograph of the compound semiconductor layer 2 deposited on the surface is shown in FIG. 7A, and it can be seen that a crystal film diameter of 2 μm to 10 μm is connected to form a spherical film. Moreover, it turns out that a chalcopyrite structure is shown from the X-ray-diffraction result shown in FIG. Here, the spherical Mo substrate is not limited to this as long as Mo is deposited on at least the surface. Further, the method is not limited to the planetary ball mill, and other methods such as a sand mill and a bead mill may be used.
Ｃｕ粉末、Ｉｎ粉末、硫黄粉末をそれぞれ０.０５mol，０.０５mol，０.１mol用意し、球状電極１として直径３ｍｍの球状Ｍｏボールを用意した。それらの粉末及びボールを遊星ボールミル容器に仕込み、遊星ボールミルにて１時間ミリング処理を実施することで、球状Ｍｏ表面にＣｕＩｎＳ2のカルコパイライト構造の化合物半導体を形成した。図６にミリング実施前後の球状ボール写真図及び球状化合物半導体セル写真図を示す。また、表面に堆積された化合物半導体層２の電子顕微鏡写真を図７（ａ）に示すが、結晶粒径２μｍ～１０μｍが連なり球状膜を形成していることがわかる。また、図８に示すＸ線回折結果よりカルコパイライト構造を示すことがわかる。ここで、球状Ｍｏ基板は少なくとも表面にＭｏが堆積されていればよく、この限りではない。また、遊星ボールミルに限定せず、サンドミルやビーズミルなど他の手法でも良い。 Example 1
Cu powder, In powder, and sulfur powder were prepared as 0.05 mol, 0.05 mol, and 0.1 mol, respectively, and a spherical Mo ball having a diameter of 3 mm was prepared as the
球状電極１の表面１ｂに化合物半導体層２を形成した後、５００℃の熱処理を施すことで、図７（ｂ）に示すよう結晶粒径の大きい化合物半導体層２を得た。表面凹凸は維持しており、球状電極１の表面積よりも比表面積は増大している。熱処理温度はこれに限らず目的の結晶粒径及び結晶性に相応した温度で加熱すればよい。
After forming the compound semiconductor layer 2 on the surface 1b of the spherical electrode 1, the compound semiconductor layer 2 having a large crystal grain size was obtained as shown in FIG. The surface unevenness is maintained, and the specific surface area is larger than the surface area of the spherical electrode 1. The heat treatment temperature is not limited to this, and heating may be performed at a temperature corresponding to the target crystal grain size and crystallinity.
次に、化合物半導体層２の表面に化学溶液析出法により、膜厚５０ｎｍのＣｄＳ膜を析出させて、緩衝層３（第一の緩衝層）を形成した。化学溶液析出法は一定温度４０℃以上の化学溶液中に球状電極１に化合物半導体層２が堆積された状態で浸漬することにより行った。膜厚は５０ｎｍ～１００ｎｍであればよく、膜形成は本手法に限らず、ゾルゲル法や蒸着法やスパッタ法などでもよい。その後、ノンドープＺｎＯをゾルゲル法により溶液塗布し、大気雰囲気中で１００℃１０分の乾燥と、３００℃６０分の焼成を行い、緩衝層４（第二の緩衝層）を形成した。その後、酸化インジウムをゾルゲル法により溶液塗布し、大気雰囲気中で１００℃１０分の乾燥と、３００℃６０分の焼成を行い、透明電極層５を堆積し、球状化合物半導体セルを作製した。なお、緩衝層、透明電極層５の膜形成は、溶液塗布法、真空蒸着法、あるいはスパッタ法などでもよい。
Next, a 50 nm-thick CdS film was deposited on the surface of the compound semiconductor layer 2 by a chemical solution deposition method to form a buffer layer 3 (first buffer layer). The chemical solution deposition method was performed by immersing in a chemical solution having a constant temperature of 40 ° C. or higher with the compound semiconductor layer 2 deposited on the spherical electrode 1. The film thickness may be 50 nm to 100 nm, and the film formation is not limited to this method, and a sol-gel method, a vapor deposition method, a sputtering method, or the like may be used. Thereafter, a solution of non-doped ZnO was applied by a sol-gel method, followed by drying at 100 ° C. for 10 minutes and baking at 300 ° C. for 60 minutes to form the buffer layer 4 (second buffer layer). Thereafter, a solution of indium oxide was applied by a sol-gel method, dried at 100 ° C. for 10 minutes and baked at 300 ° C. for 60 minutes in the atmosphere, and the transparent electrode layer 5 was deposited to produce a spherical compound semiconductor cell. The film formation of the buffer layer and the transparent electrode layer 5 may be a solution coating method, a vacuum deposition method, a sputtering method, or the like.
（実施例２）
実施例１の球状化合物半導体セルにおいて、透明電極層５の表面に反射防止層６として、化学気相成長（ＣＶＤ：Chemical Vapor Deposition）法により酸化チタン（ＴｉＯ2）膜を形成した。本実施形態のように反射防止層６を形成することで、光の表面反射を低減することができ、入射光量の増加を図ることができる。 (Example 2)
In the spherical compound semiconductor cell of Example 1, a titanium oxide (TiO 2 ) film was formed as the antireflection layer 6 on the surface of the transparent electrode layer 5 by a chemical vapor deposition (CVD) method. By forming the antireflection layer 6 as in the present embodiment, the surface reflection of light can be reduced, and the amount of incident light can be increased.
実施例１の球状化合物半導体セルにおいて、透明電極層５の表面に反射防止層６として、化学気相成長（ＣＶＤ：Chemical Vapor Deposition）法により酸化チタン（ＴｉＯ2）膜を形成した。本実施形態のように反射防止層６を形成することで、光の表面反射を低減することができ、入射光量の増加を図ることができる。 (Example 2)
In the spherical compound semiconductor cell of Example 1, a titanium oxide (TiO 2 ) film was formed as the antireflection layer 6 on the surface of the transparent electrode layer 5 by a chemical vapor deposition (CVD) method. By forming the antireflection layer 6 as in the present embodiment, the surface reflection of light can be reduced, and the amount of incident light can be increased.
（実施例３）
実施例１において、球状Ｍｏの核がケイ酸塩ガラス材質のアルカリ化合物材料で構成された球状電極１を用いた。それ以外は実施例１と同様の手法で球状化合物半導体セルを作製した。 (Example 3)
In Example 1, thespherical electrode 1 in which the core of the spherical Mo was made of an alkali compound material made of silicate glass was used. Otherwise, a spherical compound semiconductor cell was produced in the same manner as in Example 1.
実施例１において、球状Ｍｏの核がケイ酸塩ガラス材質のアルカリ化合物材料で構成された球状電極１を用いた。それ以外は実施例１と同様の手法で球状化合物半導体セルを作製した。 (Example 3)
In Example 1, the
（実施例４）
上面図が図５（ａ）または（ｃ）の導電性配線を有し、且つ貫通孔を有する絶縁層８に実施例１の緩衝層まで形成した状態の球状化合物セルを配置した状態で、エッチング溶剤中へ浸漬する。この際、球状電極１の下底部のみが浸漬する程度で、球状電極１の表面１ｂの導電体が現れるまでエッチング処理を施す。乾燥処理を施した後、銀ペーストなどの導電性接着剤を貫通孔内部に充填し、球状電極１の表面１ｂの導電体と導電性支持基板１０としてのＡｌプレートの片面とを接着させた。その後、球状表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。熱処理後、実施例２の手法にて反射防止層６を形成し、図１（ａ）に示すモジュール構造を得た。本構造は球状化合物セルの全並列接続構造である。図５（ａ）および（ｃ）は全並列接続用パターンの一例であり、作製手法や構造はこの限りではなく、例えば図３は配線電極９の断面形状が図１（ａ）と異なる例である。 Example 4
Etching with a spherical compound cell in a state where the top view has the conductive wiring of FIG. 5A or 5C and the buffer layer of Example 1 is formed in the insulatinglayer 8 having a through hole. Immerse in solvent. At this time, the etching process is performed until only the lower bottom portion of the spherical electrode 1 is immersed until the conductor on the surface 1b of the spherical electrode 1 appears. After the drying treatment, a conductive adhesive such as silver paste was filled in the through hole, and the conductor on the surface 1b of the spherical electrode 1 and one side of the Al plate as the conductive support substrate 10 were adhered. Thereafter, a transparent electrode layer ZnO: Al was deposited by sputtering so as to be deposited on the spherical surface side. After the heat treatment, an antireflection layer 6 was formed by the method of Example 2 to obtain a module structure shown in FIG. This structure is an all parallel connection structure of spherical compound cells. FIGS. 5A and 5C are examples of the pattern for all parallel connection, and the manufacturing method and structure are not limited to this. For example, FIG. 3 is an example in which the cross-sectional shape of the wiring electrode 9 is different from that in FIG. is there.
上面図が図５（ａ）または（ｃ）の導電性配線を有し、且つ貫通孔を有する絶縁層８に実施例１の緩衝層まで形成した状態の球状化合物セルを配置した状態で、エッチング溶剤中へ浸漬する。この際、球状電極１の下底部のみが浸漬する程度で、球状電極１の表面１ｂの導電体が現れるまでエッチング処理を施す。乾燥処理を施した後、銀ペーストなどの導電性接着剤を貫通孔内部に充填し、球状電極１の表面１ｂの導電体と導電性支持基板１０としてのＡｌプレートの片面とを接着させた。その後、球状表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。熱処理後、実施例２の手法にて反射防止層６を形成し、図１（ａ）に示すモジュール構造を得た。本構造は球状化合物セルの全並列接続構造である。図５（ａ）および（ｃ）は全並列接続用パターンの一例であり、作製手法や構造はこの限りではなく、例えば図３は配線電極９の断面形状が図１（ａ）と異なる例である。 Example 4
Etching with a spherical compound cell in a state where the top view has the conductive wiring of FIG. 5A or 5C and the buffer layer of Example 1 is formed in the insulating
（実施例５）
上面図が図５（ｂ）の導電性配線を有し、且つ貫通孔を有する絶縁層８に実施例１の緩衝層まで形成した状態の球状化合物セルを配置した状態で、エッチング溶剤中へ浸漬する。この際、球状電極１の下底部のみが浸漬する程度で、球状電極１の表面１ｂの導電体が現れるまでエッチング処理を施す。乾燥処理を施した後、銀ペーストなどの導電性接着剤を貫通孔内部に充填し、球状電極１の表面１ｂの導電体と導電性支持基板１０としてのＡｌプレートの片面とを接着させた。その後、球状表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。熱処理後、実施例２の手法にて反射防止層６を形成しモジュール構造を得た。図５（ｂ）は４列に区切りが設けてあり、各列を直列接続することで球状化合物セル４並列接続を１区切りとし、４並列４直列接続を可能とした構造である。導電性配線パターンはこの限りでなく他のパターンでもよい。 (Example 5)
The top view has the conductive wiring of FIG. 5 (b) and is immersed in the etching solvent in a state where the spherical compound cell in the state where the buffer layer of Example 1 is formed is disposed on the insulatinglayer 8 having the through hole. To do. At this time, the etching process is performed until only the lower bottom portion of the spherical electrode 1 is immersed until the conductor on the surface 1b of the spherical electrode 1 appears. After the drying treatment, a conductive adhesive such as silver paste was filled in the through hole, and the conductor on the surface 1b of the spherical electrode 1 and one side of the Al plate as the conductive support substrate 10 were adhered. Thereafter, a transparent electrode layer ZnO: Al was deposited by sputtering so as to be deposited on the spherical surface side. After the heat treatment, an antireflection layer 6 was formed by the method of Example 2 to obtain a module structure. FIG. 5B shows a structure in which four columns are provided with a partition, and each column is connected in series, so that the parallel connection of the spherical compound cells 4 is one partition and four parallel 4 series connections are possible. The conductive wiring pattern is not limited to this, and other patterns may be used.
上面図が図５（ｂ）の導電性配線を有し、且つ貫通孔を有する絶縁層８に実施例１の緩衝層まで形成した状態の球状化合物セルを配置した状態で、エッチング溶剤中へ浸漬する。この際、球状電極１の下底部のみが浸漬する程度で、球状電極１の表面１ｂの導電体が現れるまでエッチング処理を施す。乾燥処理を施した後、銀ペーストなどの導電性接着剤を貫通孔内部に充填し、球状電極１の表面１ｂの導電体と導電性支持基板１０としてのＡｌプレートの片面とを接着させた。その後、球状表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。熱処理後、実施例２の手法にて反射防止層６を形成しモジュール構造を得た。図５（ｂ）は４列に区切りが設けてあり、各列を直列接続することで球状化合物セル４並列接続を１区切りとし、４並列４直列接続を可能とした構造である。導電性配線パターンはこの限りでなく他のパターンでもよい。 (Example 5)
The top view has the conductive wiring of FIG. 5 (b) and is immersed in the etching solvent in a state where the spherical compound cell in the state where the buffer layer of Example 1 is formed is disposed on the insulating
（実施例６）
図１（ｂ）に記載の構造は貫通孔を有する絶縁層８において、貫通孔が空孔及び配線電極９で構成されており、空孔部の貫通孔へ実施例１の緩衝層まで形成した状態の球状化合物セルを配置した状態で、エッチング溶剤中へ浸漬する。この際、球状電極１の下底部のみが浸漬する程度で、球状電極１の表面１ｂの導電体が現れるまでエッチング処理を施す。乾燥処理を施した後、銀ペーストなどの導電性接着剤を空孔部の貫通孔内部に充填し、球状電極１の表面１ｂの導電体と導電性支持基板１０としてのＡｌプレートの片面とを接着させた。その後、球状化合物表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。この際、貫通孔に充填した配線電極９と電気的に接合させる。熱乾燥処理後、実施例２の手法にて反射防止層６を形成しモジュール構造を得た。本構造は基板を応用した各球状化合物セルの直列接続を実現した構造である。 (Example 6)
In the structure shown in FIG. 1B, in the insulatinglayer 8 having a through hole, the through hole is constituted by a hole and a wiring electrode 9, and the buffer layer of Example 1 was formed to the through hole of the hole part. In a state where the spherical compound cell in the state is arranged, it is immersed in an etching solvent. At this time, an etching process is performed until the conductor on the surface 1b of the spherical electrode 1 appears so that only the lower bottom portion of the spherical electrode 1 is immersed. After performing the drying process, a conductive adhesive such as silver paste is filled in the through hole of the hole portion, and the conductor on the surface 1b of the spherical electrode 1 and one side of the Al plate as the conductive support substrate 10 are combined. Glued. Thereafter, a transparent electrode layer ZnO: Al was deposited by sputtering so as to be deposited on the spherical compound surface side. At this time, the wiring electrode 9 filled in the through hole is electrically joined. After the heat drying treatment, an antireflection layer 6 was formed by the method of Example 2 to obtain a module structure. This structure is a structure that realizes series connection of spherical compound cells using a substrate.
図１（ｂ）に記載の構造は貫通孔を有する絶縁層８において、貫通孔が空孔及び配線電極９で構成されており、空孔部の貫通孔へ実施例１の緩衝層まで形成した状態の球状化合物セルを配置した状態で、エッチング溶剤中へ浸漬する。この際、球状電極１の下底部のみが浸漬する程度で、球状電極１の表面１ｂの導電体が現れるまでエッチング処理を施す。乾燥処理を施した後、銀ペーストなどの導電性接着剤を空孔部の貫通孔内部に充填し、球状電極１の表面１ｂの導電体と導電性支持基板１０としてのＡｌプレートの片面とを接着させた。その後、球状化合物表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。この際、貫通孔に充填した配線電極９と電気的に接合させる。熱乾燥処理後、実施例２の手法にて反射防止層６を形成しモジュール構造を得た。本構造は基板を応用した各球状化合物セルの直列接続を実現した構造である。 (Example 6)
In the structure shown in FIG. 1B, in the insulating
（実施例７）
上面図が図５（ａ）または（ｃ）の導電性配線を有し、且つ貫通孔を有する絶縁層８に、実施例１の緩衝層まで形成した状態の球状化合物セルを半分に切断し、切断面を貫通孔側へ配置する。その後、銀ペーストなどの導電性接着剤を貫通孔内部に充填し、球状電極１の表面１ｂの導電体と、導電性支持基板１０としてＡｌプレートの片面を接着させた。その後、球状表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。熱処理後、実施例４の手法にて反射防止層６を形成し、図２に示すモジュール構造を得た。 (Example 7)
The top view has the conductive wiring of FIG. 5 (a) or (c), and in the insulatinglayer 8 having a through hole, the spherical compound cell in a state where the buffer layer of Example 1 is formed is cut in half, The cut surface is arranged on the through hole side. Thereafter, a conductive adhesive such as a silver paste was filled in the through hole, and the conductor on the surface 1 b of the spherical electrode 1 was bonded to one side of the Al plate as the conductive support substrate 10. Thereafter, a transparent electrode layer ZnO: Al was deposited by sputtering so as to be deposited on the spherical surface side. After the heat treatment, an antireflection layer 6 was formed by the method of Example 4 to obtain a module structure shown in FIG.
上面図が図５（ａ）または（ｃ）の導電性配線を有し、且つ貫通孔を有する絶縁層８に、実施例１の緩衝層まで形成した状態の球状化合物セルを半分に切断し、切断面を貫通孔側へ配置する。その後、銀ペーストなどの導電性接着剤を貫通孔内部に充填し、球状電極１の表面１ｂの導電体と、導電性支持基板１０としてＡｌプレートの片面を接着させた。その後、球状表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。熱処理後、実施例４の手法にて反射防止層６を形成し、図２に示すモジュール構造を得た。 (Example 7)
The top view has the conductive wiring of FIG. 5 (a) or (c), and in the insulating
（実施例８）
実施例４に記載の構造を両面に設置した構造を図４（ａ）に示す。本構造は上面図が図５（ａ）または（ｃ）の導電性配線を有し、且つ貫通孔を有する絶縁層８に実施例１の緩衝層までを形成した状態の球状化合物セルを配置した状態で、エッチング溶剤中へ浸漬する。この際、球状電極１の下底部のみが浸漬する程度で、球状電極１の表面１ｂの導電体が現れるまでエッチング処理を施す。乾燥処理を施した後、銀ペーストなどの導電性接着剤を貫通孔内部に充填し、球状電極１の表面１ｂの導電体と導電性支持基板１０としてのＡｌプレートの両面とを接着させた。その後、球状表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。熱処理後、実施例２の手法にて反射防止層６を形成し、図４（ａ）に示すモジュール構造を得た。本構造は球状化合物セルの全並列接続構造である。図５（ａ）および（ｃ）は全並列接続用パターンの一例であり、作製手法や構造はこの限りではなく、図４（ｂ）などの構造もある。 (Example 8)
FIG. 4A shows a structure in which the structure described in Example 4 is installed on both sides. In this structure, a spherical compound cell in a state where the top view has the conductive wiring of FIG. 5A or 5C and the buffer layer of Example 1 is formed in the insulatinglayer 8 having a through hole is arranged. In the state, it is immersed in an etching solvent. At this time, an etching process is performed until the conductor on the surface 1b of the spherical electrode 1 appears so that only the lower bottom portion of the spherical electrode 1 is immersed. After the drying treatment, a conductive adhesive such as silver paste was filled in the through hole, and the conductor on the surface 1b of the spherical electrode 1 and both surfaces of the Al plate as the conductive support substrate 10 were adhered. Thereafter, a transparent electrode layer ZnO: Al was deposited by sputtering so as to be deposited on the spherical surface side. After the heat treatment, an antireflection layer 6 was formed by the method of Example 2 to obtain a module structure shown in FIG. This structure is an all parallel connection structure of spherical compound cells. FIGS. 5A and 5C are examples of the all-parallel connection pattern. The manufacturing method and structure are not limited to this, and there are structures such as FIG.
実施例４に記載の構造を両面に設置した構造を図４（ａ）に示す。本構造は上面図が図５（ａ）または（ｃ）の導電性配線を有し、且つ貫通孔を有する絶縁層８に実施例１の緩衝層までを形成した状態の球状化合物セルを配置した状態で、エッチング溶剤中へ浸漬する。この際、球状電極１の下底部のみが浸漬する程度で、球状電極１の表面１ｂの導電体が現れるまでエッチング処理を施す。乾燥処理を施した後、銀ペーストなどの導電性接着剤を貫通孔内部に充填し、球状電極１の表面１ｂの導電体と導電性支持基板１０としてのＡｌプレートの両面とを接着させた。その後、球状表面側に堆積するよう透明電極層ＺｎＯ：Ａｌをスパッタ法にて堆積した。熱処理後、実施例２の手法にて反射防止層６を形成し、図４（ａ）に示すモジュール構造を得た。本構造は球状化合物セルの全並列接続構造である。図５（ａ）および（ｃ）は全並列接続用パターンの一例であり、作製手法や構造はこの限りではなく、図４（ｂ）などの構造もある。 (Example 8)
FIG. 4A shows a structure in which the structure described in Example 4 is installed on both sides. In this structure, a spherical compound cell in a state where the top view has the conductive wiring of FIG. 5A or 5C and the buffer layer of Example 1 is formed in the insulating
以上説明した本発明の実施形態により、光吸収層の投影面積が増大し、且つ材料使用量を大幅に低減可能な球状太陽電池セルを化合物半導体にて作製することができる。また、セル化の再結合及びリーク漏れ電流の抑制を図ることができる。なお、本発明は発光素子への適用も可能である。
According to the embodiment of the present invention described above, a spherical solar battery cell that can increase the projected area of the light absorption layer and can significantly reduce the amount of material used can be made of a compound semiconductor. Further, recombination of cells and suppression of leakage leakage current can be achieved. Note that the present invention can also be applied to a light emitting element.
１ 球状電極
１ａ 核
１ｂ 表面
２ 化合物半導体層
３ 緩衝層（第一の緩衝層）
４ 緩衝層（第二の緩衝層）
５ 透明電極層
６ 反射防止層
７ 電極引き出し線
８ 絶縁層
９ 配線電極
１０ 導電性支持基板
２１ 基板
２２ 電極
２３ Ｃｕ薄膜
２４ Ｉｎ薄膜
２５ カルコパイライト型化合物薄膜
２６ カルコゲン薄膜 1spherical electrode 1a nucleus 1b surface 2 compound semiconductor layer 3 buffer layer (first buffer layer)
4 Buffer layer (second buffer layer)
DESCRIPTION OF SYMBOLS 5 Transparent electrode layer 6Antireflection layer 7 Electrode lead wire 8 Insulating layer 9 Wiring electrode 10 Conductive support substrate 21 Substrate 22 Electrode 23 Cu thin film 24 In thin film 25 Chalcopyrite type compound thin film 26 Chalcogen thin film
１ａ 核
１ｂ 表面
２ 化合物半導体層
３ 緩衝層（第一の緩衝層）
４ 緩衝層（第二の緩衝層）
５ 透明電極層
６ 反射防止層
７ 電極引き出し線
８ 絶縁層
９ 配線電極
１０ 導電性支持基板
２１ 基板
２２ 電極
２３ Ｃｕ薄膜
２４ Ｉｎ薄膜
２５ カルコパイライト型化合物薄膜
２６ カルコゲン薄膜 1
4 Buffer layer (second buffer layer)
DESCRIPTION OF SYMBOLS 5 Transparent electrode layer 6
Claims (16)
- 少なくとも表面が導電体である球状電極と、前記球状電極の表面に形成されたカルコパイライト構造の化合物半導体層と、前記化合物半導体層の表面に形成された緩衝層と、前記緩衝層の表面に形成された透明電極層と、を具備することを特徴とする球状化合物半導体セル。 A spherical electrode having at least a surface of a conductor, a compound semiconductor layer having a chalcopyrite structure formed on the surface of the spherical electrode, a buffer layer formed on the surface of the compound semiconductor layer, and formed on the surface of the buffer layer A spherical compound semiconductor cell comprising: a transparent electrode layer formed on the substrate;
- 請求の範囲第１項において、前記透明電極層の表面に反射防止層を具備することを特徴とする球状化合物半導体セル。 The spherical compound semiconductor cell according to claim 1, further comprising an antireflection layer on a surface of the transparent electrode layer.
- 請求の範囲第１項において、前記緩衝層が金属酸化物、金属硫化物、または、金属窒化物のいずれかで構成されていることを特徴とする球状化合物半導体セル。 The spherical compound semiconductor cell according to claim 1, wherein the buffer layer is made of any one of a metal oxide, a metal sulfide, and a metal nitride.
- 請求の範囲第１項において、前記緩衝層が第一の緩衝層と第二の緩衝層を有し、前記第一の緩衝層を構成する材料が金属酸化物、金属硫化物、または、金属窒化物のいずれかであり、前記第二の緩衝層を構成する材料が金属酸化物であることを特徴とする球状化合物半導体セル。 The buffer layer according to claim 1, wherein the buffer layer has a first buffer layer and a second buffer layer, and a material constituting the first buffer layer is a metal oxide, a metal sulfide, or a metal nitride. A spherical compound semiconductor cell, wherein the material constituting the second buffer layer is a metal oxide.
- 請求の範囲第１項において、前記化合物半導体層は、ある１次元方向の長さが５ｎｍ～１００μｍである結晶粒径が連なり凹凸膜を構成していることを特徴とする球状化合物半導体セル。 2. The spherical compound semiconductor cell according to claim 1, wherein the compound semiconductor layer forms a concavo-convex film in which crystal grains having a length in a one-dimensional direction of 5 nm to 100 μm are connected.
- 請求の範囲第１項において、前記球状電極の直径が１００μｍ～１０ｃｍであることを特徴とする球状化合物半導体セル。 2. The spherical compound semiconductor cell according to claim 1, wherein the spherical electrode has a diameter of 100 μm to 10 cm.
- 請求の範囲第４項において、前記化合物半導体層と前記第一の緩衝層との界面近傍に、前記化合物半導体層の構成材料と前記第一の緩衝層を構成する材料との反応生成物が形成されることを特徴とする球状化合物半導体セル。 The reaction product of the constituent material of the compound semiconductor layer and the material constituting the first buffer layer is formed in the vicinity of the interface between the compound semiconductor layer and the first buffer layer. A spherical compound semiconductor cell.
- 請求の範囲第１項において、前記化合物半導体層は、材料固有のバンドギャップが０.１～５［ｅＶ］であることを特徴とする球状化合物半導体セル。 2. The spherical compound semiconductor cell according to claim 1, wherein the compound semiconductor layer has a material specific band gap of 0.1 to 5 [eV].
- 請求の範囲第１項において、前記化合物半導体層の波長４５０ｎｍ～５００ｎｍにおける吸収係数が１×１０3～１×１０10［ｃｍ-1］であることを特徴とする球状化合物半導体セル。 2. The spherical compound semiconductor cell according to claim 1, wherein the compound semiconductor layer has an absorption coefficient of 1 × 10 3 to 1 × 10 10 [cm −1 ] at a wavelength of 450 nm to 500 nm.
- 請求の範囲第１項において、前記化合物半導体層の膜厚は５ｎｍ～５００μｍであることを特徴とする球状化合物半導体セル。 2. The spherical compound semiconductor cell according to claim 1, wherein the thickness of the compound semiconductor layer is 5 nm to 500 μm.
- 少なくとも表面が導電体である球状電極と、前記球状電極の表面に形成されたカルコパイライト構造の化合物半導体層と、前記化合物半導体層の表面に形成された緩衝層と、前記緩衝層の表面に形成された透明電極層と、を具備し、前記球状電極の導電体が露出した面を有する球状化合物半導体セルと、導電性支持基板の表面に所定のパターンで貫通孔が形成され絶縁層を有する基板とを備え、
複数個の前記球状化合物半導体セルが前記絶縁層の貫通孔部にそれぞれ配置され、前記球状電極の導電体と前記導電性支持基板とが電気的に接続された構造の太陽電池モジュール。 A spherical electrode having at least a surface of a conductor, a compound semiconductor layer having a chalcopyrite structure formed on the surface of the spherical electrode, a buffer layer formed on the surface of the compound semiconductor layer, and formed on the surface of the buffer layer A transparent electrode layer, a spherical compound semiconductor cell having a surface on which the conductor of the spherical electrode is exposed, and a substrate having an insulating layer in which through holes are formed in a predetermined pattern on the surface of the conductive support substrate And
A solar cell module having a structure in which a plurality of the spherical compound semiconductor cells are respectively disposed in through-hole portions of the insulating layer, and the conductor of the spherical electrode and the conductive support substrate are electrically connected. - 球状電極の表面に化合物半導体層、透明電極層を有する球状化合物半導体セルの製造方法であって、少なくとも表面が導電体である前記球状電極と、Ｉｂ族元素、IIIｂ族元素及びVIｂ族元素を含む単元素材料または化合物元素材料の粉末を混合し、メカニカルミリング処理を施し、前記球状電極の表面にカルコパイライト構造の前記化合物半導体層を形成する工程を有することを特徴とする球状化合物半導体セルの製造方法。 A method for producing a spherical compound semiconductor cell having a compound semiconductor layer and a transparent electrode layer on the surface of a spherical electrode, comprising at least the spherical electrode whose surface is a conductor, a group Ib element, a group IIIb element and a group VIb element Production of a spherical compound semiconductor cell comprising a step of mixing powder of a single element material or compound element material, subjecting to mechanical milling, and forming the compound semiconductor layer having a chalcopyrite structure on the surface of the spherical electrode Method.
- 請求の範囲第１２項において、前記球状電極の表面にカルコパイライト構造の化合物半導体層を形成した後、前記化合物半導体層の表面に緩衝層を形成する工程と、前記緩衝層の表面に透明電極層を形成する工程とを有することを特徴とする球状化合物半導体セルの製造方法。 The step of forming a buffer layer on the surface of the compound semiconductor layer after forming a compound semiconductor layer having a chalcopyrite structure on the surface of the spherical electrode according to claim 12, and a transparent electrode layer on the surface of the buffer layer And a step of forming a spherical compound semiconductor cell.
- 請求の範囲第１３項において、前記球状電極の表面に形成した化合物半導体層を加熱する工程を有することを特徴とする球状化合物半導体セルの製造方法。 14. The method of manufacturing a spherical compound semiconductor cell according to claim 13, further comprising a step of heating the compound semiconductor layer formed on the surface of the spherical electrode.
- 少なくとも表面が導電体である球状電極の表面にカルコパイライト構造の化合物半導体層、緩衝層が順に形成された構造体を、規則的に設けられた貫通孔を有する絶縁基板の該貫通孔へ配列する工程と、
該構造体の下底部のうち貫通孔におさまる範囲内の各層を前記球状電極の表面の導電体表面まで除去する工程と、
前記貫通孔内の該球状電極の表面の導電体に電極引き出し線を形成する工程と、
該電極引き出し線を導電性支持基板の片面又は両面に接続する工程と、
前記緩衝層上に透明電極層を形成する工程と、を含むことを特徴とする球状化合物太陽電池モジュールの製造方法。 A structure in which a compound semiconductor layer having a chalcopyrite structure and a buffer layer are sequentially formed on the surface of a spherical electrode having at least a surface of a conductor is arranged in the through hole of the insulating substrate having regularly provided through holes. Process,
Removing each layer within the range of the lower bottom of the structure to fit in the through hole up to the conductor surface of the surface of the spherical electrode;
Forming an electrode lead wire on the conductor on the surface of the spherical electrode in the through hole;
Connecting the electrode lead wires to one or both sides of the conductive support substrate;
Forming a transparent electrode layer on the buffer layer, and a method for producing a spherical compound solar cell module. - 請求の範囲第１項に記載の前記球状化合物半導体セルの球状電極の表面の導電体表面が露出するように切断し、規則的に設けられた貫通孔を有する絶縁基板の該貫通孔内に前記球状化合物半導体セルの切断面を向けて配列する工程と、
前記貫通孔内の該球状電極の表面の導電体に電極引き出し線を形成する工程と、
該電極引き出し線を導電性支持基板の片面又は両面に接続する工程と、
前記球状化合物半導体セルの前記緩衝層上に透明電極層を形成する工程と、を含むことを特徴とする球状化合物太陽電池モジュールの製造方法。 The spherical compound semiconductor cell according to claim 1 is cut so that the conductor surface of the spherical electrode surface is exposed, and the insulating substrate having regularly provided through holes is inserted into the through holes. Arranging the spherical compound semiconductor cell with the cut surface facing;
Forming an electrode lead wire on the conductor on the surface of the spherical electrode in the through hole;
Connecting the electrode lead wires to one or both sides of the conductive support substrate;
Forming a transparent electrode layer on the buffer layer of the spherical compound semiconductor cell, and a method for producing a spherical compound solar cell module.
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