JP6231641B2 - Electronic device and method of manufacturing the same - Google Patents

Description

[Cross-reference of related applications]
This application claims priority from US patent application Ser. No. 14 / 879,884, filed Oct. 9, 2015. In addition, this application claims priority from US patent application Ser. No. 15 / 235,472, filed Aug. 12, 2016. Both applications are hereby incorporated by reference in their entirety.

[Technical field]
The present invention relates to an electronic device and a method for manufacturing the same, and more particularly to a printable electronic device and a method for manufacturing the same.

  Single crystal silicon is used for most electronic applications. There are also exceptions such as displays and some imagers, in which amorphous silicon is applied to non-semiconductor substrates to operate the display or imager pixels. In many applications, the display or imager is fabricated on top of silicon electronics. Amorphous silicon has provided sufficient performance for application to liquid crystal displays (LCDs). For example, active matrix (AM) drive transistors made from amorphous silicon have been found to be problematic for next-generation display devices such as organic light emitting diodes (OLEDs). Basically, LCDs use voltage devices and AM-OLEDs require current devices. Attempts to extend the conventional approach involve modifying the prior art amorphous silicon on glass. Amorphous silicon is applied to the entire substrate panel, typically more than 2 meters on a side, and then recrystallized by scanning a line focus across the panel using a large excimer laser. The laser needs to be pulsed to melt only the Si surface without melting the glass. This technique results in the formation of polycrystalline silicon rather than single crystal silicon. For some detector applications, the Si wafers are butted together to form a larger but more expensive device.

The mobility of any type of amorphous or polycrystalline transistor, including non-silicon and organic devices, is much less than that of single crystal silicon transistors. Compared to amorphous silicon having an electron mobility of about 1 cm ² / V · s, polysilicon is about 100 cm ² / V · s, and high-quality single crystal silicon is about 1500 cm ² / V · s. Therefore, it is advantageous to use single crystal silicon instead of amorphous silicon in such devices. In a preferred embodiment of the present invention, a plurality of planar single crystal silicon regions are fabricated on a non-silicon substrate at predetermined locations for electronic device fabrication purposes. For example, single crystal silicon wafers are too expensive and too small for large displays. That is, silicon wafers are typically 300 mm in diameter compared to current LCD panels that are longer than 2 meters on a side. In comparison, approximately spherical particles, spheres, or ellipsoidal particles of single crystal silicon having a size of 2 mm or less, which is larger than the individual pixel size, are manufactured. Patent entitled “Process for Producing Crystalline Spheres” filed Apr. 30, 1985, in the name of Witter et al., Incorporated herein by reference. Document 1 describes the production of crystalline spheres.

  In the past, others have attempted to place a diode on the curved surface of a silicon ellipsoid, which has proved difficult. In the prior art, attempts have been made to define the structure by lithography on a spherical surface, but this requires non-standard optics and has had limited success. Making electrical contacts on non-planar surfaces also requires non-standard techniques. The complexity associated with the production hindered any actual progress.

  Furthermore, the n-type dopant was doped into the curved surface of the Si sphere to form n-type Si surrounding the p-type Si region including most of the surface of the sphere. Embodiments of the present invention relate to the field of photovoltaic devices, where the planar surface and the region immediately below are doped with, for example, an n-type dopant and the underlying region is doped with a p-type dopant to form a solar cell. May be. The silicon sphere solar cell is described in a paper of Non-Patent Document 1.

  However, the present invention overcomes the aforementioned limitations of the prior art by conveniently utilizing the surface area and area associated with the planar surface of the planarized particles to fabricate electronic devices. A planar region having a structure formed therein provides a convenient and reliable way to provide electrical contact to different parts of the device. Such electronic devices have traditionally been fabricated using lithographic techniques. However, since lithography requires complex equipment and a controlled environment, it can be very expensive as a result.

  Another very important aspect of the present invention is the technology that has a smaller carbon footprint by allowing the present invention to build circuits that consume less power than similar circuits using LCD technology. Is to make it possible.

  In displays with previous generation LCD technology, white light is provided at the back of the display panel, and each LCD pixel emits red (Red: R), green (Green: G), or blue (Blue: B) light. Use filters to select. Filtering in this manner wastes 2/3 of the backlight energy. In addition, since the operation of the LCD pixel depends on the polarization, it suffers further loss by the polarizer. In addition, a part of each pixel is occupied by an amorphous silicon transistor, which blocks light coming through the panel.

  The present invention enables the production of large OLED panels that are more efficient than LCD panels. Since OLED pixels emit only the desired color of R, G or B, they do not waste energy by generating other colors that are exhausted by the filter and cause waste in the form of heat. In addition, since the OLED emitter can be fabricated on top of the backplane electronics, the radiation area can be maximized without blocking the light emitting area of the pixel. By placing the backplane electronics out of the optical path, the design can be optimized for speed and low power loss without being compromised by the optical path requirements.

US Pat. No. 4,637,855

Evaluation by Satoshi Omae (Satoshi OMAE), Takashi Minemoto, Mikio Mikio (Mikio MUROZONO), Hideyuki Takakura (Yoshihiro HAMAKAWA), and X-ray by Yoshihiro HAMAKAWA Crystal Charactorization of Spherical Silicon Solar Cell by X-ray Diffraction ", Japanese Journal of Applied Physics. Japan Journal of Applied Physics. 45, no. 5A, 2006, p. 3933-3937 # 2006, The Japan Society of Applied Physics

  According to an embodiment of the present invention, a method is provided for forming an active matrix OLED display, the method comprising providing a backplane, the step comprising providing a backplane substrate, Providing separately formed semiconductor particles, positioning the semiconductor particles at a predetermined position on the backplane substrate, and fixing the semiconductor particles against movement at a predetermined position on the backplane substrate. Removing a portion of each semiconductor particle so as to expose a cross-section of the semiconductor particle after the step of fixing the semiconductor particle immovable, the cross-section being a planar surface; One or more controllable gates above or below each planar surface Comprising: providing a child component, the controllable gate electronic component is configured to control the pixels of an active matrix OLED display, and a step. The method further includes providing an OLED assembly that includes one or more pixel regions, wherein the OLED assembly is electrically connected to one or more controllable gate electronic components to which at least one of the pixel regions corresponds. So that it is electrically connected to the backplane.

  The planar surface may have a longest dimension of less than 15 mm and greater than 1 μm, and the step of providing a backplane further provides at least two electrical contacts to each controllable gate electronic component supported on the planar surface. Steps may be included.

  According to another embodiment of the present invention, a method is provided for forming an active matrix OLED display, the method comprising providing a backplane, the backplane being separate from the backplane substrate and the backplane substrate. Semiconductor particles that are formed and then fixed at a predetermined position on the backplane substrate, the semiconductor particles being flat to remove a portion of the semiconductor particles and expose a planar surface in a cross section of the semiconductor particles. The backplane further includes a controllable gate electronic component above or directly below the planar surface, the controllable gate electronic component configured to control one or more pixels of the active matrix OLED display. Is done. The method further includes providing an OLED assembly that includes one or more pixel regions, wherein the OLED assembly is electrically connected to at least one of the pixel regions of the OLED assembly to a controllable gate electronic component. Thus, it is electrically connected to the backplane.

  The OLED assembly may be formed separately from the backplane on an OLED substrate that is different from the backplane substrate, the OLED assembly including one or more pixel contacts corresponding to each pixel region and electrically connected to the backplane. Providing the OLED assembly connected to the substrate may include coupling the OLED assembly to the backplane, the coupling step being capable of controlling at least one of the pixel contacts corresponding to at least one of the pixel regions. Electrically connecting to the gate electronic component.

  The method further includes aligning the OLED assembly and the backplane with each other to align at least one pixel contact corresponding to at least one of the pixel regions with the controllable gate electronic component prior to the combining step. May be included.

  The method may further include filling at least a portion of the gap between the OLED assembly and the backplane coupled together with a substantially black underfill.

  The step of electrically connecting includes connecting one or more of a conductive epoxy, solder, and low temperature solder to connect at least one of the one or more pixel contacts to the controllable gate electronic component. The step of using may be included.

  The backplane may further include a conformal coating that covers the backplane substrate and at least a portion of the semiconductor particles, and the semiconductor particles may be planarized to further remove a portion of the conformal coating, The surface may have a longest dimension of less than 15 mm, and at least a portion of the semiconductor particles directly below or above the planar surface may be doped with a first dopant of the first type, directly below or above the planar surface. Another portion of the semiconductor particles may be doped with a second dopant of the second type, one of the first and second dopants is n-type, and the controllable gate electronic component is A first contact at or above a planar surface in contact with the dopant and a second dopant; A planar contact or a second contact above the planar surface, the electrical connection comprising a conductive link between one of the first contact and the second contact and at least one pixel region. May be included.

  According to another embodiment of the present invention, an active matrix OLED display is provided that includes a backplane that is formed separately from the backplane substrate and the backplane substrate before the backplane. Semiconductor particles fixed at a predetermined position on a plain substrate, the semiconductor particles being planarized to remove a portion of the semiconductor particles and to expose a planar surface in a cross section of the semiconductor particles. The plane further includes controllable gate electronic components above or directly below the planar surface, and the active matrix OLED display further includes an OLED assembly that includes one or more pixel regions, the OLED assembly comprising: of At least one pixel area is electrically connected to the backplane such that the controllable gate electronic component is electrically connected to the controllable gate electronic component, which is connected to the at least one pixel of the OLED assembly. Configured to control the area.

  The active matrix OLED display may further include a substantially black underfill that fills at least a portion of the gap between the OLED assembly and the backplane coupled together.

  In an active matrix OLED display, the backplane may further include a conformal coating that covers the backplane substrate and at least a portion of the semiconductor particles, and the semiconductor particles are planarized to further remove a portion of the conformal coating. The planar surface may have a longest dimension of less than 15 mm, and at least a portion of the semiconductor particles directly below or above the planar surface may be doped with a first type of first dopant, Another portion of the semiconductor particles directly below or above the surface may be doped with a second type of second dopant, one of the first and second dopants being n-type, and further controllable gate electrons The component is a planar surface in contact with the first dopant or more And a planar contact in contact with the second dopant or a second contact above or above the planar contact, wherein the electrical connection is comprised of the first contact and the second contact. And a conductive link between at least one pixel region and at least one pixel region.

  In accordance with another embodiment of the present invention, an imager is provided, the imager including a detector assembly for detecting photons and generating an electrical signal in response thereto, and a backplane. Includes a backplane substrate and semiconductor particles that are formed separately from the backplane substrate and then fixed at a predetermined position of the backplane substrate. Planarized to expose a planar surface to the cross-section of the particle, the backplane further includes controllable gate electronic components above or directly below the planar surface, the imager further detecting the controllable gate electronic component and detecting Electrical connection to the container assembly, the electrical connection comprising a controllable gate electronic component There configured to allow sampling of the electrical signal.

  The detector assembly may be an x-ray detector.

  In this imager, the backplane may further include a conformal coating that covers the backplane substrate and at least a portion of the semiconductor particles, and the semiconductor particles may be planarized to further remove a portion of the conformal coating. Preferably, the planar surface may have a longest dimension of less than 15 mm, and at least a portion of the semiconductor particles directly below or above the planar surface may be doped with the first type of first dopant, A second portion of the second dopant may be doped in another portion of the semiconductor particle directly below or above the first, wherein one of the first and second dopants is n-type, and the controllable gate electronic component is A first contact on or above the planar surface in contact with the first dopant; A planar contact in contact with the two dopants or a second contact above the planar contact, the electrical connection between one of the first contact and the second contact and the detector assembly Conductive links may be included.

  In accordance with another embodiment of the present invention, a method for fabricating a backplane is provided, the method including one or more predetermined locations, each configured to receive one semiconductor particle. Providing a backplane substrate; providing semiconductor particles formed separately from the backplane substrate; placing the semiconductor particles on the backplane substrate; and mechanically stirring the backplane substrate and the semiconductor particles. A step of causing one semiconductor particle to occupy each position, a step of fixing the semiconductor particle to each of the respective positions of the backplane substrate, and a step of fixing the semiconductor particle to each of the respective positions. And removing a portion of each semiconductor particle to expose a cross-section of the semiconductor particle. Section is planar surfaces.

  The method may further include providing at least one controllable gate electronic component above or directly below each planar surface.

  The step of mechanically stirring may include vibrating the backplane substrate.

  Mechanically agitating may include one or more of rotating the backplane substrate about one or more axes and translating the backplane substrate in one or more directions. The above may be included.

  The securing step may include applying an adhesive at each location prior to placing the semiconductor particles on the backplane substrate, the adhesive backing at least one semiconductor particle at each respective location. It is configured to be fixed to a plain substrate.

  The fixing step may include heating the semiconductor particles and the backplane substrate to fuse the semiconductor particles to the backplane substrate.

  The securing step may include applying a conformal coating to the backplane substrate to at least partially cover the semiconductor particles and the backplane substrate after the mechanical agitation step, the removing step further Removing at least a portion of the conformal coating covering the semiconductor particles to expose the planar surface.

  According to another embodiment of the present specification, a method is provided for forming a plurality of electronic devices on a substrate, the method comprising providing semiconductor particles formed separately from the substrate; and placing the semiconductor particles on the substrate. A step of positioning the semiconductor particles at a predetermined position, a step of fixing the semiconductor particles so as not to move at a predetermined position of the substrate, and a step of fixing the semiconductor particles so as not to move. Removing a portion of each semiconductor particle, the cross-section being a planar surface, and one or more controllable gate electronic components above or directly below each planar surface. Providing. Providing one or more controllable gate electronic components includes, for each planar surface, a first amount of a first liquid medium that includes a dopant over a first portion of the planar surface. Depositing and depositing a second quantity of the first liquid medium on the second portion of the planar surface, the first quantity being spaced from the second quantity by a gap; Heating the first amount, the second amount, and the corresponding semiconductor particles, the heating step causing at least some of the dopant to diffuse from the first liquid medium to the planar surface. A step of depositing a dielectric material on the planar surface in the gap; selectively removing the first amount and the second amount from the planar surface; And the second part Comprising the steps of depositing an electrical contact on each, and depositing a further electrical contacts on the dielectric material.

  According to another embodiment of the present specification, an electronic device is provided, the electronic device comprising a substrate and semiconductor particles formed separately from the substrate and then fixed to the substrate, the semiconductor particles comprising the semiconductor particles The electronic device further includes a controllable gate electronic component above or directly below the planar surface to remove a portion of the planar surface to expose a planar surface in the cross section of the semiconductor particle. The controllable gate electronic component deposits a first amount of a first liquid medium containing a dopant on the first portion of the planar surface and a second on the second portion of the planar surface. Depositing an amount of the first liquid medium, wherein the first amount is spaced apart from the second amount by a gap, and wherein the first amount, the second amount, and the semiconductor particles are Heating, wherein the heating step is configured to diffuse at least some of the dopant from the first liquid medium to the planar surface; and a dielectric material on the planar surface in the gap. Depositing; selectively removing the first and second quantities from the planar surface; depositing electrical contacts on each of the first and second parts; On dielectric material It is formed by depositing a further electrical contact.

  According to another embodiment of the present specification, a method is provided for forming an electronic device on a substrate, the method comprising providing semiconductor particles formed separately from the substrate, and the semiconductor particles cannot move to the substrate. A first amount of a first liquid medium containing a dopant is deposited on the first portion of the surface of the semiconductor particle and the second of the surface Depositing a second amount of a first liquid medium on the portion, the first amount being spaced apart from the second amount by a gap; a first amount; a second amount; Heating the amount of the semiconductor particles, the heating step being configured to diffuse at least some of the dopant from the first liquid medium to the surface; and a dielectric on the surface in the gap. Material Depositing, selectively removing the first and second quantities from the surface, depositing electrical contacts on each of the first and second parts, and dielectric material Depositing further electrical contacts on the substrate.

  The method further includes forming a barrier island on the surface in the gap before depositing the first amount and the second amount, and depositing the dielectric material from the surface before depositing the dielectric material. Selectively removing.

  Forming the barrier island may include depositing a third amount of the second liquid medium including the barrier material on the surface in the gap.

  Forming the barrier island includes depositing a layer of photoreactive material on the surface, and changing the region of the photoreactive material above the gap to light configured to change the photoreactive material. Exposing and forming a barrier island comprising light-modified photoreactive material by selectively removing unexposed areas of the layer of photoreactive material from the surface.

  Depositing the dielectric material may include depositing a fourth amount of the third liquid medium including the dielectric material on a surface in the gap.

  The fourth amount may wet the first amount and the second amount with a wetting angle less than about 90 °.

  The heating step may further selectively remove the barrier island from the surface.

  The step of depositing the first amount and the second amount is a step of depositing an initial amount of the first liquid medium on the surface, the initial amount being a first portion of the surface, a second amount of the surface. Covering a portion, and a barrier island disposed between the first portion and the second portion, and at least partially evaporating one or more components of the first liquid medium Exposing the barrier island by heating the initial amount to reduce the volume of the initial amount to form a first amount and a second amount separated from each other by the barrier island. .

  This surface may comprise a planar surface.

  The planar surface may include a planarized surface of semiconductor particles.

  The first amount may be spaced from the second amount by a gap in the range of about 0.1 μm to about 100 μm.

  Depositing a first quantity; depositing a second quantity; depositing a dielectric material; depositing electrical contacts on each of the first and second parts; and further electricity Printing may be used for one or more of the steps of depositing the mechanical contacts.

  Printing may include one or more of screen printing, flexographic printing, gravure printing, stamping, offset printing, and inkjet printing.

  According to another embodiment of the present specification, a method of forming an electronic device is provided, the method comprising providing a semiconductor substrate having a surface that includes a first portion and a second portion, the method comprising: One portion is spaced from the second portion by a gap, forming a barrier island on a surface in the gap, and a first amount of dopant comprising a dopant on the first portion of the surface. Depositing a first liquid medium and depositing a second amount of the first liquid medium on a second portion of the surface, the first amount being reduced from the second amount by the barrier island. Separating and heating the first amount, the second amount, and the semiconductor substrate, the heating step causing at least some of the dopant to diffuse from the first liquid medium to the surface. In Formed, selectively removing barrier islands from the surface, depositing a dielectric material on the surface in the gap, and selectively removing the first and second quantities from the surface. Depositing electrical contacts on each of the first and second portions and depositing additional electrical contacts on the dielectric material.

  Forming the barrier island may include depositing a third amount of the second liquid medium including the barrier material on the surface in the gap.

  Forming the barrier island includes depositing a layer of photoreactive material on the surface, and changing the region of the photoreactive material above the gap to light configured to change the photoreactive material. Exposing and forming a barrier island comprising light-modified photoreactive material by selectively removing unexposed areas of the layer of photoreactive material from the surface.

  Depositing the dielectric material may include depositing a fourth amount of the third liquid medium including the dielectric material on a surface in the gap.

  The fourth amount may wet the first amount and the second amount with a wetting angle less than about 90 °.

  The heating step may further selectively remove the barrier island from the surface.

  The step of depositing the first amount and the second amount is a step of depositing an initial amount of the first liquid medium on the surface, the initial amount being a first portion of the surface, a second amount of the surface. Covering a portion, and a barrier island disposed between the first portion and the second portion, and at least partially evaporating one or more components of the first liquid medium Exposing the barrier island by heating the initial amount to reduce the volume of the initial amount to form a first amount and a second amount separated from each other by the barrier island.

  This surface may comprise a planarized surface of a semiconductor substrate.

  Depositing a first quantity; depositing a second quantity; depositing a dielectric material; depositing electrical contacts on each of the first and second parts; and further electricity Printing may be used for one or more of the steps of depositing the mechanical contacts.

  An exemplary embodiment of the present invention will be described with reference to the drawings.

FIG. 6 is a cross-sectional view showing an array of semiconductor spheres that are adhered and placed on a substrate so that the spheres are permanently attached to a predetermined location. It is a figure which shows the photograph of the arrangement | sequence of the glass sphere distribute | arranged on the non-silicon substrate. 1 is a cross-sectional view of semiconductor spherical particles deposited on a gridded substrate having a conformal coating deposited on top of the spherical particles. FIG. 3b is a cross-sectional view of the semiconductor spherical particle shown in FIG. 3a after being planarized. FIGS. 4a-4f illustrate a method of forming contacts on, for example, the planar and outer surfaces of a sphere to provide an array of solar cells. 2 is a partial cross-sectional view of complementary NMOS and PMOS circuits formed on a planarized semiconductor particle doped with p-type material when forming the particle. FIG. FIG. 3 is a cross-sectional view of a single transistor device fabricated in a single planarized sphere. FIG. 6 is an isometric view of a circuit having a symbolic representation of a gate transistor shown in a flattened spherical particle. This single cell may further form a stand-alone circuit, be packaged to function as a stand-alone device, and replace a similar device fabricated on a silicon wafer. FIG. 5b shows the spherical particles of FIG. 5b, showing that an array of such particles can be produced in adjacent particles that are not shown to have transistors in them. 6a-6d are cross-sectional views of the particles shown to have a maximum depth perpendicular to the planarized surface. It is a figure which shows the cross section of an active matrix display. FIG. 6 shows a cross section of another embodiment of an active matrix display. It is a figure which shows the cross section of the pixel area | region of an electroluminescent assembly. FIG. 6 shows a cross section of another embodiment of an active matrix display. FIGS. 11a to 11e illustrate steps of a method for forming an electronic device on a semiconductor substrate. 12a-12f illustrate steps of another method of forming an electronic device on a semiconductor substrate. Figures 13a-13g illustrate steps of another method of forming an electronic device on a semiconductor substrate. FIGS. 14a-14g illustrate steps of another method of forming an electronic device on a semiconductor substrate.

  Turning now to FIG. 1, a substrate 10 is shown, which may be plastic, glass, semiconductor material, or any other suitable stable material for supporting electronic circuits. An adhesive layer 12 having a grid 14 is applied to the upper surface of the substrate 10, which grid element 14 is suitably sized to contain semiconductor spheres 16 having a diameter of less than 15 mm, preferably less than 2 mm. With a predetermined gap between them. The term semiconductor sphere as used hereinafter shall include spheres, ellipsoids, and semiconductor sphere-like objects that may be imperfect due to defects in the formation of the sphere. The arrangement shown in FIG. 1 is where the circuit designer should place the spherical semiconductor material and, consequently, the semiconductor device that will be present on the planar surface of the sphere 16 after the sphere has been planarized. Allows a lot of control in the decision to be easily made. Although a grid with the same spacing between the grid openings is shown, a grid with non-uniform spacing may be used to place the spheres in any desired pattern. If the electronic device is fabricated on a planar surface prior to positioning the sphere on the substrate, it is very difficult to orient the sphere. Thus, after the semiconductor sphere 16 is first fixedly attached to the substrate 10, it is planarized to expose areas of high quality semiconductor material within the sphere suitable for the fabrication of silicon electronics. As an example, a CMOS device can be formed in the planar layer by doping the planar layer and the underlying sphere material. Spherical particles are described in detail and are particularly convenient for positioning and planarization, but provide a surface for fabricating electronic devices as long as the particles can be conveniently positioned and secured to a substrate. Many other particle shapes may be used as long as the particles can be planarized.

  Typically, for most chip-based electronics, device density is high because unused chip area is reduced to a minimum. Due to its high density, the unused substrate area that is wasted due to the fact that no active devices have been fabricated is small. In displays and imagers, device area is defined by non-electronic requirements. As a result, device density decreases as the display becomes larger. At some point, it is no longer desirable to coat several square meters with low quality Si to make several devices or millions compared to hundreds of millions in PC CPUs. In accordance with the present invention, a portion of the total display area for a large display is covered by placing high quality Si only where it is needed. This technical inflection point should occur as a result of an impending crossing for a faster OLED device. OLEDs are current devices and amorphous silicon on glass cannot provide the required current and speed.

  U.S. Pat. No. 4,614,835, filed December 30, 1983 in the name of Carson et al., "Photovoltaic Solar using silicon microparticles, incorporated herein by reference. Silicon spheres have long been used to produce large area photovoltaic panels, as described in Arrays Using Silicon Microparticles). For photovoltaic applications, the surface of the sphere forms the active area. Silicon spheres can be made from low cost powdered silicon and the resulting silicon dioxide recrystallized surface layer can remove significant impurities. Repeated melting cycles can improve the overall material purity. Even in the case of polycrystalline particles, the electron mobility is many times that of amorphous silicon.

In accordance with the present invention, it has been discovered that for electronic devices, it is preferable to make a device using a flat cross-sectional surface of semiconductor particles, such as a sphere, over a curved outer surface. The flat surface allows the use of standard lithographic techniques and allows the fabrication of transistors, interconnects, etc. For example, a 20 micron diameter silicon sphere provides a maximum area A = πxr ² = about 314 microns ² for device fabrication. Within this area, many transistors with gate lengths on the order of 1 micron can be fabricated. For large area displays, each pixel requires only a few transistors and the pixel size does not correspond to the display size. High definition (HD) is the standard resolution (eg, 1920 × 1080 pixels). In addition, one flat area of high quality single crystal silicon can handle more than two pixels and can provide additional functions such as self-test and display performance monitoring and correction.

  By using a flat cross-section of flattened particles, such as, for example, a cut and flattened sphere, standard photolithography fabrication techniques can be used. Further, planarization removes defects on the surface of the sphere or ellipsoid because the sphere or ellipsoid is etched or polished to expose the inner region. Conveniently, since the spheres are purified in a separate process, the glass substrate melts at a temperature lower than the standard silicon processing temperature, and therefore uses a high temperature process that is not available for amorphous silicon on glass substrates. High-purity single crystal material can be realized. This is even more important for lower melting temperature substrates such as plastics. “When cut spheres or other shaped planarizing particles are doped just below or above their planar surfaces, or are doped multiple times to expose rings or cross-sections of n-type and p-type materials. A “well” may be formed. Doping may occur later in the process. This makes it possible to produce a CMOS device as shown in FIG. The preferred way to dope a region is by ion implantation, but doping may be achieved by spin coating a dopant on the planarized surface. The outer surface may be highly doped or metallized, which is an effective backside to form a substrate contact that can be contacted from anywhere on the top surface edge or spherical surface. As used herein, the term contact may be a physical wire or a metallized contact region such as a conductive contact pad for a lead or wire or device to make electrical contact. .

  The present invention provides spherical silicon particles at known locations on a substrate, which is preferably a non-silicon substrate. The positioning of the silicon sphere on the substrate can be done by any of several techniques. Most of the techniques involve patterning the substrate with multiple locations where the sphere should be placed. Initially, a metal or dielectric grid may be applied permanently or temporarily to the substrate, or standard photolithography techniques may be used. Alternatively, dots, indentations, or other patterns of adhesive may be applied to place the sphere. An adhesive material with a melting point or adhesion at room temperature that is suitably adapted for subsequent electronic processing should be selected.

  As an alternative to the deposited or applied grid, the substrate is directly patterned using standard lithographic techniques to create holes in the substrate to deposit adhesive to secure the semiconductor spheres in. May be. In some embodiments, a fireable ceramic material may be used as the substrate. Holes may be made in the green or green ceramic using techniques including but not limited to punching or drilling.

  In another embodiment, U.S. Pat. No. 6,464,890 to Knappenberger et al., Filed August 29, 2001 and August 23, respectively, incorporated herein by reference. As described in US Pat. No. 6,679,998, silicon particles may be used to form a single layer on the semiconductor surface instead of the non-semiconductor spheres used to form the mask. As long as the particles are of a predetermined size, subsequent processing can provide planarized silicon particles, such as spherical particles, where needed.

  FIG. 1 illustrates an exemplary technique in which a metal grid 14 is used with an adhesive layer 12. A sufficient amount of spheres 16 are then placed on the surface to completely occupy the grid openings by using mechanical vibrations to move the spheres around on the grid. Mechanical vibration causes the silicon sphere 16 to move around in a volume defined by the substrate, the wall, and the cover. As long as the sphere is still available, the sphere 16 moves around in a very short time to the point where the probability of encountering an available grid location is 1. It is anticipated that other types of mechanical agitation can be used instead of and / or in addition to vibration. For example, a substrate with a sphere placed thereon may be rotated about one or more axes and / or translated in one or more directions.

  FIG. 2 shows a photomicrograph of such a device made on a glass substrate having a grid. In this exemplary case, glass spheres are used and they are 20 microns in diameter. Mechanical vibration was used to move the glass sphere around on the grid. A high voltage (V ≦ 12 kV) was then applied to the grid to help remove the spheres from the top surface of the grid. Some excess spheres and dirt are also seen, but these will be reduced or eliminated in a clean room environment and / or removed in subsequent processing steps.

  For large areas, the sphere may be applied as a dense line across the surface in one direction and then vibrated across the surface of the substrate by waves. In some embodiments, the semiconductor particles may be placed on the substrate surface to substantially or entirely cover the surface of the substrate prior to mechanically stirring the substrate and the semiconductor particles.

  It is anticipated that by using similar techniques using mechanical agitation, the substrate may include through-holes at a predetermined location to at least partially receive semiconductor particles. An adhesive layer may be applied to one surface of the substrate, and the adhesive layer may cover one end of the through hole. The semiconductor particles may be placed on the other surface of the substrate opposite the surface having the adhesive layer, and then the semiconductor particles at least partially pierce the substrate by mechanically stirring the substrate and the semiconductor particles. You may make it occupy. The semiconductor particles can adhere to the portion of the adhesive layer that is accessible through the holes and as a result are retained and / or fixed in the holes. The adhesive layer may comprise glass paste or other suitable adhesive known to those skilled in the art.

  Alternatively, referred to hereinafter as reference 1, “Mechanics of a process to assembled microspheres on a patterned electrode”, Ting Zhua, Zhigang Sub, Adam Winkleman and George M. An electric field may be applied using an external electrode to move particles on the substrate, as described in Whitesizes, Applied PHYSICS LETTERS 88, 144101 (2006). In this approach, a potential is generated using a bottom electrode placed under a dielectric substrate and a conductive grid is used as a counter electrode. The holes in the grid create a potential well into which the sphere can fall. The electric field gradient around the hole is sufficient to generate a net force acting on the particles. Due to a sufficiently large applied electric field (KV), the particles can be moved into the pores. In order to move the sphere around so that the sphere encounters the potential well, a vibration may be required first.

  In another approach, a process similar to that used for laser printing can be used. In laser printers, the charge generated by triboelectricity is applied to the toner particles. The charged toner particles are then applied to an electrostatically charged (drum) substrate. In laser printing, the toner particles are then transferred to a statically charged substrate, typically paper. In laser printing, a laser is used to write a pattern on a charged drum, but since the pattern does not change in the production environment, the laser can be replaced by a grid. In the first generation laser printer, the toner particle size of about 16 microns was on the same order as the sphere of FIG. By applying a voltage to the electrode under the dielectric substrate to attract the charged sphere and applying the opposite polarity to the grid, the sphere is selectively attracted to the hole. This approach can be shown as an improvement of the approach described in reference 1.

  In an alternative embodiment of the present invention, similar to the laser printing described, an array of spheres works similar to charged paper from a first substrate that acts like a laser printer drum. May be transferred to another unpatterned substrate. Alternatively, when the adhesive applied to the adhesive or sphere on the second unpatterned substrate has a higher melting temperature, greater adhesion or electrostatic attraction, for example, the first An array transfer from the substrate to the second substrate can be achieved. Although the exemplary device of FIG. 1 uses an adhesive layer, the substrate or grid underlayer may be a thermosoftening layer, for example, a sphere adheres to the contact because it is a thermoplastic layer at elevated temperatures, and the substrate surrounds It may remain in place when cooled to temperature. The adhesive may be a thin layer applied to the substrate. The relatively small size of the sphere means that a significant contact area is achieved for a small layer thickness of adhesive.

  Since silicon has a higher melting temperature than glass, if heated sufficiently to soften the glass and the spheres coated with silicon dioxide or stripped of oxide adhere directly to the glass, An assembly can be provided in which the substrate can be used directly and can receive higher post-processing temperatures. This can be accomplished by transferring the arrayed particles from the patterned substrate to the unpatterned glass using electrostatic attraction, similar to laser printing. By fixing the particles directly to the glass, the window for higher temperature processing can be extended to the point where the internal cross section of the semiconductor sphere is exposed. The same printing process can be used for other substrates.

As shown in FIG. 3a, which shows a coating layer 18 of SiO ₂ covering the spherical particles 16 and the grid 14, when the sphere 16 is in place, a conformal coating 18 is applied, followed by chemical mechanical polishing, for example. Planarization is performed using a modified version of the standard planarization technique. FIG. 3b shows the same arrangement as in FIG. 3a, but before the device is fabricated on a hemispherical cut sphere. Standard planarization techniques used in integrated circuit fabrication can be used. In this process, planarization can occur multiple times. Because, when multiple layers are deposited sequentially, the topography can exceed what is supported by the process, so after application of the conformal dielectric coating it is then planarized and when the conductive coating is applied This is because the surface is then flattened. Interlayer connections are made by opening holes or vias at locations defined by lithography to deposit conductive connections or plugs between the layers. This is particularly advantageous. In the case of a planarized metal layer, this layer is patterned to form the necessary interconnects. In the present invention, a US patent entitled “Planarization of multi-level interconnected metallization system” filed on Dec. 15, 1983, which is incorporated herein by reference. In contrast to the prior art surface planarization as described in US Pat. No. 4,470,874, which does not expose all the underlying elements, the planarization process is performed to expose the internal cross section of the semiconductor particles. Is called.

  Although the silicon spheres are placed in a random orientation, the Si mobility anisotropy is small, so that the resulting device will perform much better than devices made using amorphous silicon or polysilicon. Become. However, polysilicon or non-spherical particles may be used when application requirements are low, for example when high speed devices are not required.

  Although spherical particles are preferred, single crystal or polycrystalline powder silicon may be used if appropriate for the performance requirements of a particular application. In addition, to achieve different functions in the final device, particles of different sizes or different material properties such as, for example, doped or crystalline quality or atomic species such as III-V, such as GaAs, or for use as light sources Multiple placement cycles may be used to place particles such as quaternary alloys or SiGe.

Standard photolithography techniques are used to fabricate devices on exposed silicon surfaces, as well as for the fabrication of interconnects and other elements required for device function. The present invention makes it possible to fabricate almost conventional CMOS devices. In addition, it may be advantageous to use other processes. The present invention does not inherently limit the types of processes that can be used. For example, n-type and p-type silicon particles may be deposited in separate steps to achieve n-well and p-well using separate silicon particles. In conventional CMOS, the n-well shown in FIG. 5a needs to be fabricated in the entire p-type substrate. Turning now to FIG. 5b, there is shown a device similar to FIG. 5a fabricated in a spherical particle doped with p-type material to form a p-type sphere. In this figure, a hemispherical semiconductor device 50 is shown, in which a flattened sphere 56 includes, in addition to a source (S), a drain (Drain: D), and a gate (Gate: G), A gated semiconductor transistor device is formed having contacts B that form a substrate bias because the device is in a doped well as shown. In this case, a single device is formed in the planarized semiconductor sphere. Each of the lines extending from the device to B, S, D, and G is an electrical contact. The number of distinct devices that can be fabricated in / on single crystal grains depends largely on the size of the planarization region. For example, when the device has a gate length of 1 μm and a via hole of 1 μm, the entire device may be a 5 μm × 5 μm device. However, a 20 μm diameter sphere has a surface area greater than 300 μm ² and can accommodate several devices. For example, a 2 × 2 pixel array, or a single pixel and additional circuitry for eg lifetime control can be incorporated. Considerations for sphere size are cost, reliability and yield. The device shown in FIG. 5a may be fabricated on any or all of the planar spheres shown in FIG. 3b, for example.

  Symbolic representations of transistors 55a and 55b are shown in FIGS. 5c and 5d. Further doping occurs to achieve NMOS and PMOS devices in the same sphere. In FIG. 5c, an array of controllable functional devices such as transistors can be fabricated. Although not shown in the array 58 of flattening spheres 56, the array of devices is manufactured in the same process. In other words, all transistors are doped simultaneously. After the device is fabricated, a passivation layer 59 is applied just above the top of the planarizing sphere. The state before this layer 59 is placed on the active device is shown. While an advantage of the present invention is that arrays of any size can be produced, it may be desirable to cut the array into smaller functional units that can be placed in the desired location. In this case, current means for cutting silicon wafers can be used.

  The resulting electronic assembly can then be used as a basis for various devices, such as a display or imager.

  In accordance with aspects of the present invention, non-glass substrates such as plastic, Mylar ™, polyimide or other materials suitable for application can be used to achieve a flexible and moldable device as well as reduce manufacturing costs. It may be possible. As the size of the semiconductor particles is reduced, the minimum bend radius is also reduced. For silicon particles smaller than the thickness of the substrate, the mechanical properties are largely defined by the non-silicon elements of the device and can therefore be flexible or moldable or a combination thereof. In addition, devices can be fabricated that have mechanical properties that vary across the device, where mechanical stiffness is defined as a function of position within the device.

  In a further variation of the invention, a large substrate may be cut to form a small device in the same way that a silicon wafer is cut into a preferred size device. This device is smaller than the substrate. This technology is applicable when cost and performance allow the use of non-silicon substrates. For example, in many silicon devices, the area occupied by contact pads and interconnects can be on the same order as the device area. In other applications, device performance can be improved by using a substrate with high thermal conductivity. Here, the spherical backside of the particles provides a larger surface through which heat can be removed.

As previously mentioned, the present invention further enables the manufacture of solar cells using similar fabrication methods. Turning now to FIGS. 4a to 4f, the process of manufacturing a solar cell is shown, wherein the sphere 16 doped with the p-type material shown in FIG. 4a is placed in an opening by the grid 14. FIG. It is fixed to the light-transmitting substrate 10 that supports them. In FIG. 4b spheres and grids are coated on a layer 43 of SiO ₂ and in FIG. 4c a metallization layer 45 is applied. In FIG. 4 d this structure is flattened and the sphere has a planar upper surface 47. In FIG. 4e, a via and conductive plug arrangement 48 is provided. In addition, although not shown in FIG. 4e, a planar region immediately below the planar surface is doped with n-type material, and in the subsequent step of FIG. 4f, a planar shape in which all interconnects contact the p and n materials. Interconnects 46 and 49 are formed so that they are on the upper surface of the substrate. This upper planarized surface actually forms the back side of the solar panel.

  The term flattened particle or particle having a planar surface refers in a preferred embodiment to a particle having a longest dimension of 15 mm of the planar surface and a depth (depth: d) of at least 1 μm perpendicular to the planar surface. . Preferably these particles are spheres, ellipsoids, or incomplete spheres or ellipsoids. However, other particle shapes are within the scope of the present invention. FIGS. 6a to 6d illustrate various particle shapes 60 and further show the depth (d) perpendicular to the planar surface of the particles.

  An array of electronic devices fabricated according to the foregoing description, including but not limited to the electronic device shown in FIG. 5d, can be used as a backplane for an active matrix electro-optic device. These electro-optic devices can include, but are not limited to, displays and imagers. In these devices, controllable gate electronic components fabricated on and / or below a planar surface in a planarized cross-section of a semiconductor particle are electrically connected to one or more pixels of the optical portion of the electro-optic device. It may be connected. The optical part may include a light emitting part in the case of a display and / or a light detection part in the case of an imager. Controllable gate electronic devices, including but not limited to transistors, for controlling and / or powering light emitting pixels in the case of displays and / or sampling electrical signals from photodetection pixels in the case of imagers May be used.

  FIG. 7 schematically represents a cross-section of a display 700 that includes a backplane 705 that is electrically connected to a light emitting assembly. The light emitting assembly may include, but is not limited to, an organic light emitting diode (OLED) assembly 715, in which case the display 700 may be an active matrix OLED display. Although the following description refers to an OLED assembly, it is anticipated that the light emitting assembly may be any suitable electroluminescent assembly known to those skilled in the art.

  The backplane assembly for display 700 may include planarized semiconductor particles, such as planarized sphere 56, secured to substrate 10. The substrate 10 is hereinafter referred to as a “backplane substrate 10”. For purposes of this description, substrate 10 and backplane substrate 10 may be interchangeable. One or more controllable gate electronic components may be formed above and / or below the planar surface in the planarization cross section of the planarization sphere 56, including but not limited to transistor 55a. In FIG. 7, only one transistor 55 a is shown per planarization sphere 56, but 2 above and / or below the planar surface in the planarization cross section of one or more semiconductor particles of the backplane 705. One or more controllable gate electronic components may be formed. Further, these controllable gate electronic components may be of different types and designs, including but not limited to different types of transistors. The controllable gate electronic component may further include circuit elements patterned by any lithography. Although the following description refers to transistor 55a, any type and / or type of suitable circuit elements and / or electronic components known to those skilled in the art may be used in place of and / or in addition to transistor 55a. Expect to get.

  A contact 710 may be formed on and / or below the planar surface in the planarization cross section of the planarization sphere 56. Contact 710 is in electrical contact with transistor 55a. Additionally and / or alternatively, contact 710 may be in electrical contact with one or more other circuit elements and / or combinations of circuit elements. Such circuit elements may include, but are not limited to, capacitors. Although only one contact 710 is shown in FIG. 7 for transistor 55a, depending on the transistor design and / or the number and type of connections required between transistor 55a and the pixels of OLED assembly 715, It is anticipated that two or more contacts may be made to the transistor. Contact 710 may include a deposited layer of conductive material, including but not limited to a metallic material. Additionally and / or alternatively, contact 710 may include a low temperature solder including a metal filled epoxy, including but not limited to silver epoxy, carbon filled epoxy, and indium or an indium-tin alloy.

  The OLED assembly 715 may include an OLED substrate 720 and one or more organic light emitting layers 740 that are in contact with one or more electrodes. In one embodiment, the OLED assembly 715 may include one or more pixel regions 725, 730. One or more of the pixel regions 725, 730 includes a first electrode 735 deposited on the OLED substrate 720, and one or more organic light emitting layers 740 deposited on the first electrode 735, A second electrode 745 deposited on one of the organic light emitting layers 740 may be included such that at least one of the organic light emitting layers 740 is sandwiched between the first electrode 735 and the second electrode 745. Although FIG. 7 shows that each pixel region 725, 730 has its own first electrode 735, organic light emitting layer 740 and second electrode 745 stack, the first electrode 735 and the organic light emitting layer are shown. It is anticipated that one or more of 740 may span multiple pixel regions. Although a particular architecture and geometry of OLED assembly 715 is shown and described, it is anticipated that different architectures and geometries of OLED assembly 715 known to those skilled in the art may be used for display 700.

  The OLED substrate 720 may include a material that at least partially transmits light emitted from the organic light emitting layer 740. The OLED substrate 720 may include materials including but not limited to glass, plastic, and polyimide. The first electrode 735 may include a conductive material that at least partially transmits light emitted from the organic light emitting layer 740. The first electrode 735 may include indium tin oxide (ITO). In some embodiments, the OLED substrate 720 may also function as the first electrode. The second electrode 745 may include a layer of conductive material including but not limited to aluminum and / or copper.

  Adjacent pixel regions 725, 730 may be distinguished from one another by one or more of separate first electrodes 735, separate organic light emitting layers 740, and / or separate second electrodes 745. . In some embodiments, each of one or more of the pixel regions 725, 730 may have two or more separate second electrodes, which are the pixel contacts for the respective pixel region. You may play a role. In FIG. 7, a dotted line across the OLED substrate 720 defines an approximate boundary between the pixel regions 725 and 730. These dotted lines are for illustrative purposes and do not necessarily represent the physical characteristics of the OLED assembly 715.

  An active matrix OLED display includes a backplane 705 with an OLED assembly such that at least one of the pixel regions 725, 730 is electrically connected to one or more of the corresponding controllable gate electronic components, such as transistor 55a. It can be formed by electrical connection to 715. In FIG. 7, the pixel region 725 is shown as being connected to only one contact 710 of the transistor 55a. In other embodiments, other ways of connecting the pixel region to the transistor may include, but are not limited to: That is, one pixel region may be connected to multiple transistor contacts and / or multiple transistors; one transistor contact 710 and / or one transistor 55a may be connected to a plurality of separate second electrodes in the pixel region 725, That is, it may be connected to a pixel contact; and one transistor 55a may be connected to a plurality of different pixel regions 725, 730.

  The OLED assembly 715 may be electrically connected to the backplane 705 through one or more conductive links 750. Conductive link 750 may connect transistor 55a to a corresponding pixel region 725. Conductive link 750 may include a conductive bridge between contact 710 and second electrode 745. The conductive link 750 may include a soft and / or flexible conductive link. Conductive link 750 may include one or more of a conductive epoxy, such as silver epoxy, solder, and low temperature solder. In some embodiments, transistor 55a may not have a pre-formed contact 710, and conductive link 750 may connect second electrode 745 to transistor 55a. In some embodiments, the pixel region 725 may not include the second electrode 745 and the conductive link 750 may directly connect the contact 710 and / or the transistor 55a to the at least one organic light emitting layer 740. .

  By using a soft and / or flexible conductive link 750, the conductive link 750 can damage the organic light emitting layer 740 as a result of the conductive link 750 breaking through the second electrode 745 and the organic light emitting layer 740, and The possibility that the conductive link 750 may cause an electrical short circuit with the first electrode 735 can be reduced. By using a conductive link 750 that can be applied at a relatively low temperature, the possibility of thermal degradation and damage of the organic light emitting layer 740 that may be temperature sensitive can be reduced.

  An active matrix OLED display 700 can be formed by electrically connecting the backplane 705 to the OLED assembly 715 using the conductive link 750 described above. Prior to coupling the backplane 705 to the OLED assembly 715 to allow each pixel region 725, 730 to be adjacent to the corresponding transistor 55a before connecting the two, the backplane 705 and the OLED assembly 715 May be aligned with each other. This alignment may be performed using optical or physical markers on one or both of the backplane 705 and the OLED assembly 715. In addition, this alignment may be performed by placing the backplane 705 and OLED assembly 715 in a jig that positions them relative to each other.

  When the backplane 705 is coupled to the OLED assembly 715 by the conductive link 750, a gap 760 may remain between the backplane 705 and the OLED assembly 715. These gaps 760 may be partially or completely filled with backfill material to further mechanically strengthen the connection between the backplane 705 and the OLED assembly 715. In addition, the backfill material is opaque, light scattering, and / or light absorbing to reduce and / or eliminate any visible reflections from the backplane substrate 10 that may interfere with the image produced by the OLED display 700. It may be. In some embodiments, the backfill material may be substantially black. Being substantially black may include reflecting a sufficiently small portion of the incident light on the backplane so that this reflected light will cause human visible interference with the image generated by the OLED display 700. Do not configure.

  During fabrication of OLED display 700, backplane 705 and OLED assembly 715 may be formed separately and then joined together. For example, the backplane 705 may be formed according to the above description. The OLED assembly 715 may be formed on an OLED substrate 720 different from the backplane substrate 10 separately from the backplane 705. By forming the OLED assembly 715 separately from the formation of the backplane 705, each part of the fabrication process can be optimized independently. In addition, the two separate fabrication processes allow separate quality control for the OLED assembly process and the backplane fabrication process. Defects in the batch of backplanes 705 or OLED assemblies 715 do not affect the entire display 700, but only its subcomponents.

  In addition, separate fabrication of the OLED assembly 715 may allow better control over the formation of different components of the pixel regions 725, 730 including the organic light emitting layer 740. The OLED substrate 720 and / or the first electrode 735 can constitute a more suitable substrate, for example flatter or smoother, for depositing an organic light emitting layer 740 that can be sensitive to the non-uniformity of the deposited substrate. . In addition, the organic light emitting layer 740 allows for electrical contact between the first electrode 735 and the second electrode 745, the conductive link 750, and / or the contact 710 by more consistent deposition of the organic light emitting layer 740. The possibility of punch-through electrical shorts that can be caused by damage to the device can be reduced.

  In order to operate the OLED display 700, a potential is applied to the organic light emitting layer 740 by applying a potential between the first electrode 735 and the second electrode 745. The first electrode 735 may be connected to transistors, power supplies, and / or electrical leads on the backplane 705 and / or the first electrode 735 may be connected to power supplies and / or electrical leads independent of the backplane 705. May be connected. The second electrode 745 may be connected to the transistor 55a. One or more of the organic light emitting layers 740 may then emit human visible light that passes through the first electrode 735 and the OLED substrate 720 and out of the OLED assembly 715 in the direction of light emission. 755 may be emitted. Transistor 55a provides power to and / or power applied to organic light emitting layer 740 to control the emission attributes of pixel regions 725, 730, including but not limited to brightness and on / off states. You may control.

  7-10 illustrate three organic light emitting layers 740, it is anticipated that fewer or more than three organic light emitting layers may be used. When multiple organic light emitting layers 740 are present, these layers may include different materials.

  In some embodiments, each pixel region 725, 730 may emit only one color. In other embodiments, the pixel regions 725, 730 may emit multiple colors. For example, each of the pixel regions 725 and 730 may include a plurality of sub-pixel regions that each emit one color. For example, each sub-pixel may emit one of red, green, and blue light. When the pixel regions 725, 730 have sub-pixel regions, each sub-pixel region may have its own separate second electrode 745, i.e., its own separate sub-pixel contact. Each sub-pixel region may be controlled by one or more corresponding transistors.

  FIG. 8 shows a cross section of an active matrix display 800, which can be an active matrix OLED display. The backplane 705 in the display 800 is the same as the display 700 and includes transistors 55 a and contacts 710 formed on and / or below the planar surface of the planarizing sphere 56 secured to the backplane substrate 10. The display 800 differs from the display 700 in that the light emitting assembly is deposited directly on the backplane 705. For example, the organic light emitting layer 740 may be deposited directly on the planar surface of the planarizing sphere 56 such that at least one of the organic light emitting layers 740 is in electrical contact with the contact 710 of the transistor 55a.

  The first electrode 735 may be deposited on one of the organic light emitting layers 740 and / or the outermost one. Although organic light emitting layer 740 and first electrode 735 are shown as forming separate stacks on each of the different transistors 55a, one of organic light emitting layer 740 and / or first electrode 735 or It is anticipated that more may be deposited as a layer that spans multiple transistors 55a.

  In some embodiments, the organic emissive layer 740 may be deposited on the surface of the backplane substrate 10 outside the planar surface of the planarization sphere 56 in addition to the planar surface of the planarization sphere 56. Good. In some embodiments, the surface of the backplane substrate 10 may be used to reduce and / or remove porosity on the surface of the backplane substrate 10 prior to depositing subsequent layers, such as, for example, the organic light emitting layer 740. It may be coated with materials such as glass encapsulant, vitrified glass, and / or plastic. In some embodiments, a second electrode layer may be deposited over contact 710 prior to depositing organic light emitting layer 740 and first electrode 735.

  The first electrode 735 may be connected to transistors, power supplies, and / or electrical leads on the backplane 705 and / or the first electrode 735 may be connected to power supplies and / or electrical leads independent of the backplane 705. May be connected. When a potential is applied between the contact 710 and the first electrode 735, the organic light emitting layer may emit human visible light in the direction 755 of light emission. As with the display 700, each of the pixel regions 805, 810 of the display 800 may emit only one color or multiple colors. It is anticipated that other layers may be deposited as part of the display 800, and these layers may include, but are not limited to, a passivation layer, an encapsulation layer, and / or a protective layer.

  FIG. 9 shows a cross section of a pixel region 905 that may form part of an OLED assembly used to form an OLED display similar to display 700. The pixel region 905 is similar to the pixel regions 725 and 730 in that the pixel region 905 is formed on the OLED substrate 720, the first electrode 735 formed on the OLED substrate 720, and the first electrode 735. The organic light emitting layer 740 and the second electrode 910 formed on the organic light emitting layer 740 are included. The pixel area 905 is different from the pixel areas 725 and 730 in that the second electrode 910 includes an extension 915. The extension 915 may extend beyond the organic light emitting layer 740 and the first electrode 735 in the pixel region 905. The extension 915 may be formed directly on the OLED substrate 720. The second electrode 910 and / or its extension 915 may be insulated from the first electrode 735 by an insulating region 920. The insulating region 920 may include a material and / or medium having a sufficiently low conductivity to prevent an electrical short between the first electrode 735 and the second electrode 910.

  A conductive link 750 may be formed between the contact 710 and the extension 915 when connected to the backplane 705. Any damage to the extension 915 during the connection process is caused by the first electrode 735 and the second electrode 910 since the connection point is insulated from the first electrode 735 and / or spatially removed. It is hard to cause punch through short circuit. In addition, since the extension 915 has been spatially removed from the organic light emitting layer 740, any thermal, mechanical and / or chemical damage during the connection process may be susceptible to this type of damage. The organic light emitting layer 740 is hardly damaged.

  FIG. 10 shows an active matrix display 1000 that can be an OLED display. The display 1000 is similar to the display 700 in that the display 1000 includes an OLED assembly 715 having an OLED substrate 720, a first electrode 735, an organic light emitting layer 740, and a second electrode 745. is there. When a potential is applied to the pixel region 725 across the first electrode 735 and the second electrode 745, the organic light emitting layer 740 can emit human visible light, which is visible to the first electrode 735 and the OLED substrate 720. Can be emitted in the direction of emission 755.

  The display 1000 has a different backplane structure than the display 700, where the backplane substrate 1005 includes one or more vias 1015. The via 1015 may include a through passage that connects one surface of the backplane substrate 1005 to the opposite surface. Alternatively and / or additionally, the via 1015 may include a conductive path connecting one side of the backplane substrate 1005 to the opposite side. The backplane 1002 may include a transistor 55a formed above and / or below the planar surface of the planarizing sphere 56 secured to the backplane substrate 1005. Contact 1010 may be in electrical communication with transistor 55a and has an intermediate portion 1020 extending through via 1015 and over the surface of backplane substrate 1005 opposite the surface on which transistor 55a is formed. Alternatively, it may terminate at a nearby terminal portion 1025. In embodiments where the via 1015 includes a conductive path, the contact 1010 may include a conductive link between the transistor 55a and the first end of the conductive path. Thus, the second end of the conductive path near the opposing surface of the backplane substrate 1005 may serve as the terminal portion 1025 of the contact 1010. In these aspects, a conductive path may be provided between terminal portion 1025 and transistor 55a. In some embodiments, insulating portion 1030 may electrically insulate a portion of contact 1010 from a portion of planarizing sphere 56 and / or transistor 55a.

  The OLED assembly 715 can be electrically connected to the backplane 1002 via a conductive link 750 between the second electrode 745 and the terminal portion 1025 of the contact 1010. This geometry allows the OLED assembly 715 to connect to the surface of the backplane 1002 that faces the surface having the transistor 55a. Since the operation of transistor 55a can generate heat, the OLED assembly 715 can be connected to the surface of the backplane 1002 opposite to the surface having transistor 55a, so that the OLED assembly 715 is at least partially away from the heat generated from transistor 55a. Can protect. In particular, since the organic light emitting layer 740 may be susceptible to thermal damage and / or degradation, moving them away from the transistor 55a that generates heat reduces the likelihood of thermal damage and extends the life of the OLED assembly 715. be able to.

  In all embodiments described above in connection with FIGS. 7-10, the light emitting assembly, such as OLED assembly 715, for example, may be replaced with a detector assembly for detecting photons to obtain an imager instead of a display. Good. The detector assembly can detect the photons and generate an electrical signal in response. The signal can then be sampled by controllable gate electronic components such as transistor 55a and / or other suitable circuit elements on the backplane. It is anticipated that the imager's controllable gate electronic components and other circuit elements may be different from the display's controllable gate electronic components and circuit elements. The detector assembly may be an x-ray detector assembly for converting x-ray photons and generating an electrical signal in response. It is anticipated that the detector assembly may include any detector configured to detect an external event and generate an electrical signal in response thereto. For example, the detector may detect external events other than photon incidence, such as contact with molecules, atoms, and / or subatomic particles. It is believed that the detector can be integrated vertically on the top of the backplane.

  FIGS. 11 a-e illustrate the steps of a method 1100 for forming an electronic device on a semiconductor substrate. FIG. 11 a shows a semiconductor substrate 1105 having a surface 1107. A first quantity 1110 of liquid medium is deposited on a portion 1120 of surface 1107. A second quantity 1115 of liquid medium is deposited on the portion 1125 of the surface 1107. First quantity 1110 and second quantity 1115 are spaced from each other by a gap 1130.

  The liquid medium includes a dopant configured to dope the semiconductor substrate 1105. The liquid medium may include a mixture of organic components, glass precursors, and dopants. The organic material may include alpha-terpinol, isopropyl alcohol, polyvinyl alcohol, starch, carboxymethylcellulose, dextrin, wax emulsion, polyethylene glycol, lignosulfonate, methylcellulose, paraffin, polyacrylate, or any other suitable material. . In general, suitable organic materials may have one or more of the following characteristics. That is, leaving a minimum amount of ash after calcination, burning out easily at low temperatures, not being abrasive, allowing easy dispersion, not being toxic, and being inexpensive. The glass precursor may comprise silica or any other suitable material. The dopant may include boron, phosphorus, or any other suitable material. The liquid medium may be a liquid and / or paste at conditions (eg, temperature and pressure) at which it is deposited on the semiconductor substrate 1105.

  Additionally and / or alternatively, the liquid medium may comprise any other suitable material or mixture of materials, including but not limited to highly doped Si pastes. In some embodiments, the liquid medium is, for example, Hitachi Chemical Technical Report No. 1, which is incorporated herein by reference in its entirety. A mixture of a dopant, a resin, and a solvent, such as the mixture described in 56. Furthermore, the liquid medium may comprise nanoparticles dispersed in a solvent, which are expected to be doped with a dopant that can be used to dope the semiconductor substrate. For example, Yang, D., which is incorporated herein by reference in its entirety. “Doping Silicon Wafer by Use of Silicon Paste”, Journal of Materials Science and Technology (J. Mater. Sci. Technol.). .), 2013, 29 (7), 652-654. Another example of a liquid medium is “Honeywell Printable Dopants for Advanced c-Si Cell” manufactured and sold by Honeywell and incorporated herein by reference in its entirety. "Printable dopants" described in a publication entitled "Advanced c-Si Cells").

  The first quantity 1110 and the second quantity 1115 can be any droplet, droplet, globule, platelet, saucer, blob, lump, smear, smear, or any liquid medium that is deposited on the surface 1107. It may be in any one of other quantities. The first quantity 1110 and the second quantity 1115 may have the same shape and / or quantity as each other, or may have different shapes and / or quantities.

  Since the first quantity 1110 and the second quantity 1115 are made of a liquid medium, they may be printed on the surface 1107 using any suitable printing technique. Some techniques for printing include, but are not limited to, screen printing, inkjet printing, stamping, flexographic printing, gravure printing, and offset printing. In general, any suitable, depending on several factors including, but not limited to, the viscosity, resolution and / or minimum feature size, alignment accuracy, and printing throughput of the liquid medium containing the dopant Any printing technique may be used. The ability to use printing instead of lithography can significantly reduce the cost of the fabrication process.

  While the above description is directed to a liquid medium containing a dopant, it is anticipated that the dopant may be in the form of solid particles that are electrostatically deposited on a semiconductor substrate and / or may be included in such solid particles. Is done. As noted above, such deposition techniques can be similar to those used in laser printing to transfer toner particles from a laser printer drum to paper. In other words, solid particles of the dopant and / or solid particles containing the dopant may be laser printed on the semiconductor substrate to form the first and second quantities. Such laser printing techniques may not require any liquid or paste to be transferred to the semiconductor substrate. In addition, similar laser printing techniques are used to print other components (eg, gate dielectrics, source and drain contacts, gate contacts, and barrier islands) formed in connection with the fabrication of electronic devices onto a semiconductor substrate. May be used and these components are described in more detail below.

  In some embodiments, the semiconductor substrate 1105 may be pre-doped and the dopant in the liquid medium may allow a change in the doping of the semiconductor substrate 1105. For example, when the semiconductor substrate 1105 is p-predoped, the dopant in the liquid medium may allow the semiconductor substrate 1105 to be n-doped, and vice versa. In the exemplary drawing of FIG. 11, the semiconductor substrate 1105 may be pre-doped and used to form a conduction channel of a field effect transistor electronic device, the conduction channel extending between the source and drain of the transistor. Exists. The dopant from the first quantity 1110 and the second quantity 1115 may be used to further dope (and / or change the dope) of the semiconductor substrate 1105 to form the source and drain of the transistor. .

  Once the first quantity 1110 and the second quantity 1115 are deposited on the surface 1107, to diffuse at least some of the dopant from the liquid medium of each of the first quantity 1110 and the second quantity 1115 to the surface 1107. The substrate 1105, the first quantity 1110, and the second quantity 1115 may be heated. This heating step may be performed in a furnace. FIG. 11 b shows the substrate 1105 after such a heating step, which shows a first doped region 1135 doped with a dopant resulting from the first quantity 1110 and a dopant resulting from the second quantity 1115. A doped second doped region 1140 is shown.

  The shape and size of the doped region depends on a number of factors including, but not limited to, the nature of the dopant, the composition of the substrate 1105, and the heating profile (eg, temperature over time). The shape and relative size of the doped regions 1135, 1140 shown in FIG. 11b (and all subsequent figures) are for illustrative purposes only and are not intended to be limiting. Further, the shape and size of the first quantity 1110 and the second quantity 1115 are shown as not changing between FIG. 11a (before heating) and FIG. 11b (after heating). This is merely for ease of illustration, and it is expected that the shape, size, condition, and / or composition of the first quantity 1110 and the second quantity 1115 may change after the heating step. .

  In some embodiments, a laser beam may be directed onto the surface 1107 instead of heating to drive the dopant from the first quantity 1110 and the second quantity 1115 to the surface 1107. By using a laser to promote the dope, heating the entire semiconductor substrate 1105 to a high temperature can be avoided, allowing the use of a plastic and / or flexible substrate.

When substrate 1105 is doped with a dopant from a liquid medium, dielectric material 1145 may be deposited in gap 1130 on surface 1107 (gap 1130 is not shown in FIG. 11c, but is shown in FIG. 11a). ing). FIG. 11 c shows the dielectric material 1145 deposited in the gap 1130. The dielectric material 1145 may include aluminum oxide, a plastic such as polyimide, or any other suitable dielectric material. In some embodiments, the dielectric material 1145 can be formed from, for example, Ko, F., et al., Incorporated herein by reference in its entirety. "Polystyrene-block-poly (methylmethacrylate) composite material as a gated plastic for plastic thin film transistor plastic as a gate dielectric for plastic thin layer transistor applications May include polystyrene-block-poly (methyl methacrylate) composites such as those described in RSC Advances, 2014, 4, 18493. In addition, it is anticipated that a dielectric material may be grown in the gaps on the semiconductor substrate. For example, in embodiments where the semiconductor substrate includes silicon, a silicon oxide (SiO ₂ ) layer as a dielectric material may be grown in the gap.

  First quantity 1110 and second quantity 1115 may serve as a template for the deposition of dielectric material 1145 in gap 1130. In some embodiments, the dielectric material 1145 may be deposited by depositing an amount of liquid and / or paste that includes the dielectric material on the surface 1107 in the gap 1130. A liquid / paste volume containing such dielectric material may be deposited by printing the liquid / paste on the surface 1107 in the gap 1130. In embodiments in which the dielectric material is printed, the liquid / paste containing the dielectric material may be in a liquid / paste state at the condition that it is transferred and / or printed onto the surface 1107. The dielectric material 1145 may be printed using the techniques described above with respect to the first quantity 1110 and the second quantity 1115.

  Although dielectric material 1145 is shown as having a particular shape (eg, flat top and curved sides), it is anticipated that dielectric material 1145 may have any other suitable shape. The For example, when the dielectric material 1145 has a large wetting angle with the first amount 1110 and / or the second amount 1115 (ie, when the dielectric material does not easily wet the first and second amounts), the dielectric material 1145 may have a convex shape.

  As the dielectric material 1145 is deposited, the first quantity 1110 and the second quantity 1115 may be selectively removed from the surface 1107. FIG. 11d shows the semiconductor substrate 1105 when the first quantity 1110 and the second quantity 1115 have been selectively removed. For example, selective wet chemical etching may be used to remove the first quantity 1110 and the second quantity 1115 while leaving the semiconductor substrate 1105 and dielectric material 1145 intact. It is anticipated that any suitable selective removal method may be used, depending on the composition of the first quantity 1110, the second quantity 1115, the semiconductor substrate 1105, and the dielectric material 1145. For example, when the first quantity 1110 and the second quantity 1115 comprise silica / glass, the semiconductor substrate 1105 comprises silicon, and the dielectric material 1145 comprises polyimide, the first quantity 1110 and the second quantity from the surface 1107. A wet chemical etch such as, for example, hydrofluoric acid or other suitable acid may be used to selectively remove 1115.

  When the first quantity 1110 and the second quantity 1115 are selectively removed, the electrical contact 1150 over the first portion 1120 and the second portion 1125 (shown in FIG. 11a) of the surface 1107. , 1155 may be deposited. In addition, electrical contacts 1160 may be deposited over the dielectric material 1145. FIG. 11 e shows the semiconductor substrate 1105 after deposition of electrical contacts 1150, 1155, 1160. FIG. 11 e shows that electrical contact 1150 covers the entire first portion 1120 and electrical contact 1155 covers the entire second portion 1125, but electrical contact 1150 is shown as covering the first portion 1120. It is anticipated that electrical contacts 1155 may partially cover the second portion 1125 and / or may be partially coated. Electrical contacts 1160 are deposited such that they are not in electrical contact with electrical contacts 1150 and 1155.

  These electrical contacts 1150, 1155, 1160 may be printed using the techniques described above in connection with the first quantity 1110 and the second quantity 1115, or using any other suitable technique. It may be formed. One or more of the electrical contacts 1150, 1155, 1160 may comprise a metal, metal particles, or any other suitable conductive material.

  The structure shown in FIG. 11e may form a field effect transistor, where electrical contact 1150 serves as a drain contact (denoted “D” in FIG. 11e) and electrical contact 1155 is a source contact ( The electrical contact 1160 serves as a gate contact and the dielectric material 1145 serves as a gate barrier. The conduction channel of the transistor may include a region inside the semiconductor substrate 1105 (ie, below the surface 1107) between the doped regions 1135 and 1140.

  Field effect transistors (FETs) fabricated by method 1100 and other methods discussed below have advantages over lithographically fabricated FETs and thin-film transistors (TFTs). Can do. With respect to FETs fabricated by lithography, traditional lithography can be very expensive, whereas method 1100 (and other methods discussed below) uses a material printer (eg, a desktop inkjet printer) and a furnace. And can be done inexpensively. For TFTs, their fabrication can be limited by a low heat budget (because excessive heat can damage the thin layer components), and the TFT itself has poor quality of the thin layer that forms the FET. It may have limited performance (eg, relatively low electron mobility) due to what may be sufficient. In contrast, the heat balance can be increased by fabricating FETs by method 1100 (and other methods described below). Because 1) there is no thin layer that can be vulnerable to high temperatures, and 2) the semiconductor substrate 1105 may include a high quality crystalline semiconductor that may have high electron mobility, which is higher than the thin layer of TFT. This is because the susceptibility to can be lowered.

  In general, when a semiconductor substrate (used to form a conduction channel between a source and drain) of an electronic device (eg, FET) is printed, such a device can typically be achieved by printing. It may have performance limited by the low electron mobility of the semiconductor material. In contrast, in the method 1100 (and other methods described below), the semiconductor substrate 1105 (used to form the conduction channel) does not need to be printed and has a high electron mobility. It can be a quality crystalline semiconductor material. In this manner, the method 1100 provides the low cost advantages of printed electronics and the high performance (eg, high electron mobility) enabled by using a high quality crystalline semiconductor substrate on which other components can be printed. Combined with a high heat balance.

  The semiconductor substrate 1105 can comprise any semiconductor material suitable for forming electronic devices. In some embodiments, the semiconductor substrate 1105 may include planarized semiconductor particles that are secured to another substrate, such as, for example, the planarization sphere 56 shown in FIG. 5b. Other examples of the semiconductor substrate 1105 can include, but are not limited to, the planarizing sphere 16 shown in FIGS. 3 and 4.

  In some embodiments, the semiconductor substrate 1105 is composed of a semiconductor material formed in situ on another (eg, non-semiconductor) substrate by heating a particulate / powder semiconductor precursor deposited on the other substrate. A planarization island may be included. The particles may be melted and fused by heating to form a molten globule. By cooling the globules, the molten globules may be solidified and crystallized to form crystalline islands of semiconductor material fixed to the other substrate. This method of forming semiconductor islands is described in US Patent No. 9,396,932 and US Patent Application No. 15 / 184,429, both of which are hereby incorporated by reference in their entirety. Such semiconductor islands can serve as a semiconductor substrate 1105 when planarized.

  In certain circumstances, in-situ formation of semiconductor islands may result in disk-shaped semiconductor islands as described in US patent application Ser. No. 15 / 184,429. A non-limiting example of such a situation is that a silicon precursor (powder or small piece) on an alumina substrate in the presence of oxygen (in the atmosphere or in another material in contact with molten globules) will be melted into the melting point of silicon (eg, Heating to a temperature higher than 1500 ° C.). Under these conditions, a disk / layer containing silica may be formed between the crystalline silicon island and the alumina substrate, and the crystalline silicon island may be disk-shaped. Such a disk-shaped silicon island may be used as the semiconductor substrate 1105 (optionally after polishing and / or planarization).

  Surface 1107 may include a planar surface. In embodiments where the semiconductor substrate 1105 includes planarized semiconductor particles, the surface 1107 may include a planar surface formed in a planarized cross section of the planarized semiconductor particles. Furthermore, although FIGS. 11a-e show that the surface 1107 is planar, it is anticipated that the surface 1107 may be curved. For example, the surface 1107 may include a curved or otherwise non-planar outer surface of semiconductor particles, or a curved surface of a flexible semiconductor substrate. The semiconductor substrate 1105 may include a polycrystalline or single crystal semiconductor material including but not limited to silicon. The semiconductor substrate 1105 may be pre-doped before the method 1100 steps are performed.

  In some embodiments, the semiconductor substrate 1105 may include a semiconductor wafer, or other suitable polycrystalline or other than semiconductor particles that are formed separately from another substrate and then secured to the other substrate. A single crystal semiconductor substrate may be included.

  In some embodiments, the gate contact (formed by electrical contact 1160) is deposited after deposition of dielectric material 1145 and prior to selective removal of first quantity 1110 and second quantity 1115. Also good. In these embodiments, the electrical contact 1160 is resistant to and / or its effect on the selective removal method used to selectively remove the first quantity 1110 and the second quantity 1115. It is chosen not to receive.

  In some embodiments, a barrier island may be deposited on the surface in the gap before the first and second quantities are deposited. This barrier island may help control the gap length defined by the distance between the first and second quantities (among other factors). Since the gap length (along with other factors) determines the length of the FET's conduction channel inside the semiconductor substrate, the length of the conduction channel and the performance characteristics of the FET can be controlled by controlling the gap length. Get help.

  In some embodiments, the gap length, ie the distance between the first and second quantities, may range from about 0.1 μm to about 100 μm. In other embodiments, the gap length, ie the distance between the first and second quantities, may range from about 0.1 μm to about 10 μm. In yet other embodiments, the gap length, ie the distance between the first and second quantities, may range from about 0.1 μm to about 5 μm.

  Figures 12a-f illustrate the steps of a method 1200 for forming an electronic device (e.g., FET) using such a barrier island. FIG. 12 a shows a barrier island 1205 deposited on the surface 1107 in the gap 1130. Barrier island 1205 is formed of any suitable material that can form a barrier to first quantity 1110 and second quantity 1115 and that can be selectively removed from substrate 1105 as discussed in more detail below. Also good. In some embodiments, the barrier island 1205 may be deposited as an amount of liquid and / or paste. The liquid / paste comprising the barrier material (used to form the barrier island) may comprise an organic material such as a plastic such as polyimide, or any other suitable material. The liquid / paste containing the barrier material may be printed on the semiconductor substrate 1105 using the same method described above in connection with printing the first quantity 1110 and the second quantity 1115.

  One or more of the first quantity, the second quantity, the dielectric material, the barrier islands, and the electrical contacts may be deposited using a printing technique, but two to print these components. It is anticipated that more or more different printing techniques may be used.

  After depositing the barrier island 1205 in the gap 1130, a first quantity 1110 and a second quantity 1115, respectively, over the first and second portions 1120 and 1125 of the surface 1107, as shown in FIG. 12b. May be deposited. As discussed above, the barrier island 1205 may serve as a barrier that prevents the first quantity 1110 and the second quantity 1115 from entering the gap 1130 (eg, by flowing and / or spreading).

  Next, the semiconductor substrate 1105, the first and second quantities 1110 and 1115, and the barrier island 1205 are heated to diffuse at least some dopant from the first and second quantities 1110 and 1115 to the surface 1107, Doped regions 1135 and 1140 as shown in FIG. 12c may be formed, respectively. In addition, this heating may selectively remove (eg, burn) the barrier island 1205 and leave a surface 1107 in the gap 1130 to later deposit dielectric material 1245 as shown in FIG. 12d. Good. In some embodiments, the barrier island 1205 may be selectively removed using a selective removal method other than wet chemical etching or other heating.

  Dielectric material 1245 may have a similar composition as dielectric material 1145 and be deposited in a similar manner. The dielectric material 1245 may have a small wetting angle with the first quantity 1110 and the second quantity 1115. The dielectric material 1245 may wet the first quantity 1110 and the second quantity 1115 with a wetting angle less than about 90 °. In other words, the dielectric material 1245 can easily wet the first quantity 1110 and the second quantity 1115. This can define the shape of the dielectric material 1245 as shown in FIGS. 12d-f, ie, having a concave top and curved sides.

  After deposition of dielectric material 1245, the steps of method 1200 shown in FIGS. 12d, 12e, and 12f are generally similar to the steps of method 1100 shown in FIGS. 11c, 11d, and 11e, with one difference. That is, the shape of the electrical contact 1260 is different from that of the electrical contact 1160. The shape of the electrical contact 1260 is defined by the curvature of the top surface of the dielectric material 1245. In embodiments in which electrical contact 1260 is deposited and / or printed as a liquid, the concave top of dielectric material 1245 can pool and / or orient this electrical contact away from electrical contacts 1150 and 1155. This may help prevent any electrical shorts between electrical contact 1260 and electrical contacts 1150 and 1155, respectively.

  Although dielectric material 1145 in FIG. 11 is shown as having a different shape than dielectric material 1245 in FIG. 12, the dielectric material in one or both of methods 1100 and 1200 is either dielectric material 1145 or dielectric material 1245. It is anticipated that it may be similar in shape to either one.

  In some embodiments, the barrier island 1205 may comprise the same material as the dielectric material 1245, where the barrier island 1205 is not selectively removed and remains on the surface 1107 throughout the steps of the method 1200. However, in these embodiments, the barrier island 1205 may not have the same shape as the dielectric material 1245 because the barrier island 1205 is deposited prior to the deposition of the first quantity 1110 and the second quantity 1115.

  In some embodiments, the first and second amounts of liquid medium may be reduced in volume after being deposited on the surface of the semiconductor substrate. This volume reduction may be due to various factors including, but not limited to, evaporation of some or all of any volatile components of the liquid medium during the “bake out” step. FIGS. 13a-g illustrate the steps of a method 1300 for forming an electronic device, which uses this volume reduction.

  First, a barrier island 1205 is deposited on the surface 1107, as shown in FIG. 13a. This step may be similar to the first step of the method 1200 shown in FIG. 12a. Next, as shown in FIG. 13b, an initial amount 1305 of liquid medium (including dopant) is deposited on the surface 1107 to cover the first portion 1120 and the second portion 1125 of the surface 1107, and the gap A barrier island 1205 that covers 1130 may be coated. As discussed above, the barrier island 1205 may be disposed within the gap 1130 between the first portion 1120 and the second portion 1125. The volume of the initial amount 1305 is larger than the combined volume of the first amount 1110 and the second amount 1115.

  As discussed above, the volume of the initial amount 1305 is reduced during the bakeout step. The bakeout and the accompanying volume reduction may be by preheating or any other step that can result in a volume reduction of the initial amount 1305 by at least partially losing the volatile components of the liquid medium. Good. FIG. 13c shows that after the volume of the initial amount 1305 is reduced during the bakeout, the pre-covered barrier island 1205 may be exposed and the first amount 1110 and the second amount that the initial amount 1305 is smaller. It can be shown that a quantity 1115 can be formed. FIG. 13c shows that the first quantity 1110 is the same shape and size as the second quantity 1115, but the first and second quantities formed as a result of the bakeout are different shapes and sizes. It is anticipated that it may have In addition, in FIGS. 13c-e, the first quantity 1110 and the second quantity 1115 are assumed to be similar in shape and size to the corresponding first and second quantities in FIGS. 11a-c and 12b-d. Although shown, the first and second quantities obtained by volume reduction of the initial quantity 1305 (in method 1300) were deposited on semiconductor substrate 1105 in methods 1100 (FIG. 11) and 1200 (FIG. 12). It is anticipated that it may have a different shape and / or size than the first and second quantities.

  The last five steps of the method 1300 shown in FIGS. 13c-13g may be similar to the last five steps of the method 1200 shown in FIGS. 12b-f and will not be described again here in detail.

  In some embodiments, the barrier island deposits a layer of photoreactive material on the surface of the semiconductor substrate, and the range of photoreactive material overlying the gap is changed to light for changing the photoreactive material. It may be formed by forming a barrier island containing light-modified photoreactive material by exposing to and selectively removing unexposed areas of photoreactive material from the surface. The photoreactive material may include a photoresist including, but not limited to, a negative photoresist such as Shipley BPR ™ -100 photoresist. Exposing the photoreactive material to light can be done without the need for expensive and / or complex photolithographic equipment. For example, light exposure may be performed using a light source such as a UV LED or a laser attached to the print head of an inkjet printer.

  FIGS. 14a-g illustrate steps in a method 1400 of forming a barrier island by exposing a layer of photoreactive material and then selectively removing unexposed portions. FIG. 14 a shows a layer of photoreactive material 1405 deposited on the substrate 1105. The photoreactive material 1405 may be spin coated or deposited on the semiconductor substrate using any other suitable technique. The photoreactive material 1405 may comprise a photoresist or any other suitable material, including but not limited to a negative photoresist such as, for example, Shipley BPR ™ -100 photoresist.

  The region of photoreactive material above the gap 1130 (shown in FIG. 14b) may then be exposed to light configured to alter the photoreactive material. After this exposure and modification, as shown in FIG. 14b, the unexposed portions of the layer of photoreactive material 1405 are selectively removed to form a barrier island 1410 containing the photoreactive material modified by light. May be. By using a light source such as a UV laser with a micron or sub-micron spot size, for example, small features such as barrier island 1410 can be directly written. The selective removal step may remove unexposed portions of the layer of photoreactive material 1405 while leaving the exposed portion of the photoreactive material and the semiconductor substrate intact. Selective removal may include wet chemical etching or any other suitable selective removal method.

  Once the barrier island 1410 is formed, a first quantity 1110 may be deposited over the first portion 1120 of the surface 1107 and a second portion 1125 over the second portion 1125, as shown in FIG. 14c. A quantity 1115 may be deposited. The last five steps of the method 1400 shown in FIGS. 14c-g may be similar to the last five steps of the method 1200 shown in FIGS. 12b-f and will not be described again here in detail.

  Methods 1100, 1200, 1300, and 1400 may be used to form and / or fabricate controllable gate electronic components, including but not limited to transistors such as FETs. As discussed above, these methods may be performed on a semiconductor substrate that is a planarized semiconductor particle that is formed separately from another substrate and then secured to the other substrate so that it cannot move. The For example, the transistors 55a, 55b shown in FIGS. 5c, 7, 8, and 10 may be formed using one or more of the methods 1100, 1200, 1300, and 1400.

The above-described embodiments of the present invention are intended to be examples of the invention and by those skilled in the art without departing from the scope of the invention, which is defined only by the claims appended hereto. Changes and modifications may be made to these embodiments.

Claims (23)

A method of forming a plurality of electronic devices on a substrate, the method comprising:
Providing semiconductor particles formed separately from the substrate;
Positioning the semiconductor particles at a predetermined position on the substrate;
Fixing the semiconductor particles so as not to move at the predetermined position of the substrate;
After fixing the semiconductor particles immovably, removing a portion of each of the semiconductor particles to expose a cross section of the semiconductor particles, the cross section being a planar surface; and
Providing one or more controllable gate electronic components above or directly below each planar surface, wherein said providing said one or more controllable gate electronic components comprises each planar Against the surface,
Depositing a first amount of a first liquid medium comprising a dopant on a first portion of the planar surface and a second amount of the first liquid on a second portion of the planar surface; Depositing the liquid medium, wherein the first quantity is spaced apart from the second quantity by a gap;
Heating the first amount, the second amount, and the corresponding semiconductor particles, wherein the heating step transfers at least some of the dopant from the first liquid medium to the planar surface. A step configured to diffuse; and
Depositing a dielectric material on the planar surface in the gap;
Selectively removing the first amount and the second amount from the planar surface;
Depositing electrical contacts on each of the first portion and the second portion;
Depositing further electrical contacts on the dielectric material. A method of forming an electronic device on a substrate, the method comprising:
Providing semiconductor particles formed separately from the substrate;
Fixing the semiconductor particles so as not to move on the substrate;
After the immobilizing step, depositing a first amount of a first liquid medium containing a dopant on the first portion of the surface of the semiconductor particle and on the second portion of the surface. Depositing a second quantity of the first liquid medium, wherein the first quantity is spaced apart from the second quantity by a gap;
Heating the first amount, the second amount, and the semiconductor particles, wherein the heating step causes at least some of the dopant to diffuse from the first liquid medium to the surface. Composed of steps,
Depositing a dielectric material on the surface in the gap;
Selectively removing the first amount and the second amount from the surface;
Depositing electrical contacts on each of the first portion and the second portion;
Depositing further electrical contacts on the dielectric material. Forming a barrier island on the surface in the gap prior to the step of depositing the first amount and the second amount;
3. The method of claim 2 , further comprising selectively removing the barrier island from the surface prior to the step of depositing the dielectric material. The step of forming the barrier island comprises:
4. The method of claim 3 , comprising depositing a third amount of a second liquid medium comprising a barrier material on the surface in the gap. The step of forming the barrier island comprises:
Depositing a layer of photoreactive material on the surface;
Exposing a region of the photoreactive material overlying the gap to light configured to alter the photoreactive material;
Forming the barrier island comprising the photoreactive material modified by the light by selectively removing unexposed regions of the layer of the photoreactive material from the surface. 3. The method according to 3 . The step of depositing the dielectric material comprises:
The method of claim 2 , comprising depositing a fourth amount of a third liquid medium comprising the dielectric material on the surface in the gap. The method of claim 6 , wherein the fourth amount wets the first amount and the second amount at a wetting angle less than about 90 °. The method of claim 3 , wherein the heating step further selectively removes the barrier island from the surface. Depositing the first quantity and the second quantity comprises:
Depositing an initial amount of the first liquid medium on the surface, wherein the initial amount includes the first portion of the surface, the second portion of the surface, and the first portion; Covering the barrier island disposed between the second portion; and
Exposing the barrier island by heating the initial amount to reduce the volume of the initial amount by at least partially evaporating one or more components of the first liquid medium. , and forming the first amount and the second amount being separated from each other by the barrier island, the method of claim 3. The method of claim 2 , wherein the surface comprises a planar surface. The method of claim 10 , wherein the planar surface comprises a planarized surface of the semiconductor particles. 3. The method of claim 2, wherein the first amount is spaced from the second amount by the gap in the range of about 0.1 [mu] m to about 100 [mu] m. Depositing the first amount;
Depositing the second amount;
Depositing the dielectric material;
Depositing the electrical contacts on each of the first portion and the second portion; and
The method of claim 2 , wherein printing is used for one or more of the steps of depositing the additional electrical contacts. The printing is
Screen printing,
Flexographic printing,
Gravure printing,
Stamping,
Offset printing, and
14. The method of claim 13 , comprising one or more of inkjet printing. A method of forming an electronic device, the method comprising:
Providing a semiconductor substrate having a surface including a first portion and a second portion, wherein the first portion is spaced from the second portion by a gap;
Forming a barrier island on the surface in the gap;
Depositing a first amount of a first liquid medium comprising a dopant on the first portion of the surface and a second amount of the first liquid on the second portion of the surface; Depositing media, wherein the first quantity is separated from the second quantity by the barrier island;
Heating the first amount, the second amount, and the semiconductor substrate, wherein the heating step causes at least some of the dopant to diffuse from the first liquid medium to the surface. Composed of steps,
Selectively removing the barrier island from the surface;
Depositing a dielectric material on the surface in the gap;
Selectively removing the first amount and the second amount from the surface;
Depositing electrical contacts on each of the first portion and the second portion;
Depositing further electrical contacts on the dielectric material. The step of forming the barrier island comprises:
The method of claim 15 , comprising depositing a third amount of a second liquid medium comprising a barrier material on the surface in the gap. The step of forming the barrier island comprises:
Depositing a layer of photoreactive material on the surface;
Exposing a region of the photoreactive material overlying the gap to light configured to alter the photoreactive material;
Forming the barrier island comprising the photoreactive material modified by the light by selectively removing unexposed regions of the layer of the photoreactive material from the surface. 15. The method according to 15 . The step of depositing the dielectric material comprises:
16. The method of claim 15 , comprising depositing a fourth amount of a third liquid medium comprising the dielectric material on the surface in the gap. The method of claim 18 , wherein the fourth amount wets the first amount and the second amount at a wetting angle less than about 90 °. The method of claim 15 , wherein the heating step further selectively removes the barrier island from the surface. Depositing the first quantity and the second quantity comprises:
Depositing an initial amount of the first liquid medium on the surface, wherein the initial amount includes the first portion of the surface, the second portion of the surface, and the first portion; Covering the barrier island disposed between the second portion; and
Exposing the barrier island by heating the initial amount to reduce the volume of the initial amount by at least partially evaporating one or more components of the first liquid medium. , and forming the first amount and the second amount being separated from each other by the barrier island, the method of claim 15. The method of claim 15 , wherein the surface comprises a planarized surface of the semiconductor substrate. Depositing the first amount;
Depositing the second amount;
Depositing the dielectric material;
Depositing the electrical contacts on each of the first portion and the second portion; and
The method of claim 15 , wherein printing is used for one or more of the steps of depositing the additional electrical contacts.

Images