WO2011096601A1 - Matrice de mémoires flash nor empilées et procédé de fabrication - Google Patents

Matrice de mémoires flash nor empilées et procédé de fabrication Download PDF

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WO2011096601A1
WO2011096601A1 PCT/KR2010/000704 KR2010000704W WO2011096601A1 WO 2011096601 A1 WO2011096601 A1 WO 2011096601A1 KR 2010000704 W KR2010000704 W KR 2010000704W WO 2011096601 A1 WO2011096601 A1 WO 2011096601A1
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layer
semiconductor
insulating film
substrate
layers
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PCT/KR2010/000704
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Korean (ko)
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박병국
윤장근
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서울대학교산학협력단
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Publication of WO2011096601A1 publication Critical patent/WO2011096601A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present invention relates to a noah flash memory array and a method of manufacturing the same, and more particularly, the memory cells are formed in series along each word line while being stacked vertically, vertically intersecting the word lines of each layer and the source of each cell.
  • a bit line is formed in contact with a drain, and stacked vertically to increase the memory capacity as much as possible.
  • bit-cost the cost per unit bit
  • bit-cost the cost per unit bit
  • an object of the present invention is to provide a Stephen flash memory array having a stacked three-dimensional structure capable of stacking word lines vertically and increasing memory capacity as much as possible, and a method of manufacturing the same.
  • the stacked Arthur flash memory array comprises a plurality of word lines stacked vertically spaced apart on the substrate; A plurality of semiconductor layers in which channel regions and sources / drains are repeatedly formed in a word line direction with an insulating film having a charge storage layer parallel to each other on one side of each word line; A plurality of interlayer insulating films formed on the upper and lower surfaces of the semiconductor lines parallel to the word lines and the word lines; And a plurality of bit lines passing through at least one of the plurality of interlayer insulating layers and having vertical connection plugs to contact upper and lower sources / drains of the semiconductor layers and intersect the word lines.
  • a separate insulating film is formed on an opposite side of each word line on which the semiconductor layers are formed, and the interlayer insulating film forms a stacked structure with the separated insulating film, wherein each word line and the charge storage layer are formed around the stacked structure.
  • An insulating film having a semiconductor layer and a basic array formed to be symmetrical with each semiconductor layer is repeatedly formed in a bit line direction, and the vertical connection plugs of the bit lines are in common contact with a source / drain of a semiconductor layer located between the base arrays. It may have a first form formed.
  • a basic array in which the word lines, the insulating film having the charge storage layer, the semiconductor layer and the interlayer insulating film are symmetrically around the vertical connection plugs of the respective bit lines is repeatedly formed in the bit line direction.
  • the semiconductor array may have a second shape, in which a semiconductor substrate may be formed to be in contact with opposite sides of the word lines in which the semiconductor layers are adjacent to each other.
  • n is repeatedly stacked n times in the order of "interlayer insulating film-> separating insulating film" on a predetermined substrate, and the n + 1 interlayer insulating film is formed on the nth insulating insulating film.
  • the method is repeatedly stacked n times on the predetermined substrate in the order of "stacking media layer-> semiconductor layer", and n + 1th stacking is performed on the nth semiconductor layer.
  • the Noah flash memory array according to the present invention, it is possible to increase the memory capacity by stacking word lines vertically without miniaturizing each memory cell.
  • FIG. 1 to 10 are process perspective views exemplarily illustrating a step of manufacturing a first form of a noah flash memory array according to the present invention.
  • FIG. 11 is a cross-sectional view illustrating main parts of an inner structure by cutting one side of FIG. 10.
  • FIG. 12 is an enlarged view illustrating main parts of the main part to explain a basic structure and an operation relationship of a no-flash memory array according to the present invention.
  • FIG. 13 is an electrical characteristic diagram illustrating that the program interference can be effectively prevented by plotting an unselected bit line during a program operation with the basic structure of FIG. 12.
  • FIGS. 14 to 25 are process perspective views exemplarily illustrating steps for manufacturing a second form of a noah flash memory array according to the present invention.
  • FIG. 26 is a cross-sectional view illustrating main parts of an inner structure by cutting one side of FIG. 25.
  • substrate etch stop material layer (nitride film)
  • interlayer insulating film interlayer insulating film
  • 60, 600 insulating film having a charge storage layer
  • etching prevention layer (nitride film)
  • an embodiment of the structure of a noah flash memory array according to the present invention is basically, on the substrate (10, 100), as commonly expressed in Figures 10, 11, 12, 25 and 26 A plurality of word lines (WL11, WL21) or (WL12, WL22) stacked vertically spaced apart from each other; The channel region [(74b, 74d) or 324b] and the source / drain [(74a) in the wordline direction with an insulating film 60 or 600 having a charge storage layer horizontally side by side on each side of each wordline.
  • a plurality of interlayer insulating films [32, 34, 36 or (512, 522, 532)] formed on and under each of the word lines and the semiconductor layers parallel to the word lines; Vertical connection to pass through at least one of the plurality of interlayer insulating films and to contact upper and lower sources / drains (72a, 74a), (72c, 74c) or (314a, 324a, (314c, 324c)) of the semiconductor layers; It includes a plurality of bit lines (BL1, BL2) having a plug (92a or 922) formed to cross each of the word lines.
  • BL1, BL2 bit lines
  • the word line 54a2 and the semiconductor layer 74 are formed to be parallel to each other with the insulating film 60 having the charge storage layer 64 interposed therebetween, and the semiconductor layer 74 is disposed.
  • the core technology is that the bit lines 92 are vertically stacked and the upper and lower sources / drains (eg, 72a and 74a) formed at corresponding positions of the respective semiconductor layers are commonly contacted with the vertical connection plugs 92a.
  • a plurality of word lines are vertically stacked (eg, 52a2, 54a2) with the interlayer insulating films 32, 34, and 36 interposed therebetween in the first direction (for example, the z-axis direction), and the bit lines are aligned with the first direction.
  • the plurality of bit lines are spaced apart in a second vertical direction (eg, x-axis direction) (eg, 92 and 94), and the bit lines are horizontally parallel to the respective word lines by vertical connection plugs (eg, 92a).
  • the upper and lower corresponding sources / drains (eg, 72a and 74a) of the formed plurality of semiconductor layers (eg, 72 and 74) may be contacted in common.
  • the insulating film having the charge storage layer may be formed in a blocking oxide film 62 / nitride film 64 / tunneling oxide film 66 structure from each word line (eg, 54a2), as shown in FIG.
  • the charge storage layer may be a nitride layer 64, but is not limited thereto and may have a floating gate structure that forms a charge storage layer as a conductive layer instead of the nitride layer.
  • the insulating layer having the charge storage layer may be formed to surround three surfaces of each of the semiconductor layers 72 and 74, as shown in FIG. 11, and as illustrated in FIG. 26, three surfaces of each word line 722 and 742. It may be formed surrounding the.
  • the NOR flash memory array can also increase the memory capacity vertically as much as possible. Unlike the upper structure, the area expansion for contact of each memory cell does not occur as the memory capacity increases.
  • FIG. 12 illustrates an example of applying power to bit lines and word lines connected to each source / drain when a program operation is performed with the array according to the embodiment
  • FIG. 13 shows a source when operating as shown in FIG. 12.
  • the charge amount of electrons injected into the left storage node 64a of the specific cell including (S; 74a), the channel region 74b, and the drain (D; 74c) of the electrons injected into the right storage node 64b of the neighboring cell.
  • S storage node 64a of the specific cell
  • D; 74c drain
  • an isolation insulating layer (eg, 42a) is formed on an opposite side of each word line (eg, 52a2) on which each of the semiconductor layers (eg, 72) is formed.
  • Each of the interlayer insulating layers (eg, 32 or 34) forms a stack structure with the isolation insulating layer, and each of the word lines (eg, 52a2) and the charge storage centering around the isolation insulating layer (eg, 42a) forming the stack structure.
  • An insulating film 60 having a layer and a basic array (for example, the structure shown in FIG. 10 or 11) formed such that each semiconductor layer (for example, 72) is symmetrically formed (refer to FIG. 10 or 11), Vertical connection plugs (e.g.
  • each bit line e.g., 92
  • the source / drain e.g., 72a, 74a and not shown neighboring base arrays
  • Is formed In common with Is formed
  • a plurality of word lines and a plurality of bit lines (structure of the basic embodiment) formed vertically intersecting with each other on a vertical xz plane are formed based on a separation insulating layer formed in a stacked structure with each interlayer insulating layer on opposite sides of each word line.
  • a basic array (for example, the structure shown in FIG. 10 or 11) to be symmetrically, and the basic array is repeatedly formed with a vertical connection plug of each bit line in the y-axis direction.
  • the separated oxide layer 82 is disposed between the bit lines including the vertical connection plugs to cover the channel regions 72b and 72d of the semiconductor layers 74b and 74d and to block electrical connections between neighboring bit lines 92 and 94. , 84, 86).
  • the isolation insulating films 42a and 44a are for preventing electrical connection and interference between word lines 52a1, 52a2; 54a1, 54a2 of the basic array symmetrically formed on both sides, and an insulating film having an oxide film or a high dielectric constant is preferable. Do.
  • each of the interlayer insulating films 32, 34, and 36 is an insulating material having an etch rate different from that of the insulating insulating films 42a and 44a
  • the interlayer insulating films 32 may be formed of a nitride film if the insulating insulating film is an oxide film.
  • the word lines 52a1, 52a2, 54a1, and 54a2 may be conductive materials having an etch rate different from those of the interlayer insulating films 32, 34, and 36. If the interlayer insulating films are nitride films, the silicon doped with impurities may be used. It may be formed of a material layer (eg, doped polycrystalline silicon or doped amorphous silicon).
  • Each of the semiconductor layers 72 and 74 may be a semiconductor material layer that can be deposited on the insulating film 60 having the charge storage layer.
  • each of the semiconductor layers 72 and 74 may be formed of a silicon-based material layer (polycrystalline silicon or amorphous silicon). have.
  • Each of the bit lines 92 and 94 may be formed of a silicon-based material layer (eg, doped polysilicon or doped amorphous silicon) that is doped with a metal or an impurity as a conductive material.
  • a silicon-based material layer eg, doped polysilicon or doped amorphous silicon
  • the substrate 10 may be any material capable of supporting the array structure as described above, and a flexible material (eg, a plastic material) may be selected and used as long as the substrate structure can be maintained.
  • a flexible material eg, a plastic material
  • each of the word lines 52a1, 52a2, 54a1, 54a2, each of the semiconductor layers 72, 74, and the bit lines 92, 94 is formed of silicon while using a silicon substrate as the substrate 10.
  • a material layer eg, nitride film
  • a material layer 20 having a difference in etching rate between silicon is prevented in order to prevent etching of the substrate during the manufacturing process. Can be further formed.
  • the insulating film 60 having the charge storage layer has an ONO (blocking oxide film: 62 / nitride film: 64 / tunneling oxide film: 66) structure as shown in FIG. 12, and as shown in FIG. 11, the substrate etch stop material layer 20
  • ONO blocking oxide film: 62 / nitride film: 64 / tunneling oxide film: 66
  • the interlayer insulating layers 32, 34, and 36 and the word lines 52a1, 52a2, 54a1, and 54a2 constituting the basic array may be formed on the substrate.
  • a basic array (for example, the structure shown in FIG. 25 or FIG. 26) formed such that the insulating film 600 having a layer, each of the semiconductor layers (eg, 316) and each of the interlayer dielectrics (eg, 524) are symmetrical to each other
  • the insulating insulating layer 800 is formed in contact with the opposite side of each word line (eg, 724) on which the semiconductor layer (eg, 316) is formed between the base arrays.
  • a plurality of word lines and a plurality of bit lines (structure of the basic embodiment) formed vertically intersecting with each other on a vertical xz plane may be symmetrically with respect to the vertical connection plug of each bit line (eg, FIG. 25).
  • isolation oxide layers 832 and 834 are filled between the vertical connection plugs to cover the channel regions 314b and 324b of the semiconductor layers and to block electrical connections between neighboring vertical connection plugs.
  • the isolation insulating film 800 is to block the electrical connection and interference between the word lines exposed to the same height between the basic array is preferably an oxide film or an insulating film having a high dielectric constant.
  • Each of the interlayer insulating films 512, 522, 532; 524, and 534 may be formed of the same material as the isolation insulating film 800.
  • Each word line 722, 724, 742, 744 and each bit line 920, 940 are formed of a silicon-based material layer (eg, doped polysilicon or doped amorphous silicon) or a metal layer doped with impurities. Can be.
  • a silicon-based material layer eg, doped polysilicon or doped amorphous silicon
  • a metal layer doped with impurities can be.
  • Each of the semiconductor layers 314, 316, 324, and 326 is preferably formed of a single crystal silicon layer.
  • the substrate 10 may be any material capable of supporting the array structure as described above, and a flexible material (eg, a plastic material) may be selected and used as long as the substrate structure can be maintained.
  • a flexible material eg, a plastic material
  • An etch stop layer (eg, nitride layers 410 and 420) may be further formed on uppermost interlayer insulating layers 532 and 534 among the plurality of interlayer insulating layers so as to be symmetrical with respect to the vertical connection plugs (eg, 922) of the bit lines. .
  • the insulating film 600 having the charge storage layer has an ONO structure as shown in FIG. 12, and as shown in FIG. 26, an interlayer insulating film 512, 522, 532; 524, 534 constituting a basic array on a substrate, and a semiconductor.
  • the layers 314, 316, 324 and 326 may be formed to surround the etch stop layers 410 and 420.
  • This is a method of manufacturing the shape according to the first embodiment of the Arthur flash memory array structure, and is manufactured through the steps illustrated in FIGS. 1 to 10.
  • n layers are repeatedly stacked in order of " interlayer insulating film 32-> separation insulating film 42 " on the predetermined substrate 10 (in FIG.
  • the n + 1th interlayer insulating layer 36 is further stacked on the nth isolation insulating layer 44 and then etched with a first mask patterned in the word line direction to form a plurality of basic array patterns 32, 42, 34, 44, 36).
  • FIG. 1 only the basic array pattern is illustrated, but the plurality of basic array patterns are spaced at a predetermined interval in the bit line direction (a first step).
  • the isolation insulating films 42 and 44 are intended to block electrical connection and interference between neighboring word lines in the future, the isolation insulating films 42 and 44 may be formed of an oxide film or an insulating film having a high dielectric constant.
  • the interlayer insulating films 32, 34, and 36 may be formed of an insulating material having a difference in etching rate from that of the isolation insulating films 42 and 44, and thus may be formed of a nitride film having a lower etching rate than that of the insulating insulating film.
  • the substrate 10 may be any material capable of supporting the array structure, and a flexible material (eg, a plastic material) may be selected and used as long as the substrate structure can be maintained.
  • a flexible material eg, a plastic material
  • a silicon substrate is used as the substrate 10 and at least one or more of a word line, a semiconductor layer, and a bit line are formed of a silicon based material layer in a subsequent process, as shown in FIG. It is preferable to further form the etch stop material layer 20 and to proceed with the above process.
  • the plurality of basic array patterns are isotropically etched by using the difference in the etch rate between the interlayer insulating layers 32, 34, and 36 and the separation insulating layers 42 and 44 to laterally align the separation insulating layers.
  • Recess (second step). 2 shows recessed isolation films 42a and 44a.
  • the word line material is deposited on the entire surface of the substrate and etched anisotropically to fill the recessed portions of the respective basic array patterns with the word line materials 52 and 54 (third step).
  • the word line material may be a conductive material having an etch rate different from that of the interlayer insulating films 32, 34, and 36.
  • the interlayer insulating film is a nitride film
  • a silicon-based material eg, doped polycrystalline silicon or doped with impurities
  • Amorphous silicon is preferred for depositing and etching to fill the recessed areas.
  • the filled wordline materials 52 and 54 are isotropically etched to recess laterally (fourth step). 4 shows recessed wordline materials 52a and 54a.
  • the recess depth of the word line material is 1/2 to 2/3 of the depth of the isolation insulating film recess in the second step.
  • the silicon-based material is larger than 2/3, the isolation insulating film is relatively reduced, so that the distance between neighboring word lines is reduced. This is because there is a problem of insulation or interference or a problem of unnecessarily increasing the horizontal area.
  • an insulating film having a charge storage layer is formed on the recessed wordline materials 52a and 54a (a fifth step).
  • an insulating film 60 having the charge storage layer may be formed on the entire surface of the substrate including the recessed word line materials 52a and 54a.
  • a blocking oxide film 62-> nitride film 64-> tunnel oxide film 66 is sequentially formed as in a known method.
  • a semiconductor material is deposited on the entire surface of the substrate, and anisotropically etched to fill the recessed portions on the insulating layer 60 with the semiconductor materials 72 and 74 (sixth step).
  • the semiconductor material may be a semiconductor capable of being deposited on the insulating layer 60 having the charge storage layer.
  • the semiconductor material may be formed of silicon-based material (polycrystalline silicon or amorphous silicon).
  • the separation oxide film 80 is deposited and planarized on the entire surface of the substrate (seventh step).
  • a second mask 89 patterned in the bit line direction is formed on the planarized separation oxide film 80 using a photoresist film PR, and the like, and the separation oxide film is etched as shown in FIG. 9.
  • the filled semiconductor material 72, 74 is exposed between the etched separated oxide layers 82, 84, and 86 (Eighth Step).
  • ion implantation is performed on the exposed semiconductor materials 72 and 74 to form source / drain 72a and 72c and 74a and 74c of the memory cell as shown in FIG. 11 (ninth step).
  • ion implantation may use plasma doping or the like.
  • bit line material eg, a silicon-based material or a metal doped with impurities
  • a bit line material is deposited and planarized on the entire surface of the substrate, thereby forming the bit line 92 between the etched isolation oxide layers 82, 84, and 86. 94) (step 10).
  • bit line material directly contacts the ion implanted source / drain, the conventional contact process for connecting (contacting) each cell is unnecessary.
  • n-layers are repeatedly stacked on a predetermined substrate 100 in the order of "stacking media layer 210-> semiconductor layer 310" (in FIG. 14, the layers are repeatedly stacked twice). Further, the n + 1 th stacking layer 230 and the etch stop layer 400 are further stacked on the n th semiconductor layer 320, and then etched with a first mask patterned in a word line direction to form a plurality of basic array patterns ( 210, 310, 220, 320, 230, 400). In FIG. 14, only the basic array pattern is illustrated, but the plurality of basic array patterns are spaced at a predetermined interval in the bit line direction (a first step).
  • the substrate 100 may be any material capable of supporting the array structure, and a flexible material (eg, a plastic material) may be selected and used as long as the substrate structure can be maintained.
  • a flexible material eg, a plastic material
  • the stacking layers 210, 220, and 230 are similar to silicon and have a lattice structure but have different etching rates (eg, silicon germanium).
  • 310 and 320 may be formed of a material having a similar lattice structure to that of the stacking layer and having an etch rate difference (for example, silicon), alternately by epitaxy.
  • the etch stop layer 400 is preferably formed of a nitride film to function as an etch stopper during the planarization process.
  • the plurality of basic array patterns are isotropically etched to recess the stacking layers 210, 220, and 230 laterally (second step). 15 shows recessed stacking layers 212, 222, 232.
  • the stacking layer 210, 220, 230 is sufficiently recessed to leave only a portion of the space for forming the vertical connection plug of the bit line.
  • an interlayer insulating film material such as an oxide film is deposited on the entire surface of the substrate, and anisotropically etched to fill the recessed portions of the respective basic array patterns with the interlayer insulating film materials 510, 520, and 530 ( Third step).
  • each of the filled basic array patterns is etched again isotropically, and this time, the semiconductor layers 310 and 320 are laterally recessed (fourth step). 17 shows recessed semiconductor layers 312 and 322.
  • the depth of the recess is lower than the depth of the stacking layer in the second step.
  • an insulating film having a charge storage layer is formed on the recessed semiconductor layer (fifth step).
  • an insulating film 600 having the charge storage layer may be formed on the entire surface of the substrate including the recessed semiconductor layers 312 and 322.
  • a blocking oxide film-> nitride film-> tunneling oxide film is sequentially formed as in a known method.
  • a word line material is deposited on the entire surface of the substrate and anisotropically etched to fill the recessed portions on the insulating layer with the word line materials 720 and 740 (Sixth Step).
  • the word line materials 720 and 740 may be a metal as well as a silicon-based material doped with impurities.
  • a separation insulating film 800 is deposited and planarized on the entire surface of the substrate (seventh step).
  • the isolation insulating film 800 fills between the basic array patterns and prevents electrical insulation and interference between neighboring word lines exposed between the basic array patterns, an oxide film or an insulating film having a high dielectric constant is preferable.
  • planarization process may be performed by a known CMP process, in which case the nitride film formed of the etch stop layer 400 serves as an etch stopper. In this case, the insulating layer 600 having the charge storage layer formed on the etch stop layer 400 in FIG. 20 is removed.
  • a second mask 810 opened in a word line direction is formed in the center of the etch stop layer 400 using a photoresist film PR, and the like, using the etch stop layer 400 / n + 1.
  • a second trench mediation layer 232 / n "semiconductor layer / lamination media layer" (322/222/312/212) is sequentially etched to form a trench 820 in the center to separate each of the basic array pattern (second) Step 8).
  • the stacking layer 234 remaining in each of the separated basic array patterns is removed, and as shown in FIG. 23, the interlayer insulating film material 830 is filled in the separated space 822. Planarize (ninth step).
  • the planarization process may be performed by a known CMP process.
  • the nitride films 410 and 420 separated by the etch stop layer serve as an etch stopper.
  • the insulating layer 600 having the charge storage layer formed on the etch stop layers 410 and 420 separated from FIG. 23 is removed.
  • an interlayer insulating film material 830 filling the separated space portion with a third mask (not shown) having a plurality of openings 824 at predetermined intervals in a word line direction on the separated space portion.
  • the semiconductor layers 324 and 326 are etched to expose the semiconductor layers 324 and 326, and as shown in FIG. 26, ion implanted into each of the exposed semiconductor layers to source / drain the memory cells 314a and 314c; 324a and 324c; 316a. 326a) (step 10).
  • the etching of the interlayer insulating material 830 may be such that the height of the minimum interlayer insulating film 510 remains so that the vertical connection plugs of the bit lines are not electrically connected to the substrate afterwards. 24), the ion implantation may use plasma doping or the like.
  • bit line material is deposited and etched on the entire surface of the substrate to form bit lines 920 and 940 having vertical connection plugs 922 and 942 contacting the source / drain of the memory cell (see FIG. 25). Eleventh step).
  • a silicon-based material doped with impurities as the bit line material may be used, but a metal is more preferable.
  • bit line material directly contacts the ion implanted source / drain, the conventional contact process for connecting (contacting) each cell is unnecessary.

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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne une matrice de mémoires flash NOR et un procédé de fabrication de cette dernière et, en particulier, une matrice de mémoires flash NOR empilées et un procédé de fabrication de celle-ci, selon lequel les cellules mémoire sont empilées verticalement et placées horizontalement côte à côte en série le long de chaque ligne de mot, une ligne de bits étant formée de façon qu'elle coupe perpendiculairement une ligne de mot de chaque couche et se trouve en contact avec une source/un drain de chaque cellule, permettant de la sorte d'augmenter la capacité mémoire autant que nécessaire par un empilement vertical.
PCT/KR2010/000704 2010-02-05 2010-02-05 Matrice de mémoires flash nor empilées et procédé de fabrication WO2011096601A1 (fr)

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PCT/KR2010/000704 WO2011096601A1 (fr) 2010-02-05 2010-02-05 Matrice de mémoires flash nor empilées et procédé de fabrication

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WO2011096601A1 true WO2011096601A1 (fr) 2011-08-11

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210375935A1 (en) * 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Three-Dimensional Memory Device and Method
CN114026676A (zh) * 2019-07-09 2022-02-08 日升存储公司 水平反或型存储器串的三维阵列制程
US20230027039A1 (en) * 2020-05-28 2023-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. Three-Dimensional Memory Device and Method
US11917821B2 (en) 2019-07-09 2024-02-27 Sunrise Memory Corporation Process for a 3-dimensional array of horizontal nor-type memory strings

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KR20090047614A (ko) * 2007-11-08 2009-05-13 삼성전자주식회사 수직형 반도체 소자 및 그 제조 방법.
KR20090093770A (ko) * 2008-02-29 2009-09-02 삼성전자주식회사 수직형 반도체 소자 및 이의 제조 방법.
KR20090123481A (ko) * 2008-05-28 2009-12-02 주식회사 하이닉스반도체 플래시 메모리 소자 및 제조 방법
KR20100009321A (ko) * 2008-07-18 2010-01-27 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법

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KR20090047614A (ko) * 2007-11-08 2009-05-13 삼성전자주식회사 수직형 반도체 소자 및 그 제조 방법.
KR20090093770A (ko) * 2008-02-29 2009-09-02 삼성전자주식회사 수직형 반도체 소자 및 이의 제조 방법.
KR20090123481A (ko) * 2008-05-28 2009-12-02 주식회사 하이닉스반도체 플래시 메모리 소자 및 제조 방법
KR20100009321A (ko) * 2008-07-18 2010-01-27 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114026676A (zh) * 2019-07-09 2022-02-08 日升存储公司 水平反或型存储器串的三维阵列制程
CN114026676B (zh) * 2019-07-09 2023-05-26 日升存储公司 水平反或型存储器串的三维阵列制程
US11917821B2 (en) 2019-07-09 2024-02-27 Sunrise Memory Corporation Process for a 3-dimensional array of horizontal nor-type memory strings
US20210375935A1 (en) * 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Three-Dimensional Memory Device and Method
US20230027039A1 (en) * 2020-05-28 2023-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. Three-Dimensional Memory Device and Method
US11716855B2 (en) * 2020-05-28 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method

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