Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
  • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
  • G01T1/16—Measuring radiation intensity
  • G01T1/24—Measuring radiation intensity with semiconductor detectors
  • G01T1/243—Modular detectors, e.g. arrays formed from self contained units
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
  • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
  • G01T1/16—Measuring radiation intensity
  • G01T1/24—Measuring radiation intensity with semiconductor detectors
  • G01T1/247—Detector read-out circuitry
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N25/773—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/107—Integrated devices having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
  • G01J1/00—Photometry, e.g. photographic exposure meter
  • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
  • G01J1/44—Electric circuits
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
  • H04N23/30—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from X-rays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors

Definitions

• the present invention relates to a new, very high frame rate, read out chip designed for single photon counting in combination with a separate semiconductor material for the photoelectric effect.
• This chip is the basic module for new detector systems for X-ray applications at synchrotrons or with lab equipment (lab diffractometers) : material science, crystallography, non destructive testing and medical applications; energy range: 1-200 keV.
• Hybrid pixel detectors consist of a pixilated X-ray
• the readout chip contains an array of n x m independently working channels (pixels) .
• Each channel has a charge sensitive preamplifier with tunable gain, a signal shaper with tunable shaping time, a comparator and a counter with simple pixel control and readout logic.
• a photon impinging a sensor pixel generates electron-hole pairs. These electron- hole pairs are separated by an electric field generating a charge pulse. This charge signal from the sensor is
• the shaped signal is fed to a comparator with a global reference voltage and an on-pixel trim DAC . An incoming signal exceeding this threshold will toggle the comparator state. If the chip is in Expose mode (counting the photons), the comparator pulse increments the digital counter by one.
• the pixel counter states are serially transferred to the chip periphery, where they are readout via dedicated readout logic.
• a single photon counting pixel detector chip comprising :
• said readout unit cell comprising:
• nibble counters each nibble counter having an individual number of bits, wherein for each bit a basic counter cell is provided; said basic counter cell comprising a counting element, a switch, a temporary storage element and an output stage, wherein said basic counter cells are cascaded; e) a side shift register to read out the nibble counters row-wise with a predetermined number of nibble row selections wherein the data stored in the temporary storage elements on the selected nibble counter row are sent on a parallel bus as currents and are transformed in digital levels by parallel bus receivers.
• the present chip therefore enable to measure incident photons at high frame rates with almost no dead time for data readout.
• the temporary storage element enables to take the next image while the previous one is being readout.
• the chip Due to the split of the pixel counter into a number of nibble counters for each pixel the chip further enables to readout at flexible bit depths according to the chosen dynamic range of the counter. Further, the crosstalk from digital to analogue signal lines is tremendously reduced: the readout takes place at lower signal rates due to the parallel readout in the range of the analogue pixel section and a faster serial readout data transfer at the digital sections in the periphery of the chip placed already enough apart from the sensitive analogue part.
• a preferred embodiment of the present invention may comprise the temporary storage elements implemented as an array of capacitors wherein this array of capacitors is physically placed on top of the pixel counter. Since the counter consumes already about 75 to 80% of the pixel area, this option does not occupy more space due to the stacked arrangement of the array of capacitors.
• a further preferred embodiment of the present invention provides columns of a predetermined number of pixels grouped together to form a supercolunm; every supercolumn being independent from the other ones whereby the readout is carried out in parallel on the number of resulting supercolumns . Assuming for example a chip
• a super column may comprise eight columns of pixel resulting in 32 super columns in total.
• N nibble counters
• DDR Double Data Rate
• SSR side shift register
• the outputs of the bus receivers are being stored for each super column in a receiving latch and serialized at a higher speed as compared to the speed of readout of a super column.
• the frequency of the respective clock is at maximum at 25 MHz wherein this chip zone is already rather far from the sensitive analogue pixel array.
• the array of readout unit cells may feature a triple well design placing P transistors and N transistors on separate substrates which are not shared with other transistors.
• three substrate zones may correspond to four separate power domains, wherein a charge amplifier
• transistor and I/O drivers are disposed on two completely separate substrate zones and power domains.
• a further option may provide the digital signal lines crossing analog pixel sections being shielded in order to minimize the coupling with the neighboring circuitry.
• this measure also contributes in reducing the crosstalk at the chip and printed circuit board level.
• global signals are generated with special care.
• global signals are generated in a manner to avoid crosstalk, wherein pixel counter RESET, STORE and EXPOSE signals occur as general signals; said RESET signal being distributed on a column base and being refreshed after a predetermined number of rows; said STORE signal causing an extra power consumption to copy the content of all bits into the respective temporary storage elements thereby biasing the switch in order to limit the maximum current flow through it; and said EXPOSE signal generate a high peak current substantially due to a short circuit current flowing from VDD to Ground during switching in a AND gate after a comparator wherein in the periphery of the chip a circuitry generates from a resulting ENABLE signal a two-phases signal which drives a P side and a N side of the readout unit cells in different time windows.
• Figure 1 illustrated a sketch of a basic counter cell (with readout circuitry) of a pixel counter chip
• Figure 2 shows a block diagram of the pixel counter and the pixel control logic
• Figure 3 depicts the pixel counter chip top level
• Figure 4 illustrates the design of columns, each comprising eight pixels that are grouped together to form a unit called hereinafter "supercolumn” .
• the following description explains an innovative single photon counting pixel detectors targeting problems
• the chip features double buffered storage, so a next image can already be taken while the previous one is being readout (i.e. Expose and Readout phases can happen at the same time) .
• This requires the storage of the pixel counters on a temporary buffer, so that counters can be reset to
• a standard design approach would be to copy the counter content into a set of latches, or to have two independent counters per pixel. Because 75 to 80% of the pixel area is already consumed by the counters, this approach would make the required area about 1.8 times higher than needed, conflicting with the requirement for a smaller pixel size.
• FIG. 1 is illustrating a basic counter cell 2, comprising a counting element T-Flip flop having an output Q, the capacitor C st0 re as temporary storage element and output stage (M1-M2) .
• the pixel counter 4 (Fig. 2) for each pixel is composed by 12 such cascaded basic counter cells 2.
• this array of capacitors C s tore can be physically placed on top of the pixel counter 4, they do not occupy more space, allowing a much smaller pixel size.
• the pixel of the current chip is actually in the range of 75 2 ⁇ 2 , compared with a range of 100 2 ⁇ 2 a double counter approach would require. This approach reduces the dead time to a minimum of less than 1 ⁇ is , needed to disable the pixel counters, perform the buffering, reset, and finally re-enable the pixel counters again. Because of the volatile character of the analogue storage, the readout has to occur before the capacitor C st0 re
• FIG. 2 shows the block diagram of the pixel counter 4 and the pixel control logic.
• the pixel counter 4 is composed by three sub-counters 4a to 4c of four bits each, which can be chained and controlled to form a pixel counter 4 which can be selected to be 4 (BitO to Bit3), 8 (BitO to Bit7) or 12 bit (BitO to Bitll) deep. This results in a dynamic range of 15, 255 and 4095 counts, respectively.
• An overflow logic receives as an input the chip mode (Mode) and the state of the sub-counters 4a to 4c. To inhibit wrap-around the pixel counter 4 is frozen in a reserved "overflow" state if the dynamic range is exceeded.
• the time needed to readout the chip in 12 bit mode is 121 ⁇ is (see section 3 hereinafter) .
• the chip gives the user the possibility to trade off dynamic range with frame rate speed. By setting the actual pixel counter depth to 8 or 4 bits readout times of 81 s, and 41 ]is respectively, can be achieved .
• the main cross talk mechanisms are coupling through the substrate of the silicon CMOS chip, through the power supply or through direct crosstalk between digital and analogue signal lines.
• the following measures are, therefore, implemented to minimize the cross talk. i) Separate substrate for the input transistor
• circuitry (to reduce the usually big crosstalk of the I/O pads to the substrate)
• Figure 3 shows the chip top level architecture and floorplanning . It was conceived based on point vi)-vii) .
• the idea consists in having fast signals only at the chip periphery, and slower and slower signals approaching the chip sensitive area. At the same time, the parallelism is increased and additional care is taken to avoid crosstalk due to high levels of switching activity.
• the 12 bit pixel counter 4 is split in three Nibble Counters (NCs) 4a to 4c, so a nibble row is formed by 256 NCs (1024 bits) .
• the readout based on a row- shift register (called Side Shift Register: SSR), is also carried out nibble-wise. A one (logical high) is fed in at the first cell of the SSR at the beginning of the readout cycle, and is then clocked through the register.
• the nibble row which corresponds to the SSR cell carrying the one is said to be "selected", and sends data stored in the on-pixel temporary storage capacitor C st0 re to the output readout circuitry .
• a pixel row readout can consist of 1, 2 or 3 nibble row selections, which results in 256, 512 or 768 nibble row selections for a complete frame readout in 4, 8 and 12 bit mode, respectively.
• the SSR is thus equipped with some additional control circuitry which allows skipping one or two nibble selections, in 8 and 4 bit mode respectively, to perform a correspondingly faster readout.
• Data stored on the selected NC row are sent on a parallel bus PB as currents, and transformed in digital levels by the array of 256 x 4 current comparators which act as bus receivers BR.
• the output of the bus receivers BR (i.e. the content of the NCs) of each super column SC are then stored in a receiving 32-bit latch BL and serialized at high speed by some dedicated circuitry ( superserializer 6) .
• the maximum frequency of digital signals generated or received by blocks which are very close to the sensitive pixel array is 6.25MHz (point vi) .
• a column selection circuitry is responsible for selecting the nibble to be presented at the input of the
• the superserialiser 6 serializes the four bits of every NC in pulses which are 5ns long.
• the chip was designed with a special care in layout, to minimize digital to analog crosstalk (point i to iv) .
• the technology used has the "triple well" feature, so that not only P-transistors , but also N-transistors can be placed on a separate substrate, which is not shared with other transistors. Three separate substrate zones are comprised, corresponding to 4 separate power domains.
• the charge amplifier transistors, as well as the I/O drivers, are on two completely separate substrates and power domains.
• the shaper and the pixel logic are connected to two separate power domains, but their transistors share the same
• the global signals (pixel counters RESET, STORE and EXPOSE) are generated with special care. In fact, they have to drive all the pixels (or even all the chip bits) at the same time, and this could cause very high crosstalk and even chip malfunctioning/failure .
• the RESET is distributed on a column base, and is refreshed every second row with weak drivers. This generates a
• switching domino wave which distributes as evenly as possible the extra power consumption generated by the reset both in space and, most of all, in time. Moreover, the signal is widened to >100ns, to be sure that the wave started by the positive edge is over before the wave started by the negative edge is taking place.
• the switch S (see Figure 1) is designed and biased so that it limits the maximum current flow through it. Setting and clearing the EXPOSE signal generates also a high peak current, which is mostly due to a short circuit current flowing from Vdd to Ground during switching in the AND gate after the comparator (see Figure 2) .
• special circuitry in the chip periphery generates from the incoming ENABLE pulses a 2-phases signal which drives the P and N side of the pixel circuitry in different time windows, so that no short circuit path Vdd-GND is present at any time.
• synchronization mode In "synchronization mode" a preloaded pattern can be read out continuously such that the chip behaves like a DDRII RAM. This is useful for synchronization with the external control circuitry.
• crosstalk minimization use of triple wells, separate power domains, shielding and starving of digital lines crossing the pixel analog section, special care for global signals generation and distribution, use of LVDS signals where possible.

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• 2010
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