Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current 
  • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
  • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current 
  • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
  • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
  • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

• This relates generally to DC-DC converters and voltage regulators, and more particularly to very low power implementations thereof that are especially adapted for use with energy harvesters.
• FIG. 1 shows a conventional DC-DC converter or LDO (low drop out) voltage regulator 1 including a voltage reference circuit 3 which applies a reference voltage VREF to the (-) input of an error amplifier 2.
• Voltage reference 3 typically is a 1.2 volt bandgap circuit.
• Output 2A of error amplifier 2 is connected to the input of an output stage 4.
• Output stage 4 produces an output voltage VOUT on conductor 5, which is connected to one terminal of a load 6.
• the other terminal of load 6 is connected to ground.
• a resistive voltage divider circuit including series-connected resistors RO and Rl is connected between VOUT and ground.
• the junction between resistors R0 and Rl is coupled by conductor 7 to the (+) input of error amplifier 2.
• Error amplifier 2 and output stage 4 are coupled between VDD and ground.
• the voltage regulation loop of DC-DC converter or LDO voltage regulator 1 includes output stage 4, error amplifier 2, voltage reference 3, and resistive voltage divider R0,R1.
• Resistive voltage divider R0,R1 sets the desired value of the DC output voltage V O UT, and allows the value of VOUT to be set to a level below, equal to, or above VREF.
• Resistors R0 and Rl usually are external resistors mounted on a printed circuit board along with an integrated circuit chip including the other components of DC-DC converter 1. External resistors R0 and Rl typically have values of no more than about 1 to 2 megohms, because of leakage currents in the printed circuit board.
• resistors R0 and Rl are formed on the integrated circuit chip, then they are expensive because of the large amount of chip area occupied by them. In either case, the power dissipation in the feedback resistor network R0,R1 is dominant if very low-power circuitry that is commonly referred to as "nanopower" circuitry is used to implement error amplifier 2 and output stage 4 in extremely low-power applications such as energy harvester systems.
• the typical several microampere current through resistor divider R0,R1 is a substantial or even major part of the overall current consumed by the DC-DC converter or LDO voltage regulator 1 and therefore substantially diminishes the efficiency of converter 1 at small load currents of a few microamperes or less.
• DC-DC converter as used herein is intended to encompass various kinds of DC-DC converters such as boost converters, buck converters, and buck/boost converters, and also is intended to encompass LDO voltage regulators.
• nonpower as used herein is intended to encompass circuits and/or circuit components which draw DC current of less than approximately 1 microampere.
• FIG. 6 shows a known low power error amplifier.
• an embodiment of the invention provides a converter (10) for converting a first DC voltage (VDD) to a second DC voltage (VOUT) includes an output stage (40) for producing the second DC voltage (V O UT) in response to both the first DC voltage (VDD) and an output of an error amplifier (20).
• a sampling circuit (15) periodically energizes a voltage divider (R0,R1) by periodically coupling a first terminal thereof to the second DC voltage and periodically couples an output (14) of the energized voltage divider to a feedback conductor (7) to refresh a first capacitor (CO) coupled between the second DC voltage and the feedback conductor.
• the feedback conductor (7) is coupled to an input of the error amplifier.
• the converter (10) is especially useful in nanopower energy harvester applications.
• the invention provides a DC-to-DC conversion circuit for converting a first DC voltage (VDD) to a second DC voltage (V O UT), including an error amplifier (20) having a first input (-) coupled to receive a first reference voltage (VREF) and an output stage (40) for producing the second DC voltage (V O UT) on an output conductor (5).
• the output stage (40) has a first input coupled to an output (2A) of the error amplifier (20) and a second input coupled receive the first DC voltage (VDD)-
• a first capacitor (CO) has a first terminal coupled to the output conductor (5) and a second terminal coupled by a feedback conductor (7) to a second input (+) of the error amplifier (20).
• a voltage divider (R0,R1) has a first terminal coupled to a second reference voltage (GND).
• a sampling circuit (15) includes a first sampling switch (SO) having a first terminal coupled to a second terminal of the voltage divider (R0,R1) and a second terminal coupled to the output conductor (5), and a second sampling switch (SI) having a first terminal coupled to the feedback conductor (7) and a second terminal coupled to an output (14) of the voltage divider (RO.Rl).
• a timing circuit (11) has a first output (12) coupled to a control terminal of the first sampling switch (SO) to periodically energize the voltage divider (R0,R1) and a second output (13) coupled to a control terminal of the second sampling switch (SI) to periodically refresh the first capacitor (CO) while the voltage divider (R0,R1) is energized, so as to reduce average power consumption in the voltage divider.
• a second capacitor (CI) is coupled between the feedback conductor (7) and the second reference voltage (GND).
• the voltage divider includes a first resistor (RO) having a first terminal coupled to the first terminal of the first sampling switch (SO) and a second terminal coupled to the output (14) of the voltage divider, and a second resistor (Rl) having a first terminal coupled to the output (14) of the voltage divider and a second terminal coupled to the second reference voltage (GND).
• the second capacitor (CI) has a capacitance equal to a capacitance (CO) of the first capacitor multiplied by the ratio of a resistance (RO) of the first resistor divided by a resistance (Rl) of the second resistor.
• the first sampling switch (SO) includes a first transistor (M0), wherein the first, second, and control terminals of the first sampling switch (SO) are first and second current carrying electrodes and a control electrode, respectively, of the first transistor (MO), and wherein the second sampling switch (SI) includes a second transistor (Ml), wherein the first, second, and control terminals of the second sampling switch (SI) are first and second current carrying electrodes and a control electrode, respectively, of the second transistor (Ml).
• the output stage (40) includes low drop out voltage regulator circuitry.
• the output stage (40) includes a buck/boost converter (22) having an input coupled to the first DC voltage (VDD), a control input coupled to the output (2 A) of the error amplifier (20), and an output coupled to the output conductor (5).
• the output stage (40) includes a transistor (M2 in FIG. 5A) having a source coupled to the first DC voltage (VDD), a gate coupled to the output (2 A) of the error amplifier (20), and a drain coupled to the output conductor (5).
• the first DC voltage (VDD) is a harvested voltage from an energy harvesting device.
• the timing circuit ( 1 1) energizes the voltage divider (R0,R1) for at least an amount of time sufficient to allow the first capacitor (CO) to recover charge loss due to parasitic leakage current while the second switch (SI) is open. In one embodiment, the timing circuit ( 1 1) energizes the voltage divider (R0,R1) at least approximately once per second.
• the timing circuit (1 1) includes an oscillator ( 17) coupled to drive a frequency divider (18) and a decode circuit (20) for decoding various outputs of the frequency divider ( 18) so as to generate signals on the first (12) and second ( 13) outputs of the timing circuit (1 1).
• the error amplifier (20) is a transconductance amplifier.
• the invention provides a method for decreasing power consumption of a converter ( 10) for converting a first DC voltage (VDD) to a second DC voltage (V O UT) including coupling a first input (-) of an error amplifier (20) of the converter (10) to receive a first reference voltage (VREF) and coupling an output (2A) of the error amplifier (20) to an input of an output stage (40) of the converter ( 10), the converter (10) having a second input coupled receive the first DC voltage (VDD), to produce the second DC voltage (VOUT) on an output (5) of the converter ( 10); and periodically energizing a voltage divider (R0,R1) by periodically coupling a first terminal thereof to the second DC voltage (VOUT) and periodically coupling an output ( 14) of the energized voltage divider (R0.R1) to refresh a first capacitor (CO) coupled between the second DC voltage (VOUT) and a feedback conductor (7) coupled to a second input (+) of the error amplifier (20).
• a voltage divider R0,R
• this includes periodically closing a first sampling switch (SO) to energize the voltage divider (R0,R1) from the output conductor (5) and closing a second sampling switch (SI) to couple the output ( 14) of the energized voltage divider (R0,R1) to the feedback conductor (7) for a sufficient amount of time to ensure that the voltage across the first capacitor (CO) has recovered from any parasitic leakage of charge from the first capacitor (CO) that may occur while the voltage divider (R0,R1) is not energized.
• SO first sampling switch
• SI second sampling switch
• the method includes ensuring stability of the error amplifier
• the invention provides circuitry for decreasing power consumption of a converter (10) for converting a first DC voltage (VDD) to a second DC voltage (VOUTX including means (40) for producing the second DC voltage (VOUT) on an output (5) of the converter (10) in response to an output of an error amplifier (20) and in response to the first DC voltage (VDD); and means (15) for periodically energizing a voltage divider (R0,R1) by periodically coupling a first terminal thereof to the second DC voltage (VOUT) by coupling an output (14) of the energized voltage divider (R0,R1) to a feedback conductor (7) to refresh a first capacitor (CO) coupled between the second DC voltage (VOUT) and the feedback conductor (7), the feedback conductor (7) being coupled to an input of the error amplifier (20).
• FIG. 1 is a schematic drawing of a conventional DC-DC converter or LDO voltage regulator.
• FIG. 2 is a schematic diagram of a very low power implementation of the DC-DC converter or LDO voltage regulator of FIG. 1.
• FIG. 3 includes a schematic diagram of circuit 15 in FIG. 2.
• FIG. 4 is a block diagram of a conventional implementation of timing circuit 11 in
• FIGS. 5A and 5B are block diagrams of implementations of output circuit 40 in
• FIG. 6 is a schematic diagram of a very low power implementation of error amplifier 20 in FIG. 2.
• the problem of high power consumption in the converter 1 of FIG. 1 is solved by removing resistive voltage divider R0, Rl from the feedback loop of converter 1 and instead providing either a feedback capacitor CO alone or by providing capacitive feedback voltage divider CO, CI as shown in DC-DC converter 10 of FIG. 2.
• the resistive voltage divider R0,R 1 is periodically energized to substantially reduce its average power consumption, and an output of the energized resistive voltage divider R0,R1 is sampled long enough to refresh the feedback capacitor CO or capacitive feedback voltage divider CO, CI by replacing any DC charge lost therefrom due to parasitic currents.
• DC-DC converter 10 in FIG. 2 may be a conventional DC-DC converter or a
• LDO voltage regulator includes a nanopower voltage reference circuit 3 which applies a reference voltage VREF to the (-) input of a nanopower error amplifier 20.
• a nanopower voltage reference circuit 3 which applies a reference voltage VREF to the (-) input of a nanopower error amplifier 20.
• Various very low- power, i.e., nanopower, known implementations of bandgap reference circuit (for which VREF which is approximately 1.2 volts) or a reverse bandgap reference circuit (for which VREF is approximately 200 millivolts) can be used.
• the output 2A of error amplifier 20 is connected to the input of a nanopower output stage 40.
• Output stage 40 produces output voltage VOUT on conductor 5, which is connected to one terminal of load 6.
• the other terminal of load 6 is connected to ground.
• Various implementations of error amplifier 20 may be used, such as the one shown in FIG. 6.
• Feedback capacitor CO is coupled between output conductor 5 and feedback conductor 7.
• An optional capacitor CI is connected between feedback conductor 7 and ground so that capacitors CO and CI form a capacitive feedback voltage divider between VOUT and the (+) input of error amplifier 20.
• Error amplifier 20 and output stage 40 are coupled between VDD and ground.
• a resistive voltage divider circuit including series-connected resistors R0 and l has one terminal connected to ground and another terminal coupled to a first terminal of a first sampling switch SO.
• Sampling switch SO has a second terminal coupled to VOUT and a control terminal coupled by conductor 12 to the output of a timing circuit 11.
• the junction 14 between resistors R0 and Rl is the output of resistive divider R0,R1 and is coupled to a first terminal of a second sampling switch SI having a second terminal connected to feedback conductor 7.
• the control terminal of sampling switch SI is coupled by conductor 13 to another output of timing circuit 11.
• Feedback conductor 7 is coupled to the (+) input of error amplifier 20.
• Sampling switches SO and SI and timing circuit 11 are included in a sampling circuit 15. If capacitor CI is utilized, it preferably has a capacitance equal to CO x (R0/R1).
• resistive divider R0, Rl is periodically energized from V O UT through sampling switch SO, which is controlled by a first sampling signal generated on conductor 12 by timing circuit 11.
• the amount of DC charge in feedback capacitor CO is periodically refreshed from output conductor 14 of resistive voltage divider R0, Rl through sampling switch SI in response to a second sampling signal generated on conductor 13 by timing circuit 11.
• This periodic refreshing of feedback capacitor CO is necessary because parasitic leakage currents may significantly diminish the voltage across feedback capacitor CO.
• the refresh interval during which sampling switch SI is on typically would be a few microseconds and must occur at least approximately every second by turning on sampling switch SO while resistive voltage divider R0,R1 is energized.
• Timing circuit 11 determines the duration and period of each energizing of resistive voltage divider RO, Rl and the duration of each sampling of the output voltage on conductor 14 of the energized resistive divider RO, Rl.
• capacitive divider CO, CI performs essentially the same feedback function as resistive divider RO, Rl in FIG. 1, and further helps ensure stability of error amplifier 20 in FIG. 2.
• the invention replaces the power-consuming resistive feedback network of FIG. 1 with a capacitive feedback circuit that is periodically refreshed by sampling a periodically energized resistive divider circuit, as shown in FIG. 2.
• a voltage is sampled across the capacitor CO from the output 14 of resistive voltage divider network R0, Rl via switch SI and feedback conductor 7.
• Capacitor CO stores a voltage equal to the difference between reference voltage V EF and Vout.
• an advantage to using both of capacitors CI and CO is that it provides error amplifier 20 with a gain of roughly 2 rather than the unity gain that occurs if only feedback capacitor CO is used. This results in the above mentioned improved stability of error amplifier 20.
• FIG. 3 shows one implementation of sampling circuit 15, wherein timing circuit
• FIG. 2 applies "energize” pulses via conductor 12 to the gate of P-channel transistor M0, which is utilized as switch SO.
• the source of transistor M0 is connected to output conductor 5, and the drain of transistor M0 is connected to the upper terminal of divider resistors R0.
• the durations of the "energize” pulses on conductor 12 is sufficient to energize resistive divider R0, Rl at least long enough to allow refreshing of capacitor CO, and also of capacitor CI if it is utilized.
• Timing circuit 11 also applies to "refresh” pulses via conductor 13 to the gate of P- channel transistor Ml, which is utilized as switch SI, while resistive divider R0, Rl is energized.
• Each "refresh” pulse turns transistor Ml on for an amount of time sufficient to refresh feedback capacitor CO.
• the period of the pulses on conductors 12 and 13 is at least long enough to ensure that parasitic currents do not diminish the voltage across feedback capacitor CO more than a predetermined amount.
• FIG. 4 shows a conventional implementation of timer 11 in FIG. 2, including a conventional clock oscillator 17, the output of which derives a conventional frequency divider 18 including a chain of flip-flops.
• Various taps 19 of frequency divider 18 are decoded by decode and control circuit 20 to generate the above described switch control signals on conductors 12 and 13.
• FIGS. 5 A and 5B show two implementations of output circuit 40 in FIG.
• Output circuit 40 as shown in FIG. 5A includes a P-channel transistor M2 having its source coupled to VDD, its gate connected to the output 2A of error amplifier 20, and its drain connected to VOUT conductor 5.
• Output circuit 40 as shown in FIG. 5B includes a conventional buck/boost converter 22 having its input terminal coupled to VDD, its control input coupled to output 2A of error amplifier 20, and its output connected to VOUT conductor 5.
• FIG. 6 shows an implementation of previously mentioned low power error amplifier 20 in FIG. 2.
• Error amplifier 20 as shown in FIG. 6 is implemented as a nanopower class AB transconductance error amplifier. It should be appreciated that one of the most important parameters of a low power or nanopower DC-DC converter is its no-load quiescent current, which usually is dominated by the error amplifier therein.
• the bandwidth of the error amplifier needs to be larger than the bandwidth of the DC-DC converter, and is roughly proportional to the quiescent current of the error amplifier.
• the gain of the error amplifier determines the frequency stability of the DC-DC converter and should be kept stable within 5 to 10%.
• the offset of the error amplifier determines the accuracy of the DC-DC converter and should be as low as possible, ideally below 1 millivolt.
• the currents of transistors M0 and Ml are equal to the currents 12 and 13, respectively, as long as there is a gain greater than 1 in the feedback loop including transistors M0 and Ml in FIG. 6 and the feedback loop including transistors Ml and M5.
• the current II should be equal to 13
• the current 10 is delivered by feedback loop M6-M7-M8-M9, just enough to keep the circuit operational and provide the current through transistor M4 and the current through transistor M5 both equal to the current lout produced by error amplifier 20 in conductor 2A.
• the quiescent current Iq of error amplifier 20 is approximately equal to 12 + 13.
• the values of 12 and 13 determine the bandwidth of the feedback loops Ml, M5 and M0-M6-M7-M8-M9 and should be chosen according to the required bandwidth of error amplifier 20. Simulations indicate that the quiescent current Iq is equal to approximately 1 microampere per 100 kHz of bandwidth for a CMOS manufacturing process having a 0.35 micron minimum channel length. The accuracy and offset of amplifier 20 is improved by keeping the drain voltages of transistors M0 and Ml in FIG. 6 equal.
• the invention solves the above mentioned problem of the prior art by utilizing a capacitive feedback network that is periodically refreshed by sampling a voltage representative of the DC output voltage from a resistive voltage divider that itself is periodically energized. This substantially reduces the average current and power consumption of the resistive voltage divider and therefore allows a practical implementation of an extremely low power DC- DC converter that is useful in energy harvesting applications.

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• 2010
  • 2010-01-22 US US12/657,543 patent/US8222881B2/en active Active
  • 2010-12-23 CN CN201080065703.2A patent/CN102822760B/zh active Active
  • 2010-12-23 JP JP2012549999A patent/JP5864438B2/ja active Active
  • 2010-12-23 WO PCT/US2010/062035 patent/WO2011090687A2/en not_active Ceased

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