WO2011083667A1 - Method and apparatus for processing compound semiconductor wafer - Google Patents

Method and apparatus for processing compound semiconductor wafer Download PDF

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Publication number
WO2011083667A1
WO2011083667A1 PCT/JP2010/072602 JP2010072602W WO2011083667A1 WO 2011083667 A1 WO2011083667 A1 WO 2011083667A1 JP 2010072602 W JP2010072602 W JP 2010072602W WO 2011083667 A1 WO2011083667 A1 WO 2011083667A1
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Prior art keywords
semiconductor wafer
surface plate
compound semiconductor
wafer
soft material
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PCT/JP2010/072602
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French (fr)
Japanese (ja)
Inventor
義雄 目崎
哲弥 山崎
隆幸 西浦
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住友電気工業株式会社
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Priority to CN2010800606149A priority Critical patent/CN102696096A/en
Priority to JP2011548939A priority patent/JPWO2011083667A1/en
Publication of WO2011083667A1 publication Critical patent/WO2011083667A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/24—Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/26—Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved

Definitions

  • the present invention relates to a processing method and a processing apparatus for lapping both sides of a compound semiconductor wafer.
  • this compound semiconductor wafer was sandwiched between upper and lower surface plates and simultaneously lapped on both sides.
  • set the compound semiconductor wafer on the lower surface plate using a jig lower the upper surface plate and press it against the compound semiconductor wafer, and wrap using an abrasive while applying an appropriate load.
  • the cleaved surface portion is chamfered, the cleaved surface portion is not accurate in optical alignment using a microscope at the time of pattern exposure.
  • the surface plate hits an edge in an acute angle state, there is a problem that the corner is chipped with a considerable probability, and in some cases, the wafer is broken from the chipped portion.
  • Patent Document 2 discloses a method in which the upper surface plate is lowered to some extent and then the lower surface plate is finely raised to place the wafer. By this method, the incidence of cracking defects was reduced to about half that of the prior art, but the cracking defects were not completely eliminated.
  • Patent Document 3 discloses a technique for preventing the cracking of the wafer by providing a large number of grooves having a V-shaped cross section on the surface plate, but it still does not completely eliminate the cracking defect.
  • JP 2002-367940 A JP 04-258119 A Japanese Patent Application Laid-Open No. 06-015561
  • the present invention is to provide a processing method capable of eliminating wafer chipping and cracking defects during lapping of a compound semiconductor wafer.
  • An embodiment of the present invention is a method for lapping both surfaces of a compound semiconductor wafer, including a step of lapping by placing the semiconductor wafer between an upper surface plate and a lower surface plate,
  • the present invention relates to a compound semiconductor wafer processing method, characterized in that a soft material is attached to a wafer side surface.
  • the soft material has a thickness of 0.5 mm to 5 mm and an Asker C hardness of 40 to 90.
  • a groove is formed on the wafer-side surface of the soft material.
  • the groove has a width of 1 mm or more and 5 mm or less.
  • Another embodiment of the present invention is a processing apparatus that includes an upper surface plate and a lower surface plate, a semiconductor wafer is disposed between the upper surface plate and the lower surface plate, and the both surfaces thereof are lapped.
  • the present invention relates to a processing apparatus in which a soft material is attached to a surface of the surface plate on the wafer side.
  • the soft material has a thickness of 0.5 mm to 5 mm and an Asker C hardness of 40 to 90.
  • a groove is formed on the wafer-side surface of the soft material.
  • the groove has a width of 1 mm or more and 5 mm or less.
  • the compound semiconductor wafer processing method of the present invention is a method of lapping both surfaces of a compound semiconductor wafer, including a step of lapping the semiconductor wafer by placing the semiconductor wafer between an upper surface plate and a lower surface plate, A soft material is attached to the surface of the surface plate on the wafer side.
  • the compound semiconductor wafer processing apparatus of the present invention is used in the processing method of the present invention.
  • FIG. 1 is a processing apparatus for lapping both surfaces of a compound semiconductor wafer.
  • the semiconductor wafer 4 is placed between the upper surface plate 1 and the lower surface plate 2 and lapping is performed.
  • a soft material 3 is attached to the surface of the upper surface plate 1 on the wafer side.
  • the soft material 3 examples include a nonwoven fabric impregnated with a urethane resin, ultrahigh molecular weight polyethylene, urethane foam, and silicon rubber. These are preferably processed to the same size as the upper surface plate 1 and attached to the entire surface of the upper surface plate.
  • the method of attaching is not particularly limited, but may be attached with a double-sided tape or directly with an adhesive.
  • the thickness of the soft material 3 is preferably 0.5 mm or more and 5 mm or less. If it is less than 0.5 mm, the effect of the soft material may not be obtained and the wafer may be broken. If it exceeds 5 mm, the amount of sinking of the wafer into the soft material increases, and the sagging (roll-off) of the wafer edge portion becomes too large.
  • the Asker C hardness of the soft material 3 is preferably 40 or more and 90 or less. If the Asker C hardness is less than 40, roll-off occurs, which may cause a defect during pattern exposure due to surface fringing. If the Asker C hardness exceeds 90, the effect of reducing chipping at the edge portion is reduced. Is also not preferred.
  • a groove in the soft material 3 it is preferable to form a groove in the soft material 3 on the side that comes into contact with the wafer during lapping. It is preferable to provide a large number of grooves in a lattice shape.
  • the groove improves the flow of the polishing liquid and enables smooth polishing. Further, when the groove is formed, it is possible to prevent the wafer from being lifted together with the upper surface plate when the upper surface plate 1 is raised after the polishing process is completed. When there is no groove, the polishing liquid flows poorly, so that the polishing time becomes long but polishing is possible. Further, when there is no groove, the semiconductor wafer may be lifted together with the upper surface plate, so that it is necessary to carefully raise the upper surface plate after the polishing.
  • the width of the groove is preferably 1 mm or more and 5 mm or less. If the thickness is less than 1 mm, the wafer may be lifted together with the upper surface plate when the upper surface plate is raised after the polishing process is completed. If the thickness exceeds 5 mm, unevenness is exerted on the pressure applied to the wafer, so that wafer accuracy such as thickness variation (TTV: Totol Thickness Variation) and local flatness (LTV: Local Thickness Variation) deteriorates.
  • TTV Totol Thickness Variation
  • LTV Local Thickness Variation
  • the spacing (pitch) between the ridge grooves is preferably 10 mm or more and 50 mm or less. If it is less than 10 mm or exceeds 50 mm, the wafer is lifted together with the upper surface plate when the upper surface plate is raised after the polishing process is completed, which is not preferable.
  • the depth of the groove is preferably 0.1 to 1.0 mm. If it is less than 0.1 mm, the wafer is lifted together with the upper surface plate, and if it exceeds 1.0 mm, the polishing liquid that has entered the groove tends to solidify.
  • the upper surface plate 1 is not particularly limited, but is preferably manufactured from cast iron, SUS (stainless steel), or the like. Of these, SUS (stainless steel) is particularly desirable.
  • the lower surface plate 2 does not attach a soft material.
  • the surface of the compound semiconductor wafer is polished by the lower surface plate 2 so as to have a desired surface roughness to obtain a finished surface.
  • the lower surface plate 2 is preferably manufactured from glass, tin or the like, but is not particularly limited.
  • the upper limit of the hardness of the lower surface plate 2 is the hardness of the compound semiconductor wafer to be polished, for example, Vickers hardness Hv750 for GaAs and Hv450 for InP.
  • the lower limit is preferably Hv220. If the hardness of the lower surface plate is too hard, fine scratches are likely to enter the surface of the compound semiconductor wafer. On the other hand, if it is too soft, the lower surface plate is worn quickly during polishing, leading to deterioration in wafer accuracy.
  • the compound semiconductor wafer 4 is not particularly limited, but is, for example, GaAs, InP, or GaN.
  • a jig 5 is arranged on the lower surface plate 2 so as to sandwich or surround the compound semiconductor wafer 4.
  • This jig has a gear on the outer peripheral portion so that the compound semiconductor wafer 4 moves with respect to the surface plate.
  • the soft material 3 is attached to the upper surface plate 1.
  • the soft material 3 include a nonwoven fabric impregnated with a urethane resin, ultrahigh molecular weight polyethylene, urethane foam, and silicon rubber. These are preferably processed to the same size as the upper surface plate 1 and attached to the entire surface of the upper surface plate 1.
  • the method of attaching is not particularly limited, but may be attached with a double-sided tape or directly with an adhesive.
  • the lower surface plate 2 and the upper surface plate 1 to which the soft material 3 is attached are attached to a processing device (polishing device).
  • the lower surface plate 2 and the upper surface plate 1 (soft material 3) may be shaved and flattened using a flat jig (not shown) (correction work).
  • the semiconductor wafer 4 and the jig 5 are arranged on the lower surface plate 2.
  • the compound semiconductor wafer 4 for double-sided processing should just be prepared by this stage at least.
  • the compound semiconductor wafer 4 is not specifically limited, For example, compound semiconductors, such as GaAs, InP, and GaN, are mentioned.
  • the jig 5 is arranged on the lower surface plate 2 so as to sandwich or surround the compound semiconductor wafer 4.
  • the jig 5 is provided with a gear at the outer peripheral portion so that the compound semiconductor wafer 4 moves with respect to the surface plate.
  • the polishing condition may be, for example, a platen rotation speed of 10 to 50 rpm with a load of about 50 g / cm 2 per wafer unit area.
  • a soft material was affixed to the upper surface plate with double-sided tape.
  • the soft material was a non-woven fabric with Asker C hardness of 72, and the thickness was 1.5 mm.
  • this nonwoven fabric grooves having a pitch of 10 mm, a width of 3 mm, and a depth of 0.5 mm were provided in a lattice shape.
  • the upper surface plate was attached to an existing polishing machine, and the compound semiconductor wafer was polished.
  • a compound semiconductor is manufactured by a VB method, and contains a GaAs crystal containing 5 ⁇ 10 17 to 3 ⁇ 10 18 atoms / cc of Si as a dopant and having an in-plane average value of crystal defects EPD of 500 / cm 2 or less.
  • a wafer obtained by slicing at (100) 15 ° off ⁇ 111> ⁇ 0.1 ° and cleaving the (0-1-1) plane of the wafer and chamfering the outer periphery of the wafer other than the cleaved surface was used.
  • the lower surface plate was made of borosilicate glass having a hardness of Hv450 and slits of 10 cm square. 300 wafers were polished, but no chipping or cracking occurred.
  • a compound semiconductor wafer was polished using an upper surface plate to which no soft material was attached. After 300 sheets were polished, 2% chipping and cracking occurred.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

Disclosed is a polishing method whereby chipping and breaking failures of a compound semiconductor wafer can be reduced. The method for polishing the compound semiconductor wafer, i.e., a method for lapping both the surfaces of the compound semiconductor wafer, includes a step of lapping the semiconductor wafer by disposing the semiconductor wafer between the upper platen and the lower platen, and a soft material is adhered on the upper platen surface on the wafer side. The processing apparatus includes the upper platen and the lower platen, and laps both the surfaces of the semiconductor wafer by having the semiconductor wafer disposed between the upper platen and the lower platen, and the processing apparatus has the soft material adhered on the upper platen surface on the wafer side.

Description

化合物半導体ウェハの加工方法及び加工装置Compound semiconductor wafer processing method and processing apparatus
  本発明は、化合物半導体ウェハを両面ラッピングする加工方法及び加工装置に関するものである。 The present invention relates to a processing method and a processing apparatus for lapping both sides of a compound semiconductor wafer.
  レーザーダイオード等を製作する化合物半導体ウェハでは、従来よりウェハの円周部の一部を直線に劈開し、正確な結晶面を出しておき、その後のデバイスプロセスでのパターン露光時のアライメントをその劈開面を基準とされる。これにより、レーザー素子端面（劈開面）とレーザー光路（パターン露光で作成）との、角度のズレを最小限に抑えることで、レーザー光の出力バラツキの抑制並びに素子の歩留りの向上が図られてきた（特許文献１）。 In compound semiconductor wafers for manufacturing laser diodes, etc., conventionally, a part of the wafer's circumference is cleaved in a straight line to produce an accurate crystal plane, and the alignment during pattern exposure in subsequent device processes is cleaved. The plane is the reference. As a result, the laser output variation and the element yield can be improved by minimizing the angle deviation between the laser element end face (cleavage face) and the laser optical path (created by pattern exposure). (Patent Document 1).
  この化合物半導体ウェハは、研磨工程において、上下の定盤に挟み込んで両面同時にラッピングする加工方法が採られていた。すなわち、下定盤の上に必要に応じて治具を用いて化合物半導体ウェハをセットし、上定盤を下降させて化合物半導体ウェハに押し当てて、適当な荷重をかけながら研磨剤を用いてラッピング加工を行っていた。 加工 In this polishing process, this compound semiconductor wafer was sandwiched between upper and lower surface plates and simultaneously lapped on both sides. In other words, if necessary, set the compound semiconductor wafer on the lower surface plate using a jig, lower the upper surface plate and press it against the compound semiconductor wafer, and wrap using an abrasive while applying an appropriate load. We were processing.
  ところが、上定盤を化合物半導体ウェハに押し当てた（着盤）時、化合物半導体ウェハが欠けたり割れたりする問題があった。特に、劈開面の部分は、面取り加工を行うと、パターン露光時に、顕微鏡を用いた光学的なアライメントでの精度がでないため、なるべく鋭角な状態でのエッジ（角）が望まれる。しかし、鋭角な状態のエッジに定盤が当ると、かなりの確率で角が欠け、場合によってはその欠け部分からウェハが割れてしまうという問題があった。 However, when the upper surface plate is pressed against the compound semiconductor wafer (landing), there is a problem that the compound semiconductor wafer is chipped or broken. In particular, when the cleaved surface portion is chamfered, the cleaved surface portion is not accurate in optical alignment using a microscope at the time of pattern exposure. However, when the surface plate hits an edge in an acute angle state, there is a problem that the corner is chipped with a considerable probability, and in some cases, the wafer is broken from the chipped portion.
  そこで、特許文献２では、上定盤をある程度下降させた後、下定盤を微細に上昇させてウェハを着盤させる方法が開示されている。この方法により、割れ不良の発生率が従来の半分程度に減少したが、割れ不良が完全になくなってはいない。 Therefore, Patent Document 2 discloses a method in which the upper surface plate is lowered to some extent and then the lower surface plate is finely raised to place the wafer. By this method, the incidence of cracking defects was reduced to about half that of the prior art, but the cracking defects were not completely eliminated.
  また、特許文献３では、定盤に断面形状Ｖ字状である溝を多数設けることにより、ウェハの割れを防止する技術が開示されているが、やはり割れ不良を完全になくすには至っていない。 In addition, Patent Document 3 discloses a technique for preventing the cracking of the wafer by providing a large number of grooves having a V-shaped cross section on the surface plate, but it still does not completely eliminate the cracking defect.
特開２００２－３６７９４０号公報JP 2002-367940 A 特開平０４－２５８１１９号公報JP 04-258119 A 特開平０６－０１５５６１号公報Japanese Patent Application Laid-Open No. 06-015561
  本発明は、化合物半導体ウェハのラッピング加工時のウェハの欠け、割れ不良をなくすことができる加工方法を提供することである。 The present invention is to provide a processing method capable of eliminating wafer chipping and cracking defects during lapping of a compound semiconductor wafer.
  本発明の実施形態は、化合物半導体ウェハの両面をラッピング加工する方法であって、上定盤と下定盤の間に前記半導体ウェハを配置してラッピング加工する工程を含み、前記上定盤の前記ウェハ側の面に軟質材が貼り付けられていることを特徴とする化合物半導体ウェハの加工方法に関する。 An embodiment of the present invention is a method for lapping both surfaces of a compound semiconductor wafer, including a step of lapping by placing the semiconductor wafer between an upper surface plate and a lower surface plate, The present invention relates to a compound semiconductor wafer processing method, characterized in that a soft material is attached to a wafer side surface.
  本発明の加工方法の他の実施形態では、前記軟質材が、厚さ０．５ｍｍ以上５ｍｍ以下であり、且つ、ＡｓｋｅｒＣ硬度４０以上９０以下である。 In another embodiment of the processing method of the present invention, the soft material has a thickness of 0.5 mm to 5 mm and an Asker C hardness of 40 to 90.
　本発明の加工方法の他の実施形態では、前記軟質材の前記ウェハ側の面に溝が形成されている。 In another embodiment of the processing method of the present invention, a groove is formed on the wafer-side surface of the soft material.
  本発明の加工方法の他の実施形態では、前記溝が幅１ｍｍ以上５ｍｍ以下である。 In another embodiment of the processing method of the present invention, the groove has a width of 1 mm or more and 5 mm or less.
　本発明の他の実施形態は、上定盤と下定盤を含み、前記上定盤と下定盤の間に半導体ウェハを配置してその両面をラッピング加工するための加工装置であって、前記上定盤の前記ウェハ側の面に軟質材が貼り付けられていることを特徴とする加工装置に関する。 Another embodiment of the present invention is a processing apparatus that includes an upper surface plate and a lower surface plate, a semiconductor wafer is disposed between the upper surface plate and the lower surface plate, and the both surfaces thereof are lapped. The present invention relates to a processing apparatus in which a soft material is attached to a surface of the surface plate on the wafer side.
  本発明の加工装置の他の実施形態では、前記軟質材が、厚さ０．５ｍｍ以上５ｍｍ以下であり、且つ、ＡｓｋｅｒＣ硬度４０以上９０以下である。 In another embodiment of the processing apparatus of the present invention, the soft material has a thickness of 0.5 mm to 5 mm and an Asker C hardness of 40 to 90.
  本発明の加工装置の他の実施形態では、前記軟質材の前記ウェハ側の面に溝が形成されている。 In another embodiment of the processing apparatus of the present invention, a groove is formed on the wafer-side surface of the soft material.
  本発明の加工装置の他の実施形態では、前記溝が幅１ｍｍ以上５ｍｍ以下である。 In another embodiment of the processing apparatus of the present invention, the groove has a width of 1 mm or more and 5 mm or less.
  本発明によれば、化合物半導体ウェハのラッピング加工時のウェハの割れ不良をなくすことができる。 れ ば According to the present invention, it is possible to eliminate wafer cracking failure during lapping of a compound semiconductor wafer.
本発明の化合物半導体ウェハの加工装置の断面模式図である。It is a cross-sectional schematic diagram of the processing apparatus of the compound semiconductor wafer of this invention.
  本発明の化合物半導体ウェハの加工方法は、化合物半導体ウェハの両面をラッピング加工する方法であって、上定盤と下定盤の間に前記半導体ウェハを配置してラッピング加工する工程を含み、前記上定盤の前記ウェハ側の面に軟質材が貼り付けられていることを特徴とする。本発明の化合物半導体ウェハの加工装置は、本発明の加工方法に用いられる。 The compound semiconductor wafer processing method of the present invention is a method of lapping both surfaces of a compound semiconductor wafer, including a step of lapping the semiconductor wafer by placing the semiconductor wafer between an upper surface plate and a lower surface plate, A soft material is attached to the surface of the surface plate on the wafer side. The compound semiconductor wafer processing apparatus of the present invention is used in the processing method of the present invention.
　まず、図１を参照して、本発明の化合物半導体ウェハの加工装置について説明する。
　図１は、化合物半導体ウェハの両面をラッピング加工する加工装置である。上定盤１と下定盤２の間に前記半導体ウェハ４を配置してラッピング加工される。前記上定盤１の前記ウェハ側の面に軟質材３が貼り付けられている。 First, the compound semiconductor wafer processing apparatus of the present invention will be described with reference to FIG.
FIG. 1 is a processing apparatus for lapping both surfaces of a compound semiconductor wafer. The semiconductor wafer 4 is placed between the upper surface plate 1 and the lower surface plate 2 and lapping is performed. A soft material 3 is attached to the surface of the upper surface plate 1 on the wafer side.
  軟質材３としては、ウレタン樹脂を含浸させた不織布、超高分子ポリエチレン、発泡ウレタン、シリコンゴム等を挙げることができる。これらを、好ましくは上定盤１と同じ大きさに加工して、上定盤の全面に貼り付けられる。貼り付ける方法は特に限定されないが、両面テープで貼り付けてもよいし、接着剤で直接貼り付けてもよい。
　軟質材３の厚さは、０．５ｍｍ以上、５ｍｍ以下とすることが好ましい。０．５ｍｍ未満であると、軟質材の効果がなくウェハが割れることがある。５ｍｍを超えると、ウェハの軟質材への沈み込み量が大きくなり、ウェハエッジ部のダレ（ロールオフ）が大きくなりすぎる。 Examples of the soft material 3 include a nonwoven fabric impregnated with a urethane resin, ultrahigh molecular weight polyethylene, urethane foam, and silicon rubber. These are preferably processed to the same size as the upper surface plate 1 and attached to the entire surface of the upper surface plate. The method of attaching is not particularly limited, but may be attached with a double-sided tape or directly with an adhesive.
The thickness of the soft material 3 is preferably 0.5 mm or more and 5 mm or less. If it is less than 0.5 mm, the effect of the soft material may not be obtained and the wafer may be broken. If it exceeds 5 mm, the amount of sinking of the wafer into the soft material increases, and the sagging (roll-off) of the wafer edge portion becomes too large.
  軟質材３のＡｓｋｅｒＣ硬度は、好ましくは４０以上９０以下である。ＡｓｋｅｒＣ硬度４０未満の場合は、ロールオフが発生し、その面だれによりパターン露光時の不良の原因となり、ＡｓｋｅｒＣ硬度が９０を超える場合は、エッジ部の欠け低減の効果がおちるため、いずれの場合も好ましくない。 The Asker C hardness of the soft material 3 is preferably 40 or more and 90 or less. If the Asker C hardness is less than 40, roll-off occurs, which may cause a defect during pattern exposure due to surface fringing. If the Asker C hardness exceeds 90, the effect of reducing chipping at the edge portion is reduced. Is also not preferred.
  軟質材３には、ラッピング加工時にウェハと当接する側に、溝を形成することが好ましい。溝は、格子状に多数設けることが好ましい。溝により、研磨液の流れを良くして、研磨加工を円滑に行えるようになる。また、溝を形成すると、研磨加工終了後に、上定盤１を上昇させたときに、ウェハが上定盤と一緒に持ち上がることを防止することができる。溝がない場合は、研磨液の流れが悪いので、研磨時間が長くなるが研磨は可能である。また、溝がない場合は、半導体ウェハが上定盤とともに持ち上がる可能性があるため研磨終了後に慎重に上定盤を上昇させる必要がある。 It is preferable to form a groove in the soft material 3 on the side that comes into contact with the wafer during lapping. It is preferable to provide a large number of grooves in a lattice shape. The groove improves the flow of the polishing liquid and enables smooth polishing. Further, when the groove is formed, it is possible to prevent the wafer from being lifted together with the upper surface plate when the upper surface plate 1 is raised after the polishing process is completed. When there is no groove, the polishing liquid flows poorly, so that the polishing time becomes long but polishing is possible. Further, when there is no groove, the semiconductor wafer may be lifted together with the upper surface plate, so that it is necessary to carefully raise the upper surface plate after the polishing.
  溝の幅は、１ｍｍ以上、５ｍｍ以下が好ましい。１ｍｍ未満であると、研磨加工終了後、上定盤を上昇させた時に、ウェハが上定盤と一緒に持ち上がる可能性がある。５ｍｍを超えるとウェハへの加圧力にムラがでるため、厚さばらつき（ＴＴＶ：Totol Thickness Variation）や局所の平坦度（ＬＴＶ：Local Thickness Ｖariation）等のウェハ精度が悪化する。 The width of the groove is preferably 1 mm or more and 5 mm or less. If the thickness is less than 1 mm, the wafer may be lifted together with the upper surface plate when the upper surface plate is raised after the polishing process is completed. If the thickness exceeds 5 mm, unevenness is exerted on the pressure applied to the wafer, so that wafer accuracy such as thickness variation (TTV: Totol Thickness Variation) and local flatness (LTV: Local Thickness Variation) deteriorates.
  溝と溝の間隔（ピッチ）は、１０ｍｍ以上、５０ｍｍ以下が好ましい。１０ｍｍ未満、あるいは５０ｍｍを超えると、研磨加工終了後、上定盤を上昇させた時に、ウェハが上定盤と一緒に持ち上がるので好ましくない。 The spacing (pitch) between the ridge grooves is preferably 10 mm or more and 50 mm or less. If it is less than 10 mm or exceeds 50 mm, the wafer is lifted together with the upper surface plate when the upper surface plate is raised after the polishing process is completed, which is not preferable.
　溝の深さは、好ましくは０．１～１．０ｍｍである。０．１ｍｍ未満の場合、ウェハが上定盤と一緒に持ち上がり、１．０ｍｍを超える場合は溝内部に侵入した研磨液が固化しやすいため、いずれの場合も好ましくない。 The depth of the groove is preferably 0.1 to 1.0 mm. If it is less than 0.1 mm, the wafer is lifted together with the upper surface plate, and if it exceeds 1.0 mm, the polishing liquid that has entered the groove tends to solidify.
　上定盤１は、特に限定されないが、好ましくは鋳鉄、ＳＵＳ（ステンレス鋼）等から製造される。このうち、特に、ＳＵＳ（ステンレス鋼）が望ましい。 The upper surface plate 1 is not particularly limited, but is preferably manufactured from cast iron, SUS (stainless steel), or the like. Of these, SUS (stainless steel) is particularly desirable.
  下定盤２は、軟質材を貼り付けない。下定盤２により、化合物半導体ウェハの表面を、所望の表面粗さとなるように研磨して、仕上がり面とする。 The lower surface plate 2 does not attach a soft material. The surface of the compound semiconductor wafer is polished by the lower surface plate 2 so as to have a desired surface roughness to obtain a finished surface.
  下定盤２は、好ましくはガラス、スズ等から製造されるが、特に限定されない。下定盤２の硬度の上限は、研磨加工される化合物半導体ウェハの硬度、例えば、ＧａＡｓであればビッカース硬度Ｈｖ７５０であり、ＩｎＰであればＨｖ４５０である。下限はＨｖ２２０が望ましい。下定盤の硬度が硬くなりすぎると化合物半導体ウェハの表面に細かな傷が入りやすい。また、軟らかすぎると研磨時の下定盤の摩耗が早くなり、ウェハの精度悪化につながる。 The lower surface plate 2 is preferably manufactured from glass, tin or the like, but is not particularly limited. The upper limit of the hardness of the lower surface plate 2 is the hardness of the compound semiconductor wafer to be polished, for example, Vickers hardness Hv750 for GaAs and Hv450 for InP. The lower limit is preferably Hv220. If the hardness of the lower surface plate is too hard, fine scratches are likely to enter the surface of the compound semiconductor wafer. On the other hand, if it is too soft, the lower surface plate is worn quickly during polishing, leading to deterioration in wafer accuracy.
　化合物半導体ウェハ４は、特に限定されないが、たとえば、ＧａＡｓ、ＩｎＰ、ＧａＮである。 The compound semiconductor wafer 4 is not particularly limited, but is, for example, GaAs, InP, or GaN.
　下定盤２上には、化合物半導体ウェハ４を挟むようにして、或いは囲むようにして治具５が配されている。この治具は、化合物半導体ウェハ４が定盤に対して一定の移動をするよう外周部分にギアが備わっている。 A jig 5 is arranged on the lower surface plate 2 so as to sandwich or surround the compound semiconductor wafer 4. This jig has a gear on the outer peripheral portion so that the compound semiconductor wafer 4 moves with respect to the surface plate.
　次に、本発明の化合物半導体ウェハの加工方法について説明する。
　まず、上定盤１に軟質材３を貼り付ける。軟質材３としては、ウレタン樹脂を含浸させた不織布、超高分子ポリエチレン、発泡ウレタン、シリコンゴム等を挙げることができる。これらを、好ましくは上定盤１と同じ大きさに加工して、上定盤１の全面に貼り付ける。貼り付ける方法は特に限定されないが、両面テープで貼り付けてもよいし、接着剤で直接貼り付けてもよい。尚、軟質材に溝を形成する場合は、たとえば、ダイヤモンド砥石で削る方法を用いてもよい。
　次に、下定盤２と、軟質材３を貼り付けた上定盤１を加工装置（研磨装置）に取り付ける。取り付けた後、平坦な治具（図示せず）を用いて下定盤２と上定盤１（軟質材３）を削り平面化してもよい（修正作業）。
　そして、下定盤２上に半導体ウェハ４と治具５を配置する。
　両面加工のための化合物半導体ウェハ４は、少なくともこの段階までに準備できていればよい。化合物半導体ウェハ４は、特に限定されないが、たとえば、ＧａＡｓ、ＩｎＰ、ＧａＮ等の化合物半導体が挙げられる。
　前記治具５は、化合物半導体ウェハ４を挟むようにして、或いは囲むようにして下定盤２上に配されている。この治具５は、化合物半導体ウェハ４が定盤に対して一定の移動をするよう外周部分にギアが備わっている。
　次に、前記加工装置により、所定の研磨条件で半導体ウェハ４を研磨する。前記研磨条件は、たとえば、ウェハ単位面積あたり約５０ｇ／ｃｍ２の荷重で定盤回転数１０～５０ｒｐｍであってもよい。 Next, the processing method of the compound semiconductor wafer of this invention is demonstrated.
First, the soft material 3 is attached to the upper surface plate 1. Examples of the soft material 3 include a nonwoven fabric impregnated with a urethane resin, ultrahigh molecular weight polyethylene, urethane foam, and silicon rubber. These are preferably processed to the same size as the upper surface plate 1 and attached to the entire surface of the upper surface plate 1. The method of attaching is not particularly limited, but may be attached with a double-sided tape or directly with an adhesive. In addition, when forming a groove | channel in a soft material, you may use the method of shaving with a diamond grindstone, for example.
Next, the lower surface plate 2 and the upper surface plate 1 to which the soft material 3 is attached are attached to a processing device (polishing device). After the mounting, the lower surface plate 2 and the upper surface plate 1 (soft material 3) may be shaved and flattened using a flat jig (not shown) (correction work).
Then, the semiconductor wafer 4 and the jig 5 are arranged on the lower surface plate 2.
The compound semiconductor wafer 4 for double-sided processing should just be prepared by this stage at least. Although the compound semiconductor wafer 4 is not specifically limited, For example, compound semiconductors, such as GaAs, InP, and GaN, are mentioned.
The jig 5 is arranged on the lower surface plate 2 so as to sandwich or surround the compound semiconductor wafer 4. The jig 5 is provided with a gear at the outer peripheral portion so that the compound semiconductor wafer 4 moves with respect to the surface plate.
Next, the semiconductor wafer 4 is polished under predetermined polishing conditions by the processing apparatus. The polishing condition may be, for example, a platen rotation speed of 10 to 50 rpm with a load of about 50 g / cm 2 per wafer unit area.
  上定盤に軟質材を両面テープで貼り付けた。軟質材は、ＡｓｋｅｒＣ硬度７２の不織布で、厚みは、１．５ｍｍであった。この不織布には、ピッチ１０ｍｍ、幅３ｍｍ、深さ０．５ｍｍの溝を格子状に設けた。 A soft material was affixed to the upper surface plate with double-sided tape. The soft material was a non-woven fabric with Asker C hardness of 72, and the thickness was 1.5 mm. In this nonwoven fabric, grooves having a pitch of 10 mm, a width of 3 mm, and a depth of 0.5 mm were provided in a lattice shape.
  既存の研磨機に上記上定盤を取り付け、化合物半導体ウェハを研磨した。化合物半導体は、ＶＢ法で製造され、ドーパントとしてＳｉを５×１０１７～３×１０１８ａｔｏｍｓ／ｃｃ含有し、結晶欠陥ＥＰＤの面内平均値が、５００個／ｃｍ２以下であるＧａＡｓ結晶を（１００）１５°ｏｆｆ＜１１１＞±０．１°でスライスし、ウェハの（０－１－１）面を劈開した後、劈開面以外のウェハの外周を面取り加工したウェハを用いた。下定盤は、１０ｃｍ角でスリットを入れた硬度Ｈｖ４５０のホウケイ酸ガラスを用いた。３００枚のウェハを研磨したが、欠け、割れ不良は発生しなかった。 The upper surface plate was attached to an existing polishing machine, and the compound semiconductor wafer was polished. A compound semiconductor is manufactured by a VB method, and contains a GaAs crystal containing 5 × 10 17 to 3 × 10 18 atoms / cc of Si as a dopant and having an in-plane average value of crystal defects EPD of 500 / cm 2 or less. A wafer obtained by slicing at (100) 15 ° off <111> ± 0.1 ° and cleaving the (0-1-1) plane of the wafer and chamfering the outer periphery of the wafer other than the cleaved surface was used. The lower surface plate was made of borosilicate glass having a hardness of Hv450 and slits of 10 cm square. 300 wafers were polished, but no chipping or cracking occurred.
  比較のために、軟質材が貼り付けられていない上定盤を用いて、化合物半導体ウェハを研磨した。３００枚研磨して、欠け、割れ不良が２％発生した。 For comparison, a compound semiconductor wafer was polished using an upper surface plate to which no soft material was attached. After 300 sheets were polished, 2% chipping and cracking occurred.
  軟質材を表１に示すものにして、実施例１と同様に化合物半導体ウェハを３００枚ずつ研磨した。その結果を表１に示す。なお、不織布のＡｓｋｅｒＣ硬度は、樹脂の含浸量、もしくはウレタン原料の配合比を変えることによって変更した。 ３００ Using the soft materials shown in Table 1, 300 compound semiconductor wafers were polished in a similar manner to Example 1. The results are shown in Table 1. The Asker C hardness of the nonwoven fabric was changed by changing the impregnation amount of the resin or the blending ratio of the urethane raw material.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
  表１から判るように、ＡｓｋｅｒＣ硬度２０～９０の軟質材を上定盤に貼り付けると、欠け、割れ不良をなくすことができる。但し、ＡｓｋｅｒＣ硬度２０（軟らかい）場合、ロールオフが大きくなり、実質的に使用できない。ＡｓｋｅｒＣ硬度が４０であれば、ロールオフは発生したが、使用することができる。 As can be seen from Table 1, chipping and cracking defects can be eliminated by attaching a soft material with Asker C hardness of 20 to 90 to the upper surface plate. However, when the Asker C hardness is 20 (soft), the roll-off becomes large and cannot be practically used. If Asker C hardness is 40, roll-off has occurred but can be used.
　比較のために、実施例１における軟質材の代わりに、ロックウェル硬度ＨＲＲ１２６のＰＥＥＫ（ポリエーテルエーテルケトン）、ロックウェル硬度ＨＲＲ１２０のＰＣ（ポリカーボネート）、ロックウェル硬度ＨＲＲ１００のＰＰ（ポリプロピレン）を貼り付けて、実施例１と同様に研磨加工を行ったところ、欠け、割れ不良をなくすことはできなかった。 For comparison, PEEK (polyetheretherketone) with Rockwell hardness HRR126, PC (polycarbonate) with Rockwell hardness HRR120, and PP (polypropylene) with Rockwell hardness HRR100 are pasted instead of the soft material in Example 1. Then, when polishing was performed in the same manner as in Example 1, it was not possible to eliminate chipping and cracking defects.
  本発明によれば、化合物半導体ウェハのラッピング加工時のウェハの欠け、割れ不良をなくすことができる。 に よ According to the present invention, it is possible to eliminate wafer chipping and cracking defects during lapping of a compound semiconductor wafer.
  １    上定盤
  ２    下定盤
  ３    軟質材
  ４    化合物半導体ウェハ
  ５    治具 1 Upper surface plate 2 Lower surface plate 3 Soft material 4 Compound semiconductor wafer 5 Jig

Claims (8)

  1.   化合物半導体ウェハの両面をラッピング加工する方法であって、上定盤と下定盤の間に前記半導体ウェハを配置してラッピング加工する工程を含み、前記上定盤の前記ウェハ側の面に軟質材が貼り付けられていることを特徴とする化合物半導体ウェハの加工方法。 A method of lapping both sides of a compound semiconductor wafer, including a step of lapping by placing the semiconductor wafer between an upper surface plate and a lower surface plate, and a soft material on the wafer side surface of the upper surface plate A process for processing a compound semiconductor wafer, wherein:
  2.   前記軟質材が、厚さ０．５ｍｍ以上５ｍｍ以下であり、且つ、ＡｓｋｅｒＣ硬度４０以上９０以下であることを特徴とする請求項１に記載の化合物半導体の加工方法。 2. The method of processing a compound semiconductor according to claim 1, wherein the soft material has a thickness of 0.5 mm or more and 5 mm or less and an Asker C hardness of 40 or more and 90 or less.
  3. 　前記軟質材の前記ウェハ側の面に溝が形成されていることを特徴とする請求項１又は２に記載の化合物半導体ウェハの加工方法。 3. A method of processing a compound semiconductor wafer according to claim 1, wherein a groove is formed on a surface of the soft material on the wafer side.
  4.   前記溝が幅１ｍｍ以上５ｍｍ以下であることを特徴とする請求項３に記載の化合物半導体ウェハの加工方法。 4. The method for processing a compound semiconductor wafer according to claim 3, wherein the groove has a width of 1 mm or more and 5 mm or less.
  5. 　上定盤と下定盤を含み、前記上定盤と下定盤の間に半導体ウェハを配置してその両面をラッピング加工するための加工装置であって、
    　前記上定盤の前記ウェハ側の面に軟質材が貼り付けられていることを特徴とする加工装置。     A processing apparatus for arranging a semiconductor wafer between the upper surface plate and the lower surface plate and lapping both surfaces thereof, including an upper surface plate and a lower surface plate;
    A processing apparatus, wherein a soft material is attached to a surface of the upper surface plate on the wafer side.
  6.   前記軟質材が、厚さ０．５ｍｍ以上５ｍｍ以下であり、且つ、ＡｓｋｅｒＣ硬度４０以上９０以下であることを特徴とする請求項５に記載の加工装置。 The processing apparatus according to claim 5, wherein the soft material has a thickness of 0.5 mm to 5 mm and an Asker C hardness of 40 to 90.
  7. 　前記軟質材の前記ウェハ側の面に溝が形成されていることを特徴とする請求項５又は６に記載の加工装置。 7. A processing apparatus according to claim 5, wherein a groove is formed on a surface of the soft material on the wafer side.
  8.   前記溝が幅１ｍｍ以上５ｍｍ以下であることを特徴とする請求項７に記載の加工装置。 The processing apparatus according to claim 7, wherein the groove has a width of 1 mm or more and 5 mm or less.
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JPH08216034A (en) * 1995-02-14 1996-08-27 Furukawa Electric Co Ltd:The Abrasive and polishing method using same
JP2001244221A (en) * 2000-02-03 2001-09-07 Wacker Siltronic G Fuer Halbleitermaterialien Ag Manufacturing method of semiconductor wafer and this kind of semiconductor wafer
WO2001082354A1 (en) * 2000-04-24 2001-11-01 Sumitomo Mitsubishi Silicon Corporation Method of manufacturing semiconductor wafer
JP2004343126A (en) * 2003-05-15 2004-12-02 Siltronic Ag Method for simultaneous polishing of front surface and back surface of semiconductor wafer
JP2005150216A (en) * 2003-11-12 2005-06-09 Hitachi Cable Ltd Polishing apparatus of semiconductor wafer

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JP3516203B2 (en) * 1999-11-08 2004-04-05 株式会社日鉱マテリアルズ Compound semiconductor wafer
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Publication number Priority date Publication date Assignee Title
JPH08216034A (en) * 1995-02-14 1996-08-27 Furukawa Electric Co Ltd:The Abrasive and polishing method using same
JP2001244221A (en) * 2000-02-03 2001-09-07 Wacker Siltronic G Fuer Halbleitermaterialien Ag Manufacturing method of semiconductor wafer and this kind of semiconductor wafer
WO2001082354A1 (en) * 2000-04-24 2001-11-01 Sumitomo Mitsubishi Silicon Corporation Method of manufacturing semiconductor wafer
JP2004343126A (en) * 2003-05-15 2004-12-02 Siltronic Ag Method for simultaneous polishing of front surface and back surface of semiconductor wafer
JP2005150216A (en) * 2003-11-12 2005-06-09 Hitachi Cable Ltd Polishing apparatus of semiconductor wafer

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