WO2011082778A3 - Verfahren zur herstellung eines in ein isolierendes material eingebetteten bauteils mit bumps und mit die bumps überlappenden leiterzügen und entsprechende vorrichtung - Google Patents

Verfahren zur herstellung eines in ein isolierendes material eingebetteten bauteils mit bumps und mit die bumps überlappenden leiterzügen und entsprechende vorrichtung Download PDF

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Publication number
WO2011082778A3
WO2011082778A3 PCT/EP2010/007628 EP2010007628W WO2011082778A3 WO 2011082778 A3 WO2011082778 A3 WO 2011082778A3 EP 2010007628 W EP2010007628 W EP 2010007628W WO 2011082778 A3 WO2011082778 A3 WO 2011082778A3
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WIPO (PCT)
Prior art keywords
bumps
conductive layer
layer
component
overlap
Prior art date
Application number
PCT/EP2010/007628
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English (en)
French (fr)
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WO2011082778A2 (de
Inventor
Andreas Ostmann
Manessis Dionysios
Lars BÖTTCHER
Stefan Karaszkiewicz
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V
Technische Universität Berlin
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Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V, Technische Universität Berlin filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V
Priority to EP10792842A priority Critical patent/EP2513957A2/de
Priority to US13/515,137 priority patent/US8975116B2/en
Publication of WO2011082778A2 publication Critical patent/WO2011082778A2/de
Publication of WO2011082778A3 publication Critical patent/WO2011082778A3/de

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969—Apertured conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0353—Making conductive layer thin, e.g. by etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zur Herstellung einer elektronischen Baugruppe (1), bei der mindestens ein elektronisches Bauteil (2) in ein isolierendes Material (4) zumindest teilweise eingebettet ist, mit folgenden Schritten: Bereitstellen einer Folienanordnung (7' + 10), die mindestens eine leitfähige Schicht (7') und eine Trägerschicht (10) aufweist, oder nur einer leitfähigen Schicht (7), Strukturieren der leitfähigen Schicht (7, 7'), derart, dass Öffnungen in Form von Sacklöchern oder Durchgangslöchern (8) für die Aufnahme von Bumps (3) hergestellt werden, die mit den Kontaktflächen des mindestens einen elektronischen Bauteils (2) verbunden sind, Aufbringen einer Klebeschicht (5) auf die mit Öffnungen (8) versehene leitfähige Schicht (7, 7'), Aufsetzen des mindestens einen Bauteils(2) auf die Folienanordnung (7' + 10) bzw. in die leitfähige Schicht (7) derart, dass die Bumps (3) in die Öffnungen (8) der leitfähigen Schicht (7, 7') eingreifen, teilweises Einbetten des mindestens einen Bauteils (2) von der den Bumps (3) entgegengesetzten Seite in eine Dielektrikumsschicht (4), Entfernen der Trägerschicht (10) der Folienanordnung (10 + 7') oder eines Teils der leitfähigen Schicht ( 7) derart, dass die Oberfläche der Bumps (3) freigelegt wird, Abscheiden einer Metallisierungsschicht auf die Seite der verbleibenden leitenden Schicht (7') mit den freigelegten Bumps (3), Strukturieren der Metallisierungsschicht und der leitenden Schicht (7') zur Herstellung von Leiterzügen (6), die mit den Bumps (3) überlappen. Die Erfindung betrifft ferner eine durch ein derartiges Verfahren hergestellte elektronische Baugruppe (1).
PCT/EP2010/007628 2009-12-15 2010-12-14 Verfahren zur herstellung einer elektronischen baugruppe und elektronische baugruppe WO2011082778A2 (de)

Priority Applications (2)

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EP10792842A EP2513957A2 (de) 2009-12-15 2010-12-14 Verfahren zur herstellung einer elektronischen baugruppe und elektronische baugruppe
US13/515,137 US8975116B2 (en) 2009-12-15 2010-12-14 Electronic assembly including an embedded electronic component

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DE102009058764A DE102009058764A1 (de) 2009-12-15 2009-12-15 Verfahren zur Herstellung einer elektronischen Baugruppe und elektronische Baugruppe
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RU2597210C1 (ru) * 2015-05-28 2016-09-10 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" Способ изготовления микроэлектронного узла на пластичном основании
US10373856B2 (en) * 2015-08-03 2019-08-06 Mikro Mesa Technology Co., Ltd. Transfer head array
JP6693441B2 (ja) * 2017-02-27 2020-05-13 オムロン株式会社 電子装置およびその製造方法
RU2752013C1 (ru) * 2020-10-26 2021-07-21 Федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский государственный электротехнический университет "ЛЭТИ" им. В.И. Ульянова (Ленина) Способ изготовления микросборки бескорпусных электронных компонентов на гибких органических подложках

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US20130015572A1 (en) 2013-01-17
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EP2513957A2 (de) 2012-10-24
DE102009058764A1 (de) 2011-06-16

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