Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N50/00—Galvanomagnetic devices
  • H10N50/80—Constructional details
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N50/00—Galvanomagnetic devices
  • H10N50/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N50/00—Galvanomagnetic devices
  • H10N50/10—Magnetoresistive devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N50/00—Galvanomagnetic devices
  • H10N50/80—Constructional details
  • H10N50/85—Magnetic active materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Definitions

• the present disclosure is generally related to magnetic tunnel junction devices.
• Magnetic Random Access Memory is a nonvolatile memory
• An MRAM generally includes a plurality of magnetic cells in an array. Each cell typically represents one bit of data.
• a cell includes a magnetic element, such as a magnetic tunnel junction (MTJ).
• MTJ magnetic tunnel junction
• Ferromagnetic plates of an MTJ typically include a free layer and a pinned layer separated by a thin tunneling barrier layer. The plates are associated with a
• magnetization direction (or orientation of magnetic moments).
• the magnetization direction is free to rotate.
• An anti-ferromagnetic layer may be used to fix the magnetization of the pinned layer in a particular direction.
• a bit is written to the MTJ by changing the magnetization direction of one of the ferromagnetic plates of the MTJ.
• the resistance of the MTJ depends upon the orientations of the magnetic moments of the free layer and the pinned layer.
• an MTJ device is formed by depositing a first free layer of a magnetically permeable material on a tunneling barrier layer, depositing a spacer layer on the first free layer, depositing a second free layer on the spacer layer, and depositing a spin torque enhancement layer above the second free layer.
• the spacer layer is chosen of a material or materials and a thickness to substantially inhibit exchange coupling between the first and second free layers.
• the first free layer and the second free layer are strongly magneto- statically coupled.
• the magnetic polarizations of the first and second free layers are anti-parallel, regardless of whether the device is switched to a logic "1" state or a logic "0" state.
• an MTJ device has a first free layer having a first thickness, a second free layer, and a spin torque enhancement layer.
• the device also includes a spacer layer between the first free layer and the second free layer.
• the spacer layer is of a material and a thickness to substantially inhibit exchange coupling between the first and second free layers.
• the first free layer is magnetio- statically coupled to the second free layer.
• the spacer layer can be of a combination of materials having a total thickness to substantially inhibit exchange coupling between the first and second free layers.
• the combination material may include two different non-magnetic materials or more than two different non-magnetic materials.
• the spacer layer can be of multiple layers and have a total thickness to substantially inhibit exchange coupling between the first and second free layer.
• the spacer layer can include two non-magnetic layers made of different materials or more than two non-magnetic layers made of different materials.
• a method of manufacturing an MTJ device includes depositing a first free layer on a tunnel barrier layer of an MTJ structure.
• the first free layer includes a magnetically permeable material and has a first thickness.
• the method also includes depositing a spacer layer on the first free layer.
• the spacer layer includes a substantially non-magnetically permeable insulator material and has a thickness that substantially inhibits exchange coupling.
• the method further includes depositing a second free layer on the spacer layer.
• the second free layer includes a magnetically permeable material.
• the method further includes depositing a spin torque enhancement layer above the second free layer.
• a computer readable tangible medium stores instructions executable by a computer to facilitate manufacture of an MTJ device.
• the stored instructions are executable by the computer to control depositing of a first free layer on a tunnel barrier layer of an MTJ structure, the first free layer including a magnetically permeable material and having a first thickness.
• the stored instructions are executable by the computer to control depositing of a spacer layer on the first free layer.
• the spacer layer includes a substantially non-magnetically permeable insulator material having a thickness that substantially inhibits exchange coupling between the first free layer and a second free layer.
• the stored instructions are executable by the computer to control depositing of a second free layer on the spacer layer.
• the second free layer includes a magnetically permeable material.
• the stored instructions are executable by the computer to control depositing of a spin torque enhancement layer above the second free layer.
• a method of designing an MTJ device is
• the method includes receiving design information representing at least one physical property of a semiconductor device.
• the semiconductor device includes a first free layer having a first thickness, a second free layer having a second thickness, a spin torque enhancement layer, and a spacer layer between the first free layer and the second free layer.
• the spacer layer includes a material or more than one material and has a thickness that substantially inhibits exchange coupling between the first and second free layers.
• the spacer layer may also include two or more than two non-magnetic layers made of different materials, and have a total thickness that substantially inhibits exchange coupling between the first and second free layers.
• the first free layer is magneto-statically coupled to the second free layer.
• the method further includes transforming the design information to comply with a file format and generating a data file including the transformed design information.
• a method of positioning a packaged MTJ device includes receiving design information including physical positioning information of a packaged semiconductor device on a circuit board.
• the packaged semiconductor device includes a semiconductor structure that includes a first free layer having a first thickness, a second free layer having a second thickness, a spin torque enhancement layer, and a spacer layer between the first free layer and the second free layer.
• the first free layer is magneto-statically coupled to the second free layer.
• the method further includes transforming the design information to generate a data file.
• a method of manufacturing a circuit board that includes a packaged MTJ device includes receiving a data file with design information including physical positioning information of a packaged semiconductor device on a circuit board. The method further includes manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information.
• the packaged semiconductor device comprises a first free layer having a first thickness, a second free layer having a second thickness, a spin torque enhancement layer, and a spacer layer between the first free layer and the second free layer.
• the first free layer is magneto-statically coupled to the second free layer.
• One particular advantage provided by disclosed embodiments is a lower
• FIG. 1 is a cross sectional view of an embodiment of a magnetic tunnel junction
• MMTJ magnetic resonance imaging
• FIG. 2 is a cross sectional view of a first embodiment of a dual free layer
• FIG. 3 shows a cross sectional view of a second embodiment and a third
• FIG. 4 is a graph showing switching current versus layer thickness of
• FIG. 5 is a flow chart of an embodiment of a method of forming an MTJ device
• FIG. 6 is a flow chart of another embodiment of a method of forming an MTJ device.
• FIG. 7 is flow chart of an embodiment of a design and manufacture process of a semiconductor device that includes an embodiment of an MTJ device. V. Detailed Description
• FIG. 1 is a cross sectional view of an embodiment of an MTJ device in a first state 120, (logic "1"), and in a second state 130, (logic "0").
• the embodiment of FIG. 1 includes multiple layers above a substrate 101.
• the substrate 101 may be a
• a first layer 102 above the substrate is a bottom layer which may form an electrode and include Ta. Ta provides better growing texture for an Anti- Ferromagnetic (AFM) pinning layer, and provides a smooth surface for growing the MTJ.
• the bottom layer can be composed of multiple layers of different materials.
• a layer 103 is an Anti-Ferromagnetic (AFM) pinning layer.
• the AFM pinning layer 103 acts to pin the magnetic moments in layers 104 and 108.
• the AFM pinning layer 103 may include an anti-ferromagnetic material such as MnPt, IrMn, FeMn, or NiO.
• An example thickness of the AFM pinning layer 103 is 15nm. Other thicknesses may be employed for the AFM pinning layer 103.
• the layers 104, 106 and 108 form a Synthetic Anti-Ferromagnetic (SAF) layer.
• SAF Synthetic Anti-Ferromagnetic
• the layer 104 is pinned by layer 103 by an exchange coupling mechanism.
• the layer 108 is pinned to layer 104 by exchange coupling through a spacer layer 106.
• the spacer layer 106 may be Ru, Rh, or Cr or other material that does not substantially inhibit exchange coupling.
• the layers 104 and 108 are ferromagnetic and may include Fe, Ni, Co, or B, or a combination of these elements, such as, for example, CoFeB.
• the magnetic moments in layers 104 and 108 are anti-parallel, thus forming an anti-ferromagnetic layer.
• An example thickness of the SAF layer is 2nm (nanometers) for layer 104, 0.9nm for layer 106, 2nm for layer 108. Other thicknesses may be employed for the SAF layer.
• the layer 110 is a tunnel barrier layer that may be formed of a dielectric such as
• An example thickness of the tunnel barrier layer 110 is lnm. Other thicknesses may be employed for the tunnel barrier layer.
• the layer 112 is a first free layer that is magnetizable and has a first thickness.
• the layer 114 is a spacer layer comprising a material and a thickness that substantially inhibits exchange coupling between the first free layer 112 and the second free layer 116.
• the spacer layer 114 may be composed of multiple layers or multiple materials such as an alloy.
• the spacer layer may comprise one of AlCu, AlRu, and AlAg.
• the spacer layer may comprise two layers of one of Ta and MgO, Ta and Mg, and Ta and Ru.
• the thickness of the spacer layer is at least 4 Angstroms (4xl0 ⁇ 10 meters).
• the layer 116 is a second free layer that is magnetizable and may have a second thickness that is different from, or the same as, the thickness of the first free layer 112.
• the thickness of the second free layer 116 is greater than the thickness of the first free layer 112. In some embodiments, the thickness of the first free layer 112 is between 5 and 25 Angstroms. In other embodiments, the thickness of the first free layer 112 is between 15 and 20 Angstroms. In some embodiments, the thickness of the second free layer 116 is between 10 and 60 Angstroms. In other embodiments, the thickness of the second free layer 116 is between 30 and 50 Angstroms. In some embodiments, a capping layer 122 is deposited on the second free layer 116. The capping layer 122 is a non-magnetic layer and forms a spin barrier or top electrode but is not a pinning layer. In a logic "0" state, the magnetic polarizations of the two upper free layers 112,
• a magnetic tunnel junction device may be in a memory cell where a current applied across the magnetic tunnel junction device changes a data value stored in the cell.
• the resistance of the device is low and the device is in the logic "0" state.
• the resistance of the device is high and the MTJ device is in the logic "1" state.
• FIG. 2 shows a portion of a representative MTJ device that includes multiple free layers.
• a layer 212 is a first free layer that is magnetizable and has a first thickness.
• the layer 212 may include a ferrous alloy such as CoFeB.
• a layer 214 is spacer layer formed of a dielectric such as Ta or MgO that substantially inhibits exchange coupling between the first free layer 212 and a second free layer 216.
• Exchange coupling may also be substantially inhibited by a thickness of the spacer layer 214.
• the thickness of the spacer layer 214 is at least 4
• the layer 216 is a second free layer that may include a ferrous alloy such as NiFe.
• the second free layer 216 is magnetizable.
• the layer 214 may also be a multiple spacer layer formed of a multiple dielectrics such as Ta and MgO, Ta and Mg, Ta and Ru, but will not be limited to those materials.
• the magnetic moment, M3, in the first free layer 112, 212 is anti-parallel to the magnetic moment, M4, in the second free layer 116, 216.
• the magnetic moments in the first and second free layers are anti-parallel, regardless of the state of the MTJ device.
• the magnetic moments in the free layers are anti-parallel because they are magneto-statically coupled, but substantially not exchange-coupled, as shown by the dashed lines in FIG. 2 at 208.
• the dashed lines show a magnetic field, H, that is circuitous and couples the first and second free layers, magneto-statically.
• a layer 212 is a first free layer that is magnetizable and has a first thickness.
• the layer 212 may include a ferrous alloy such as CoFeB.
• a layer 214 is a spacer layer formed of a dielectric such as Ta or MgO that substantially inhibits exchange coupling between the first free layer 212 and a second free layer 216. Exchange coupling may also be substantially inhibited by a thickness of the spacer layer 214. In some embodiments, the thickness of the spacer layer 214 is at least 4 Angstroms (4x10 ⁇ 10 meters). In other embodiments, the thickness of the spacer layer is at least 8 Angstroms.
• the layer 216 is a second free layer that may include a ferrous alloy such as NiFe. The second free layer 216 is magnetizable.
• the layer 214 may also be a multiple spacer layer formed of a multiple dielectrics such as Ta and MgO, Ta and Mg, Ta and Ru, but will not be limited to those materials.
• FIG. 3 shows a second embodiment and a third embodiment of a portion of a representative MTJ device that includes two free layers 312 and 316 separated by a spacer layer 314.
• a spin torque enhancement layer 320 is added above the second free layer 316.
• the spin torque enhancement layer 320 reduces a damping constant of the free layers.
• the spin torque enhancement layer 320 may include MgO, SiN, TaO, or other suitable material.
• a spin accumulation layer 318 is added between the second free layer 316 and the spin torque enhancement layer 320.
• the spin accumulation layer 318 has a high conductivity and a long diffusion length that may cause accumulation of angular momentum.
• the spin accumulation layer may include Mg, Cu, Al, or other suitable material.
• FIG. 4 is a graph 400 showing switching current versus layer thickness of
• Line 402 indicates switching current as a function of thickness of a first free layer in an embodiment of an MTJ that does not include a second free layer.
• Line 404 indicates switching current as a function of thickness of an embodiment of an MTJ device that includes first and second free layers. More specifically, the first free layer includes CoFeB having a thickness of 20
• the second free layer includes NiFe.
• Line 406 indicates switching current as a function of thickness of another embodiment of an MTJ device having two free layers.
• the first free layer includes CoFeB having a thickness of 15 Angstroms and the second free layer includes NiFe.
• a lower switching current can be achieved at greater free layer thickness with MTJ devices that include a second free layer over a spacer, as shown in FIG. 1 and FIG. 2.
• the switching current grows more slowly as a function of the thickness of the first free layer.
• having a CoFeB first free layer that is 15 Angstroms thick and a second free layer that has a total thickness of between 25 and 50 Angstroms yields a switching current of about 300 micro-amperes.
• line 402 shows that the switching current exceeds 400 micro-amperes when the thickness of the free layer, CoFeB, exceeds 25 Angstroms.
• the first free layer has a thickness in the range of 5 to 25 Angstroms, and the second free layer has a thickness in the range of 10 to 60 Angstroms. In other embodiments, the first free layer has a thickness in the range of 15 to 20 Angstroms, and the second free layer has a thickness of 30-50 Angstroms. In some embodiments, the thickness of the spacer layer is in the range of .4-30 Angstroms.
• the presence of a second free layer that is magneto-statically coupled to the first free layer, but substantially not exchange coupled to the first free layer can provide an advantage of a lower switching current of the MTJ device to change the state of the device.
• the presence of the second free layer also increases an energy barrier to a movement of electrons away from the first free layer, resulting in greater efficiency.
• the presence of the second free layer may also reduce magneto-striction in the first free layer, thereby improving the switching uniformity of the MTJ device.
• FIG. 5 is a flow chart 500 of an embodiment of a method of forming an MTJ device.
• a first free layer including a magnetically permeable material is deposited on a tunneling barrier layer of an MTJ structure.
• the first free layer has a first thickness.
• a layer of CoFeB can be deposited onto a tunnel barrier layer as shown in FIG. 1, (layer 112).
• a spacer layer that is substantially non-magnetically permeable is deposited on the first free layer.
• the spacer layer is an insulator material having a thickness that substantially inhibits exchange coupling between the first free layer and a second free layer deposited upon the spacer layer.
• a layer of Ta or MgO can be deposited onto the first free layer as shown in FIG. l, (layer 114).
• the spacer layer may itself be a multilayer structure that includes materials such as TaMg, TaRu, MgOTa, MgTa, or RuTa.
• a second free layer including a magnetically permeable material is deposited on the spacer layer.
• a layer of NiFe can be deposited onto the spacer layer as shown in FIG. 1, layer 116.
• a spin torque enhancement layer is deposited on or above the second free layer.
• some embodiments include a method of manufacturing a magnetic tunnel junction device.
• the method includes depositing a first free layer on a tunnel barrier layer of a magnetic tunnel junction structure, the first free layer including a
• FIG. 6 is a flow chart 600 of another illustrative embodiment of a method of forming an MTJ device.
• an anti-ferromagnetic (AFM) pinning layer is deposited on a substrate, (e.g., substrate 101 of FIG. 1). As shown in FIG. 1, a bottom layer may be deposited on the substrate before depositing the AFM layer.
• a synthetic anti-ferromagnetic (SAF) layer is deposited on the AFM pinning layer.
• the SAF layer 104, 106, and 108 may be deposited on the AFM pinning layer 102, as shown in FIG. 1.
• a tunnel barrier layer is deposited on the SAF layer, (e.g., layer 110 of FIG. 1 may be deposited on layer 108).
• a first free layer is deposited on the tunnel barrier layer, the first free layer having a first thickness, (e.g., layer 112 of FIG. 1).
• a spacer layer is deposited on the first free layer, as shown for layer 114 of FIG. 1.
• the spacer layer is of a material or materials and has a thickness that substantially inhibits exchange coupling between the first free layer and a second free layer.
• a second free layer e.g., layer 116 of FIG. 1
• the presence of the second free layer that is magneto statically coupled, but substantially not exchange coupled, to the first free layer results in a lower switching current to change the state of the MTJ device.
• a spin torque enhancement layer is deposited on or above the second free layer.
• a capping layer is deposited on the second free layer.
• the capping layer (e.g., layer 122 of FIG. 1) forms a spin barrier or top electrode but is not a pinning layer.
• the capping layer 122 may be formed of Ta, TaN, or Ru. An example thickness of the capping layer is 0.2-200nm.
• any one or more of the layers described herein may be deposited using a vapor deposition process, a vacuum evaporation process, or other suitable deposition process.
• An MTJ device as described herein may be located in each one of a plurality of memory cells forming an array of Magnetic Random Access Memory.
• the MTJ devices are in cells of a Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM).
• STT-MRAM Spin-Transfer-Torque Magnetic Random Access Memory
• an MTJ device is placed in one state to store a logic "1" value and is placed in an opposite state to store a logic "0" value.
• a memory cell may be placed in one state or the other by applying a current across the MTJ device forming the cell.
• RTL RTL, GDSII, GERBER, etc.
• Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in electronic devices.
• FIG. 7 depicts a particular illustrative embodiment of an electronic device
• Physical device information 702 is received in the manufacturing process 700, such as at a research computer 706.
• the physical device information 702 may include design information representing at least one physical property of a semiconductor device, such as memory devices including memory cells including the MTJ device with dual free layers as illustrated in FIG. 1 and FIG. 2.
• the physical device information 702 may include physical parameters, material characteristics, and structure information that is entered via a user interface 704 coupled to the research computer 706.
• the research computer 706 includes a processor 708, such as one or more processing cores, coupled to a computer readable medium such as a memory 710.
• the memory 710 may store computer readable instructions that are executable to cause the processor 708 to transform the physical device information 702 to comply with a file format and to generate a library file 712.
• the library file 712 includes at least one data file including the transformed design information.
• the library file 712 may include a library of semiconductor devices, including the MTJ device, or memory arrays including MTJ devices with dual free layers as shown in FIG. 1 or FIG. 2, that is provided for use with an electronic design automation (EDA) tool 720.
• EDA electronic design automation
• the library file 712 may be used in conjunction with the EDA tool 720 at a
• the design computer 714 including a processor 716, such as one or more processing cores, coupled to a memory 718.
• the EDA tool 720 may be stored as processor executable instructions at the memory 718 to enable a user of the design computer 714 to design a circuit using the MTJ device with dual free layers of FIG. 1 or FIG. 2 of the library file 712.
• a user of the design computer 714 may enter circuit design information 722 via a user interface 724 coupled to the design computer 714.
• the circuit design information 722 may include design information representing at least one physical property of a semiconductor device, such as the MTJ device of FIG. 1 or FIG. 2.
• the circuit design property may include identification of particular circuits and relationships to other elements in a circuit design, positioning information, feature size information, interconnection information, or other information representing a physical property of a semiconductor device.
• the design computer 714 may be configured to transform the design
• the file format may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format.
• the design computer 714 may be configured to generate a data file including the transformed design information, such as a GDSII file 726 that includes information describing the MTJ device with dual free layers of FIG. 1 or FIG. 2.
• the data file may include information corresponding to a system-on-chip (SOC) that includes the MTJ device with dual free layers of FIG. 1 or FIG. 2 and that also includes additional electronic circuits and components within the SOC.
• SOC system-on-chip
• the GDSII file 726 may be received at a fabrication process 728 to manufacture the MTJ device of FIG. 1 or FIG. 2, according to transformed information in the GDSII file 726.
• a device manufacture process may include providing the GDSII file 726 to a mask manufacturer 730 to create one or more masks, such as masks to be used for photolithography processing, illustrated as a representative mask 732.
• the mask 732 may be used during the fabrication process to generate one or more wafers 734, which may be tested and separated into dies, such as a representative die 736.
• the die 736 includes a circuit including the MTJ device of FIG. 1 or FIG. 2.
• the die 736 may be provided to a packaging process 738 where the die 736 is incorporated into a representative package 740.
• the package 740 may include the single die 736 or multiple dies, such as a system-in-package (SiP) arrangement.
• the package 740 may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.
• JEDEC Joint Electron Device Engineering Council
• Information regarding the package 740 may be distributed to various product designers, such as via a component library stored at a computer 746.
• the computer 746 may include a processor 748, such as one or more processing cores, coupled to a memory 750.
• a printed circuit board (PCB) tool may be stored as processor executable instructions at the memory 750 to process PCB design information 742 received from a user of the computer 746 via a user interface 744.
• the PCB design information 742 may include physical positioning information of a packaged semiconductor device on a circuit board.
• the packaged semiconductor device corresponds to the package 740 including the MTJ device with dual free layers of FIG. 1 or FIG. 2.
• the computer 746 may be configured to transform the PCB design information
• the data file generated by the transformed PCB design information may have a format other than a GERBER format.
• the GERBER file 752 may be received at a board assembly process 754 and used to create PCBs, such as a representative PCB 756, manufactured in accordance with the design information stored within the GERBER file 752.
• the GERBER file 752 may be uploaded to one or more machines for performing various steps of a PCB production process.
• the PCB 756 may be populated with electronic components including the package 740 to form a representative printed circuit assembly (PC A) 758.
• PC A printed circuit assembly
• the PC A 758 may be received at a product manufacture process 760 and
• first representative electronic device 762 integrated into one or more electronic devices, such as a first representative electronic device 762 and a second representative electronic device 764.
• first representative electronic device 762 the second representative electronic device 764.
• second representative electronic device 764 the first representative electronic device 762, the second
• representative electronic device 764 may be selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.
• PDA personal digital assistant
• one or more of the electronic devices 762 and 764 may be remote units such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
• PCS personal communication systems
• GPS global positioning system
• navigation devices fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
• the disclosure is not limited to these exemplary illustrated units.
• Embodiments of the disclosure may be suitably employed in any device that includes active integrated circuitry including memory.
• the MTJ device of FIG. 1 or FIG. 2 may be fabricated, processed, and incorporated into an electronic device, as described in the illustrative process 700.
• One or more aspects of the embodiments disclosed with respect to FIGS. 1-2 may be included at various processing stages, such as within the library file 712, the GDSII file 726, and the GERBER file 752, as well as stored at the memory 710 of the research computer 706, the memory 718 of the design computer 714, the memory 750 of the computer 746, the memory of one or more other computers or processors (not shown) used at the various stages, such as at the board assembly process 754, and also incorporated into one or more other physical embodiments such as the mask 732, the die 736, the package 740, the PCA 758, other products such as prototype circuits or devices (not shown), or any combination thereof.
• stages of production from a physical device design to a final product are depicted, in other embodiments fewer stages may be used or additional stages may be included.
• process 700 may be performed by a single entity, or by one or more entities performing various stages of the process 700.
• a software module may reside in random access memory (RAM), including MRAM and STT-MRAM, flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable
• RAM random access memory
• MRAM magnetic RAM
• STT-MRAM flash memory
• ROM read-only memory
• PROM programmable read-only memory
• EPROM erasable programmable read-only memory
• EEPROM programmable read-only memory
• CD-ROM compact disc read-only memory
• An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
• the storage medium may be integral to the processor.
• the processor and the storage medium may reside in an application-specific integrated circuit (ASIC).
• the ASIC may reside in a computing device or a user terminal.
• the processor and the storage medium may reside as discrete components in a computing device or user terminal.

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