WO2011071573A2 - Amplificateurs comprenant des transistors à film mince à appauvrissement et enrichissement et procédés associés - Google Patents

Amplificateurs comprenant des transistors à film mince à appauvrissement et enrichissement et procédés associés Download PDF

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Publication number
WO2011071573A2
WO2011071573A2 PCT/US2010/047336 US2010047336W WO2011071573A2 WO 2011071573 A2 WO2011071573 A2 WO 2011071573A2 US 2010047336 W US2010047336 W US 2010047336W WO 2011071573 A2 WO2011071573 A2 WO 2011071573A2
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WO
WIPO (PCT)
Prior art keywords
transistor
terminal
operating mode
threshold voltage
target
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PCT/US2010/047336
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English (en)
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WO2011071573A3 (fr
Inventor
Sameer M. Venugopal
Aritra Dey
David R. Allee
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Arizona Board Of Regents, For And On Behalf Of Arizona State University
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Application filed by Arizona Board Of Regents, For And On Behalf Of Arizona State University filed Critical Arizona Board Of Regents, For And On Behalf Of Arizona State University
Publication of WO2011071573A2 publication Critical patent/WO2011071573A2/fr
Publication of WO2011071573A3 publication Critical patent/WO2011071573A3/fr
Priority to US13/411,356 priority Critical patent/US8319561B2/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor

Definitions

  • Atti omeys Bryan Cave, LLP (Phoenix, Arizona, USA)
  • This invention relates generally to semiconductor devices, and relates, more particularly, to amplifiers with depletion and enhancement mode thin film transistors and related methods.
  • semiconductor process flows may be limited to yield only specific types of transitors.
  • one semiconductor process flow may be streamlined to yield integrated circuits having only N-type enhancement mode transistors, such as for the manufacture of displays like active matrix thin film transistor displays.
  • N-type enhancement mode transistors such as for the manufacture of displays like active matrix thin film transistor displays.
  • Such integrated circuits would normally use external amplifiers, or integrated amplifiers that use only the type of transistor generated by the streamlined semiconductor process flow.
  • the use of external amplifiers can add cost and complexity to the development and/or production process.
  • being restricted to a single type of transistor for the integrated amplifiers can limit the performance of such integrated circuits. Therefore, a need exists to develop integrated amplifiers and related methods with transistors having selectively alterable characteristics to overcome or mitigate the limitations described above.
  • FIG. 1 illustrates a schematic of an integrated circuit comprising an amplifier in accordance with one embodiment of the present disclosure.
  • FIG. 2 illustrates sample models of first and second transistors for the amplifier of FIG. 1.
  • FIG. 3 illustrates sample waveforms for input and output signals processed by the amplifier of
  • FIG. 1 based on the sample models of FIG. 2.
  • FIG. 4 illustrates a flowchart of a method for providing an integrated circuit comprising an amplifier.
  • FIG. 5 illustrates a schematic of another integrated circuit comprising another amplifier in accordance with another embodiment of the present disclosure.
  • Couple should be broadly understood and refer to connecting two or more elements or signals, electrically, mechanically and/ or otherwise.
  • Two or more electrical elements may be electrically coupled together but not be mechanically or otherwise coupled together; two or more mechanical elements may be mechanically coupled together, but not be electrically or otherwise coupled together; two or more electrical elements may be mechanically coupled together, but not be electrically or otherwise coupled together.
  • Coupling may be for any length of time, e.g., permanent or semi-permanent or only for an instant.
  • An electrical “coupling” and the like should be broadly understood and include coupling involving any electrical signal, whether a power signal, a data signal, and/or other types or combinations of electrical signals.
  • a mechanical “coupling” and the like should be broadly understood and include mechanical coupling of all types. The absence of the word “removably,” “removable,” and the like near the word “coupled,” and the like does not mean that the coupling, etc. in question is or is not removable.
  • an apparatus comprises an integrated circuit comprising an amplifier.
  • the amplifier can comprise a first transistor over a substrate of the integrated circuit, and a second transistor over the substrate and coupled to the first transistor.
  • the first transistor can comprise a first source terminal, a first drain terminal, and a first gate terminal.
  • the second transistor can comprise a second source terminal, a second drain terminal, and a second gate terminal.
  • An input node of the amplifier can be coupled to the second transistor, such as to the second gate terminal.
  • An output node of the amplifier can be coupled between the first and second transistors, such as by coupling the second drain terminal and the first source terminal together at the output node.
  • the first and second transistors comprise thin film transistors
  • the substrate comprises a flexible substrate.
  • the first transistor comprises a threshold voltage alterable from an initial threshold voltage value to a target threshold voltage value, and the first gate terminal the first source terminal are configured to be selectively coupled together.
  • FIG. 1 illustrates a schematic of integrated circuit 100 comprising amplifier 1000 in accordance with one embodiment of the present disclosure.
  • Amplifier 1000 comprises transistor 1100 having control terminal 1130 configured to control channel 1150 between terminals 1110 and 1120 of transistor 1100.
  • Amplifier 1000 also comprises transistor 1200 having control terminal 1230 configured to control channel 1250 between terminals 1210 and 1220 of transistor 1200.
  • Input node 1510 of amplifier 1000 is coupled to transistor 1200, while output node 1520 of amplifier 1000 is coupled between transistors 1 00 and 1200.
  • FIG. 1 also shows source 1910 coupled to input node 1510, where source 1910 can be used to provide input signal 1911, which is amplified by amplifier 1000, and to output the signal as output signal 1912 via output node 1520.
  • Source 1910 comprises a sinusoidal voltage source in the present example, although in other examples the voltage source need not be sinusoidal.
  • terminals 1110, 1120, and 130 comprise drain, source, and gate terminals, respectively, of transistor 1100.
  • terminals 1210, 1220, and 1230 comprise drain, source, and gate terminals, respectively, of transistor 1200.
  • Transistors 1100 and 1200 comprise thin film transistors (TFTs), and are both located over substrate 10. Accordingly, at least transistor 1100 comprises a threshold voltage that is alterable from an initial threshold voltage value to a target threshold voltage value. As will be described below, the threshold voltage of transistor 1100 can be altered by electrically stressing channel 1150 via control terminal 130. In some examples, portions of transistor 1100, such as channel 1150, can comprise an amorphous material, such as amorphous silicon, a metal oxide material, such as zinc oxide, a mixed oxide material, such as Indium/Gallium/Zinc Oxide (IGZO), a nanocrystalline material, such as nanocrystalline silicon, and/or an organic material, such as pentacene. In the present example, substrate 10 comprises a flexible substrate, and both of transistors 1100 and 1200 are fabricated simultaneously over substrate 10 via a common semiconductor process flow. Transistor 1200 can also comprise a similarly alterable threshold voltage.
  • TFTs thin film transistors
  • substrate 10 can be a plastic substrate, and/or can comprise at least one of a flexible polyethylene naphthalate (PEN) material, such as that available from Teijin DuPont Films of Tokyo, Japan, under the tradename planarized "Teonex® Q65," a polyethylene terephthalate (PET) material, a polyethersulfone (PES) material, a polyimide, a polycarbonate, a cyclic olefin copolymer, and/or a liquid crystal polymer.
  • PEN flexible polyethylene naphthalate
  • PET polyethylene terephthalate
  • PES polyethersulfone
  • substrate 110 can comprise other materials such as a stainless steel material, a silicon material, an iron nickel (FeNi) alloy material (e.g., FeNi, FeNi36, or InverTM; where InverTM comprises an alloy of iron (64 percent (%)) and nickel (36%) (by weight) with some carbon and chromium), an iron nickel cobalt (FeNiCo) alloy material (e.g., KovarTM, where KovarTM typically comprises 29% nickel, 17% cobalt, 0.2% silicon, 0.3% manganese, and 53.5% iron (by weight)), a titanium material, a tantalum material, a molybdenum material, an aluchrome material, and/or an aluminum material.
  • substrate 10 can be rigid and can comprise a semiconductor material such as silicon.
  • FIG. 1 further describes the interconnection between transistors 1100 and 1200 of ampHfier 1000.
  • terminals 1120 and 1210 couple transistors 1100 and 1200 together at output node 1520.
  • input node 1510 is coupled to transistor 1200 at terminal 1230.
  • Terminal 1110 is coupled to path 1530 to voltage source 1920 of integrated circuit 100.
  • Terminal 1220 of transistor 1200 is coupled to ground via node 1540.
  • the coupling to ground couples terminal 1220 to substrate 10.
  • the present example also shows control terminal 1130 and terminal 1120 of transistor 1100 selectively coupled together via antifuse 1600.
  • amplifier 1000 comprises a common source amplifier with depletion load when antifuse 1600 couples or otherwise shorts terminals 1130 and 1120 together.
  • channel 1150 of transistor 1100 can be subject to electrical stress degradation that can alter its conducting characteristics.
  • stress voltage source 1930 is coupled to control terminal 1130 of transistor 1100 via a path through node 1550, where stress voltage source 1930 is configured to provide a stress voltage to alter the characteristics of channel 1150.
  • the threshold voltage of transistor 1100 can be altered from the initial threshold voltage value to the target threshold voltage value, and can remain altered at the target threshold voltage value even after the stress voltage is no longer applied.
  • the alteration of the threshold voltage can be due to charge injection into a gate insulator of transistor 1100, and/or due to a creation of defect states in channel 1150.
  • the initial threshold voltage value for transistor 1100 can be of approximately 1 volt to approximately 3 volts, and/or the target threshold voltage can be of approximately -1 volt to approximately -3 volts.
  • the stress voltage applied to control terminal 1130 can comprise approximately -10 volts to approximately -20 volts, and/or the stress voltage can be applied to control terminal 1130 from approximately 100 seconds to approximately 200 seconds.
  • the quantities above may be scaled or otherwise modified depending on the type or size of transistor 1100 and/or 1200, or depending on other ranges of initial and target threshold voltage values.
  • channels 1150 and 1250 of transistors 1100 and 1200 are both N-type channels.
  • Transistor 1100 also comprises an initial operating mode before alteration of its threshold voltage as described above, and a target operating mode achieved after alteration of its threshold voltage to the target threshold voltage value.
  • the initial operating mode for transistor 1100 comprises an enhancement mode
  • the target operating mode comprises a depletion mode.
  • transistor 1200 also comprises an operating mode that matches the initial operating mode of transistor 1100, and that remains unchanged when the threshold voltage of transistor 1100 is altered.
  • amplifier 1000 is suitable for inclusion as part of integrated circuits based on a process flow that yields transistors of a single channel type and/ or of a single operating mode.
  • integrated circuit 100 comprises integrated display circuitry built on substrate 10 with a process flow configured to yield only N-type enhancement mode transistors
  • amplifier 1000 could be added as part of the integrated display circuit without having to alter the process flow.
  • the target operating mode of transistor 1 00 could then be altered to the depletion mode, thus allowing the flexibility to configure amplifier 1000 as an N-type common source amplifier with N-type depletion load while still using a process flow configured to yield only enhancement mode transistors.
  • the configuration described for amplifier 1000 can also be beneficial over other configurations that rely on P-type load devices, because the mobilities of the N-type channels are greater than those of P- type channels.
  • both transistors 1100 and 1200 comprise the depletion mode in their initial operating mode.
  • FIG. 5 for integrated circuit 500 with amplifier 5000, where integrated circuit 500 is a different embodiment of, yet similar to, integrated circuit 100 of FIG. 1.
  • stress voltage source 1930 is coupled to control terminal 1230 of transistor 1200, rather than to control terminal 1130 of transistor 1100.
  • stress voltage source 1930 can be configured to provide a stress voltage to alter the characteristics of channel 1250 of transistor 1200, and thereby convert transistor 1200 to a target operating mode comprising the enhancement mode.
  • FIG. 5 for integrated circuit 500 with amplifier 5000, where integrated circuit 500 is a different embodiment of, yet similar to, integrated circuit 100 of FIG. 1.
  • stress voltage source 1930 is coupled to control terminal 1230 of transistor 1200, rather than to control terminal 1130 of transistor 1100.
  • stress voltage source 1930 can be configured to provide a stress voltage to alter the characteristics of channel 1250 of transistor 1200, and thereby convert transistor 1200 to a target operating mode comprising the enhancement mode.
  • the stress voltage supplied by stress voltage source 1930 could comprise a positive voltage value.
  • Antifuse 1600 may not be needed in embodiments where the initial operating mode of transistors 1100 and 1200 comprises the depletion mode.
  • integrated circuit 500 in FIG. 5 dispenses with antifuse 1600, and terminals 1120 and 1130 are directly shorted together therein. Regardless of whether the threshold voltage of transistor 1100 or of transistor 1200 is altered or not in one or more of the embodiments described herein, the channel type of channels 1150 and/or 1250 can remain unchanged.
  • transistor 1100 can be configured to serve as a load device for amplifier 1000.
  • amplifier 1000 can comprise a constant current source comprising transistor 1100, such that a current output of the constant current source can be tuned or adjusted by altering the threshold voltage of transistor 1100 towards the target threshold voltage value.
  • the target threshold voltage value for transistor 1100 can be established based on a target current output for the constant current source.
  • the ability to alter the threshold voltage of transistor 1100 and thereby establish the depletion mode as the target operating mode for transistor 1100 can permit configuration of elements of integrated circuit 100, such as amplifier 1000, even after fabrication of integrated circuit 100.
  • amplifier 1000 can be configured to comprise transistor 1100 as a depletion load transistor, even if the semiconductor process flow used to manufacture amplifier 1000 over substrate 10 only yields transistors of a single channel type and/or of a single initial operating mode.
  • such flexibility permits the use of transistor 1100 as a depletion load device, thereby affording greater gains for amplifier 1000 than a similar amplifier limited to using an enhancement-type load device.
  • Antifuse 1600 can be used in some examples to establish of the target operating mode for transistor 1100 by isolating control terminal 1130 from the rest of amplifier 1000 until after the threshold voltage of transistor 1100 has been altered. Antifuse 1600 can thus be actua table to selectively couple together terminals 1130 and 1120 of transistor 1100.
  • an impedance of antifuse 1600 is alterable from an initial high impedance value to a target low impedance value when antifuse 1600 is actuated. As a result, antifuse 1600 can short terminals 1130 and 1120 together, normally after application of the stress voltage to terminal 1130.
  • antifuse 1600 can comprise an antifuse reactive layer coupled between two antifuse conductors, where the antifuse reactive layer comprises a material that is initially non-conductive but that becomes conductive when activated.
  • antifuse 1600 can be actuated by sourcing a current through the antifuse reactive layer to thereby short the two antifuse conductors.
  • the shorting of the two antifuse conductors can be permanent once accomplished.
  • the antifuse reactive layer can comprise one or more of a metal oxide layer, a tantalum oxide layer, or an amorphous silicon layer.
  • the antifuse conductors can comprise a metallic material, such as a tantalum material, an aluminum material, and/or a molybdenum material.
  • the configuration of amplifier 1100 as a common source amplifier with depletion load after the actuation of antifuse 1600 can be beneficial to prevent or limit the degradation in performance of amplifier 1100 over time.
  • amplifiers rely on TFTs as load devices
  • channel degradation due to gate to source bias of the load device can tend to diminish the performance of such amplifiers, yielding lower gains at their output nodes.
  • the gate to source bias is unchecked and can eventually degrade the performance of such enhancement load TFT.
  • control terminal 1130 acts as the gate terminal for transistor 1100
  • terminal 1120 acts as the source terminal for transistor 1100
  • transistor 1100 acts as a depletion mode load device for amplifier 1100 when terminals 1130 and 1120 are coupled or otherwise shorted together by antifuse 1600 and when transistor 1100 operates in its target operating mode. Because the gate and source terminals for transistor 1100 would then be effectively shorted together, the gate to source bias can be thereby limited or neutralized, such that the degradation of transistor 1100 as a load device for amplifier 1000 can also be thereby limited and/or prevented.
  • Substrate can also support a display, such as a TFT display, and in this embodiment, integrated circuit 100 also includes the TFT display.
  • antifuse 1600 is also located over substrate 10.
  • Substrate 10 can also optionally support source 1910 and/or stress voltage source 1930.
  • FIG. 2 illustrates sample models for transistors 1100 and 1200 of amplifier 1000 for the example of FIG. 1.
  • the models for transistors 1100 and 1200 differ only in their respective threshold voltages.
  • Transistor 1100 has already been altered to the depletion mode as the target operating mode, and is configured to turn off at the threshold voltage of -3.25 volts.
  • Transistor 1200 remains in its initial operating mode as an enhancement mode transistor, configured to turn on at the threshold voltage of 1.25 volts. In its initial operating mode, transistor 1100 has the same model characteristics as shown for transistor 1200 in FIG. 2.
  • FIG. 3 illustrates sample waveforms for input signal 1911 and output signal 1912 for amplifier 1000 of FIG. 1 based on the models of FIG. 2.
  • amplifier 1000 can provide a gain of about 20 volts per volt for input signal 1911 using the models described in FIG. 2. Such high gain is possible in the present embodiment as a result of the depletion load configuration for transistor 1100 in FIG. 1.
  • FIG. 4 illustrates a flowchart of a method 4000 for providing an integrated circuit.
  • the integrated circuit can be similar to integrated circuit 100, at least a part of which is shown in FIG. 1.
  • Method 4000 comprises block 4100 for providing an amplifier as part of the integrated circuit, where the amplifier for block 4100 can be similar to amplifier 1000 as described above with respect to FIGs. 1-3.
  • block 4100 of method 4000 can comprise several sub-blocks, as described below.
  • block 4100 of method 4000 comprises sub-block 4110 and 4120, where sub-block 4110 comprises providing a first transistor over a substrate, and sub-block 4120 comprises providing a second transistor over the substrate of sub-block 4110.
  • the first transistor can be similar to transistor 1100 (FIGs. 1-2), comprising a first terminal similar to terminal 1110 (FIG. 1), a second terminal similar to terminal 1120 (FIG. 1), a control terminal similar to control terminal 1130 (FIG. 1), and a channel between the first and second terminals, similar to channel 1150 (FIG. 1).
  • the second transistor of block 4120 can be similar to transistor 1200 (FIGs.
  • the first and second transistors can comprise thin film transistors in some embodiments, as described above for transistor 1100 and 1200.
  • the substrate over which the first and second transistors of block 4100 are located can be similar to substrate 10, as described above for FIG. 1.
  • the substrate can comprise a flexible substrate and/or material.
  • providing the second transistor in block 4120 can comprise providing a channel type of the second transistor as one of an N-type channel or a P-type channel, and can also comprise providing the initial operating mode of the second transistor as one of the enhancement mode or the depletion mode.
  • providing the first transistor in block 4110 can comprise providing a channel type of the first transistor to match the channel type of the second transistor, and can also comprise providing the initial operating mode of the first transistor to match the initial operating mode of the second transistor.
  • Amplifier 1000 of FIG. 1 can be an example of the above, where both channels 1150 and 1250 of transistors 1100 and 1200, respectively, comprise N-type channels, and where the initial operating mode of both transistors 1100 and 1200 is the enhancement mode.
  • Block 4100 of method 4000 can also comprise in some examples sub-block 4130, comprising coupling the first terminal of the second transistor and the second terminal of the first transistor together at an output node of the amplifier of block 4100.
  • the coupling in block 4100 can be configured as illustrated in FIG. 1, where terminals 1120 and 1220 of transistors 1100 and 1200, respectively, are coupled together at output node 1520 of amplifier 1000.
  • block 4100 can comprise in some examples sub-block 4140 for coupling the control terminal of the second transistor with an input node of the amplifier of block 4100.
  • the coupling in block 4140 can be configured as illustrated in FIG. 1 in some examples, where control terminal 1230 of transistor 1200 is coupled with input node 1510 over substrate 10.
  • Block 4100 can in some examples comprise sub-block 4150 for coupkng a stress voltage source path to the control terminal of the first transistor.
  • the stress voltage source path can be similar to the path through node 1550 between stress voltage source 1930 and control terminal 1130 of transistor 1100 (FIG. 1).
  • Method 4000 can further comprise block 4200 for altering an operating mode of the first transistor from an initial operating mode to a target operating mode.
  • altering the operating mode of the first transistor in block 4200 can comprise altering a threshold voltage of the first transistor from an initial threshold voltage value to a target threshold voltage value.
  • the threshold voltage of the first transistor can be altered as described above with respect to the threshold voltage for transistor 1100, such as by applying a stress voltage to the control terminal of the first transistor of sub-block 4110.
  • the alteration of the operating mode of the first transistor can also be achieved as described above with respect to altering the operating mode of transistor 1100.
  • the channel of the first transistor can comprise an N-type channel, where the initial operating mode of the first transistor comprises the enhancement mode, and/ or where the initial threshold voltage value of the first transistor comprises a positive voltage value.
  • the stress voltage could be applied as a negative voltage to the control terminal of the first transistor to establish the target threshold voltage of the first transistor as a negative voltage and/or to thereby establish the target operating mode for the first transistor as the depletion mode.
  • providing the first transistor in sub-block 4110 could comprise configuring the threshold voltage of the first transistor to remain altered after the stress voltage has been applied to the control terminal of the first transistor.
  • the initial operating mode of the second transistor is maintained when block 4200 is implemented.
  • the channel types of the first and/or second transistors can also be maintained when block 4200 is implemented.
  • the alteration of the threshold voltage in block 4200 can be achieved by applying the stress voltage to the control terminal of transistor 1100 either iteratively or continuously.
  • the stress voltage from stress voltage source 1930 could be appHed to control terminal 1130 of transistor 1100 (FIG. 1) continuously for a predetermined amount of time calculated to bring the threshold voltage proximate to the target threshold voltage value.
  • the stress voltage could be appked iteratively instead, where the threshold voltage of transistor 1100 is measured between iterations of the application of the stress voltage to determine when the target threshold voltage value is realized for transistor 1100.
  • applying the stress voltage iteratively may result in a more consistent or precise target threshold voltage value.
  • the first transistor can serve as a constant current source for the amplifier of block 4100.
  • Method 4000 of FIG. 4 further comprises block 4300 for coupling together the control terminal of the first transistor and the second terminal of the first transistor.
  • Block 4300 can be implemented in some examples as described for FIG. 1, where terminals 1130 and 1120 of transistor 1100 are coupled together, after the target operating mode for transistor 1100 has been altered to the depletion mode, to configure amplifier 1000 as a common source amplifier with depletion load.
  • block 4300 can comprise providing an antifuse mechanism which can be actuated to selectively couple the control terminal and the second terminal of the first transistor together, and providing an antifuse impedance of the antifuse mechanism to be alterable from a high impedance magnitude to a low impedance magnitude upon actuation of the antifuse mechanism.
  • the antifuse mechanism can comprise antifuse 1600, as described above for FIG. 1 to couple terminals 1130 and 1120 of transistor 100 together and thereby establish transistor 100 as a depletion load for amplifier 1000.
  • the antifuse mechanism can also be actuated as described above for antifuse 1500.
  • the integrated circuit of method 4000 can be field programmable as part of a programmable logic device.
  • the integrated circuit may comprise one or more amplifiers similar to amplifier 1000 (FIG. 1), and individual ones of such one or more amplifiers can be enabled by the programmable logic device by altering the operating mode of their respective first transistors and by actuating their respective antifuse mechanisms.
  • one or more of the different blocks of method 4000 can be combined into a single step.
  • blocks 4110 and 4120 in FIG. 4 can be combined into a single block where the first and second transistors are fabricated simultaneously.
  • blocks 4130 and 4140 can be combined, and block 4150 can be combined with blocks 4130 and/ or 4140.
  • the sequence of one or more of the different blocks of method 4000 can be changed.
  • the sequence of blocks 4130 and 4140 be reversed if needed in some examples to write to the memory cell before reading the memory cell, and/ or the sequence of blocks 4110 and 4120 can be reversed.
  • method 4000 can comprise further or different steps.
  • source 1910 has been represented in FIG. 1 as a sinusoidal source, there can be embodiments where source 1910 comprises a constant source.
  • nodes 1510, 1520, 1530, and 1550 have been represented in FIG. 1 at a periphery of substrate 10, in the same or other embodiments such nodes and other elements of integrated circuit 100, such as source 1910, stress voltage source 1930, and/or voltage source 1920, can be formed or located over substrate 10.
  • block 4100 of method 4000 can include providing a display, such as a TFT display, as part of the integrated circuit.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne, dans un mode de réalisation, un appareil comprenant un circuit intégré doté d'un amplificateur. L'amplificateur peut comprendre un premier transistor sur un substrat du circuit intégré, et un second transistor sur le substrat, couplé au premier transistor. Le premier transistor peut comprendre une première borne de source, une première borne de drain, et une première borne de grille. Le second transistor peut comprendre une seconde borne de source, une seconde borne de drain, et une seconde borne de grille. Un nœud d'entrée de l'amplificateur peut être couplé au second transistor, par exemple à la seconde borne de grille. Un nœud de sortie de l'amplificateur peut être couplé entre le premier transistor et le second transistor, en couplant par exemple la seconde borne de drain et la première borne de source au niveau du nœud de sortie. Dans le même mode de réalisation, ou dans d'autres modes de réalisation, le premier transistor et le second transistor comprennent des transistors à film mince, et le substrat comprend un substrat souple. Le premier transistor comprend une tension de seuil modifiable entre une valeur de tension de seuil initiale et une valeur de tension de seuil cible, et la première borne de grille et la première borne de source sont configurées pour être sélectivement couplées l'une à l'autre. D'autres exemples et modes de réalisation sont également décrits.
PCT/US2010/047336 2009-09-02 2010-08-31 Amplificateurs comprenant des transistors à film mince à appauvrissement et enrichissement et procédés associés WO2011071573A2 (fr)

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KR101700470B1 (ko) * 2009-09-16 2017-01-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 구동 회로, 구동 회로를 포함하는 표시 장치 및 표시 장치를 포함하는 전자 기기
US10608588B2 (en) * 2017-12-26 2020-03-31 Nxp Usa, Inc. Amplifiers and related integrated circuits

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020012271A1 (en) * 2000-02-29 2002-01-31 Leonard Forbes Static NVRAM with ultra thin tunnel oxides
US6567066B1 (en) * 1999-02-16 2003-05-20 Nec Corporation Driving circuit of display device
US20030128575A1 (en) * 2002-01-04 2003-07-10 Kuo-Tso Chen Three-transistor sram device
US20080157128A1 (en) * 2006-09-14 2008-07-03 Johns Hopkins University Methods for producing multiple distinct transistors from a single semiconductor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726589A (en) * 1995-11-01 1998-03-10 International Business Machines Corporation Off-chip driver circuit with reduced hot-electron degradation
FR2764713B1 (fr) * 1997-06-11 1999-07-16 Commissariat Energie Atomique Procede de commande d'au moins un transistor du type igbt apte a permettre le fonctionnement de celui-ci sous irradiation
US6351160B1 (en) * 2000-12-06 2002-02-26 International Business Machines Corporation Method and apparatus for enhancing reliability of a high voltage input/output driver/receiver
JP3625194B2 (ja) * 2001-06-22 2005-03-02 松下電器産業株式会社 オフセット補償機能付きコンパレータおよびオフセット補償機能付きｄ／ａ変換装置
DE10392172B4 (de) * 2002-10-09 2016-10-06 Mitsubishi Denki K.K. Konstantstromschaltung, Treiberschaltung und Bildanzeigevorrichtung
WO2007091191A1 (fr) * 2006-02-10 2007-08-16 Koninklijke Philips Electronics N.V. circuits à film mince de grande surface
US8255850B2 (en) * 2008-01-21 2012-08-28 Texas Instruments Incorporated Fabricating IC with NBTI path delay within timing constraints

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6567066B1 (en) * 1999-02-16 2003-05-20 Nec Corporation Driving circuit of display device
US20020012271A1 (en) * 2000-02-29 2002-01-31 Leonard Forbes Static NVRAM with ultra thin tunnel oxides
US20030128575A1 (en) * 2002-01-04 2003-07-10 Kuo-Tso Chen Three-transistor sram device
US20080157128A1 (en) * 2006-09-14 2008-07-03 Johns Hopkins University Methods for producing multiple distinct transistors from a single semiconductor

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US8319561B2 (en) 2012-11-27
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