WO2011070766A1 - Dispositif d'affichage à plasma et procédé de commande d'un panneau d'affichage à plasma - Google Patents

Dispositif d'affichage à plasma et procédé de commande d'un panneau d'affichage à plasma Download PDF

Info

Publication number
WO2011070766A1
WO2011070766A1 PCT/JP2010/007098 JP2010007098W WO2011070766A1 WO 2011070766 A1 WO2011070766 A1 WO 2011070766A1 JP 2010007098 W JP2010007098 W JP 2010007098W WO 2011070766 A1 WO2011070766 A1 WO 2011070766A1
Authority
WO
WIPO (PCT)
Prior art keywords
determination
result
load value
value
output
Prior art date
Application number
PCT/JP2010/007098
Other languages
English (en)
Japanese (ja)
Inventor
朋之 齊藤
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to JP2011545081A priority Critical patent/JP5170322B2/ja
Priority to US13/513,999 priority patent/US20120242721A1/en
Priority to KR1020127010370A priority patent/KR101333471B1/ko
Priority to CN2010800551057A priority patent/CN102640204A/zh
Publication of WO2011070766A1 publication Critical patent/WO2011070766A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
    • G09G3/2927—Details of initialising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data

Definitions

  • the present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.
  • a typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other.
  • a front plate a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other.
  • a dielectric layer and a protective layer are formed so as to cover the display electrode pairs.
  • a plurality of parallel data electrodes are formed on a back glass substrate, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes.
  • the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.
  • the front plate and the back plate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed.
  • a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.
  • ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.
  • the subfield method is generally used as a method for driving the panel.
  • one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield.
  • Each subfield has an initialization period, an address period, and a sustain period.
  • an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell.
  • wall charges necessary for the subsequent address operation are formed, and priming particles (excitation particles for generating the address discharge) for generating the address discharge stably are generated.
  • scan pulses are sequentially applied to the scan electrodes (hereinafter, this operation is also referred to as “scan”), and the address pulses are selectively applied to the data electrodes based on the image signal to be displayed.
  • scan pulses are sequentially applied to the scan electrodes
  • the address pulses are selectively applied to the data electrodes based on the image signal to be displayed.
  • an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”).
  • the number of sustain pulses determined for each subfield is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode.
  • a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”. Also written as “lit”.)
  • each discharge cell emits light at a luminance corresponding to the luminance weight determined for each subfield.
  • each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed on the image display surface of the panel.
  • One of the subfield methods is the following drive method.
  • an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed in an initializing period of one subfield among a plurality of subfields, and in an initializing period of another subfield.
  • black luminance the luminance of the black display area where no sustain discharge is generated
  • the panel drive load tends to increase with the increase in screen size and resolution.
  • the difference in drive load generated between the display electrode pairs tends to increase, and the difference in voltage drop of the drive voltage also tends to increase.
  • the brightness of the image displayed on the panel is one of the important factors in judging the display quality of the image. Therefore, when an unnatural change occurs in the brightness of the display image, it may be recognized by the user as image quality degradation.
  • the plasma display device of the present invention includes a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode and a plurality of pixels each including a plurality of discharge cells that emit light of different colors, and an input. And an image signal processing circuit for converting the image signal into image data indicating lighting / non-lighting for each subfield in the discharge cell.
  • the image signal processing circuit calculates the number of discharge cells to be lit for each display electrode pair and for each subfield, and calculates the load value of each discharge cell based on the calculation result in the number of lighting cells calculation unit.
  • a load value calculation unit a correction gain calculation unit that calculates a correction gain of each discharge cell based on a calculation result in the load value calculation unit; a pattern detection unit that determines whether or not a loading phenomenon occurs in a display image; and a pattern detection unit A correction gain changing unit that changes the correction gain based on the determination result in, and a correction unit that subtracts the result obtained by multiplying the output of the correction gain changing unit and the input image signal from the input image signal.
  • the pattern detection unit divides the image display surface of the panel into a plurality of areas by comparing the gradation value assigned to each discharge cell between adjacent pixels and performing a correlation determination, and dividing the image display surface of the panel into a plurality of regions.
  • the load value fluctuation determination unit that calculates the sum of the load values in each of the regions and compares the load value between two adjacent regions to determine the load value fluctuation, and the correlation in the adjacent pixel correlation determination unit
  • a continuity determination unit that determines whether or not a loading phenomenon occurs in the display image based on the determination result and the load value fluctuation determination result;
  • the pattern detection unit determines whether or not the loading phenomenon occurs in the display image, and changes the correction gain output from the correction gain calculation unit based on the determination result, so that the loading phenomenon is expected to occur. It is possible to perform loading correction only when displaying. Therefore, it is possible to reduce unnecessary luminance changes in the display image and perform more accurate loading correction. As a result, it is possible to greatly improve the image display quality in the plasma display device using a large-screen, high-definition panel.
  • the panel driving method drives a panel including a plurality of discharge cells each having a pair of display electrodes each including a scan electrode and a sustain electrode and a plurality of pixels each including a plurality of discharge cells that emit light of different colors.
  • the number of discharge cells to be lit is calculated for each display electrode pair and for each subfield, and the load value of each discharge cell is calculated based on the number of discharge cells to be lit.
  • the correction gain of each discharge cell is calculated, the gradation value assigned to each discharge cell is compared between adjacent pixels to determine the correlation, and the image display surface of the panel is divided into a plurality of regions, The sum of the load values is calculated in each of the areas, the load value fluctuation is determined by comparing the sum of the load values between two adjacent areas, the correlation determination result and the load value fluctuation determination result are First, determine whether a loading phenomenon has occurred in the display image, change the correction gain based on the determination result, multiply the corrected correction gain by the input image signal, and subtract the multiplication result from the input image signal. Thus, the input image signal is corrected.
  • FIG. 1 is an exploded perspective view showing a structure of a panel according to an embodiment of the present invention.
  • FIG. 2 is an electrode array diagram of the panel according to the embodiment of the present invention.
  • FIG. 3 is a drive voltage waveform diagram applied to each electrode of the panel according to the embodiment of the present invention.
  • FIG. 4 is a circuit block diagram of the plasma display device in one embodiment of the present invention.
  • FIG. 5A is a schematic diagram for explaining a difference in light emission luminance caused by a change in driving load.
  • FIG. 5B is a schematic diagram for explaining a difference in light emission luminance caused by a change in driving load.
  • FIG. 6A is a diagram for schematically explaining the loading phenomenon.
  • FIG. 6B is a diagram for schematically explaining the loading phenomenon.
  • FIG. 6A is a diagram for schematically explaining the loading phenomenon.
  • FIG. 6C is a diagram for schematically explaining the loading phenomenon.
  • FIG. 6D is a diagram for schematically explaining the loading phenomenon.
  • FIG. 7 is a diagram for explaining the outline of loading correction according to an embodiment of the present invention.
  • FIG. 8 is a circuit block diagram of an image signal processing circuit in one embodiment of the present invention.
  • FIG. 9 is a schematic diagram for explaining a “load value” calculation method according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram for explaining a “maximum load value” calculation method according to the embodiment of the present invention.
  • FIG. 11 is a circuit block diagram of the pattern detection unit in one embodiment of the present invention.
  • FIG. 12 is a circuit block diagram of the adjacent pixel correlation determining unit according to the embodiment of the present invention.
  • FIG. 13 is a circuit block diagram of a load value variation determination unit in one embodiment of the present invention.
  • FIG. 14 is a schematic diagram for explaining an example of the operation of the load value variation determination unit in the embodiment of the present invention.
  • FIG. 15 is a circuit block diagram of the continuity determination unit in one embodiment of the present invention.
  • FIG. 16 is a circuit block diagram of the horizontal direction continuity determination unit in one embodiment of the present invention.
  • FIG. 17 is a circuit block diagram of the vertical direction continuity determination unit according to the embodiment of the present invention.
  • FIG. 18 is a schematic diagram for explaining an example of the operation of the vertical continuity determination unit in the embodiment of the present invention.
  • FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention.
  • a plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21.
  • a dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.
  • the protective layer 26 is made of a material mainly composed of magnesium oxide (MgO).
  • a plurality of data electrodes 32 are formed on the rear substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon.
  • a phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.
  • the front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween.
  • the outer peripheral part is sealed with sealing materials, such as glass frit.
  • a mixed gas of neon and xenon is sealed in the discharge space inside as a discharge gas.
  • a discharge gas having a xenon partial pressure of about 10% is used to improve luminous efficiency.
  • the discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32.
  • a color image is displayed on the panel 10 by discharging and emitting (lighting) these discharge cells.
  • R red
  • G green
  • B blue discharge cells
  • the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.
  • the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.
  • FIG. 2 is an electrode array diagram of panel 10 according to an embodiment of the present invention.
  • the panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction.
  • M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged.
  • m ⁇ n discharge cells are formed in the discharge space, and a region where m ⁇ n discharge cells are formed becomes an image display surface of the panel 10.
  • the plasma display device in this embodiment performs gradation display by a subfield method.
  • the subfield method one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield.
  • An image is displayed on the panel 10 by controlling light emission / non-light emission of each discharge cell for each subfield.
  • one field is composed of eight subfields (first SF, second SF,..., Eighth SF), and each subfield is set so that the luminance weight becomes larger in the later subfield.
  • each subfield is set so that the luminance weight becomes larger in the later subfield.
  • the R signal, the G signal, and the B signal can be displayed with 256 gradations from 0 to 255, respectively.
  • an initializing operation is performed in all the cells to generate an initializing discharge in the initializing period of one subfield, and an immediately preceding period is set in the initializing period of the other subfield.
  • a selective initializing operation for selectively generating an initializing discharge is performed on a discharge cell that has generated a sustaining discharge in the sustain period of the subfield.
  • the all-cell initialization operation is performed in the initialization period of the first SF and the selective initialization operation is performed in the initialization period of the second SF to the eighth SF.
  • the light emission not related to the image display is only the light emission due to the discharge of the all-cell initializing operation in the first SF. Therefore, the black luminance, which is the luminance of the black display region where no sustain discharge occurs, is only weak light emission in the all-cell initialization operation, and an image with high contrast can be displayed on the panel 10.
  • the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined proportional constant is applied to each display electrode pair 24.
  • This proportionality constant is the luminance magnification.
  • the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above values.
  • the structure which switches a subfield structure based on an image signal etc. may be sufficient.
  • FIG. 3 is a waveform diagram of drive voltage applied to each electrode of panel 10 in one embodiment of the present invention.
  • scan electrode SC1 that performs the address operation first in the address period
  • scan electrode SCn that performs the address operation last in the address period
  • sustain electrode SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm are applied.
  • a drive voltage waveform is shown.
  • FIG. 3 shows driving voltage waveforms of two subfields.
  • the two subfields are a first subfield (first SF) that is an all-cell initializing subfield and a second subfield (second SF) that is a selective initializing subfield.
  • the drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses generated in the sustain period is different.
  • scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the electrodes based on image data (data indicating lighting / non-lighting for each subfield).
  • the first SF which is an all-cell initialization subfield, will be described.
  • 0 (V) is applied to each of the data electrode D1 to the data electrode Dm and the sustain electrode SU1 to the sustain electrode SUn.
  • Voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn.
  • Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
  • a ramp waveform voltage that gently rises from voltage Vi1 to voltage Vi2 is applied to scan electrode SC1 through scan electrode SCn.
  • this ramp waveform voltage is referred to as “up-ramp voltage L1”.
  • Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
  • An example of the gradient of the up-ramp voltage L1 is a numerical value of about 1.3 V / ⁇ sec.
  • the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.
  • a scan pulse of voltage Va is sequentially applied to scan electrode SC1 through scan electrode SCn.
  • a write pulse of a positive voltage Vd is applied to m).
  • the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference between the externally applied voltages (voltage Vd ⁇ voltage Va). It will be added.
  • the voltage difference between data electrode Dk and scan electrode SC1 exceeds the discharge start voltage, and a discharge is generated between data electrode Dk and scan electrode SC1.
  • the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (voltage Ve2 ⁇ voltage Va) and sustain electrode SU1.
  • the difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added.
  • the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do.
  • a discharge generated between the data electrode Dk and the scan electrode SC1 can be triggered to generate a discharge between the sustain electrode SU1 and the scan electrode SC1 in the region intersecting the data electrode Dk.
  • an address discharge is generated in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Is accumulated.
  • an address operation is performed in which an address discharge is generated in the discharge cells that should emit light in the first row and a wall voltage is accumulated on each electrode.
  • the voltage at the intersection between the data electrode 32 and the scan electrode SC1 to which the address pulse is not applied does not exceed the discharge start voltage, so the address discharge does not occur.
  • the address operation described above is performed until the discharge cell in the n-th row, and the address period ends.
  • sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cell that has generated the address discharge, and the discharge cell emits light.
  • a sustain pulse of positive voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn.
  • the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi added to sustain pulse voltage Vs. It will be a thing.
  • the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. Then, the phosphor layer 35 emits light by the ultraviolet rays generated by this discharge. Further, due to this discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.
  • 0 (V) as a base potential is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse is applied to sustain electrode SU1 through sustain electrode SUn.
  • the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage.
  • a sustain discharge is generated again between sustain electrode SUi and scan electrode SCi, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi.
  • the number of sustain pulses obtained by multiplying the luminance weight by the luminance magnification is alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. By doing so, sustain discharge is continuously generated in the discharge cells that have generated address discharge in the address period.
  • 0 (V) is applied to scan electrode SC1 to scan electrode SCn while 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm.
  • 0 (V) is applied to scan electrode SC1 to scan electrode SCn while 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm.
  • this ramp waveform voltage is referred to as “erasing ramp voltage L3”.
  • the erasing ramp voltage L3 is set to a steeper slope than the rising ramp voltage L1.
  • a numerical value of about 10 V / ⁇ sec can be cited.
  • the charged particles generated by the weak discharge are accumulated on the sustain electrode SUi and the scan electrode SCi so as to alleviate the voltage difference between the sustain electrode SUi and the scan electrode SCi. Therefore, in the discharge cell in which the sustain discharge has occurred, part or all of the wall voltage on scan electrode SCi and sustain electrode SUi is erased while leaving the positive wall charge on data electrode Dk. That is, the discharge generated by the erasing ramp voltage L3 functions as an “erasing discharge” for erasing unnecessary wall charges accumulated in the discharge cell in which the sustain discharge has occurred.
  • a drive voltage waveform in which the first half of the initialization period in the first SF is omitted is applied to each electrode.
  • Voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm.
  • Scan electrode SC1 through scan electrode SCn are applied with down-ramp voltage L4 that gently falls from voltage Vi3 ′ (eg, 0 (V)) that is less than the discharge start voltage toward negative voltage Vi4 that exceeds the discharge start voltage. .
  • voltage Vi3 ′ eg, 0 (V)
  • a numerical value of about ⁇ 2.5 V / ⁇ sec can be given.
  • the initializing operation in the second SF is a selective initializing operation in which initializing discharge is generated for the discharge cells that have generated sustain discharge in the sustain period of the immediately preceding subfield.
  • a drive voltage waveform similar to that in the first SF address period and sustain period is applied to each electrode.
  • the same drive voltage waveform as that of the second SF is applied to each electrode except for the number of sustain pulses.
  • FIG. 4 is a circuit block diagram of plasma display device 1 according to one embodiment of the present invention.
  • the plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).
  • the image signal processing circuit 41 assigns a gradation value to each discharge cell based on the input image signal sig. Then, the gradation value is converted into image data indicating light emission / non-light emission for each subfield.
  • each gradation value of R, G, and B is assigned to each discharge cell based on the R signal, the G signal, and the B signal.
  • the input image signal sig includes a luminance signal (Y signal) and a saturation signal (C signal, RY signal and BY signal, or u signal and v signal)
  • the luminance signal and Based on the saturation signal, R signal, G signal, and B signal are calculated, and then R, G, and B gradation values (gradation values expressed in one field) are assigned to each discharge cell.
  • the R, G, and B gradation values assigned to each discharge cell are converted into image data indicating light emission / non-light emission for each subfield.
  • the image signal processing circuit 41 performs correction called “loading correction” on the image signal.
  • the image signal processing circuit 41 assigns R, G, and B image data to each discharge cell based on the image signal after the correction.
  • the timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V. Then, the generated timing signal is supplied to each circuit block (image signal processing circuit 41, data electrode drive circuit 42, scan electrode drive circuit 43, sustain electrode drive circuit 44, etc.).
  • Scan electrode drive circuit 43 has an initialization waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown).
  • the initialization waveform generating circuit generates an initialization waveform to be applied to scan electrode SC1 through scan electrode SCn during the initialization period.
  • the sustain pulse generating circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn during the sustain period.
  • the scan pulse generating circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period.
  • Scan electrode driving circuit 43 drives scan electrode SC1 through scan electrode SCn based on the timing signal supplied from timing generation circuit 45, respectively.
  • the data electrode drive circuit 42 converts the data for each subfield constituting the image data into signals corresponding to the data electrodes D1 to Dm. Then, based on the signal and the timing signal supplied from the timing generation circuit 45, the data electrodes D1 to Dm are driven.
  • Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit for generating voltage Ve1 and voltage Ve2 (not shown). Based on the timing signal supplied from timing generation circuit 45, sustain electrode SU1 to sustain electrode SUn are provided. To drive.
  • FIG. 5A and 5B are schematic diagrams for explaining a difference in light emission luminance caused by a change in driving load.
  • FIG. 5A shows an ideal display image when an image generally called a “window pattern” is displayed on the panel 10.
  • the region B and the region D shown in the drawing are regions having the same signal level (for example, 20%), and the region C is a region having a lower signal level (for example, 5%) than the region B and the region D.
  • the “signal level” used in this embodiment may be a gradation value of a luminance signal, or may be a gradation value of an R signal, a gradation value of a B signal, or a gradation value of a G signal. There may be.
  • FIG. 5B is a diagram schematically showing a display image when the “window pattern” shown in FIG. 5A is displayed on the panel 10, and a diagram showing a signal level 201 and a light emission luminance 202.
  • the display electrode pairs 24 are arranged so as to extend in the row direction (direction parallel to the long side of the panel 10 and in the horizontal direction in the drawing) as in the panel 10 shown in FIG. Shall.
  • 5B shows the signal level of the image signal in the line A1-A1 shown in the panel 10 of FIG. 5B.
  • the horizontal axis represents the magnitude of the signal level of the image signal
  • the vertical axis Represents the display position of the panel 10 along the line A1-A1.
  • 5B indicates the emission luminance of the display image along the line A1-A1 of the panel 10.
  • the horizontal axis indicates the emission luminance of the display image
  • the vertical axis indicates the panel 10.
  • the display position on the A1-A1 line is shown.
  • the region B and the region D have the same signal level as shown in the light emission luminance 202. There may be a difference in emission luminance between the region B and the region D. This is considered to be due to the following reasons.
  • the display electrode pairs 24 are arranged extending in the row direction (direction parallel to the long side of the panel 10, in the horizontal direction in the drawing). Therefore, as shown in the panel 10 of FIG. 5B, when the “window pattern” is displayed on the panel 10, a display electrode pair 24 that passes through only the region B and a display electrode pair 24 that passes through the region C and the region D are generated.
  • the display electrode pair 24 passing through the region C and the region D is smaller in driving load than the display electrode pair 24 passing through the region B. This is because the region C has a lower signal level and lower emission luminance than the region B, so that the discharge current flowing through the display electrode pair 24 passing through the region C and the region D is the display electrode pair 24 passing through the region B. This is because it is less than the discharge current flowing through the.
  • the voltage drop of the drive voltage is smaller in the display electrode pair 24 passing through the region C and the region D than in the display electrode pair 24 passing through the region B. Therefore, for example, regarding the sustain pulse, the voltage drop in the display electrode pair 24 passing through the region C and the region D is smaller than that in the display electrode pair 24 passing through the region B.
  • the sustain discharge in the discharge cells included in the region D has a higher discharge intensity than the sustain discharge in the discharge cells included in the region B, and the region D is more in spite of the same signal level. It is considered that the emission luminance is higher than that in the region B.
  • a phenomenon is referred to as a “loading phenomenon”. That is, the loading phenomenon is a phenomenon in which the light emission luminance of the discharge cells is different for each row due to the difference in the driving load of the display electrode pair 24 that occurs for each row.
  • FIG. 6A, 6B, 6C, and 6D are diagrams for schematically explaining the loading phenomenon.
  • the “window pattern” the area of the region C having a low signal level is gradually changed and displayed on the panel 10.
  • FIG. It is the figure which showed schematically the display image when it did.
  • the region D1 in FIG. 6A, the region D2 in FIG. 6B, the region D3 in FIG. 6C, and the region D4 in FIG. 6D each have the same signal level (for example, 20%) as the region B.
  • the region C2 in 6B, the region C3 in FIG. 6C, and the region C4 in FIG. 6D have the same signal level (for example, 5%).
  • the display electrode pair 24 that passes through the region C and the region D as the area of the region C1, the region C2, the region C3, the region C4, and the region C increases.
  • the driving load is reduced.
  • the discharge intensity of the discharge cells included in the region D gradually increases, and the light emission luminance in the region D gradually increases to the region D1, the region D2, the region D3, and the region D4.
  • the increase in light emission luminance due to the loading phenomenon changes as the drive load varies.
  • the purpose of this embodiment is to reduce this loading phenomenon and to improve the image display quality in the plasma display device 1. Note that processing performed to reduce the loading phenomenon is hereinafter referred to as “loading correction”.
  • FIG. 7 is a diagram for explaining an outline of the loading correction in the embodiment of the present invention, and schematically shows a display image when the “window pattern” shown in FIG. 5A is displayed on the panel 10. It is a figure which shows the figure, the signal level 211, the signal level 212, and the light emission luminance 213. 7 schematically shows the display image when the “window pattern” shown in FIG. 5A is displayed on the panel 10 after performing the loading correction in the present embodiment. It is a thing. 7 indicates the signal level of the image signal on the line A2-A2 shown in the panel 10 of FIG. 7, and the horizontal axis indicates the magnitude of the signal level of the image signal. Represents the display position of the panel 10 along the line A2-A2. Further, the signal level 212 in FIG.
  • 7 shows the signal level on the A2-A2 line of the image signal after performing the loading correction in the present embodiment, and the horizontal axis indicates the signal of the image signal after the loading correction.
  • the level represents the level
  • the vertical axis represents the display position of the panel 10 along the line A2-A2.
  • 7 indicates the light emission luminance of the display image along the line A2-A2 of the panel 10.
  • the horizontal axis indicates the light emission luminance of the display image
  • the vertical axis indicates the panel 10. This represents the display position on the line A2-A2.
  • a correction value based on the driving load of the display electrode pair 24 passing through the discharge cell is calculated, and loading correction is performed by correcting the image signal.
  • the region B and the region D have the same signal level, but the display electrode pair 24 passing through the region D also passes through the region C. It can be determined that the driving load is small. Therefore, the signal level in region D is corrected as indicated by signal level 212 in FIG. Accordingly, as shown by the light emission luminance 213 in FIG. 7, the magnitudes of the light emission luminances of the region B and the region D in the display image are matched to reduce the loading phenomenon.
  • the loading phenomenon is reduced by correcting the image signal in the region where the loading phenomenon is expected to occur and reducing the light emission luminance in the display image in the region.
  • the pattern detection unit to be described later determines whether or not a loading phenomenon has occurred in the display image, and based on the result, changes are made to the correction gain used for the loading correction and the loading correction is performed.
  • the loading correction in this embodiment will be described in detail.
  • FIG. 8 is a circuit block diagram of the image signal processing circuit 41 according to the embodiment of the present invention.
  • FIG. 8 shows blocks related to loading correction in the present embodiment, and other circuit blocks are omitted.
  • the image signal processing circuit 41 has a loading correction unit 70.
  • the loading correction unit 70 includes a lighting cell number calculation unit 60, a load value calculation unit 61, a correction gain calculation unit 62, a pattern detection unit 63, a selection circuit 64 that is a correction gain changing unit, a multiplier 68, And a correction unit 69.
  • the lighting cell number calculation unit 60 calculates the number of discharge cells to be lit for each display electrode pair 24 and for each subfield.
  • discharge cells that are lit are referred to as “lighted cells”, and discharge cells that are not lit are referred to as “non-lighted cells”.
  • the load value calculation unit 61 receives the calculation result from the lighting cell number calculation unit 60 and performs an operation based on the driving load calculation method in the present embodiment. This calculation is a calculation for calculating a “load value” and a “maximum load value” described later.
  • the correction gain calculation unit 62 calculates the correction gain based on the calculation result in the load value calculation unit 61.
  • the pattern detection unit 63 determines whether or not a loading phenomenon has occurred in the display image based on the calculation result in the image signal and the load value calculation unit 61, and outputs the determination result as a “continuity detection flag”. Details of the pattern detection unit 63 will be described later.
  • the selection circuit 64 serving as a correction gain changing unit changes the correction gain output from the correction gain calculating unit 62 based on the continuity detection flag output from the pattern detecting unit 63.
  • the pattern detection unit 63 determines that the loading phenomenon occurs in the display image, that is, when it is determined that the design that is expected to cause the loading phenomenon is included in the display image, the correction is performed.
  • the correction gain output from the gain calculation unit 62 is selected and output to the subsequent stage. When it is determined that this is not the case, “0” is selected instead of the correction gain output from the correction gain calculation unit 62 and the subsequent stage is selected. Output.
  • the pattern detection unit 63 sets the continuity detection flag to “1” when it is determined that a loading phenomenon occurs in the display image, and sets the continuity detection flag to “0” otherwise.
  • the multiplier 68 multiplies the output of the selection circuit 64 by the input image signal and outputs it as a correction signal.
  • the output of the selection circuit 64 is either the correction gain output from the correction gain calculation unit 62 or “0”.
  • the correction unit 69 subtracts the correction signal output from the multiplier 68 from the input image signal and outputs it as a corrected image signal.
  • this calculation is performed in the number-of-light-cells calculation unit 60, the load value calculation unit 61, and the correction gain calculation unit 62.
  • load value two numerical values called “load value” and “maximum load value” are calculated based on the calculation result in the lighting cell number calculation unit 60.
  • the “load value” and “maximum load value” are numerical values used for estimating the amount of occurrence of the loading phenomenon in the discharge cell.
  • load value in the present embodiment will be described with reference to FIG. 9, and subsequently, “maximum load value” in the present embodiment will be described with reference to FIG.
  • FIG. 9 is a schematic diagram for explaining a method of calculating the “load value” in one embodiment of the present invention, and schematically shows a display image when the “window pattern” shown in FIG. 5A is displayed on the panel 10.
  • FIG. 5 is a diagram showing a diagram, a lighting state 221 and a calculated value 222;
  • the lighting state 221 in FIG. 9 is a schematic diagram showing lighting / non-lighting of each discharge cell in the A3-A3 line shown in the panel 10 of FIG.
  • the display position in the A3-A3 line is represented, and the vertical column represents a subfield. “1” indicates lighting, and a blank indicates non-lighting.
  • FIG. 9 is a diagram schematically showing a method of calculating the “load value” in the present embodiment, and the horizontal columns are “lighted cell number”, “ “Luminance weight”, “Lighting state of discharge cell B”, “Calculated value” are represented, and the vertical column represents a subfield.
  • the number of discharge cells in the row direction is 15 in order to simplify the description. Therefore, the following description will be made assuming that 15 discharge cells are arranged on the line A3-A3 shown in the panel 10 of FIG. However, actually, the following calculations are performed in accordance with the number of discharge cells in the row direction of the panel 10 (for example, 1920 ⁇ 3).
  • the lighting state in each subfield of each of the 15 discharge cells arranged on the A3-A3 line shown in the panel 10 of FIG. 9 is as shown in the lighting state 221, for example. That is, in the central five discharge cells included in the region C shown in the panel 10 of FIG. 9, the first SF to the third SF are lit and the fourth SF to the eighth SF are not lit. In each of the five discharge cells, the first SF to the sixth SF are turned on, and the seventh SF and the eighth SF are not turned on.
  • the “load value” in one of the discharge cells is obtained as follows. .
  • the number of lighting cells in each subfield is calculated.
  • the number of lighting cells from the first SF to the third SF is “15”.
  • the number of lighting cells from the fourth SF to the sixth SF is “10”.
  • the number of lighting cells from the fourth SF to the sixth SF is “0”.
  • each column of “number of lighted cells” of the calculated value 222 of FIG. 9 is “15” from the first SF to the third SF, “10” from the fourth SF to the sixth SF, and “7” for the seventh SF and the eighth SF is “ 0 ".
  • the number of lighting cells in each subfield thus obtained is multiplied by the luminance weight of each subfield and the lighting state of each subfield in the discharge cell B.
  • the result of this multiplication is the “calculated value” in the present embodiment.
  • the luminance weights of the subfields are sequentially (1, 2, 4,...) From the first SF to the eighth SF, as shown in each column of “luminance weight” of the calculated value 222 in FIG. 8, 16, 32, 64, 128). In this embodiment, lighting is “1” and non-lighting is “0”.
  • the lighting state in the discharge cell B is (1, 1, 1, 1, 1, 1, 1) in order from the first SF to the eighth SF, as shown in each column of the “lighting state of the discharge cell B” of the calculated value 222. , 0, 0).
  • the multiplication results are (15, 30, 60, 80, 160, 320, 0, 0) in order from the first SF to the eighth SF, as shown in each column of “calculated value” of the calculated value 222.
  • the sum total of those calculated values is calculated
  • FIG. 10 is a schematic diagram for explaining a “maximum load value” calculation method according to an embodiment of the present invention.
  • a display image when the “window pattern” shown in FIG. 5A is displayed on the panel 10 is shown.
  • FIG. 6 is a diagram schematically showing a lighting state 231 and a calculated value 232.
  • the lighting state 231 in FIG. 10 is a schematic diagram showing lighting / non-lighting for each subfield when the lighting state of the discharge cell B is applied to all the discharge cells on the line A4-A4 shown in the panel 10 of FIG.
  • the horizontal column represents the display position on line A4-A4 of panel 10, and the vertical column represents the subfield.
  • FIG. 10 is a diagram schematically showing a method of calculating the “maximum load value” in the present embodiment, and the horizontal columns are “lighted cell number”, “Luminance weight”, “lighting state of discharge cell B”, “calculated value” are represented, and the vertical column represents a subfield.
  • the “maximum load value” is calculated as follows. For example, when calculating the “maximum load value” in the discharge cell B, all the discharge cells on the line A4-A4 are lit in the same state as the discharge cell B as shown in the lighting state 231 of FIG. Assuming that the number of lighted cells for each subfield is calculated.
  • the lighting states of the subfields in the discharge cell B are sequentially (1, 1, 1,...) In order from the first SF to the eighth SF, as shown in each column of the “lighting state of the discharge cell B” of the calculated value 222 in FIG. 1, 1, 1, 0, 0).
  • the lighting state of all the discharge cells on the A4-A4 line is as shown in each column of the lighting state 231 in FIG. 10 from the first SF to the sixth SF. “1”, and the seventh SF and the eighth SF are “0”. Accordingly, the number of lighting cells is (15, 15, 15, 15, 15, 15, 0, in order from the first SF to the eighth SF, as shown in each column of “number of lighting cells” of the calculated value 232 of FIG. 0). However, in this embodiment, each discharge cell on the A4-A4 line is not actually put into the lighting state shown in the lighting state 231.
  • the lighting state shown in the lighting state 231 indicates a lighting state when it is assumed that each discharge cell is in the same lighting state as the discharge cell B in order to calculate the “maximum load value”.
  • the “number of lit cells” shown in FIG. 6 is the number of lit cells calculated on the assumption.
  • the number of lighting cells in each subfield thus obtained is multiplied by the luminance weight of each subfield and the lighting state of each subfield in the discharge cell B.
  • the luminance weights of the subfields are sequentially (1, 2, 1) from the first SF to the eighth SF as shown in each column of “luminance weight” of the calculated value 232 in FIG. 4, 8, 16, 32, 64, 128).
  • the lighting state in the discharge cell B is (1, 1, 1, 1, 1, 1, 1) in order from the first SF to the eighth SF as shown in each column of the “lighting state of the discharge cell B” of the calculated value 232. , 0, 0).
  • the result of the multiplication is sequentially (15, 30, 60, 120, 240, 480, 0, 0) from the first SF to the eighth SF. It becomes. Then, the sum of those calculated values is obtained. For example, in the example indicated by the calculated value 232 in FIG. 10, the total sum of the calculated values is “945”. This sum is the “maximum load value” in the discharge cell B. In the present embodiment, such a calculation is performed on each discharge cell, and a “maximum load value” is obtained for each discharge cell.
  • the “maximum load value” in the discharge cell B is obtained by multiplying the luminance weight of each subfield by the total number of discharge cells formed on the display electrode pair 24, and the multiplication result of each subfield in the discharge cell B. It is good also as a structure which multiplies each with a lighting state and calculates
  • the total number of discharge cells formed on the display electrode pair 24 is “15”, and the luminance weight of each subfield is (1, 2, 4, 8, 16, 32, 64, 128), and the lighting state of each subfield in the discharge cell B is (1, 1, 1, 1, 1, 1, 0, 0) in order from the first SF.
  • the multiplication results are (15, 30, 60, 120, 240, 480, 0, 0) in order from the first SF. Therefore, the sum of the multiplication results is “945”, and the same result as the above-described calculation is obtained.
  • the correction gain in each discharge cell is calculated using the numerical value obtained from the following equation (1).
  • the pattern detection unit 63 determines whether or not a loading phenomenon has occurred in the display image. First, the pattern detection unit 63 determines whether or not the display image includes a symbol in which a loading phenomenon is likely to occur (a symbol in which a loading phenomenon is expected to occur). When it is determined that the display image includes a symbol that is likely to cause a loading phenomenon, it is determined that a loading phenomenon occurs in the display image, and a continuity detection flag that is a signal representing the determination result is set to “1”. " If it is determined that a symbol that is likely to cause a loading phenomenon is not included in the display image, it is determined that the loading phenomenon does not occur in the display image, and the continuity detection flag is set to “0”.
  • Correction gain after change Correction gain x Continuity detection flag Equation (3) Therefore, in equation (3), the post-change correction gain is either the correction gain calculated in equation (2) or “0”. Therefore, in this embodiment, the selection circuit 64 that is the correction gain changing unit is connected to the correction gain output from the correction gain calculating unit 62 when the continuity detection flag is “1” as shown in FIG. Is selected and output to the subsequent stage. When the continuity detection flag is “0”, “0” is selected and output to the subsequent stage.
  • the post-change correction gain is substituted into the following equation (4) to correct the input image signal.
  • Output image signal input image signal ⁇ input image signal ⁇ corrected correction gain (4)
  • the driving load of the scan electrode 22 and the sustain electrode 23 tends to increase.
  • the difference of the drive load between the display electrode pairs 24 tends to become large depending on the design of the display image, and the loading phenomenon tends to occur.
  • the “load value” and the “maximum load value” are calculated and used for calculating the correction gain for loading correction.
  • the minimum value or the intermediate value may be used as the correction gain of the pixel.
  • the pattern detection unit 63 determines whether or not a loading phenomenon has occurred in the display image, and based on the continuity detection flag indicating the determination result, the correction gain is changed as shown in Equation (3). To make the corrected gain after change. Then, as shown in Expression (4), loading correction is performed using the corrected gain after change.
  • the continuity detection flag is "1”
  • the display image is subjected to loading correction, and when it is not, that is, the continuity detection flag.
  • “0” is “0”
  • the input image signal is multiplied by the post-change correction gain and subtracted from the input image signal. Therefore, the brightness of the display image may change between when no loading correction is performed and when loading correction is performed.
  • the loading correction can be performed only when displaying an image determined to cause the loading phenomenon, an unnecessary luminance change in the display image is reduced, and the image display quality is further improved. It becomes possible.
  • FIG. 11 is a circuit block diagram of the pattern detection unit 63 according to the embodiment of the present invention.
  • the pattern detection unit 63 includes an adjacent pixel correlation determination unit 90, a load value variation determination unit 91, and a continuity determination unit 92.
  • the adjacent pixel correlation determining unit 90 compares the gradation values assigned to each discharge cell between adjacent pixels, and determines whether or not the correlation between adjacent pixels is high.
  • the load value variation determination unit 91 divides the image display surface of the panel 10 into a plurality of regions, calculates the sum of the load values in each of the plurality of regions based on the load values calculated by the load value calculation unit 61, The load value fluctuation determination is performed by comparing the sum of the load values between the areas to be performed.
  • the continuity determination unit 92 determines whether or not a loading phenomenon has occurred in the display image based on the correlation determination result in the adjacent pixel correlation determination unit 90 and the load value variation determination result in the load value variation determination unit 91. To do.
  • FIG. 12 is a circuit block diagram of the adjacent pixel correlation determining unit 90 according to the embodiment of the present invention.
  • the adjacent pixel correlation determination unit 90 includes a horizontal adjacent pixel correlation determination unit 51, a vertical adjacent pixel correlation determination unit 52, an RGB level determination unit 53 that is a gradation level determination unit, a delay circuit 126, and an AND gate. 125, a gradation value is compared between one pixel (hereinafter also referred to as “target pixel”) and a pixel adjacent to the pixel, and correlation determination is performed on the target pixel.
  • target pixel one pixel
  • correlation determination is performed on the target pixel.
  • the horizontal adjacent pixel correlation determination unit 51 includes a delay circuit 101, a delay circuit 104, a delay circuit 107, a subtraction circuit 102, a subtraction circuit 105, a subtraction circuit 108, a comparison circuit 103, a comparison circuit 106, A comparison circuit 109 and an AND gate 110 are included. Then, regarding two pixels of a pixel of interest and a pixel adjacent to a direction in which the display electrode pair 24 extends with respect to the pixel (hereinafter referred to as “horizontal direction”), a gradation value between discharge cells of the same color And the horizontal adjacent pixel correlation is determined by comparing each difference with the horizontal adjacent pixel threshold value.
  • the delay circuit 101 delays the red signal (R signal) of the image signal by one pixel.
  • the delay of one pixel can be expressed as, for example, a time obtained by dividing the time of one field of the image signal by the number of pixels constituting the panel 10 (for example, 1920 ⁇ 1080 pixels).
  • the subtraction circuit 102 subtracts the gradation value of the R signal delayed by the delay circuit 101 from the gradation value of the R signal, and outputs the absolute value of the subtraction result. This makes it possible to calculate the difference between the gradation values assigned to the R discharge cells of two pixels arranged adjacent to each other in the horizontal direction.
  • the comparison circuit 103 compares the output of the subtraction circuit 102 with a predetermined horizontal adjacent pixel threshold value. Then, “1” is output when the output of the subtraction circuit 102 is equal to or smaller than the horizontal adjacent pixel threshold value, and “0” is output otherwise. Thereby, it is possible to determine whether or not the R signal gradation values are highly correlated with respect to the R discharge cells of two pixels adjacent in the horizontal direction (whether the gradation values are similar to each other).
  • the delay circuit 104 delays the green signal (G signal) of the image signal by one pixel.
  • the subtraction circuit 105 subtracts the gradation value of the G signal delayed by the delay circuit 104 from the gradation value of the G signal, and outputs the absolute value of the subtraction result. This makes it possible to calculate the difference between the gradation values assigned to the G discharge cells of two pixels lined up adjacent in the horizontal direction.
  • the comparison circuit 106 compares the output of the subtraction circuit 105 with the horizontal adjacent pixel threshold value. Then, “1” is output when the output of the subtraction circuit 105 is equal to or smaller than the horizontal adjacent pixel threshold value, and “0” is output otherwise. As a result, it is possible to determine whether or not the G signal gradation value is highly correlated with respect to the G discharge cells of two pixels adjacent in the horizontal direction.
  • the delay circuit 107 delays the blue signal (B signal) in the image signal by one pixel.
  • the subtraction circuit 108 subtracts the gradation value of the B signal delayed by the delay circuit 107 from the gradation value of the B signal, and outputs the absolute value of the subtraction result. As a result, the difference between the gradation values assigned to the B discharge cells of the two pixels arranged adjacent to each other in the horizontal direction can be calculated.
  • the comparison circuit 109 compares the output of the subtraction circuit 108 with the horizontal adjacent pixel threshold value. Then, “1” is output when the output of the subtraction circuit 108 is equal to or smaller than the horizontal adjacent pixel threshold value, and “0” is output otherwise. As a result, it is possible to determine whether or not the B signal gradation value is highly correlated with respect to the B discharge cells of two pixels adjacent in the horizontal direction.
  • the AND gate 110 performs an AND operation on the output of the comparison circuit 103, the output of the comparison circuit 106, and the output of the comparison circuit 109. Therefore, the AND gate 110 outputs “1” when all the outputs of the comparison circuit 103, the comparison circuit 106, and the comparison circuit 109 are “1”, and outputs “0” otherwise.
  • the output of the AND gate 110 that is, the output of the horizontal adjacent pixel correlation determination unit 51 is the R discharge cell, the G discharge cell, and the two pixels of the pixel of interest and the pixel adjacent to the pixel in the horizontal direction. In any of the B discharge cells, “1” is obtained when the gradation value is highly correlated, and “0” is otherwise obtained. In this way, the horizontal adjacent pixel correlation determination unit 51 performs horizontal adjacent pixel correlation determination as to whether or not the correlation between two pixels adjacent in the horizontal direction is high.
  • the vertical adjacent pixel correlation determination unit 52 includes a delay circuit 111, a delay circuit 114, a delay circuit 117, a subtraction circuit 112, a subtraction circuit 115, a subtraction circuit 118, a comparison circuit 113, a comparison circuit 116, A comparison circuit 119 and an AND gate 120 are included. Then, regarding two pixels of the pixel of interest and a pixel adjacent to the pixel in a direction orthogonal to the display electrode pair 24 (hereinafter referred to as “vertical direction”), a gradation value between discharge cells of the same color Are compared, and the vertical adjacent pixel correlation determination is performed by comparing each difference with the vertical adjacent pixel threshold value.
  • the delay circuit 111 delays the R signal by one horizontal synchronization period.
  • the subtracting circuit 112 subtracts the gradation value of the R signal delayed by the delay circuit 111 from the gradation value of the R signal, and outputs the absolute value of the subtraction result. As a result, the difference between the gradation values assigned to the R discharge cells of the two pixels arranged adjacent to each other in the vertical direction can be calculated.
  • the comparison circuit 113 compares the output of the subtraction circuit 112 with a predetermined vertical adjacent pixel threshold value. Then, “1” is output when the output of the subtraction circuit 112 is equal to or less than the vertical adjacent pixel threshold value, and “0” is output otherwise. As a result, it is possible to determine whether or not the R signal gradation value is highly correlated with respect to the R discharge cells of two pixels adjacent in the vertical direction.
  • the delay circuit 114 delays the G signal by one horizontal synchronization period.
  • the subtraction circuit 115 subtracts the gradation value of the G signal delayed by the delay circuit 114 from the gradation value of the G signal, and outputs the absolute value of the subtraction result. This makes it possible to calculate the difference between the gradation values assigned to the G discharge cells of the two pixels arranged adjacent to each other in the vertical direction.
  • the comparison circuit 116 compares the output of the subtraction circuit 115 with the vertical adjacent pixel threshold value. Then, “1” is output when the output of the subtraction circuit 115 is equal to or less than the vertical adjacent pixel threshold value, and “0” is output otherwise. Thereby, it is possible to determine whether or not the G signal gradation value is highly correlated with respect to the G discharge cells of two pixels adjacent in the vertical direction.
  • the delay circuit 117 delays the B signal by one horizontal synchronization period.
  • the subtraction circuit 118 subtracts the gradation value of the B signal delayed by the delay circuit 117 from the gradation value of the B signal, and outputs the absolute value of the subtraction result. As a result, the difference between the gradation values assigned to the B discharge cells of the two pixels arranged adjacent to each other in the vertical direction can be calculated.
  • the comparison circuit 119 compares the output of the subtraction circuit 118 with the vertical adjacent pixel threshold value. Then, “1” is output when the output of the subtraction circuit 118 is equal to or less than the vertical adjacent pixel threshold value, and “0” is output otherwise. As a result, it is possible to determine whether or not the B signal gradation value is highly correlated with respect to the B discharge cells of two pixels adjacent in the vertical direction.
  • the AND gate 120 performs an AND operation on the output of the comparison circuit 113, the output of the comparison circuit 116, and the output of the comparison circuit 119. Therefore, the AND gate 120 outputs “1” when all the outputs of the comparison circuit 113, the comparison circuit 116, and the comparison circuit 119 are “1”, and outputs “0” otherwise.
  • the output of the AND gate 120 that is, the output of the vertical adjacent pixel correlation determination unit 52 is the R discharge cell, the G discharge cell, the two pixels of the pixel of interest and the pixel vertically adjacent to the pixel. In any of the B discharge cells, “1” is obtained when the gradation value is highly correlated, and “0” is otherwise obtained. In this manner, the vertical adjacent pixel correlation determination unit 52 performs vertical adjacent pixel correlation determination as to whether or not the correlation between two pixels adjacent in the vertical direction is high.
  • the RGB level determination unit 53 includes a comparison circuit 121, a comparison circuit 122, a comparison circuit 123, and an OR gate 124. Then, regarding the three discharge cells constituting the target pixel, the level determination is performed by comparing the gradation value assigned to each discharge cell with the level determination threshold value.
  • the comparison circuit 121 compares the gradation value of the R signal with a predetermined level determination threshold value. Then, “1” is output when the gradation value of the R signal is equal to or higher than the level determination threshold value, and “0” is output otherwise.
  • the comparison circuit 122 compares the gradation value of the G signal with the level determination threshold value. Then, “1” is output when the gradation value of the G signal is equal to or higher than the level determination threshold value, and “0” is output otherwise.
  • the comparison circuit 123 compares the gradation value of the B signal with the level determination threshold value. Then, “1” is output when the gradation value of the B signal is equal to or higher than the level determination threshold value, and “0” is output otherwise.
  • the OR gate 124 performs an OR operation on the output of the comparison circuit 121, the output of the comparison circuit 122, and the output of the comparison circuit 123. Therefore, the OR gate 124 outputs “1” when at least one of the outputs of the comparison circuit 121, the comparison circuit 122, and the comparison circuit 123 is “1”, and outputs “0” otherwise. Accordingly, the output of the OR gate 124, that is, the output of the RGB level determination unit 53, is determined by at least one of the gradation values assigned to the discharge cells of the R discharge cell, the G discharge cell, and the B discharge cell. It is “1” for pixels that are greater than or equal to the threshold value, and “0” for pixels that are not. In this way, the RGB level determination unit 53 determines the level of the target pixel.
  • the delay circuit 126 delays the output of the vertical adjacent pixel correlation determination unit 52 by one pixel.
  • the AND gate 125 outputs the output of the horizontal adjacent pixel correlation determination unit 51, that is, the result of the horizontal adjacent pixel correlation determination in the horizontal adjacent pixel correlation determination unit 51, and the output of the vertical adjacent pixel correlation determination unit 52, that is, The result of the vertical adjacent pixel correlation determination in the vertical adjacent pixel correlation determination unit 52, the output of the RGB level determination unit 53, that is, the result of the level determination in the RGB level determination unit 53, and the output of the delay circuit 126, that is, the vertical adjacent pixel An AND operation is performed on the result of the vertical adjacent pixel correlation determination in the correlation determination unit 52 with the result delayed by one pixel. Therefore, the AND gate 125 outputs “1” when the outputs of the horizontal adjacent pixel correlation determination unit 51, vertical adjacent pixel correlation determination unit 52, RGB level determination unit 53, and delay circuit 126 are all “1”. Otherwise, “0” is output.
  • the output of the AND gate 125 that is, the output of the adjacent pixel correlation determination unit 90 is the R discharge cell and the G discharge for the two pixels of the pixel of interest and the pixel adjacent to the pixel in the horizontal direction.
  • Both the cell and the B discharge cell have high gradation value correlation, and the R discharge cell, the G discharge cell, the two pixels of the pixel of interest and the pixel adjacent to the pixel in the vertical direction,
  • the R discharge cell has high correlation between gradation values, and the two pixels, which are a pixel adjacent to the target pixel in the horizontal direction and a pixel adjacent to the pixel in the vertical direction.
  • the gradation value is highly correlated in any of the G discharge cell and the B discharge cell, and the gradation value is determined in the level of at least one of the R discharge cell, the G discharge cell, and the B discharge cell of the target pixel.
  • This is “correlation determination” in the adjacent pixel correlation determination unit 90.
  • the adjacent pixel correlation determination unit 90 performs this correlation determination on all the pixels constituting the image display surface of the panel 10 and outputs the result of the correlation determination for each pixel.
  • the result of the correlation determination (the output of the adjacent pixel correlation determination unit 90) is referred to as an “adjacent pixel correlation flag”.
  • the reason why the above-described correlation determination is performed in the adjacent pixel correlation determination unit 90 is to determine whether or not such a design is included in the display image.
  • the horizontal adjacent pixel threshold value is set to 5% of the maximum gradation value
  • the vertical adjacent pixel threshold value is set to 5% of the maximum gradation value
  • each threshold value is not limited to these numerical values.
  • Each threshold value is preferably set optimally based on the characteristics of the panel 10, the specifications of the plasma display device 1, a visual test of a display image, an experiment for displaying an image on which a loading phenomenon easily occurs on the panel 10, and the like.
  • FIG. 13 is a circuit block diagram of the load value fluctuation determining unit 91 according to the embodiment of the present invention.
  • the load value variation determination unit 91 includes a region load value variation determination unit 54, an adder circuit 138, and a comparison circuit 139. Then, the load value fluctuation determination is performed by comparing the sum of the load values between two regions adjacent in the vertical direction.
  • a set of all pixels formed on one display electrode pair 24 is referred to as one line.
  • the load value fluctuation determining unit 91 sets a plurality of areas on one display electrode pair 24. Specifically, one line is divided into a plurality of regions so that the number of pixels in each region is equal. Then, the sum of the load values is calculated in each region, and the region load value fluctuation determination is performed by comparing the sum of the load values between two regions adjacent in the vertical direction. Therefore, it is assumed that the load value variation determination unit 91 has the same number of region load value variation determination units 54 as the number of regions set for one line. In the present embodiment, one line is divided into 16 regions (region (1) to region (16)), and the load value variation determining unit 91 includes 16 region load value variation determining units 54 (region load).
  • region load value variation determination unit 54 (1) that performs region load value variation determination regarding the region (1) will be described as an example.
  • the region load value fluctuation determination unit 54 (1) includes a load value sum calculation circuit 130 (1), a delay circuit 131, a subtraction circuit 132, a comparison circuit 133, a comparison circuit 134, a comparison circuit 135, and an OR gate 136. And an AND gate 137, and the region load value fluctuation determination in the region (1) is performed.
  • the load value total calculation circuit 130 (1) integrates the load values output from the load value calculation unit 61 in one area (area (1)) obtained by dividing one line into 16 areas. The sum of the load values in 1) is calculated.
  • the delay circuit 131 delays the output of the load value sum calculation circuit 130 (1) by one horizontal synchronization period.
  • the subtraction circuit 132 subtracts the output of the load value sum calculation circuit 130 (1) delayed by the delay circuit 131 from the output of the load value sum calculation circuit 130 (1), and outputs the absolute value of the subtraction result. Thereby, in two regions arranged adjacent to each other in the vertical direction, the difference between the sums of the load values in each region, that is, the amount of change in the sum of the load values can be calculated.
  • the comparison circuit 135 compares the output of the subtraction circuit 132 with a predetermined load value fluctuation threshold value. Then, “1” is output when the output of the subtraction circuit 132 is equal to or greater than the load value fluctuation threshold value, and “0” is output otherwise. As a result, the total sum of the load values changed greatly (over the load value fluctuation threshold) between the two regions, the region (1) and the region (1) ′ adjacent to the region (1) in the vertical direction. It can be determined whether or not.
  • the comparison circuit 133 compares the output of the load value sum calculation circuit 130 (1) with the load value level threshold value. Then, “1” is output when the output of the load value sum calculation circuit 130 (1) is equal to or greater than the load value level threshold, and “0” is output otherwise.
  • the comparison circuit 134 compares the output of the load value sum calculation circuit 130 (1) delayed by the delay circuit 131 with the load value level threshold value. Then, “1” is output when the output of the load value sum calculation circuit 130 (1) delayed by the delay circuit 131 is equal to or greater than the load value level threshold, and “0” is output otherwise.
  • the OR gate 136 performs an OR operation on the output of the comparison circuit 133 and the output of the comparison circuit 134
  • the AND gate 137 performs an AND operation on the output of the OR gate 136 and the output of the comparison circuit 135. Therefore, the AND gate 137 outputs “1” when the output of the comparison circuit 135 is “1” and at least one of the output of the comparison circuit 133 and the output of the comparison circuit 134 is “1”; Sometimes “0” is output.
  • the output of the AND gate 137 that is, the output of the region load value variation determination unit 54 (1), is divided into two regions, the region (1) and the region (1) ′ that is adjacent to the region (1) in the vertical direction.
  • the sum of the load values changes between the regions over the load value fluctuation threshold, and at least one of the sum of the load values in region (1) and the sum of the load values in region (1) ′ is at the load value level. It is “1” when it is determined that the threshold value is exceeded, and “0” otherwise. In this manner, the region load value variation determination unit 54 (1) determines whether or not the sum of the load values has greatly changed compared to the region (1) 'with respect to the region (1). This is “region load value variation determination” in the region load value variation determination unit 54 (1).
  • region load value variation determination unit 54 (2) Each circuit from the region load value variation determination unit 54 (2) to the region load value variation determination unit 54 (16) that performs region load value variation determination in each region from the region (2) to the region (16)
  • the configuration and operation are the same as the above-described region load value variation determination unit 54 (1) except that the region subject to region load value variation determination is different, and the description thereof will be omitted (region load value variation determination unit 54 ( 2) to the region load value fluctuation determination unit 54 (15) are not shown).
  • the addition circuit 138 integrates the outputs of the respective circuits from the region load value variation determination unit 54 (1) to the region load value variation determination unit 54 (16). That is, the region load value fluctuation determination results in all the regions set on one line (in this embodiment, 16 regions from region (1) to region (16)) are integrated.
  • the comparison circuit 139 compares the integration result output from the addition circuit 138 with a predetermined load value fluctuation determination threshold value, and when the output of the addition circuit 138 is equal to or greater than the load value fluctuation determination threshold value, “1” is output, otherwise “0” is output. This is “load value fluctuation determination” in the load value fluctuation determination unit 91. Then, the load value fluctuation determination unit 91 performs this load value fluctuation determination for all lines, and outputs the result of the load value fluctuation determination for each line.
  • the result of the load value fluctuation determination (output of the load value fluctuation determination unit 91) is referred to as “load value fluctuation flag”. In this way, the load value variation determination unit 91 detects a line in which the load value changes greatly between lines adjacent in the vertical direction.
  • the load value fluctuation determination unit 91 performs the above-described load value fluctuation determination is to detect whether or not the display image does not include a symbol in which such a loading phenomenon is likely to occur.
  • the load value fluctuation threshold is set to 10% of the maximum value calculated by load value total calculation circuit 130, and the load value level threshold is set to 20% of the maximum value.
  • each threshold value is not limited to these numerical values.
  • Each threshold value is preferably set optimally based on the characteristics of the panel 10, the specifications of the plasma display device 1, a visual test of a display image, an experiment for displaying an image on which a loading phenomenon easily occurs on the panel 10, and the like.
  • FIG. 14 is a schematic diagram for explaining an example of the operation of the load value variation determination unit 91 according to the embodiment of the present invention.
  • the output of the load value sum calculation circuit 130, the output of the delay circuit 131, the output of the comparison circuit 135, the output of the comparison circuit 133, the output of the comparison circuit 134, and the output of the AND gate 137 in the circuit block are shown.
  • “1” is output from the comparison circuit 133 of the region load value fluctuation determination unit 54 (1).
  • “1” is output from the comparison circuit 134 of the region load value fluctuation determination unit 54 (16), and the comparison of the region load value fluctuation determination unit 54 (2). The description will be made assuming that “1” is also output from the circuit 133 and the comparison circuit 134.
  • the output of the AND gate 137 is “1”. This indicates that in the region (1), the sum of the load values is greatly increased as compared with the region (1) ′.
  • the output of the comparison circuit 135 is “1”, but the outputs of the comparison circuit 133 and the comparison circuit 134 are both “0”.
  • the output is “0”. This is because, in the region (3), the sum of the load values changed from the region (3) ′ to the load value fluctuation threshold or more, but both the region (3) and the region (3) ′ are loaded. Since the sum of the values is less than the load value level threshold, the change indicates that the loading phenomenon does not occur so much.
  • both the outputs of the comparison circuit 133 and the comparison circuit 134 are “1”, but the output of the comparison circuit 135 is “0”.
  • the output is “0”. This is because the sum of the load values is greater than or equal to the load value level threshold value in both the region (2) and the region (2) ′, but the sum of the load values is between the region (2) and the region (2) ′. This means that the change is less than the load value fluctuation threshold.
  • FIG. 15 is a circuit block diagram of continuity determination unit 92 in one embodiment of the present invention.
  • the continuity determination unit 92 includes a horizontal direction continuity determination unit 55 and a vertical direction continuity determination unit 56. Then, it is determined whether or not a loading phenomenon has occurred in the display image.
  • the horizontal direction continuity determination unit 55 performs horizontal direction continuity determination based on the adjacent pixel correlation flag output from the adjacent pixel correlation determination unit 90, and outputs the result.
  • the result of the horizontal continuity determination (the output of the horizontal continuity determination unit 55) is referred to as a “horizontal continuity flag”.
  • the vertical direction continuity determination unit 56 generates a loading phenomenon in the display image based on the load value variation flag output from the load value variation determination unit 91 and the horizontal direction continuity flag output from the horizontal direction continuity determination unit 55. The presence or absence is determined and the result is output. In the present embodiment, this determination result (the output of the vertical direction continuity determination unit 56) is referred to as a “continuity detection flag”. The continuity detection flag output from the vertical direction continuity determination unit 56 becomes the output of the pattern detection unit 63.
  • FIG. 16 is a circuit block diagram of the horizontal direction continuity determination unit 55 in an embodiment of the present invention.
  • the horizontal continuity determination unit 55 includes a delay circuit 140, an adder circuit 141, an AND gate 142, a maximum value detection circuit 143, and a comparison circuit 144.
  • the delay circuit 140, the adder circuit 141, and the AND gate 142 constitute a circuit that accumulates the adjacent pixel correlation flags output from the adjacent pixel correlation determination unit 90 for each pixel.
  • the adder circuit 141 adds the output of the delay circuit 140 that delays the input signal by one pixel and the adjacent pixel correlation flag.
  • the addition result output from the adder circuit 141 is input to the delay circuit 140 via the AND gate 142.
  • the adder circuit 141 adds a new adjacent pixel correlation flag to the output of the delay circuit 140.
  • the AND gate 142 performs an AND operation between the output of the adder circuit 141 and the adjacent pixel correlation flag, and resets the integrated value of the adjacent pixel correlation flag to “0” when the adjacent pixel correlation flag is “0”.
  • the integrated value of the adjacent pixel correlation flag is reset to “0” for each line. Therefore, the maximum output value of the AND gate 142 is equal to the number of pixels in one line. This reset can be performed, for example, by setting the adjacent pixel correlation flag to “0” when the line is switched (when the current line is changed to the next line).
  • the maximum value detection circuit 143 detects the maximum value of the output of the AND gate 142 for each line. For example, when the numerical value output from the AND gate 142 changes to “100”, “250”, and “80” in the period of one line, “250” that is the maximum value is output from the maximum value detection circuit 143. It becomes. That is, the output of the maximum value detection circuit 143 represents the maximum value in one line of the number of pixels in which the adjacent pixel correlation flag is “1” consecutive in the horizontal direction.
  • the comparison circuit 144 compares the output of the maximum value detection circuit 143 with a predetermined horizontal direction continuity determination threshold value. Then, “1” is output when the output of the maximum value detection circuit 143 is equal to or greater than the horizontal direction continuity determination threshold, and “0” is output otherwise. As a result, the output of the comparison circuit 144 is “1” in a line in which many pixels having high correlation with adjacent pixels are continuous in the horizontal direction (continuous over the horizontal direction continuity determination threshold). Otherwise, it is “0”. In this way, the horizontal direction continuity determination unit 55 performs horizontal direction continuity determination.
  • the horizontal direction continuity determination unit 55 can detect a line in which many pixels having high correlation with adjacent pixels are continuously arranged.
  • a state in which a large number of pixels having high correlation with adjacent pixels continue in the horizontal direction is referred to as “high continuity in the horizontal direction”.
  • FIG. 17 is a circuit block diagram of the vertical direction continuity determination unit 56 according to the embodiment of the present invention.
  • the vertical continuity determination unit 56 includes a delay circuit 145, an adder circuit 146, an AND gate 147, a comparison circuit 148, an AND gate 149, a selection circuit 150, a delay circuit 151, a selection circuit 152, and an addition.
  • the circuit 153 includes an AND gate 154, a delay circuit 155, and a comparison circuit 156.
  • the delay circuit 145, the adder circuit 146, and the AND gate 147 constitute a circuit that integrates the horizontal continuity flag output from the horizontal continuity determination unit 55 for each line. Specifically, the adder circuit 146 adds the output of the delay circuit 145 that delays the input signal by one horizontal synchronization period and the horizontal continuity flag. The addition result output from the adder circuit 146 is input to the delay circuit 145 via the AND gate 147. The adder circuit 146 adds a new horizontal continuity flag to the output of the delay circuit 145. By repeating this series of operations, the horizontal continuity flag is accumulated in the vertical direction for each line.
  • the AND gate 147 performs an AND operation on the output of the adder circuit 146 and the horizontal continuity flag, and when the horizontal continuity flag is “0”, the integrated value of the horizontal continuity flag is set to “0”. Reset.
  • the integrated value of the horizontal continuity flag is reset to “0” for each field. Therefore, the maximum value of the output of the AND gate 147 is equal to the number of lines constituting the panel 10 (the number of display electrode pairs 24). This reset can be performed, for example, by setting the horizontal continuity flag to “0” when the field is switched (when the current field is changed to the next field).
  • the comparison circuit 148 compares the output of the AND gate 147 with a predetermined vertical continuity determination threshold value. Then, “1” is output when the output of the AND gate 147 is equal to or greater than the vertical direction continuity determination threshold value, and “0” is output otherwise. As a result, the output of the comparison circuit 148 is “1” when a large number of lines having high continuity in the horizontal direction are continuously arranged in the vertical direction (ie, they are continuously arranged in the vertical direction continuity determination threshold). Otherwise, it is “0”. Thus, in this embodiment, the vertical continuity determination is performed.
  • the vertical direction continuity determination unit 56 can determine whether or not the display image is an image in which many lines having high continuity in the horizontal direction are continuously arranged in the vertical direction.
  • a state in which many lines having high continuity in the horizontal direction are continued in the vertical direction is referred to as “high continuity in the vertical direction”.
  • the AND gate 149 performs an AND operation on the result of the vertical continuity determination output from the comparison circuit 148 and the load value variation flag output from the load value variation determination unit 91, and outputs the output of the comparison circuit 148 and the load value.
  • both of the fluctuation flags are “1”, “1” is output, and otherwise “0” is output.
  • the output of the AND gate 149 is “1” for such a line.
  • the selection circuit 150 selects and outputs one of the two input signals based on the output of the AND gate 149. Specifically, when the output of the AND gate 149 is “1”, “1” is selected, and when the output of the AND gate 149 is “0”, the output of the selection circuit 152 is selected and output.
  • the delay circuit 151 delays the output of the selection circuit 150 by one horizontal synchronization period.
  • the selection circuit 152 selects and outputs one of the two input signals based on the horizontal continuity flag. Specifically, when the horizontal continuity flag is “1”, the output of the delay circuit 151 is selected, and when the horizontal continuity flag is “0”, “0” is selected and output.
  • the circuit constituted by the selection circuit 150, the delay circuit 151, and the selection circuit 152 continues until the output of the AND gate 149 once becomes “1”, and then the horizontal continuity flag becomes “0”. Then, the operation of continuously outputting “1” is performed.
  • the addition circuit 153, the AND gate 154, and the delay circuit 155 constitute a circuit that integrates the signal output from the selection circuit 150 for each line. Specifically, the adding circuit 153 adds the output of the selection circuit 150 and the output of the delay circuit 155 that delays the input signal for one horizontal synchronization period. The addition result output from the adder circuit 153 is input to the delay circuit 155 via the AND gate 154. The adder circuit 153 adds the new output of the selection circuit 150 to the output of the delay circuit 155. By repeating this series of operations, the output of the selection circuit 150 is integrated in the vertical direction for each line.
  • the AND gate 154 performs an AND operation on the output of the adder circuit 153 and the output of the selection circuit 150.
  • the output of the selection circuit 150 is “0”
  • the integrated value output from the adder circuit 153 is “0”. Reset to.
  • the numerical value (output of the AND gate 154) output from the circuit constituted by the adder circuit 153, the AND gate 154, and the delay circuit 155 is “the vertical continuity determination result, the load value fluctuation determination result, and the horizontal It is a numerical value calculated based on the direction continuity determination result.
  • the integrated value output from the adder circuit 153 is reset to “0” for each field. Therefore, the maximum output value of the AND gate 154 is equal to the number of lines constituting the panel 10 (the number of display electrode pairs 24). This reset can be performed, for example, by setting the horizontal continuity flag to “0” when the field is switched (when the current field is changed to the next field).
  • the comparison circuit 156 compares the output of the AND gate 154 with the vertical direction continuity determination threshold value. Then, “1” is output when the output of the AND gate 154 is equal to or greater than the vertical continuity determination threshold value, and “0” is output otherwise.
  • such an image is assumed to be an “image in which a loading phenomenon is likely to occur”. That is, the comparison result in the comparison circuit 156 is used as a determination result of whether or not the loading phenomenon occurs in the display image.
  • the vertical continuity determination unit 56 determines whether or not the loading phenomenon has occurred in the display image.
  • the horizontal continuity determination threshold is set to 15% of the number of pixels in one line
  • the vertical continuity determination threshold is set to 10% of the number of lines constituting the panel 10.
  • An example of setting can be given.
  • each threshold value is not limited to these numerical values, and each threshold value causes the characteristics of the panel 10, the specifications of the plasma display device 1, the visual test of the display image, and the loading phenomenon. It is desirable to set optimally based on an experiment for displaying an easy-to-use image on the panel 10 or the like.
  • FIG. 18 is a schematic diagram for explaining an example of the operation of the vertical continuity determination unit 56 according to the embodiment of the present invention, and schematically shows the panel 10 displaying an image that is thought to easily cause a loading phenomenon. It is a figure which shows schematically operation
  • the panel 10 has a medium luminance (for example, 30%) region (region B in the drawing) to a low luminance (for example, 0%) region (region C in the drawing). It is assumed that an image in which the switching is located is displayed in a region (region D in the drawing) having high brightness (for example, 100%). When such an image is displayed on the panel 10, as described with reference to FIG. 5B, in the region D that is in contact with the region C, the luminance may be higher than in the region that is in contact with the region B. It is considered that the loading phenomenon is likely to occur.
  • FIG. 18 shows the horizontal continuity flag (indicated as “W1” in FIGS. 17 and 18) input to the adding circuit 146 and the output of the comparison circuit 148 (“W2 in FIGS. 17 and 18). ), A load value fluctuation flag input to the AND gate 149 (indicated as “W3” in FIGS. 17 and 18), and an output of the selection circuit 150 (in FIG. 17 and FIG. 18, “W4”). And a comparison result (continuity detection flag) in the comparison circuit 156.
  • the vertical axis represents time
  • the horizontal axis represents the output value in each circuit.
  • the number of lines in which pixels having high correlation with adjacent pixels continue is increased as compared with the case where an image other than that is displayed. For this reason, when an image on which the loading phenomenon is likely to occur is displayed on the panel 10, the number of lines in which the horizontal continuity flag is “1” increases compared to when an image other than that is displayed.
  • FIG. 18 shows an example when the horizontal continuity flag is “1” in all lines (W1 graph).
  • the value of the horizontal direction continuity flag is continuously accumulated during the period in which the horizontal direction continuity flag is “1”, so that the output of the AND gate 147 continues to increase during that period. Then, at time t1 when the output of the AND gate 147 becomes equal to or higher than the vertical continuity determination threshold value, the output of the comparison circuit 148 (W2 graph) changes from “0” to “1”.
  • the load value fluctuation determination unit 91 sets the threshold values of the load value level threshold value, the load value fluctuation threshold value, and the load value fluctuation determination threshold value appropriately, so that the line adjacent in the vertical direction is set. It is possible to detect a point where the sum of the load values changes greatly between the two. In such a line, the load value fluctuation flag is “1”. In the example shown in FIG. 18, since the sum of the load values greatly changes at the boundary between the region B and the region C shown on the panel 10, as shown in the graph of W3, the load value is indicated on the line located at the boundary. The variation flag is “1”.
  • the output of the AND gate 154 continues to increase during that period. Then, at time t3 when the output of the AND gate 154 becomes equal to or higher than the vertical continuity determination threshold, the output of the comparison circuit 156, that is, the continuity detection flag changes from “0” to “1”.
  • the display image includes a symbol that is likely to cause a loading phenomenon, and for images that can be determined to include a symbol that is likely to cause a loading phenomenon.
  • the continuity detection flag is set to “1”, and the continuity detection flag is set to “0” for images that are not.
  • the correction gain changing unit when displaying on the panel 10 an image in which the continuity detection flag is “1”, that is, an image that can be determined to contain a symbol that is likely to cause a loading phenomenon, the correction gain changing unit It is assumed that a correction gain output from the correction gain calculation unit 62 is selected in a selection circuit 64, and the display image is subjected to loading correction using the correction gain. Further, when displaying on the panel 10 an image for which the continuity detection flag is “0”, that is, an image that can be determined to have a low possibility of occurrence of a loading phenomenon, the selection circuit 64 performs a correction output from the correction gain calculation unit 62. It is assumed that “0” is selected instead of the gain, and the display image is not subjected to loading correction.
  • correction is performed on an image signal in an area where a loading phenomenon is expected to occur, and emission luminance in a display image in the area is reduced. Reduce the loading phenomenon. Therefore, in order to prevent an unnecessary luminance change in the display image, it is desirable to perform loading correction only when displaying an image in which a loading phenomenon is expected to occur.
  • the loading correction is not performed only during the period when the continuity detection flag is “1”, but the loading correction is performed for all regions in the image where the continuity detection flag is “1”. And Accordingly, although not shown, after the determination result in the pattern detection unit 63 is obtained, an image signal input to the pattern detection unit 63 and the panel so that an image on which the determination is based are displayed on the panel 10 It is assumed that an appropriate time difference is provided with respect to the image displayed in FIG.
  • the “gain value” and the “maximum load value” are calculated for each discharge cell to calculate the correction gain.
  • the difference in driving load can be detected with higher accuracy, and the optimum correction gain corresponding to the lighting state of the discharge cell can be calculated. Therefore, it is possible to calculate with high accuracy the correction gain according to the increase in light emission luminance that is expected to occur due to the loading phenomenon, and it is possible to perform loading correction with high accuracy.
  • the pattern detection unit 63 determines whether or not a loading phenomenon has occurred in the display image, and changes the correction gain output from the correction gain calculation unit 62 based on the determination result. This makes it possible to perform loading correction only when displaying an image in which a loading phenomenon is expected to occur. Therefore, it is possible to reduce unnecessary luminance change in the display image and perform more accurate loading correction, and to improve the image display quality in the plasma display device 1 using the large-screen, high-definition panel 10. It is possible to greatly improve.
  • the load value fluctuation determining unit 91 when one area load value fluctuation determining unit 54 is operating, the other area load value fluctuation determining units 54 are not operating.
  • the integrated value of 54 is reset for each region, and the output is held for a predetermined period (for example, one horizontal synchronization period), so that the operation equivalent to the operation of the 16 region load value fluctuation determination units 54 can be performed. It can also be realized by one area load value variation determination unit 54.
  • the gradation value and the lighting / non-lighting of each subfield are associated with each other in the previous stage.
  • the tone value of the image signal may be temporarily replaced with image data using a coding table.
  • the luminance weight of each subfield is multiplied by the lighting state of each subfield in the discharge cell when calculating “load value” and “maximum load value”.
  • the number of sustain pulses in each subfield may be used instead of the luminance weight.
  • determining whether or not a loading phenomenon occurs in a display image refers to whether or not a loading phenomenon occurs when an image is displayed on the panel 10 without performing loading correction on the image signal. This does not mean that it is determined whether or not the loading phenomenon has occurred in the display image after the loading correction is performed.
  • scan electrode SC1 to scan electrode SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is a scan electrode belonging to the first scan electrode group.
  • two-phase driving which includes a first address period in which a scan pulse is applied to each of the first and second address periods in which a scan pulse is applied to each of the scan electrodes belonging to the second scan electrode group.
  • the present invention can also be applied to a driving method. In that case, the same effect as described above can be obtained.
  • the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other, that is, the arrangement of the electrodes provided on the front substrate is “... , Scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,...
  • each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.
  • the specific numerical values shown in the embodiments of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 24 of 1080. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with the characteristics of the panel and the specifications of the plasma display device. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Further, the number of subfields and the luminance weight of each subfield are not limited to the values shown in the embodiment of the present invention, and the subfield configuration may be switched based on an image signal or the like. Good.
  • the present invention reduces a change in luminance that occurs in a display image due to a difference in driving load between display electrode pairs even in a panel with a large screen and a high definition, and also eliminates an unnecessary luminance change in the display image. Since it is possible to provide a method for driving a plasma display device and a panel that can be reduced to improve image display quality, it is useful as a method for driving a plasma display device and a panel.
  • Plasma display apparatus 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25,33 Dielectric layer 26 Protective layer 31 Back substrate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 51 Horizontal adjacent pixel correlation determination unit 52 Vertical adjacent pixel correlation determination unit 53 RGB level determination unit 54 Area load value fluctuation determination unit 55 Horizontal direction continuity determination unit 56 Vertical direction continuity determination unit 60 Number of lit cells calculation unit 61 Load value calculation unit 62 Correction gain calculation unit 63 Pattern detection unit 64, 150, 152 Selection circuit 68 Multiplier 69 Correction unit 70 Loading correction unit 90 Adjacent pixel correlation determination unit 91 Load value fluctuation judgment 92 Continuity determination unit 101, 104, 107, 111, 114, 117, 126, 131, 140, 145, 151, 155 Delay circuit 102, 105, 108, 112, 115, 118,

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

Afin d'améliorer la qualité d'affichage de l'image et de réduire un phénomène de chargement dans le panneau d'affichage à plasma concerné, un circuit de traitement de signal d'image (41) comprend : une unité de calcul de la quantité de cellules éclairées (60) qui calcule le nombre de cellules éclairées ; une unité de calcul de valeur de charge (61) qui calcule la valeur de charge de chaque cellule de décharge en fonction des résultats de calcul de l'unité de calcul de quantité de cellules éclairées (60) ; une unité de calcul de gain ajusté (62) qui calcule le gain ajusté de chaque cellule de décharge en fonction des résultats de calcul de l'unité de calcul de valeur de charge (61) ; une unité de détection de motif (63) qui détermine si oui ou non un phénomène de chargement se produit dans une image affichée ; un circuit de sélection (64), qui est une unité de modification de gain ajusté qui modifie le gain ajusté en fonction des résultats de détermination de l'unité de détection de motif (63) ; et une unité d'ajustement (69) qui ajuste un signal d'image d'après le gain ajusté post-modification.
PCT/JP2010/007098 2009-12-09 2010-12-07 Dispositif d'affichage à plasma et procédé de commande d'un panneau d'affichage à plasma WO2011070766A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2011545081A JP5170322B2 (ja) 2009-12-09 2010-12-07 プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
US13/513,999 US20120242721A1 (en) 2009-12-09 2010-12-07 Plasma display device and method for driving plasma display panel
KR1020127010370A KR101333471B1 (ko) 2009-12-09 2010-12-07 플라즈마 디스플레이 장치 및 플라즈마 디스플레이 패널의 구동 방법
CN2010800551057A CN102640204A (zh) 2009-12-09 2010-12-07 等离子显示装置及等离子显示面板的驱动方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009279159 2009-12-09
JP2009-279159 2009-12-09

Publications (1)

Publication Number Publication Date
WO2011070766A1 true WO2011070766A1 (fr) 2011-06-16

Family

ID=44145328

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/007098 WO2011070766A1 (fr) 2009-12-09 2010-12-07 Dispositif d'affichage à plasma et procédé de commande d'un panneau d'affichage à plasma

Country Status (5)

Country Link
US (1) US20120242721A1 (fr)
JP (1) JP5170322B2 (fr)
KR (1) KR101333471B1 (fr)
CN (1) CN102640204A (fr)
WO (1) WO2011070766A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120060241A (ko) * 2009-12-14 2012-06-11 파나소닉 주식회사 플라즈마 디스플레이 장치 및 플라즈마 디스플레이 패널의 구동 방법
US11423829B2 (en) * 2020-03-02 2022-08-23 Silicon Works Co., Ltd. Clock generating circuit for LED driving device and method for driving

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005208369A (ja) * 2004-01-23 2005-08-04 Matsushita Electric Ind Co Ltd Ａｃ型プラズマディスプレイの駆動装置及び駆動方法
JP2006184843A (ja) * 2004-12-03 2006-07-13 Fujitsu Hitachi Plasma Display Ltd 画像表示装置およびその駆動方法
JP2009186715A (ja) * 2008-02-06 2009-08-20 Panasonic Corp プラズマディスプレイ装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5294670B2 (ja) * 2008-03-27 2013-09-18 三洋電機株式会社 投写型映像表示装置及びこれを用いた投写型映像表示システム
KR20120060241A (ko) * 2009-12-14 2012-06-11 파나소닉 주식회사 플라즈마 디스플레이 장치 및 플라즈마 디스플레이 패널의 구동 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005208369A (ja) * 2004-01-23 2005-08-04 Matsushita Electric Ind Co Ltd Ａｃ型プラズマディスプレイの駆動装置及び駆動方法
JP2006184843A (ja) * 2004-12-03 2006-07-13 Fujitsu Hitachi Plasma Display Ltd 画像表示装置およびその駆動方法
JP2009186715A (ja) * 2008-02-06 2009-08-20 Panasonic Corp プラズマディスプレイ装置

Also Published As

Publication number Publication date
KR20120064117A (ko) 2012-06-18
US20120242721A1 (en) 2012-09-27
CN102640204A (zh) 2012-08-15
KR101333471B1 (ko) 2013-11-26
JPWO2011070766A1 (ja) 2013-04-22
JP5170322B2 (ja) 2013-03-27

Similar Documents

Publication Publication Date Title
JP5293736B2 (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2009186715A (ja) プラズマディスプレイ装置
KR100901893B1 (ko) 플라즈마 디스플레이 패널 구동 방법
JP5387581B2 (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP5234192B2 (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP5170322B2 (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2011081335A (ja) プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置
US20120081418A1 (en) Driving method for plasma display panel, and plasma display device
JP5387696B2 (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
WO2011074251A1 (fr) Dispositif d'affichage à plasma et procédé de pilotage de panneau d'affichage à plasma
JP2011257515A (ja) プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置
WO2011086894A1 (fr) Dispositif d'affichage à plasma et procédé de pilotage d'un écran d'affichage à plasma
JP2010164741A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2011248268A (ja) プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置
JP2009300644A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2009192647A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2009186807A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2010197905A (ja) プラズマディスプレイパネルの駆動方法
JP2009251266A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2010181533A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2010197903A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2010175666A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
JP2009300729A (ja) プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201080055105.7

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10835692

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2011545081

Country of ref document: JP

ENP Entry into the national phase

Ref document number: 20127010370

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 13513999

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10835692

Country of ref document: EP

Kind code of ref document: A1