WO2011045956A1 - Semiconductor device, display device provided with same, and method for manufacturing semiconductor device - Google Patents

Semiconductor device, display device provided with same, and method for manufacturing semiconductor device Download PDF

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Publication number
WO2011045956A1
WO2011045956A1 PCT/JP2010/059598 JP2010059598W WO2011045956A1 WO 2011045956 A1 WO2011045956 A1 WO 2011045956A1 JP 2010059598 W JP2010059598 W JP 2010059598W WO 2011045956 A1 WO2011045956 A1 WO 2011045956A1
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Prior art keywords
layer
gate electrode
semiconductor device
semiconductor
light
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PCT/JP2010/059598
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French (fr)
Japanese (ja)
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宮本　忠芳
一秀 冨安
加藤　純男
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シャープ株式会社
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Priority to US13/501,830 priority Critical patent/US20120200546A1/en
Publication of WO2011045956A1 publication Critical patent/WO2011045956A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to a semiconductor device, a display device including the same, and a method for manufacturing the semiconductor device. More specifically, the present invention relates to a semiconductor device in which a plurality of types of semiconductor elements are formed on the same insulating substrate, and a display device including the semiconductor device. And a method of manufacturing a semiconductor device.
  • a liquid crystal panel of such a liquid crystal display device includes a thin film transistor (hereinafter referred to as “TFT”) functioning as a switching element for each pixel formation portion formed in a display area for displaying an image, and a touch sensor. And a photodiode functioning as a.
  • TFT thin film transistor
  • a gate driver, a source driver, and the like constituted by TFTs are often formed.
  • Patent Document 1 describes a liquid crystal panel in which a photodiode that functions as a touch sensor and a TFT that functions as a switching element of a pixel formation portion are formed on the same transparent substrate.
  • the channel layer of the TFT is made of a crystalline silicon layer obtained by crystallizing an amorphous silicon layer, and the gate electrode is formed above the channel layer.
  • the photodiode is a pn junction diode in which an n-type silicon region made of amorphous silicon and a p-type silicon region are formed at the same time as the TFT channel layer.
  • a light shielding layer is formed on the glass substrate below the photodiode so that light from the backlight source does not enter the photodiode.
  • the gate electrode of the TFT is formed above the silicon layer and the light shielding layer is formed below the silicon layer, the gate electrode and the light shielding layer cannot be formed in the same process. This complicates the manufacturing process of the liquid crystal panel and increases the manufacturing cost.
  • the TFT described in Patent Document 1 is replaced with a bottom gate type TFT in which the gate electrode is formed on a glass substrate.
  • the manufacturing process of the liquid crystal panel can be simplified and the manufacturing cost can be reduced.
  • the film thickness of the gate electrode is equal to the film thickness of the light shielding layer. If the gate electrode is thick, the step between the glass substrate and the edge of the gate electrode becomes large. Therefore, the step of the amorphous silicon layer formed so as to cover the gate electrode is also the edge of the gate electrode. Become bigger in the department.
  • laser light is irradiated from the upper surface of the amorphous silicon layer to melt the amorphous silicon layer. It flows to the side and solidifies to become a polycrystalline silicon layer. In this case, the polycrystalline silicon layer is disconnected at the end of the gate electrode and does not function as a channel layer of the TFT.
  • the energy of the laser beam irradiated on the amorphous silicon layer becomes thermal energy.
  • the gate electrode is formed of a material having high thermal conductivity, part of the thermal energy escapes to the gate wiring through the gate electrode. Therefore, since the amorphous silicon layer cannot be maintained at a high temperature for a long time, the crystal grain size of the polycrystalline silicon layer is not sufficiently large, and the mobility of the polycrystalline silicon layer is small.
  • the thickness of the light shielding layer of the photodiode is too thin, the light from the backlight source cannot be sufficiently shielded, so that the photodiode also detects light directly incident from the backlight source. For this reason, the detection sensitivity of the light of the backlight light source reflected by a finger or the like deteriorates.
  • the TFT gate electrode and the light-shielding layer of the photodiode are formed of the same conductive film, their film thicknesses are equal. Therefore, even if the TFT gate electrode is optimal, the light-shielding of the photodiode is achieved. There is a problem as a layer, and conversely, there is a problem as a gate electrode of a TFT even though it is optimal as a light shielding layer of a photodiode.
  • the gate electrode of the bottom gate type TFT and the light shielding layer of the photodiode are formed in separate steps, the respective film thicknesses can be set to optimum film thicknesses.
  • the manufacturing process of the liquid crystal panel becomes complicated and the manufacturing cost increases.
  • a first aspect of the present invention is a semiconductor device in which at least a first semiconductor element and a second semiconductor element of a different type from the first semiconductor element are formed on the same insulating substrate,
  • the first semiconductor element is: A first structure having a step and comprising a first layer; A polycrystalline semiconductor layer formed to cover at least the step of the first structure portion,
  • the second semiconductor element is: Including a second layer made of the same material as the first layer, and comprising a second structure part thicker than the first structure part,
  • the step of the first structure portion is a step that can be formed without breaking the polycrystalline semiconductor layer.
  • At least the shape of the step of the first structure portion is tapered.
  • the first semiconductor element is a bottom-gate thin film transistor;
  • the first structure portion is a gate electrode of the bottom-gate thin film transistor;
  • the polycrystalline semiconductor layer is a channel layer of the bottom-gate thin film transistor;
  • the second semiconductor element is an optical sensor that receives light incident from a first surface side of the insulating substrate on which the bottom-gate thin film transistor is formed,
  • the second structure portion is a light shielding layer that shields light incident on the photosensor from a second surface side facing the first surface in the insulating substrate.
  • the light shielding layer consists only of the second layer,
  • the second layer has a thickness greater than that of the gate electrode.
  • the light shielding layer is composed of a plurality of layers including the second layer,
  • the thickness of the second layer is equal to the thickness of the gate electrode.
  • the channel layer is a polycrystalline semiconductor layer including a lateral crystal whose major axis is formed in the channel length direction.
  • the optical sensor is a photodiode having a lateral pin structure.
  • the wiring further includes a third layer made of a material having a higher conductivity than the first layer, which is laminated on the upper surface of the first layer.
  • a ninth aspect of the present invention is a display device including a plurality of pixel formation portions each including a semiconductor device according to the third aspect on an insulating substrate, Each of the plurality of pixel formation portions includes A pixel electrode; A thin film transistor that applies a voltage to the previous pixel electrode by switching from an off state to an on state; and A first photosensor that receives light incident on the pixel formation portion, The thin film transistor and the first photosensor are a first semiconductor element and a second semiconductor element, respectively.
  • a driving circuit for driving the pixel forming unit is configured by the first semiconductor element.
  • An eleventh aspect of the present invention is the ninth aspect of the present invention, A backlight light source; A second optical sensor that is disposed outside a display area in which the plurality of pixel forming portions are formed and detects the intensity of external light; A backlight control circuit that controls the luminance of the backlight light source based on the output of the second photosensor; The second optical sensor is the second semiconductor element.
  • a twelfth aspect of the present invention is a method for manufacturing a semiconductor device in which a bottom gate thin film transistor and a photosensor having a light shielding layer are formed on the same insulating substrate, Forming a first conductive layer on the insulating substrate; Forming a second conductive layer on the first conductive layer; By exposing using a halftone mask, a first resist pattern is formed in a region to be a gate electrode on the second conductive layer, and the first resist pattern is formed in a region to be a light shielding layer.
  • Forming a thicker second resist pattern Forming a thicker second resist pattern; and Etching the second conductive layer and the first conductive layer in this order using the first and second resist patterns as a mask to form the light shielding layer; Exposing the surface of the second conductive layer covered with the first resist pattern by simultaneously reducing the thickness of the first and second resist patterns; And removing the second conductive layer whose surface is exposed to form the gate electrode.
  • a thirteenth aspect of the present invention is the twelfth aspect of the present invention, Forming an amorphous semiconductor layer so as to cover the gate electrode and the light shielding layer; Irradiating the amorphous semiconductor layer with laser light of a continuous wave laser and melting the amorphous semiconductor layer and then solidifying the amorphous semiconductor layer to form a polycrystalline semiconductor layer; Forming a channel layer of the thin film transistor covering the gate electrode by patterning the polycrystalline semiconductor layer, and simultaneously forming a semiconductor layer of the photosensor above the light shielding layer. To do.
  • the polycrystalline semiconductor layer is formed so as to cover at least the step of the first structure portion, and the step of the first structure portion is formed of the polycrystalline semiconductor.
  • the level difference is such that the polycrystalline semiconductor layer does not break when the layer is formed. For this reason, it can be prevented that the first semiconductor element does not operate due to the disconnection of the polycrystalline semiconductor layer.
  • the second semiconductor element since the thickness of the second structure portion is larger than the thickness of the first structure portion, the second structure portion is used as a light shielding layer or a wiring having a low wiring resistance. be able to.
  • the polycrystalline semiconductor layer is difficult to be cut by the step of the first structure portion. Therefore, it is possible to further prevent the first semiconductor element from operating due to the disconnection of the polycrystalline semiconductor layer.
  • the channel layer is formed of a polycrystalline semiconductor layer. Therefore, the mobility of the channel layer is increased, and the bottom gate thin film transistor can be operated at high speed. In addition, since the polycrystalline silicon layer can be prevented from being disconnected at the end of the gate electrode, the bottom gate thin film transistor can be operated reliably.
  • the optical sensor light incident from the second surface facing the first surface of the insulating substrate on which the bottom-gate thin film transistor is formed can be shielded by the light shielding layer, and thus the optical sensor is used as a touch sensor. In this case, the detection sensitivity of the optical sensor can be increased.
  • the light shielding layer is composed of only the second layer made of the same material as the gate electrode, the light shielding layer can be easily formed. Further, since the thickness of the second layer is larger than the thickness of the gate electrode, the light shielding layer can shield light incident from the second surface side.
  • the light shielding layer is composed of a plurality of layers including the second layer having the same thickness as that of the gate electrode, so that the light incident from the second surface side is further shielded. be able to.
  • the channel layer of the bottom-gate thin film transistor is a polycrystalline semiconductor layer including a lateral crystal having a large crystal grain size and having a major axis direction formed in the channel length direction.
  • the mobility of the channel layer is increased. Therefore, the bottom gate thin film transistor can be operated at high speed.
  • the optical sensor is a photodiode having a lateral pin structure. Therefore, the quantum efficiency of the photosensor can be increased and the response speed can be increased.
  • the wiring connected to the gate electrode of the bottom-gate thin film transistor has a third layer made of a material having a higher conductivity than the first layer on the upper surface of the first layer. including. Thereby, delay of a signal applied to the gate electrode through the wiring can be prevented.
  • the bottom gate type thin film transistor which is the first semiconductor element of the semiconductor device according to the third invention is used as the thin film transistor included in the pixel formation portion of the display device formed on the insulating substrate. If the photosensor which is the second semiconductor element of the semiconductor device is used as the first photosensor, the thin film transistor can be operated at high speed and the detection sensitivity of the first photosensor can be increased. . For this reason, the display device can have a touch panel function.
  • the driving circuit for driving the pixel forming portion of the display device is constituted by the bottom gate type thin film transistor which is the first semiconductor element of the semiconductor device according to the third invention, the thin film transistor As a result, the operating speed of the driving circuit can be increased.
  • the display device is provided with a second optical sensor capable of detecting the intensity of external light. If the optical sensor which is the second semiconductor element of the semiconductor device according to the third invention is used as the second optical sensor, the intensity of external light can be detected without being affected by the light from the backlight light source. Therefore, the second optical sensor functions as an ambient sensor. Thereby, the display apparatus can adjust the illumination intensity of a backlight light source according to the intensity
  • the first resist pattern is formed on the region to be the gate electrode by the photolithography method using the halftone mask, and the first resist pattern is formed on the region to be the light shielding layer.
  • a second resist pattern having a thickness larger than that of the resist pattern is formed.
  • the laminated film is etched using the first and second resist patterns as a mask. Thereby, a light shielding layer is formed. Further, if the thicknesses of the first and second resist patterns are reduced simultaneously, the first resist pattern is removed and the surface of the second conductive layer in the region to be the gate electrode is exposed.
  • the gate electrode is formed by removing the second conductive layer whose surface is exposed while leaving the second resist pattern.
  • the gate electrode and the light shielding layer having different thicknesses are formed in one photolithography process by using the difference in thickness between the first resist pattern and the second resist pattern formed using the halftone mask. Therefore, the manufacturing method of the semiconductor device can be simplified, and the manufacturing cost can be reduced.
  • a polycrystalline semiconductor layer is formed by irradiating the deposited amorphous semiconductor layer with laser light of a continuous wave laser. Since the crystal grains of the polycrystalline semiconductor layer thus formed are lateral crystals, the mobility of the polycrystalline semiconductor layer is increased. Therefore, the thin film transistor can be operated at high speed.
  • FIG. 5 is a cross-sectional view illustrating a configuration of the semiconductor device illustrated in FIG. 4.
  • FIGS. 6A to 6F are process cross-sectional views illustrating each manufacturing process of the semiconductor device shown in FIG. FIGS.
  • 6G to 6J are process cross-sectional views illustrating the manufacturing steps of the semiconductor device illustrated in FIG. It is a figure which shows the mobility of the polycrystalline-silicon layer crystallized using the continuous wave laser and the excimer laser. It is sectional drawing which shows the structure of the semiconductor device provided with TFT which the shape of the edge part of a gate electrode concerns on the 1st modification of this invention. It is sectional drawing which shows the structure of the semiconductor device containing the double gate type TFT based on the 3rd modification of this invention. It is a perspective view which shows the structure of the liquid crystal panel provided with the photodiode which functions as an ambient light sensor based on the 4th modification of this invention.
  • FIG. 1 is a perspective view showing a configuration of a liquid crystal panel 10 having a touch panel function included in an active matrix liquid crystal display device according to an embodiment of the present invention.
  • FIG. 1 shows a plurality of pixel formation portions including TFTs, photodiodes, etc., out of two low alkali glass substrates (hereinafter referred to as “glass substrates”) arranged to face each other so as to sandwich a liquid crystal layer.
  • a substrate 11 hereinafter referred to as “TFT substrate 11” formed in a matrix, and a backlight light source 13 disposed on the back side (lower side in FIG. 1) of the TFT substrate 11 so as to face the TFT substrate 11. Is shown.
  • the glass substrate disposed opposite to the surface side of the TFT substrate 11 (upper side in FIG. 1) and having a color filter or the like formed thereon, and sandwiched between the TFT substrate 11 and the CF substrate.
  • the liquid crystal layer thus formed is omitted.
  • a display area 21 is formed in the vicinity of the center of the TFT substrate 11 and includes a plurality of pixel forming portions and displays an image. As will be described later, in each pixel formation portion, a TFT functioning as a switching element and a photodiode functioning as a touch sensor are formed.
  • a gate driver 22 that outputs a control signal for controlling the timing of turning on / off the TFT to the gate wiring, a video signal for displaying an image on the pixel forming portion, and a timing for outputting the video signal
  • the gate driver and the source driver may be collectively referred to as “driving circuit” that outputs a control signal for controlling the source to the source wiring.
  • a position detection circuit 24 for detecting the touched position is provided.
  • FIG. 2 is a circuit diagram showing the configuration of the display area 21 of the liquid crystal panel 10.
  • the liquid crystal panel 10 includes a plurality of pixel forming portions 31, a plurality of gate lines GL, a plurality of source lines SL, and a plurality of sensor lines FL formed on a glass substrate (not shown).
  • the source lines SL and sensor lines FL are formed in parallel with each other and alternately.
  • the gate line GL is formed in a direction crossing the source line SL and the sensor line FL.
  • the pixel formation portion 31 is disposed in the vicinity of the intersection of the gate line GL and the source line SL, and includes a liquid crystal cell 32 and a photodiode 50.
  • the liquid crystal cell 32 displays an image by adjusting the amount of transmitted light among the light from the backlight light source 13.
  • the photodiode 50 receives light incident on the pixel forming unit 31 by reflecting light from the backlight light source 13 by a finger, a touch pen (sometimes collectively referred to as a “contact”), or the like.
  • the liquid crystal cell 32 includes a TFT 40 that functions as a switching element and a pixel capacitor 45.
  • the TFT 40 has a gate electrode connected to the gate line GL, a source electrode connected to the source line SL, and a drain electrode connected to a pixel electrode (not shown).
  • the pixel capacitor 45 includes a pixel electrode, a counter electrode (not shown) formed on the CP substrate so as to face the pixel electrode, and a liquid crystal layer sandwiched between these electrodes.
  • the photodiode 50 is disposed in the vicinity of the intersection of the gate line GL and the sensor line FL, the anode electrode of the photodiode 50 is connected to the gate line GL, and the cathode electrode is connected to the sensor line FL.
  • the signal voltage of the video signal applied to the source wiring SL is applied to the drain electrode via the TFT 40. And held in the pixel capacitor 45. Then, according to the held signal voltage, light from the backlight light source 13 is transmitted through the liquid crystal cell 32, and an image is displayed on the display area 21 of the liquid crystal panel 10.
  • a current having a magnitude corresponding to the intensity of light incident on the photodiode 50 flows from the gate wiring GL to the sensor wiring FL via the photodiode 50.
  • the position detection circuit 24 detects the intensity of light received by the photodiode 50 by detecting the current flowing through the sensor wiring FL, and specifies the touched position on the CF substrate.
  • FIG. 3 is a cross-sectional view showing a cross section of the display region 21 of the liquid crystal panel 10 shown in FIG.
  • the liquid crystal panel 10 is disposed so as to face the TFT substrate 11 and the TFT substrate 11 on which the TFT 40 and the photodiode 50 are formed for each pixel forming portion 31, and a CF on which a color filter or the like is formed.
  • the light from the backlight light source 13 is transmitted in the order of the TFT substrate 11, the liquid crystal layer, and the color filter (not shown) of the CF substrate 12, and becomes light with a light amount corresponding to the signal voltage held in the pixel capacitor. An image is displayed in the area 21.
  • the light shielding layer 60 is formed on the TFT substrate 11 below the photodiode 50. For this reason, the light from the backlight light source 13 is reflected by the light shielding layer 60 and does not enter the light receiving surface of the photodiode 50.
  • the photodiode 50 disposed below the touched position receives only the light reflected by the finger or the like, and the position detection circuit 24 can easily identify the touched position.
  • the light shielding layer 60 has a sufficient thickness so that at least the light from the backlight source 13 does not directly enter the photodiode 50. In addition, it must be formed to have a larger area than the photodiode 50 in plan view.
  • FIG. 4 is a plan view showing a configuration of a bottom gate type TFT 40 (hereinafter, abbreviated as “TFT 40”) and a photodiode 50 included in the semiconductor device 100 according to the embodiment of the present invention.
  • TFT 40 bottom gate type TFT 40
  • photodiode 50 included in the semiconductor device 100 according to the embodiment of the present invention.
  • one TFT 40 and one photodiode 50 are disposed on the glass substrate 101, but a plurality of TFTs 40 and a plurality of photodiodes 50 may be disposed.
  • the gate electrode 110 is formed on the glass substrate 101.
  • the end of the gate electrode 110 is formed so as to be substantially perpendicular to the glass substrate 101.
  • an island-like silicon layer 120 functioning as a channel layer is formed in a direction orthogonal to the gate electrode 110 via a gate insulating film (not shown).
  • the island-like silicon layer 120 is composed of a polycrystalline silicon layer crystallized by applying laser annealing to an amorphous silicon layer.
  • a source region 120a and a drain region 120b doped with n-type impurities at a high concentration are formed.
  • a channel layer 120c is formed in a region located above the gate electrode 110 and sandwiched between the source region 120a and the drain region 120b.
  • the source region 120a and the drain region 120b are electrically connected to the source electrode 140a and the drain electrode 140b through contact holes 135a and 135b formed in an interlayer insulating film (not shown), respectively.
  • the source electrode 140a is electrically connected to a source wiring (not shown), and the drain electrode 140b is electrically connected to a pixel electrode (not shown).
  • the end portion of the gate electrode 110 is electrically connected to the gate connection electrode 140c through the contact hole 130c, and the gate connection electrode 140c is electrically connected to a gate wiring (not shown).
  • a light shielding layer 60 is formed on the glass substrate 101.
  • the light shielding layer 60 is made of a laminated metal film in which a second metal layer is laminated on the first metal layer so as not to transmit light from the backlight source, and the material and thickness of the first metal layer are the gate. It is the same as the material and film thickness of the electrode 110.
  • An island-like silicon layer 180 is formed above the light shielding layer 60 through the gate insulating film so as not to protrude from the light shielding layer 60 at least.
  • the island-like silicon layer 180 is a polycrystalline silicon layer formed in the same process as the island-like silicon layer 120 of the TFT 40.
  • an n-type region 180a doped with a high-concentration n-type impurity and a p-type region 180b doped with a high-concentration p-type impurity are formed.
  • N-type region 180a and p-type region 180b are electrically connected to cathode electrode 190a and anode electrode 190b through contact holes 185a and 185b formed in the interlayer insulating film, respectively.
  • the photodiode 50 is a lateral pin structure diode with high quantum efficiency and capable of high-speed response, but may be a pn junction diode in which a p-type region and an n-type region are directly joined. Note that the n-type region 180a, intrinsic region 180c, and p-type region 180b of a diode having a lateral pin structure may be collectively referred to as a semiconductor layer.
  • FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device 100 shown in FIG. FIG. 5 shows, in order from the left, a cross-sectional view along the line AA of the TFT 40 shown in FIG. 4, a cross-sectional view along the line BB of the TFT 40, and a cross-section along the line CC of the photodiode 50. The figure is shown.
  • the gate electrode 110 of the TFT 40 and the light shielding layer 60 of the photodiode 50 are formed on the glass substrate 101 which is an insulating substrate.
  • the material of the gate electrode 110 is preferably a refractory metal such as tungsten (W), molybdenum (Mo), tantalum (Ta), titanium (Ti), etc. in consideration of heat treatment in a later manufacturing process. Is 30 to 100 nm.
  • the gate electrode 110 is made of an alloy containing tungsten as a main component, and the film thickness is 50 nm.
  • the light shielding layer 60 of the photodiode 50 is made of a laminated metal film in which two metal layers are laminated.
  • the material and thickness of the first metal layer 111 formed on the glass substrate 101 are the same as those of the gate electrode 110. is there. Therefore, in the semiconductor device 100, the first metal layer 111 of the light shielding layer 60 is also made of an alloy containing tungsten as a main component, and the thickness thereof is 50 nm.
  • the second metal layer 113 laminated on the upper surface of the first metal layer 111 is preferably made of aluminum (Al), copper (Cu), or the like, which is a material having a higher conductivity than the first metal layer 111.
  • the preferred film thickness is 50 to 200 nm.
  • the second metal layer 113 is made of an alloy containing aluminum as a main component, and the film thickness is 100 nm. Therefore, in the semiconductor device 100, the thickness of the gate electrode 110 of the TFT 40 is 50 nm, and the thickness of the light shielding layer 60 of the photodiode 50 is 150 nm. The reason why the thickness of the gate electrode 110 is thus reduced will be described later.
  • the reason why the second metal layer 113 is formed using a material having a high conductivity is as follows.
  • the gate wiring GL electrically connected to the gate electrode 110 of the TFT 40 is formed in the same manufacturing process as the light shielding layer 60.
  • the gate wiring GL has a role of supplying a control signal supplied from the gate driver to the gate electrode 110. Therefore, it is necessary to reduce the resistance value of the gate wiring GL and prevent the delay of the control signal by the gate wiring GL by forming the second metal layer 113 using a material having high conductivity. .
  • a gate insulating film 128 is formed so as to cover the entire glass substrate 101 including the gate electrode 110 and the light shielding layer 60.
  • the gate insulating film 128 may be configured by one type of insulating film, or may be configured by a laminated film in which a plurality of types of insulating films are stacked.
  • a preferable film thickness of the gate insulating film 128 is 50 to 300 nm, and a more preferable film thickness is 100 to 200 nm.
  • an insulating film made of silicon oxide (SiO 2 ), silicon nitride (SiNx), or silicon oxynitride (SiON) is preferably used.
  • an island-shaped silicon layer 120 serving as a channel layer of the TFT 40 and an island-shaped silicon layer 180 of the photodiode 50 are formed on the gate insulating film 128, an island-shaped silicon layer 120 serving as a channel layer of the TFT 40 and an island-shaped silicon layer 180 of the photodiode 50 are formed.
  • the island-like silicon layers 120 and 180 are made of polycrystalline silicon that is crystallized by irradiating laser light to amorphous silicon, and a preferable film thickness is 30 to 150 nm. Is 50 to 100 nm. For this reason, in the semiconductor device 100, the film thickness of the island-like silicon layers 120 and 180 are both 50 nm.
  • the island-like silicon layer 120 of the TFT 40 includes a channel region 120c formed above the gate electrode 110, LDD regions 120d doped with low-concentration n-type impurities, respectively, formed on the left and right sides of the channel region 120c, and LDD A source region 120a and a drain region 120b doped with a high-concentration n-type impurity are formed respectively outside the region 120d.
  • the polycrystalline silicon crystal constituting the island-like silicon layer 120 of the TFT 40 may be a granular crystal having a large crystal grain size, but is more preferably a lateral crystal extending long in a predetermined direction.
  • the size of the lateral crystal depends on the film thickness of the amorphous silicon, and in the semiconductor device 100, the length of the long side is several ⁇ m and the length of the short side is 0.5 to 1.0 ⁇ m. This is larger than the crystal grain size of 0.3 to 0.5 ⁇ m of polycrystalline silicon crystallized by irradiating the excimer laser beam.
  • the mobility of the island-shaped silicon layer 120 made of a lateral crystal is increased, and the operation speed of the TFT 40 using the island-shaped silicon layer 120 as a channel layer is increased.
  • the operating speed of the TFT 40 is further increased. A method for growing such a lateral crystal will be described later.
  • an n-type region 180a doped with a high-concentration n-type impurity and a p-type region 180b doped with a high-concentration p-type impurity are formed at both ends of the island-like silicon layer 180 of the photodiode 50.
  • an intrinsic region 180c is formed in a region sandwiched between the n-type region 180a and the p-type region 180b.
  • the photodiode 50 is a diode having a lateral pin structure.
  • a protective film 130 made of silicon oxide is formed on the upper surfaces of the island-like silicon layers 120 and 180, respectively, and further, the first glass made of silicon nitride is formed so as to cover the entire glass substrate 101 including the protective film 130.
  • An interlayer insulating film 131 is formed.
  • the film thickness of the first interlayer insulating film 131 is preferably 100 to 400 nm.
  • a second interlayer insulating film 132 made of silicon oxide is formed on the first interlayer insulating film 131.
  • the thickness of the second interlayer insulating film 132 is preferably 200 to 600 nm.
  • An electrode 190b is formed.
  • the source electrode 140a, the drain electrode 140b, the gate connection electrode 140c, the cathode electrode 190a, and the anode electrode 190b are made of a metal having high conductivity such as aluminum or molybdenum. .
  • aluminum is used as these electrode materials.
  • a planarizing film 148 made of a photosensitive acrylic resin is formed so as to cover the entire glass substrate 101 including the TFT 40 and the photodiode 50, and is made of a transparent metal such as ITO (Indium Tin Oxide) on the planarizing film 148.
  • a pixel electrode 161 is formed. The pixel electrode 161 is electrically connected to the drain electrode 140 b of the TFT 40 through a contact hole opened in the planarization film 148.
  • a recess 160 reaching the surface of the second interlayer insulating film 132 is opened above the intrinsic region 180c of the island-like silicon layer 180 so that the intensity of reflected light from a finger or the like does not decrease. .
  • the pixel electrode 161 is formed from the surface of the planarization film 148 above the cathode electrode 190a to the inner surface of the recess 160 and further to the surface of the planarization film 148 above the anode electrode 190b. Further, a black matrix 162 made of a light shielding material such as chromium (Cr) is formed on the pixel electrode 161 of the TFT 40 and on the pixel electrode 161 above the cathode electrode 190 a and the anode electrode 190 b of the photodiode 50.
  • chromium Cr
  • 6 and 7 are process cross-sectional views showing the manufacturing process of the semiconductor device 100 shown in FIG. 6 and 7, the cross-sectional view along the line AA shown in FIG. 4 is omitted.
  • a method for manufacturing the semiconductor device 100 will be described with reference to FIGS.
  • a first metal layer 111 made of an alloy containing tungsten as a main component and having a thickness of 50 nm is formed over a glass substrate 101 by a sputtering method.
  • a second metal layer 113 made of an alloy containing aluminum as a main component and having a thickness of 100 nm is formed over the first metal layer 111.
  • a photoresist is applied to form a resist film (not shown), and the resist film is exposed using a halftone mask to form resist patterns 171a and 171b having desired shapes.
  • a halftone mask not only a pattern composed of a light shielding part that completely shields exposure light but also a pattern composed of a semitransparent part that transmits the exposure light at a predetermined ratio by providing a slit or the like.
  • the gate wiring (not shown) of the TFT 40 and the pattern of the light shielding layer 60 of the photodiode 50 are made of a light shielding part, and the pattern of the gate electrode 110 is a halftone mask made of a semi-transmissive part.
  • the pattern of the gate electrode 110 is a halftone mask made of a semi-transmissive part.
  • the second metal layer 113 made of an alloy containing aluminum as a main component by dry etching using the resist patterns 171a and 171b as masks and chlorine (Cl 2 ) gas as an etching gas. Is patterned.
  • the first metal layer 111 made of an alloy containing tungsten as a main component is patterned by dry etching using sulfur hexafluoride (SF 6 ) gas as an etching gas. As a result, the light shielding layer 60 of the photodiode 50 and the gate wiring of the TFT 40 are formed, and the protrusion 114 to be the gate electrode 110 is formed.
  • SF 6 sulfur hexafluoride
  • ashing is performed using oxygen (O 2 ) gas to remove the resist pattern 171a on the protrusion 114, and the surface of the second metal layer 113 is exposed.
  • O 2 oxygen
  • the second metal layer 113 of the protrusion 114 is removed by wet etching using the remaining resist pattern 171b as a mask.
  • Wet etching is performed using an etchant having a high selectivity (etching rate of an alloy containing aluminum as a main component relative to an alloy containing tungsten as a main component).
  • the resist pattern 171b is peeled off.
  • an etchant containing acetic acid (CH 3 COOH), phosphoric acid (H 3 PO 4 ), and nitric acid (HNO 3 ) is used to wet-etch the second metal layer 113 made of an alloy containing aluminum as a main component. Is done.
  • the gate electrode 110 is formed.
  • the second metal layer 113 may be removed by dry etching.
  • a gate insulating film 128 made of is formed.
  • an amorphous silicon layer 121 having a thickness of 50 nm is formed on the gate insulating film 128 by plasma CVD using monosilane gas and hydrogen gas as source gases.
  • both the gate insulating film 128 and the amorphous silicon layer 121 are formed by a plasma CVD method, they may be continuously formed by switching the source gas. In this case, after the gate insulating film 128 is formed, the amorphous silicon layer 121 is formed without exposing the surface of the gate insulating film 128 to the atmosphere. Contamination of the interface can be prevented, and fluctuations in the threshold voltage of the TFT 40 can be suppressed.
  • the hydrogen contained in the amorphous silicon layer 121 is desorbed in advance by annealing in a nitrogen atmosphere at about 400 ° C. for about 1 to 2 hours.
  • the amorphous silicon layer 121 from which hydrogen has been eliminated is irradiated with laser light to crystallize the amorphous silicon layer 121 into a polycrystalline silicon layer 122.
  • the laser used was a continuous wave laser called Nd: YVO 4 laser with a wavelength of 532 nm, and its laser output was 11.5 W.
  • the beam shape of the laser beam is set to, for example, 0.1 ⁇ 2.0 mm so as to be a long shape, and the laser beam is scanned in parallel with the surface of the amorphous silicon layer 121.
  • a preferable scanning speed of the laser beam is 300 to 500 mm / sec.
  • the amorphous silicon layer 121 in the region irradiated with the laser light is completely melted, and the gate electrode 110 is made of a first alloy composed of a relatively small tungsten alloy having a thermal conductivity of 174 W / m ⁇ K.
  • the metal layer 111 is formed. Part of the thermal energy generated in the amorphous silicon layer 121 is given to the gate electrode 110 by thermal radiation. However, since the heat energy given to the gate electrode 110 is more difficult to be transmitted to the gate wiring, it is difficult to dissipate heat through the gate wiring.
  • the amorphous silicon layer 121 maintains a high temperature state for a long time, the molten silicon slowly cools and hardens, and is a polycrystal made of a long lateral crystal whose major axis is the scanning direction of the laser beam.
  • a silicon layer 122 is formed.
  • the thickness of the gate electrode 110 is as thin as 50 nm, the inclination of the amorphous silicon layer 121 due to the step at the end of the gate electrode 110 is also gentle. For this reason, even if the amorphous silicon layer 121 is completely melted, the melted silicon is difficult to flow to the glass substrate 101 side, and the crystallized polycrystalline silicon layer 122 is difficult to be cut off at the end of the gate electrode 110. Become. On the other hand, since the thickness of the light shielding layer 60 of the photodiode 50 is as thick as 150 nm, the inclination of the amorphous silicon layer 121 formed so as to cover the light shielding layer 60 becomes steep at the end of the light shielding layer 60.
  • the amorphous silicon layer 121 is completely melted, the melted silicon flows toward the glass substrate 101, and the crystallized polycrystalline silicon layer 122 is likely to be disconnected at the end of the light shielding layer 60.
  • the polycrystalline silicon layer 122 outside the light shielding layer 60 does not constitute the island-like silicon layer 180. Therefore, in the photodiode 50, there is no problem even if the polycrystalline silicon layer 122 is cut off at the end of the light shielding layer 60.
  • FIG. 8 is a diagram showing the mobility of a polycrystalline silicon layer obtained by crystallizing an amorphous silicon layer using a continuous wave laser and an excimer laser.
  • the horizontal axis in FIG. 8 represents the energy density of the irradiated laser light
  • the vertical axis represents the mobility of the polycrystalline silicon layer crystallized by laser annealing.
  • the mobility of the crystallized polycrystalline silicon layer is increased accordingly.
  • this polycrystalline silicon layer also becomes a granular crystal, the crystal grain size becomes larger than when an excimer laser is used. Therefore, the mobility becomes larger than the mobility of the polycrystalline silicon layer crystallized using an excimer laser.
  • the energy density is increased, the mobility becomes a predetermined value, and even if the energy density is further increased, the value maintains almost the predetermined value and hardly changes. In the range where the mobility hardly changes from the predetermined value even if the energy density is changed, the mobility of the crystallized polycrystalline silicon layer can be easily set to the predetermined value by adjusting the energy density of the laser beam. Can be.
  • the crystal grains of the polycrystalline silicon layer crystallized by irradiation with laser light having an energy density that hardly changes from a predetermined value become lateral crystals.
  • the amorphous silicon layer can be easily made into a polycrystalline silicon layer made of a lateral crystal, so that the operation of the TFT Speed can be increased. Further, the range of the energy density of the laser beam necessary for forming a polycrystalline silicon layer made of a lateral crystal is wide.
  • the amorphous silicon layer varies in thickness, such as when an amorphous silicon layer is formed on a large-area glass substrate, or when the gate electrode is disposed below
  • the amorphous silicon layer is made of a lateral crystal regardless of the variation and the presence or absence of the arrangement of the gate electrode.
  • a polycrystalline silicon layer can be formed.
  • an excimer laser such as a xenon chloride (XeCl) excimer laser or a krypton fluoride (KrF) excimer laser is used instead of the continuous wave laser, and the amorphous silicon layer is formed of a granular crystal.
  • a crystalline silicon layer may be used.
  • a protective film 130 made of silicon oxide having a thickness of 50 to 100 nm is formed by plasma CVD so as to cover the polycrystalline silicon layer 122.
  • phosphorus (P) that is an n-type impurity or boron (B that is a p-type impurity) is used by using an ion implantation method or an ion doping method through the protective film 130.
  • a resist film (not shown) is formed on the protective film 130 using a photolithography technique. Next, exposure is performed from the lower surface side of glass substrate 101 (lower side in FIG.
  • the resist pattern 172 is formed in a self-aligned manner with respect to the gate electrode 110 and the light shielding layer 60.
  • the polycrystalline silicon layer 122 is doped with low-concentration phosphorus through the protective film 130 by ion implantation or ion doping.
  • a low concentration region 124 (n ⁇ region 124) is formed in the region of the polysilicon layer 122 where phosphorus is implanted. Thereafter, the resist pattern 172 is peeled off.
  • a resist pattern 173 having a shape larger than the resist pattern 172 is formed on the protective film 130 above the gate electrode 110 by using a photolithography technique, and the island of the photodiode 50 is formed.
  • a resist pattern 173 is formed above the region to be the intrinsic region 180c and the region to be the p-type region 180b of the silicon layer 180.
  • high concentration phosphorus is doped into the polycrystalline silicon layer 122 through the protective film 130 by ion implantation or ion doping.
  • the region doped with high concentration phosphorus becomes the n-type high concentration region 125, and the region sandwiched between the n-type high concentration region 125 and the channel region 120c becomes the LDD region 120d.
  • the region doped with high-concentration phosphorus in the polycrystalline silicon layer 122 becomes the n-type high-concentration region 125.
  • a resist pattern (not shown) is formed in the same manner as in FIG. 7H, and high-concentration boron is doped using the resist pattern as a mask by an ion implantation method or an ion doping method.
  • a p-type high concentration region of a p-channel TFT (not shown) and a p-type high concentration region 180b of the photodiode 50 are formed.
  • a region sandwiched between the n-type high concentration region 125 and the p-type high concentration region of the photodiode 50 becomes an intrinsic region 180c.
  • annealing is performed to activate the doped phosphorus and boron.
  • a resist pattern (not shown) having a desired shape is formed on the protective film 130 using a photolithography method.
  • the resist pattern As shown in FIG. 7I, a resist pattern (not shown) having a desired shape is formed on the protective film 130 using a photolithography method.
  • the resist pattern As shown in FIG. 7I, a resist pattern (not shown) having a desired shape is formed on the protective film 130 using a photolithography method.
  • the resist pattern As shown in FIG. 7I, a resist pattern (not shown) having a desired shape is formed on the protective film 130 using a photolithography method.
  • the resist pattern As shown in FIG. 7I, a resist pattern (not shown) having a desired shape is formed on the protective film 130 using a photolithography method.
  • the resist pattern As shown in FIG. 7I, a resist pattern (not shown) having a desired shape is formed on the protective film 130 using a photolithography method.
  • the resist pattern As shown in FIG. 7I, a resist pattern (not shown)
  • the first interlayer insulating film 131 and the second insulating film 131 and the second interlayer insulating film 131 are covered by the plasma CVD method, the low pressure CVD method, or the sputtering method so as to cover the island-like silicon layers 120 and 180 and the protective film 130 on the upper surface thereof.
  • An interlayer insulating film 132 is sequentially formed.
  • the first interlayer insulating film 131 is made of silicon nitride having a thickness of 100 to 400 nm
  • the second interlayer insulating film 132 is made of silicon oxide having a thickness of 200 to 600 nm.
  • the glass substrate 101 on which the TFT 40 and the photodiode 50 are formed is annealed in a nitrogen gas atmosphere at 300 to 400 ° C. or in a vacuum, and the hydrogen contained in the first interlayer insulating film 131 is converted into island-shaped silicon. Diffuse into layers 120, 180. As a result, dungling bonds contained in the island-like silicon layer are terminated, and interface states are less likely to be generated in the island-like silicon layers 120 and 180 of the TFT 40 and the photodiode 50. Is improved.
  • contact holes reaching the source region 120a, the drain region 120b, the n-type region 180a, the p-type region 180b, and the gate electrode 110 are opened in the first and second interlayer insulating films 131 and 132 by dry etching.
  • An aluminum film 141 is formed on the entire surface of the glass substrate 101 including the second interlayer insulating film 132 by sputtering.
  • a resist pattern 174 having a desired shape is formed on the aluminum film 141 by photolithography, and the aluminum film 141 is dry-etched using the resist pattern 174 as a mask.
  • the source electrode 140a electrically connected to the source region 120a
  • the drain electrode 140b electrically connected to the drain region 120b
  • the cathode electrode 190a electrically connected to the n-type region 180a
  • the p-type region 180b An anode electrode 190b electrically connected to the gate electrode 110 and a gate connection electrode (not shown) electrically connected to the gate electrode 110 are formed.
  • the aluminum film 141 may be wet-etched.
  • a planarizing film 148 made of a photosensitive acrylic resin is formed on the entire surface of the glass substrate 101, and the planarizing film 148 is exposed and developed to contact the drain electrode 140b.
  • a recess 160 reaching the surface of the second interlayer insulating film 132 is opened above the intrinsic region 180 c of the photodiode 50.
  • a transparent metal film (not shown) such as ITO is formed by sputtering. The transparent metal film is etched to form a pixel electrode 161 that is electrically connected to the upper surface of the drain electrode 140b through a contact hole opened in the planarization film 148.
  • the pixel electrode 161 is further formed so as to cover the inner surface of the recess 160 from the surface of the planarization film 148 above the cathode electrode 190a and further to the surface of the planarization film 148 above the anode electrode 190b.
  • a black matrix 162 made of chromium or the like is formed on the surface of the pixel electrode 161 of the TFT 40 and the surface of the pixel electrode 161 above the cathode electrode 190a and the anode electrode 190b of the photodiode 50. In this way, the semiconductor device 100 including the TFT 40 that functions as a switching element of the pixel formation portion and the photodiode 50 that functions as a touch sensor is manufactured.
  • the TFT 40 included in the semiconductor device 100 of the present embodiment has been described as a TFT that functions as a switching element of the pixel formation portion, it may be a TFT that constitutes a drive circuit such as a source driver or a gate driver. .
  • the island-like silicon layer 120 including the channel layer 120c is made of polycrystalline silicon. For this reason, the mobility of the channel layer 120c is increased, and the TFT 40 can be operated at high speed. Moreover, since the step of the island-like silicon layer 120 made of polycrystalline silicon can be prevented at the end of the gate electrode 110, the TFT 40 can be operated reliably.
  • the photodiode 50 the light incident from the surface of the glass substrate 101 opposite to the surface of the glass substrate 101 on which the TFT 40 is formed can be shielded by the light shielding layer 60, so that the detection of the photodiode 50 functioning as a touch sensor is possible. Sensitivity can be increased.
  • the gate wiring GL connected to the gate electrode 110 of the TFT 40 has the same thickness as that of the first metal layer 111 and is formed of the same material on the metal layer made of the same material as that of the second metal layer 113. Since the metal layer is formed of the laminated metal film, delay of a signal applied to the gate electrode 110 through the gate wiring GL can be prevented.
  • the TFT 40 of the semiconductor device 100 is used as the thin film transistor included in the pixel formation portion 31 formed in the display region 21 of the liquid crystal panel 10 and the photodiode 50 is used as the photodiode, the TFT can be operated at high speed. The detection sensitivity of the photodiode can be increased. For this reason, the liquid crystal panel 10 can be used as a touch panel.
  • the TFT 40 is also referred to as a first semiconductor element, and the photodiode 50 is also referred to as a second semiconductor element.
  • the gate electrode 110 of the TFT 40 is also referred to as a first structure portion or a first layer, and the island-like silicon layer 120 of the TFT 40 is also referred to as a polycrystalline silicon layer.
  • the light shielding layer 60 of the photodiode 50 is also referred to as a second structure portion, the first metal layer 111 of the photodiode 50 is also referred to as a second layer, and the second metal layer 113 is also referred to as a third layer.
  • FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device 200 including a TFT 41 having a tapered end portion of the gate electrode 210 according to the first modification of the present invention.
  • the constituent elements of the semiconductor layer 200 shown in FIG. 9 the same constituent elements as those of the semiconductor device 100 shown in FIG.
  • the shape of the end of the gate electrode 210 is tapered.
  • the inclination of the amorphous silicon layer formed so as to cover the gate electrode 210 becomes gentle at the end of the gate electrode 210.
  • the melted silicon hardly flows to the glass substrate 101 side.
  • the island-like silicon layer 120 made of a polycrystalline silicon layer obtained by solidifying molten silicon is difficult to be disconnected at the end of the gate electrode 210.
  • the end portion of the first metal layer 211 constituting the light shielding layer 260 is also tapered.
  • the shape of the edge part of the light shielding layer 260 may not be a taper shape.
  • the end portion is substantially perpendicular to the glass substrate 101 as in the gate electrode 110 shown in FIG. 5, but also at the end portion as in the gate electrode 210 shown in FIG. 9.
  • a difference in height between the surface of the glass substrate 101 and the surface of the gate electrode 210 is referred to as a step.
  • a preferable angle between the taper formed at the end of the gate electrode 210 and the glass substrate 101 is 10 to 50 degrees.
  • the taper angle is larger than 50 degrees, melted silicon tends to flow, so that disconnection is likely to occur.
  • the taper angle is smaller than 10 degrees, the molten silicon is difficult to flow, but the taper is difficult to process.
  • the second metal layer 113 made of an alloy containing aluminum as a main component is patterned by dry etching using the resist pattern 171a as a mask.
  • the first metal layer 111 made of an alloy containing tungsten as a main component is patterned by wet etching.
  • an etchant mainly containing hydrofluoric acid, hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ), or the like is used.
  • the wet etching of the first metal layer 111 isotropically proceeds to the lower side and the side surface starting from the lower surface end of the second metal layer 113.
  • the second metal layer 113 is in an overhanging state with respect to the first metal layer 111, and the first metal layer 111 becomes the first metal layer 211 whose side surface is tapered.
  • the resist pattern 171a on the projecting portion 114 to be the gate electrode 115 is removed by ashing to expose the surface of the second metal layer 113.
  • the second metal layer 113 made of an alloy containing aluminum as a main component is removed by wet etching.
  • the gate electrode 210 made only of the first metal layer 211 is formed, and the side surface of the gate electrode 210 is tapered. It becomes a shape.
  • the island-like silicon layer 120 can be prevented from being cut off at the end of the gate electrode 210 as described above, even if the end is not tapered. However, if the gate electrode 210 is not only thinned, but also its end is tapered, the island-like silicon layer 120 can be further prevented from being disconnected.
  • the light shielding layer 60 of the photodiode 50 is formed on the first metal layer 111 made of an alloy containing tungsten as a main component and the second metal layer made of an alloy containing aluminum as a main component.
  • the laminated metal film on which 113 was laminated was formed by patterning.
  • the light shielding layer may be formed by patterning a laminated metal film made of the same material as the gate electrode 110 of the TFT 40 and including the first metal layer 111 having the same film thickness and laminated with three or more metal layers. .
  • the thickness of the light shielding layer can be increased, the light from the backlight light source directly incident on the photodiode is more completely shielded, and the light from the backlight light source reflected by the finger or the like to be detected originally is reflected.
  • the detection sensitivity can be further increased.
  • the light shielding layer of the photodiode may be formed of a metal layer made of only an alloy containing tungsten as a main component.
  • the film thickness of the metal layer is, for example, 150 to 300 nm, and at least the first metal layer 111 and the second metal layer 113 of the above-described embodiment so that the role as the light shielding layer can be sufficiently achieved. It is necessary to make the film thickness to the extent of the combined thickness. In this case, instead of forming two types of metal layers, it is only necessary to adjust the film thickness of one type of metal layer to form a film, so that the film forming process can be simplified.
  • the thickness of the gate electrode of the TFT it is necessary to reduce the thickness of the region to be the gate electrode in the thick metal layer by etching.
  • an etchant mainly containing hydrofluoric acid, hydrofluoric acid, hydrogen peroxide, or the like is used for wet etching of a metal layer made of an alloy containing tungsten as a main component.
  • FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device 300 including a double gate TFT 42 according to a third modification of the present invention.
  • the same constituent elements as those of the semiconductor device 100 shown in FIG. 10 the same constituent elements as those of the semiconductor device 100 shown in FIG.
  • the first gate electrode 410 is not only formed on the glass substrate 101, but also the second gate, as in the TFT 40 of the semiconductor device 100 shown in FIG.
  • a gate electrode 415 is formed on the second interlayer insulating film 132 facing the channel region 120c.
  • the voltage applied to the second gate electrode 415 is fixed to a predetermined voltage, so that the back gate effect can be generated, and the threshold voltage can be stabilized.
  • the threshold voltage can be changed by changing the voltage applied to the second gate electrode 415. In this case, the threshold voltage can be easily changed only by changing the voltage applied to the second gate electrode 415 without changing the manufacturing process of the semiconductor device 300.
  • the second gate electrode 415 of the double-gate TFT 42 is patterned simultaneously with the source electrode 140a and the drain electrode 140b by patterning a metal film such as an aluminum film formed to form the source electrode 140a and the drain electrode 140b. It is formed. For this reason, in the manufacturing method of the above-described embodiment, it is only necessary to use another mask instead of the mask for patterning the source electrode 140a, the drain electrode 140b and the like described in FIG. There is no need to add a new.
  • FIG. 11 is a perspective view showing a configuration of a liquid crystal panel 80 including a photodiode 25 that functions as an ambient light sensor according to a fourth modification of the present invention.
  • the same components as those of the liquid crystal panel 10 shown in FIG. 10 the same components as those of the liquid crystal panel 10 shown in FIG.
  • the photodiode 25 is provided in the frame region of the TFT substrate 11, and the backlight control circuit 26 is provided adjacent to the photodiode 25. Since the backlight control circuit 26 adjusts the intensity of the light from the backlight source 13 based on the output of the photodiode 25, the brightness of the image can be adjusted according to the intensity of the external light.
  • the touch sensor and the ambient sensor are collectively referred to as an optical sensor, the touch sensor is referred to as a first optical sensor, and the ambient sensor is referred to as a second optical sensor.
  • the photodiode 50 including the light shielding layer 60 is formed on the glass substrate 101 together with the bottom gate TFT 40.
  • the semiconductor element formed together with the bottom gate TFT 40 may be a TFT having a wiring layer with low wiring resistance in order to prevent signal delay.
  • the wiring layer is formed using a laminated metal film in which a first metal layer and a second metal layer having a higher conductivity than the first metal layer are laminated.
  • the island-like silicon layer 120 made of polycrystalline silicon is formed so as to cover the step at the end of the gate electrode 110 made of a conductive material such as metal.
  • the island-like silicon layer 120 may be formed so as to cover the step at the end of the structure portion made of an insulating material.
  • the semiconductor device 100 shown in FIG. 4 is applied to the TFT substrate 11 of the active matrix liquid crystal display device.
  • the semiconductor device 100 is also applied to the TFT substrate of an active matrix organic EL (Electro-Luminescence) display device. Can do.
  • the present invention is suitable for display devices such as an active matrix type liquid crystal display device having a touch panel function and a liquid crystal display device in which the intensity of light from a backlight light source is adjusted by an ambient sensor.

Abstract

Disclosed is a semiconductor device including a plurality of types of semiconductor elements which have a thickness in accordance with each of the roles thereof, and are provided with structure sections manufactured in the same process. Specifically disclosed is a semiconductor device (100) which includes a TFT (40) and a photodiode (50). A gate electrode (110) of the TFT (40) and a light-shielding layer (60) of the photodiode (50) are formed in the same process. However, the film thickness of the gate electrode (110) is thin, so that the step separation of an island-shaped silicon layer (120) serving as a channel layer can be prevented at the end of the gate electrode (110). The film thickness of the light-shielding layer (60) is thick, so that light made incident from the surface on the reverse side from the surface of a glass substrate (101) on which the TFT is formed can be reliably shielded by the light-shielding layer (60). This makes it possible to increase the detection sensitivity of the photodiode (50).

Description

半導体装置、それを備えた表示装置、および半導体装置の製造方法Semiconductor device, display device including the same, and method for manufacturing semiconductor device
　本発明は、半導体装置、それを備えた表示装置、および半導体装置の製造方法に関し、より詳しくは、複数種類の半導体素子が同一の絶縁基板上に形成された半導体装置、それを備えた表示装置、および半導体装置の製造方法に関する。 The present invention relates to a semiconductor device, a display device including the same, and a method for manufacturing the semiconductor device. More specifically, the present invention relates to a semiconductor device in which a plurality of types of semiconductor elements are formed on the same insulating substrate, and a display device including the semiconductor device. And a method of manufacturing a semiconductor device.
　近年、タッチパネル機能を有する液晶パネルを備えたアクティブマトリクス型の液晶表示装置の開発が進められている。このような液晶表示装置の液晶パネルには、映像を表示する表示領域に形成された画素形成部ごとに、スイッチング素子として機能する薄膜トランジスタ（Thin Film Transistor：以下、「ＴＦＴ」という）と、タッチセンサとして機能するフォトダイオードとが設けられている。また、表示領域の周囲の額縁領域には、ＴＦＴによって構成されたゲートドライバやソースドライバ等が形成されることも多くなっている。 In recent years, active matrix liquid crystal display devices equipped with a liquid crystal panel having a touch panel function have been developed. A liquid crystal panel of such a liquid crystal display device includes a thin film transistor (hereinafter referred to as “TFT”) functioning as a switching element for each pixel formation portion formed in a display area for displaying an image, and a touch sensor. And a photodiode functioning as a. In addition, in the frame area around the display area, a gate driver, a source driver, and the like constituted by TFTs are often formed.
　特許文献１には、タッチセンサとして機能するフォトダイオードと、画素形成部のスイッチング素子として機能するＴＦＴとが同一の透明基板上に形成された液晶パネルが記載されている。ＴＦＴのチャネル層は非晶質シリコン層を結晶化した結晶性シリコン層からなり、ゲート電極はチャネル層の上方に形成されている。一方、フォトダイオードは、ＴＦＴのチャネル層と同時に形成された非晶質シリコンからなるｎ型シリコン領域とｐ型シリコン領域とが接合されたｐｎ接合ダイオードである。フォトダイオードには、バックライト光源からの光がフォトダイオードに入射しないように、フォトダイオードの下方のガラス基板上に遮光層が形成されている。 Patent Document 1 describes a liquid crystal panel in which a photodiode that functions as a touch sensor and a TFT that functions as a switching element of a pixel formation portion are formed on the same transparent substrate. The channel layer of the TFT is made of a crystalline silicon layer obtained by crystallizing an amorphous silicon layer, and the gate electrode is formed above the channel layer. On the other hand, the photodiode is a pn junction diode in which an n-type silicon region made of amorphous silicon and a p-type silicon region are formed at the same time as the TFT channel layer. In the photodiode, a light shielding layer is formed on the glass substrate below the photodiode so that light from the backlight source does not enter the photodiode.
　このように、ＴＦＴのゲート電極はシリコン層の上方に形成され、遮光層はシリコン層の下方に形成されるので、ゲート電極と遮光層とを同一工程で形成することはできない。このため、液晶パネルの製造工程が複雑になり、製造コストが高くなる。 Thus, since the gate electrode of the TFT is formed above the silicon layer and the light shielding layer is formed below the silicon layer, the gate electrode and the light shielding layer cannot be formed in the same process. This complicates the manufacturing process of the liquid crystal panel and increases the manufacturing cost.
　そこで、ＴＦＴのゲート電極と遮光層とを同一工程で形成するため、特許文献１に記載されたＴＦＴを、ゲート電極がガラス基板上に形成されたボトムゲート型のＴＦＴに置き換える。このようにすれば、ＴＦＴのゲート電極と遮光層とを同一工程で形成することができるので、液晶パネルの製造工程を簡略化することができ、製造コストを低減することができる。 Therefore, in order to form the gate electrode and the light shielding layer of the TFT in the same process, the TFT described in Patent Document 1 is replaced with a bottom gate type TFT in which the gate electrode is formed on a glass substrate. In this way, since the TFT gate electrode and the light shielding layer can be formed in the same process, the manufacturing process of the liquid crystal panel can be simplified and the manufacturing cost can be reduced.
日本国特開２００９－１２８５２０号公報Japanese Unexamined Patent Publication No. 2009-128520
　しかし、ＴＦＴのゲート電極と遮光層とを同一工程で同時に形成するので、ゲート電極の膜厚と遮光層の膜厚とは等しくなる。ゲート電極の膜厚が厚ければ、ゲート電極の端部で、ガラス基板との間の段差が大きくなるので、ゲート電極を覆うように形成された非晶質シリコン層の段差もゲート電極の端部で大きくなる。このような非晶質シリコン層を多結晶シリコン層にするために、非晶質シリコン層の上面からレーザ光を照射して、非晶質シリコン層を溶融させれば、溶融したシリコンがガラス基板側に流れて固化し、多結晶シリコン層になる。この場合、多結晶シリコン層は、ゲート電極の端部で段切れをおこし、ＴＦＴのチャネル層として機能しなくなる。 However, since the gate electrode of the TFT and the light shielding layer are formed simultaneously in the same process, the film thickness of the gate electrode is equal to the film thickness of the light shielding layer. If the gate electrode is thick, the step between the glass substrate and the edge of the gate electrode becomes large. Therefore, the step of the amorphous silicon layer formed so as to cover the gate electrode is also the edge of the gate electrode. Become bigger in the department. In order to make such an amorphous silicon layer into a polycrystalline silicon layer, laser light is irradiated from the upper surface of the amorphous silicon layer to melt the amorphous silicon layer. It flows to the side and solidifies to become a polycrystalline silicon layer. In this case, the polycrystalline silicon layer is disconnected at the end of the gate electrode and does not function as a channel layer of the TFT.
　また、非晶質シリコン層に照射されたレーザ光のエネルギーは熱エネルギーになる。ゲート電極が熱伝導率の大きな材料によって形成されている場合、熱エネルギーの一部はゲート電極を介してゲート配線に逃げてしまう。したがって、非晶質シリコン層を長時間に渡って高温状態に維持することができないので、多結晶シリコン層の結晶粒径は十分大きくならず、多結晶シリコン層の移動度は小さくなる。 Also, the energy of the laser beam irradiated on the amorphous silicon layer becomes thermal energy. When the gate electrode is formed of a material having high thermal conductivity, part of the thermal energy escapes to the gate wiring through the gate electrode. Therefore, since the amorphous silicon layer cannot be maintained at a high temperature for a long time, the crystal grain size of the polycrystalline silicon layer is not sufficiently large, and the mobility of the polycrystalline silicon layer is small.
　一方、フォトダイオードの遮光層の膜厚が薄すぎると、バックライト光源の光を十分に遮光することができないので、フォトダイオードはバックライト光源から直接入射する光も検出してしまう。このため、指等によって反射されたバックライト光源の光の検出感度が悪くなる。 On the other hand, if the thickness of the light shielding layer of the photodiode is too thin, the light from the backlight source cannot be sufficiently shielded, so that the photodiode also detects light directly incident from the backlight source. For this reason, the detection sensitivity of the light of the backlight light source reflected by a finger or the like deteriorates.
　このように、ＴＦＴのゲート電極とフォトダイオードの遮光層とを同じ層の導電膜によって形成すれば、それらの膜厚が等しくなるので、ＴＦＴのゲート電極としては最適であってもフォトダイオードの遮光層としては問題があったり、逆にフォトダイオードの遮光層としては最適であってもＴＦＴのゲート電極としては問題があったりする。 Thus, if the TFT gate electrode and the light-shielding layer of the photodiode are formed of the same conductive film, their film thicknesses are equal. Therefore, even if the TFT gate electrode is optimal, the light-shielding of the photodiode is achieved. There is a problem as a layer, and conversely, there is a problem as a gate electrode of a TFT even though it is optimal as a light shielding layer of a photodiode.
　一方、ボトムゲート型ＴＦＴのゲート電極とフォトダイオードの遮光層とを別工程で形成すれば、それぞれの膜厚を最適な膜厚に設定することができる。しかし、液晶パネルの製造プロセスが複雑になり、製造コストが高くなる。 On the other hand, if the gate electrode of the bottom gate type TFT and the light shielding layer of the photodiode are formed in separate steps, the respective film thicknesses can be set to optimum film thicknesses. However, the manufacturing process of the liquid crystal panel becomes complicated and the manufacturing cost increases.
　そこで、本発明の目的は、それぞれの役割に応じた厚みを有し、同一工程で製造された構造部を備える複数種類の半導体素子を含む半導体装置を提供することである。また、本発明の他の目的は、そのような半導体装置の製造プロセスを簡略化し、安価なコストで製造することができる半導体装置の製造方法を提供することである。 Therefore, an object of the present invention is to provide a semiconductor device including a plurality of types of semiconductor elements each having a thickness corresponding to each role and including a structure portion manufactured in the same process. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can be manufactured at a low cost by simplifying the manufacturing process of such a semiconductor device.
　本発明の第１の局面は、少なくとも第１の半導体素子と前記第１の半導体素子とは異なる種類の第２の半導体素子とが同一の絶縁基板上に形成された半導体装置であって、
　前記第１の半導体素子は、
　　段差を有し、第１の層からなる第１の構造部と、
　　前記第１の構造部の少なくとも前記段差を覆うように形成された多結晶半導体層とを備え、
　前記第２の半導体素子は、
　　前記第１の層と同じ材料からなる第２の層を含み、前記第１の構造部よりも厚い第２の構造部を備え、
　前記第１の構造部の段差は、前記多結晶半導体層を段切れさせることなく形成可能な段差であることを特徴とする。 A first aspect of the present invention is a semiconductor device in which at least a first semiconductor element and a second semiconductor element of a different type from the first semiconductor element are formed on the same insulating substrate,
The first semiconductor element is:
A first structure having a step and comprising a first layer;
A polycrystalline semiconductor layer formed to cover at least the step of the first structure portion,
The second semiconductor element is:
Including a second layer made of the same material as the first layer, and comprising a second structure part thicker than the first structure part,
The step of the first structure portion is a step that can be formed without breaking the polycrystalline semiconductor layer.
　本発明の第２の局面は、本発明の第１の局面において、
　少なくとも前記第１の構造部の段差の形状はテーパ状であることを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
At least the shape of the step of the first structure portion is tapered.
　本発明の第３の局面は、本発明の第１の局面において、
　前記第１の半導体素子はボトムゲート型薄膜トランジスタであり、
　　前記第１の構造部は前記ボトムゲート型薄膜トランジスタのゲート電極であり、
　　前記多結晶半導体層は前記ボトムゲート型薄膜トランジスタのチャネル層であり、
　前記第２の半導体素子は、前記絶縁基板の前記ボトムゲート型薄膜トランジスタが形成された第１の面側から入射する光を受光する光センサであり、
　　前記第２の構造部は、前記絶縁基板において、前記第１の面と対向する第２の面側から前記光センサに入射する光を遮光する遮光層であることを特徴とする。 According to a third aspect of the present invention, in the first aspect of the present invention,
The first semiconductor element is a bottom-gate thin film transistor;
The first structure portion is a gate electrode of the bottom-gate thin film transistor;
The polycrystalline semiconductor layer is a channel layer of the bottom-gate thin film transistor;
The second semiconductor element is an optical sensor that receives light incident from a first surface side of the insulating substrate on which the bottom-gate thin film transistor is formed,
The second structure portion is a light shielding layer that shields light incident on the photosensor from a second surface side facing the first surface in the insulating substrate.
　本発明の第４の局面は、本発明の第３の局面において、
　前記遮光層は前記第２の層のみからなり、
　前記第２の層の膜厚は前記ゲート電極の膜厚よりも厚いことを特徴とする。 According to a fourth aspect of the present invention, in the third aspect of the present invention,
The light shielding layer consists only of the second layer,
The second layer has a thickness greater than that of the gate electrode.
　本発明の第５の局面は、本発明の第３の局面において、
　前記遮光層は前記第２の層を含む複数の層からなり、
　前記第２の層の膜厚は前記ゲート電極の膜厚と等しいことを特徴とする。 According to a fifth aspect of the present invention, in the third aspect of the present invention,
The light shielding layer is composed of a plurality of layers including the second layer,
The thickness of the second layer is equal to the thickness of the gate electrode.
　本発明の第６の局面は、本発明の第３の局面において、
　前記チャネル層は、長軸の方向がチャネル長の方向に形成されたラテラル結晶を含む多結晶半導体層であることを特徴とする。 According to a sixth aspect of the present invention, in the third aspect of the present invention,
The channel layer is a polycrystalline semiconductor layer including a lateral crystal whose major axis is formed in the channel length direction.
　本発明の第７の局面は、本発明の第３の局面において、
　前記光センサは、ラテラル型ｐｉｎ構造のフォトダイオードであることを特徴とする。 According to a seventh aspect of the present invention, in the third aspect of the present invention,
The optical sensor is a photodiode having a lateral pin structure.
　本発明の第８の局面は、本発明の第３の局面において、
　前記薄膜トランジスタのゲート電極に接続された配線をさらに含み、
　前記配線は、前記第１の層の上面に積層された、前記第１の層よりも導電率の大きな材料からなる第３の層をさらに含むことを特徴とする。 According to an eighth aspect of the present invention, in the third aspect of the present invention,
Further comprising a wiring connected to the gate electrode of the thin film transistor,
The wiring further includes a third layer made of a material having a higher conductivity than the first layer, which is laminated on the upper surface of the first layer.
　本発明の第９の局面は、第３の局面に係る半導体装置をそれぞれが含む複数の画素形成部を絶縁基板上に備えた表示装置であって、
　前記複数の画素形成部のそれぞれは、
　　画素電極と、
　　オフ状態からオン状態に切り換わることによって電圧を前画素電極に印加する薄膜トランジスタと、
　　前記画素形成部内に入射する光を受光する第１の光センサとを備え、
　前記薄膜トランジスタおよび前記第１の光センサは、それぞれ第１の半導体素子および第２の半導体素子であることを特徴とする。 A ninth aspect of the present invention is a display device including a plurality of pixel formation portions each including a semiconductor device according to the third aspect on an insulating substrate,
Each of the plurality of pixel formation portions includes
A pixel electrode;
A thin film transistor that applies a voltage to the previous pixel electrode by switching from an off state to an on state; and
A first photosensor that receives light incident on the pixel formation portion,
The thin film transistor and the first photosensor are a first semiconductor element and a second semiconductor element, respectively.
　本発明の第１０の局面は、本発明の第９の局面において、
　前記画素形成部を駆動する駆動回路をさらに含み、
　前記駆動回路は前記第１の半導体素子によって構成されていることを特徴とする。 According to a tenth aspect of the present invention, in a ninth aspect of the present invention,
A driving circuit for driving the pixel forming unit;
The drive circuit is configured by the first semiconductor element.
　本発明の第１１の局面は、本発明の第９の局面において、
　バックライト光源と、
　前記複数の画素形成部が形成された表示領域の外側に配置され、外光の強度を検出する第２の光センサと、
　前記第２の光センサの出力に基づいて前記バックライト光源の輝度を制御するバックライト制御回路とをさらに含み、
　前記第２の光センサは前記第２の半導体素子であることを特徴とする。 An eleventh aspect of the present invention is the ninth aspect of the present invention,
A backlight light source;
A second optical sensor that is disposed outside a display area in which the plurality of pixel forming portions are formed and detects the intensity of external light;
A backlight control circuit that controls the luminance of the backlight light source based on the output of the second photosensor;
The second optical sensor is the second semiconductor element.
　本発明の第１２の局面は、ボトムゲート型薄膜トランジスタと、遮光層を有する光センサとが同一の絶縁基板上に形成された半導体装置の製造方法であって、
　前記絶縁基板上に第１の導電層を成膜する工程と、
　前記第１の導電層上に第２の導電層を成膜する工程と、
　ハーフトーンマスクを用いて露光することにより、前記第２の導電層上において、ゲート電極となるべき領域に第１のレジストパターンを形成し、遮光層となるべき領域に、前記第１のレジストパターンよりも厚い膜厚の第２のレジストパターンを形成する工程と、
　前記第１および第２のレジストパターンをマスクとして、前記第２導電層、前記第１の導電層の順にエッチングして前記遮光層を形成する工程と、
　前記第１および第２のレジストパターンの膜厚を同時に薄くすることによって、前記第１のレジストパターンで覆われていた第２の導電層の表面を露出させる工程と、
　表面を露出させた前記第２の導電層を除去して、前記ゲート電極を形成する工程とを備えることを特徴とする。 A twelfth aspect of the present invention is a method for manufacturing a semiconductor device in which a bottom gate thin film transistor and a photosensor having a light shielding layer are formed on the same insulating substrate,
Forming a first conductive layer on the insulating substrate;
Forming a second conductive layer on the first conductive layer;
By exposing using a halftone mask, a first resist pattern is formed in a region to be a gate electrode on the second conductive layer, and the first resist pattern is formed in a region to be a light shielding layer. Forming a thicker second resist pattern; and
Etching the second conductive layer and the first conductive layer in this order using the first and second resist patterns as a mask to form the light shielding layer;
Exposing the surface of the second conductive layer covered with the first resist pattern by simultaneously reducing the thickness of the first and second resist patterns;
And removing the second conductive layer whose surface is exposed to form the gate electrode.
　本発明の第１３の局面は、本発明の第１２の局面において、
　前記ゲート電極および前記遮光層を覆うように非晶質半導体層を形成する工程と、
　前記非晶質半導体層に連続発振レーザのレーザ光を照射して溶融させた後に固化させて、多結晶半導体層を形成する工程と、
　前記多結晶半導体層をパターニングすることにより、前記ゲート電極を覆う前記薄膜トランジスタのチャネル層を形成すると同時に、前記光センサの半導体層を前記遮光層の上方に形成する工程とをさらに含むことを特徴とする。 A thirteenth aspect of the present invention is the twelfth aspect of the present invention,
Forming an amorphous semiconductor layer so as to cover the gate electrode and the light shielding layer;
Irradiating the amorphous semiconductor layer with laser light of a continuous wave laser and melting the amorphous semiconductor layer and then solidifying the amorphous semiconductor layer to form a polycrystalline semiconductor layer;
Forming a channel layer of the thin film transistor covering the gate electrode by patterning the polycrystalline semiconductor layer, and simultaneously forming a semiconductor layer of the photosensor above the light shielding layer. To do.
　本発明の第１の局面によれば、第１の半導体素子では、少なくとも第１の構造部の段差を覆うように多結晶半導体層が形成され、第１の構造部の段差は、多結晶半導体層の形成時に多結晶半導体層が段切れしないような段差である。このため、多結晶半導体層の段切れにより第１の半導体素子が動作しなくなることを防止できる。一方、第２の半導体素子では、第２の構造部の厚みが第１の構造部の厚みよりも厚いので、第２の構造部を遮光層として用いたり、配線抵抗の低い配線として用いたりすることができる。 According to the first aspect of the present invention, in the first semiconductor element, the polycrystalline semiconductor layer is formed so as to cover at least the step of the first structure portion, and the step of the first structure portion is formed of the polycrystalline semiconductor. The level difference is such that the polycrystalline semiconductor layer does not break when the layer is formed. For this reason, it can be prevented that the first semiconductor element does not operate due to the disconnection of the polycrystalline semiconductor layer. On the other hand, in the second semiconductor element, since the thickness of the second structure portion is larger than the thickness of the first structure portion, the second structure portion is used as a light shielding layer or a wiring having a low wiring resistance. be able to.
　本発明の第２の局面によれば、第１の構造部の段差の形状がテーパ状になっているので、多結晶半導体層は第１の構造部の段差によって段切れしにくくなる。このため、第１の半導体素子が多結晶半導体層の段切れにより動作しなくなることをより一層防止できる。 According to the second aspect of the present invention, since the shape of the step of the first structure portion is tapered, the polycrystalline semiconductor layer is difficult to be cut by the step of the first structure portion. Therefore, it is possible to further prevent the first semiconductor element from operating due to the disconnection of the polycrystalline semiconductor layer.
　本発明の第３の局面によれば、ボトムゲート型薄膜トランジスタでは、チャネル層は多結晶半導体層によって形成される。このため、チャネル層の移動度は高くなり、ボトムゲート型薄膜トランジスタを高速で動作させることができる。また、ゲート電極の端部での多結晶シリコン層の段切れを防止できるので、ボトムゲート型薄膜トランジスタを確実に動作させることができる。光センサでは、ボトムゲート型薄膜トランジスタが形成された絶縁基板の第１の面と対向する第２の面側から入射する光を遮光層によって遮光することができるので、光センサをタッチセンサとして用いた場合、光センサの検出感度を高くすることができる。 According to the third aspect of the present invention, in the bottom gate type thin film transistor, the channel layer is formed of a polycrystalline semiconductor layer. Therefore, the mobility of the channel layer is increased, and the bottom gate thin film transistor can be operated at high speed. In addition, since the polycrystalline silicon layer can be prevented from being disconnected at the end of the gate electrode, the bottom gate thin film transistor can be operated reliably. In the optical sensor, light incident from the second surface facing the first surface of the insulating substrate on which the bottom-gate thin film transistor is formed can be shielded by the light shielding layer, and thus the optical sensor is used as a touch sensor. In this case, the detection sensitivity of the optical sensor can be increased.
　本発明の第４の局面によれば、遮光層は、ゲート電極と同じ材料からなる第２の層のみによって構成されるので、遮光層を容易に成膜することができる。また、第２の層の膜厚はゲート電極の膜厚よりも厚いので、遮光層は第２の面側から入射する光を遮光することができる。 According to the fourth aspect of the present invention, since the light shielding layer is composed of only the second layer made of the same material as the gate electrode, the light shielding layer can be easily formed. Further, since the thickness of the second layer is larger than the thickness of the gate electrode, the light shielding layer can shield light incident from the second surface side.
　本発明の第５の局面によれば、遮光層は、ゲート電極と同じ膜厚からなる第２の層を含む複数の層からなるので、第２の面側から入射する光をより一層遮光することができる。 According to the fifth aspect of the present invention, the light shielding layer is composed of a plurality of layers including the second layer having the same thickness as that of the gate electrode, so that the light incident from the second surface side is further shielded. be able to.
　本発明の第６の局面によれば、ボトムゲート型薄膜トランジスタのチャネル層は長軸の方向がチャネル長の方向に形成された、結晶粒径の大きなラテラル結晶を含む多結晶半導体層であるので、チャネル層の移動度が大きくなる。このため、ボトムゲート型薄膜トランジスタを高速で動作させることができる。 According to the sixth aspect of the present invention, the channel layer of the bottom-gate thin film transistor is a polycrystalline semiconductor layer including a lateral crystal having a large crystal grain size and having a major axis direction formed in the channel length direction. The mobility of the channel layer is increased. Therefore, the bottom gate thin film transistor can be operated at high speed.
　本発明の第７の局面によれば、光センサは、ラテラル型ｐｉｎ構造のフォトダイオードである。これにより、光センサの量子効率を大きくできると共に、応答速度を速くすることができる。 According to the seventh aspect of the present invention, the optical sensor is a photodiode having a lateral pin structure. Thereby, the quantum efficiency of the photosensor can be increased and the response speed can be increased.
　本発明の第８の局面によれば、ボトムゲート型薄膜トランジスタのゲート電極に接続された配線は、第１の層の上面に、第１の層よりも導電率の大きな材料からなる第３の層を含む。これにより、配線を介してゲート電極に与えられる信号の遅延を防止することができる。 According to the eighth aspect of the present invention, the wiring connected to the gate electrode of the bottom-gate thin film transistor has a third layer made of a material having a higher conductivity than the first layer on the upper surface of the first layer. including. Thereby, delay of a signal applied to the gate electrode through the wiring can be prevented.
　本発明の第９の局面によれば、絶縁基板上に形成された表示装置の画素形成部に含まれる薄膜トランジスタとして、第３の発明に係る半導体装置の第１の半導体素子であるボトムゲート型薄膜トランジスタを用い、第１の光センサとして半導体装置の第２の半導体素子である光センサを用いれば、薄膜トランジスタを高速で動作させることができると共に、第１の光センサの検出感度を高くすることができる。このため、表示装置にタッチパネル機能をもたせることができる。 According to the ninth aspect of the present invention, the bottom gate type thin film transistor which is the first semiconductor element of the semiconductor device according to the third invention is used as the thin film transistor included in the pixel formation portion of the display device formed on the insulating substrate. If the photosensor which is the second semiconductor element of the semiconductor device is used as the first photosensor, the thin film transistor can be operated at high speed and the detection sensitivity of the first photosensor can be increased. . For this reason, the display device can have a touch panel function.
　本発明の第１０の局面によれば、表示装置の画素形成部を駆動する駆動回路を、第３の発明に係る半導体装置の第１の半導体素子であるボトムゲート型薄膜トランジスタによって構成すれば、薄膜トランジスタの動作速度が速くなるので、駆動回路の動作速度も速くすることができる。 According to the tenth aspect of the present invention, if the driving circuit for driving the pixel forming portion of the display device is constituted by the bottom gate type thin film transistor which is the first semiconductor element of the semiconductor device according to the third invention, the thin film transistor As a result, the operating speed of the driving circuit can be increased.
　本発明の第１１の局面によれば、表示装置には、外光の強度を検出できる第２の光センサが設けられている。第２の光センサとして、第３の発明に係る半導体装置の第２の半導体素子である光センサを用いれば、バックライト光源からの光による影響を受けることなく、外光の強度を検出することができるので、第２の光センサはアンビエントセンサとして機能する。これにより、表示装置は外光の強度に応じてバックライト光源の照度を調整することができる。 According to the eleventh aspect of the present invention, the display device is provided with a second optical sensor capable of detecting the intensity of external light. If the optical sensor which is the second semiconductor element of the semiconductor device according to the third invention is used as the second optical sensor, the intensity of external light can be detected without being affected by the light from the backlight light source. Therefore, the second optical sensor functions as an ambient sensor. Thereby, the display apparatus can adjust the illumination intensity of a backlight light source according to the intensity | strength of external light.
　本発明の第１２の局面によれば、ハーフトーンマスクを用いたフォトリソグラフィ法により、ゲート電極となるべき領域上に第１のレジストパターンを形成し、遮光層となるべき領域上に、第１のレジストパターンよりも厚い膜厚を有する第２のレジストパターンを形成する。第１および第２のレジストパターンをマスクとして、積層膜をエッチングする。これにより、遮光層が形成される。さらに第１および第２のレジストパターンの膜厚を同時に薄くすれば、第１のレジストパターンが除去されて、ゲート電極となるべき領域の第２の導電層の表面が露出される。次に、第２のレジストパターンを残した状態で、表面が露出した第２の導電層を除去することにより、ゲート電極を形成する。このように、ハーフトーンマスクを用いて形成した第１のレジストパターンと第２のレジストパターンの膜厚差を利用して、膜厚の異なるゲート電極と遮光層を１回のフォトリソグラフィ工程で形成することができるので、半導体装置の製造方法を簡略化することができ、製造コストを低減できる。 According to the twelfth aspect of the present invention, the first resist pattern is formed on the region to be the gate electrode by the photolithography method using the halftone mask, and the first resist pattern is formed on the region to be the light shielding layer. A second resist pattern having a thickness larger than that of the resist pattern is formed. The laminated film is etched using the first and second resist patterns as a mask. Thereby, a light shielding layer is formed. Further, if the thicknesses of the first and second resist patterns are reduced simultaneously, the first resist pattern is removed and the surface of the second conductive layer in the region to be the gate electrode is exposed. Next, the gate electrode is formed by removing the second conductive layer whose surface is exposed while leaving the second resist pattern. In this way, the gate electrode and the light shielding layer having different thicknesses are formed in one photolithography process by using the difference in thickness between the first resist pattern and the second resist pattern formed using the halftone mask. Therefore, the manufacturing method of the semiconductor device can be simplified, and the manufacturing cost can be reduced.
　本発明の第１３の局面によれば、成膜された非晶質半導体層に連続発振レーザのレーザ光を照射して多結晶半導体層を形成する。このようにして形成された多結晶半導体層の結晶粒はラテラル結晶になるので、多結晶半導体層の移動度が大きくなる。このため、薄膜トランジスタを高速で動作させることができる。 According to the thirteenth aspect of the present invention, a polycrystalline semiconductor layer is formed by irradiating the deposited amorphous semiconductor layer with laser light of a continuous wave laser. Since the crystal grains of the polycrystalline semiconductor layer thus formed are lateral crystals, the mobility of the polycrystalline semiconductor layer is increased. Therefore, the thin film transistor can be operated at high speed.
本発明の実施形態に係るアクティブマトリクス型液晶表示装置に含まれるタッチパネル機能を備えた液晶パネルの構成を示す斜視図である。It is a perspective view which shows the structure of the liquid crystal panel provided with the touchscreen function contained in the active matrix type liquid crystal display device which concerns on embodiment of this invention. 液晶パネルの表示領域の構成を示す回路図である。It is a circuit diagram which shows the structure of the display area of a liquid crystal panel. 図１に示す液晶パネルの表示領域の断面を示す断面図である。It is sectional drawing which shows the cross section of the display area of the liquid crystal panel shown in FIG. 本発明の実施形態に係る半導体装置に含まれる、ボトムゲート型のＴＦＴとフォトダイオードの構成を示す平面図である。It is a top view which shows the structure of bottom gate type TFT and a photodiode contained in the semiconductor device which concerns on embodiment of this invention. 図４に示す半導体装置の構成を示す断面図である。FIG. 5 is a cross-sectional view illustrating a configuration of the semiconductor device illustrated in FIG. 4. （Ａ）～（Ｆ）は図５に示す半導体装置の各製造工程を示す工程断面図である。FIGS. 6A to 6F are process cross-sectional views illustrating each manufacturing process of the semiconductor device shown in FIG. （Ｇ）～（Ｊ）は図５に示す半導体装置の各製造工程を示す工程断面図である。FIGS. 6G to 6J are process cross-sectional views illustrating the manufacturing steps of the semiconductor device illustrated in FIG. 連続発振レーザとエキシマレーザを使用して結晶化した多結晶シリコン層の移動度を示す図である。It is a figure which shows the mobility of the polycrystalline-silicon layer crystallized using the continuous wave laser and the excimer laser. 本発明の第１の変形例に係る、ゲート電極の端部の形状がテーパ状であるＴＦＴを備えた半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device provided with TFT which the shape of the edge part of a gate electrode concerns on the 1st modification of this invention. 本発明の第３の変形例に係る、ダブルゲート型ＴＦＴを含む半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device containing the double gate type TFT based on the 3rd modification of this invention. 本発明の第４の変形例に係る、アンビエントライトセンサとして機能するフォトダイオードを備えた液晶パネルの構成を示す斜視図である。It is a perspective view which shows the structure of the liquid crystal panel provided with the photodiode which functions as an ambient light sensor based on the 4th modification of this invention.
＜１．　液晶表示装置＞
　図１は、本発明の実施形態に係るアクティブマトリクス型液晶表示装置に含まれるタッチパネル機能を備えた液晶パネル１０の構成を示す斜視図である。図１には、液晶層を挟持するように対向して配置された２枚の低アルカリガラス基板（以下、「ガラス基板」という）のうち、ＴＦＴやフォトダイオード等を含む複数の画素形成部がマトリクス状に形成された基板１１（以下、「ＴＦＴ基板１１」という）と、ＴＦＴ基板１１の裏面側（図１の下側）に、ＴＦＴ基板１１と対向して配置されたバックライト光源１３とが図示されている。しかし、ＴＦＴ基板１１の表面側（図１の上側）と対向して配置され、カラーフィルタ（Color Filter）等が形成されたガラス基板（ＣＦ基板）、および、ＴＦＴ基板１１とＣＦ基板とによって挟持された液晶層は省略されている。 <1. Liquid crystal display>
FIG. 1 is a perspective view showing a configuration of a liquid crystal panel 10 having a touch panel function included in an active matrix liquid crystal display device according to an embodiment of the present invention. FIG. 1 shows a plurality of pixel formation portions including TFTs, photodiodes, etc., out of two low alkali glass substrates (hereinafter referred to as “glass substrates”) arranged to face each other so as to sandwich a liquid crystal layer. A substrate 11 (hereinafter referred to as “TFT substrate 11”) formed in a matrix, and a backlight light source 13 disposed on the back side (lower side in FIG. 1) of the TFT substrate 11 so as to face the TFT substrate 11. Is shown. However, the glass substrate (CF substrate) disposed opposite to the surface side of the TFT substrate 11 (upper side in FIG. 1) and having a color filter or the like formed thereon, and sandwiched between the TFT substrate 11 and the CF substrate. The liquid crystal layer thus formed is omitted.
　図１に示すように、ＴＦＴ基板１１の中央付近に、複数の画素形成部からなり、映像が表示される表示領域２１が形成されている。各画素形成部には、後述するように、スイッチング素子として機能するＴＦＴとタッチセンサとして機能するフォトダイオードとが形成されている。表示領域２１の外側の額縁領域には、ＴＦＴをオン／オフさせるタイミングを制御する制御信号をゲート配線に出力するゲートドライバ２２、画素形成部に映像を表示させる映像信号や映像信号を出力するタイミングを制御する制御信号をソース配線に出力するソースドライバ２３（ゲートドライバとソースドライバをまとめて「駆動回路」ということがある）、およびフォトダイオードで検出された光の強度に基づいて液晶パネル１０上のタッチされた位置を検出する位置検出回路２４が設けられている。 As shown in FIG. 1, a display area 21 is formed in the vicinity of the center of the TFT substrate 11 and includes a plurality of pixel forming portions and displays an image. As will be described later, in each pixel formation portion, a TFT functioning as a switching element and a photodiode functioning as a touch sensor are formed. In the frame area outside the display area 21, a gate driver 22 that outputs a control signal for controlling the timing of turning on / off the TFT to the gate wiring, a video signal for displaying an image on the pixel forming portion, and a timing for outputting the video signal On the liquid crystal panel 10 based on the intensity of light detected by the source driver 23 (the gate driver and the source driver may be collectively referred to as “driving circuit”) that outputs a control signal for controlling the source to the source wiring. A position detection circuit 24 for detecting the touched position is provided.
　図２は、液晶パネル１０の表示領域２１の構成を示す回路図である。液晶パネル１０は、ガラス基板（図示しない）上に形成された複数の画素形成部３１、複数のゲート配線ＧＬ、複数のソース配線ＳＬ、および複数のセンサ配線ＦＬを備える。ソース配線ＳＬとセンサ配線ＦＬとは、互いに平行にかつ交互に形成されている。ゲート配線ＧＬは、ソース配線ＳＬおよびセンサ配線ＦＬと交差する方向に形成されている。 FIG. 2 is a circuit diagram showing the configuration of the display area 21 of the liquid crystal panel 10. The liquid crystal panel 10 includes a plurality of pixel forming portions 31, a plurality of gate lines GL, a plurality of source lines SL, and a plurality of sensor lines FL formed on a glass substrate (not shown). The source lines SL and sensor lines FL are formed in parallel with each other and alternately. The gate line GL is formed in a direction crossing the source line SL and the sensor line FL.
　画素形成部３１はゲート配線ＧＬとソース配線ＳＬとの交点近傍に配置され、液晶セル３２とフォトダイオード５０とを含む。液晶セル３２は、バックライト光源１３からの光のうち、透過させる光の光量を調整することにより映像を表示する。フォトダイオード５０は、バックライト光源１３からの光が指やタッチペン（これらをまとめて「接触物」ということがある）等によって反射されて、画素形成部３１に入射する光を受光する。 The pixel formation portion 31 is disposed in the vicinity of the intersection of the gate line GL and the source line SL, and includes a liquid crystal cell 32 and a photodiode 50. The liquid crystal cell 32 displays an image by adjusting the amount of transmitted light among the light from the backlight light source 13. The photodiode 50 receives light incident on the pixel forming unit 31 by reflecting light from the backlight light source 13 by a finger, a touch pen (sometimes collectively referred to as a “contact”), or the like.
　液晶セル３２は、スイッチング素子として機能するＴＦＴ４０と、画素容量４５とを備える。ＴＦＴ４０のゲート電極はゲート配線ＧＬに接続され、ソース電極はソース配線ＳＬに接続され、ドレイン電極は画素電極（図示しない）に接続されている。画素容量４５は、画素電極と、画素電極と対向するようにＣＰ基板に形成された対向電極（図示しない）と、それらの電極の間に挟持された液晶層とによって構成されている。フォトダイオード５０はゲート配線ＧＬとセンサ配線ＦＬとの交点近傍に配置され、フォトダイオード５０のアノード電極はゲート配線ＧＬに接続され、カソード電極はセンサ配線ＦＬに接続されている。 The liquid crystal cell 32 includes a TFT 40 that functions as a switching element and a pixel capacitor 45. The TFT 40 has a gate electrode connected to the gate line GL, a source electrode connected to the source line SL, and a drain electrode connected to a pixel electrode (not shown). The pixel capacitor 45 includes a pixel electrode, a counter electrode (not shown) formed on the CP substrate so as to face the pixel electrode, and a liquid crystal layer sandwiched between these electrodes. The photodiode 50 is disposed in the vicinity of the intersection of the gate line GL and the sensor line FL, the anode electrode of the photodiode 50 is connected to the gate line GL, and the cathode electrode is connected to the sensor line FL.
　ゲート配線ＧＬを順に活性化して、活性化されたゲート配線ＧＬに接続されたＴＦＴ４０をオン状態にすることにより、ソース配線ＳＬに与えられた映像信号の信号電圧はＴＦＴ４０を介してドレイン電極に与えられ、画素容量４５に保持される。そして、保持された信号電圧に応じて、バックライト光源１３からの光が液晶セル３２を透過し、映像が液晶パネル１０の表示領域２１に表示される。 By sequentially activating the gate wiring GL and turning on the TFT 40 connected to the activated gate wiring GL, the signal voltage of the video signal applied to the source wiring SL is applied to the drain electrode via the TFT 40. And held in the pixel capacitor 45. Then, according to the held signal voltage, light from the backlight light source 13 is transmitted through the liquid crystal cell 32, and an image is displayed on the display area 21 of the liquid crystal panel 10.
　また、ゲート配線ＧＬに所定の電圧が印加されると、フォトダイオード５０に入射した光の強度に応じた大きさの電流が、ゲート配線ＧＬからフォトダイオード５０を介してセンサ配線ＦＬに流れる。位置検出回路２４は、センサ配線ＦＬに流れる電流を検出することにより、フォトダイオード５０が受光した光の強度を検出し、ＣＦ基板上のタッチされた位置を特定する。 Further, when a predetermined voltage is applied to the gate wiring GL, a current having a magnitude corresponding to the intensity of light incident on the photodiode 50 flows from the gate wiring GL to the sensor wiring FL via the photodiode 50. The position detection circuit 24 detects the intensity of light received by the photodiode 50 by detecting the current flowing through the sensor wiring FL, and specifies the touched position on the CF substrate.
　図３は、図１に示す液晶パネル１０の表示領域２１の断面を示す断面図である。図３に示すように、液晶パネル１０は、画素形成部３１ごとにＴＦＴ４０とフォトダイオード５０が形成されたＴＦＴ基板１１、ＴＦＴ基板１１と対向するように配置され、カラーフィルタ等が形成されたＣＦ基板１２、ＴＦＴ基板１１とＣＦ基板１２との間に挟持された液晶層（図示しない）、および、ＣＦ基板１２と反対側に、ＴＦＴ基板１１と対向するように配置されたバックライト光源１３を含む。バックライト光源１３からの光は、ＴＦＴ基板１１、液晶層、ＣＦ基板１２のカラーフィルタ（図示しない）の順に透過して、画素容量に保持された信号電圧に応じた光量の光になり、表示領域２１に映像を表示する。 FIG. 3 is a cross-sectional view showing a cross section of the display region 21 of the liquid crystal panel 10 shown in FIG. As shown in FIG. 3, the liquid crystal panel 10 is disposed so as to face the TFT substrate 11 and the TFT substrate 11 on which the TFT 40 and the photodiode 50 are formed for each pixel forming portion 31, and a CF on which a color filter or the like is formed. A substrate 12, a liquid crystal layer (not shown) sandwiched between the TFT substrate 11 and the CF substrate 12, and a backlight light source 13 disposed on the opposite side of the CF substrate 12 so as to face the TFT substrate 11. Including. The light from the backlight light source 13 is transmitted in the order of the TFT substrate 11, the liquid crystal layer, and the color filter (not shown) of the CF substrate 12, and becomes light with a light amount corresponding to the signal voltage held in the pixel capacitor. An image is displayed in the area 21.
　このような液晶パネル１０において、フォトダイオード５０の下方のＴＦＴ基板１１上に、遮光層６０が形成されている。このため、バックライト光源１３からの光は、遮光層６０によって反射され、フォトダイオード５０の受光面に入射しない。しかし、視聴者がＣＦ基板１２の表面を指等でタッチすれば、ＣＦ基板１２を透過したバックライト光源１３からの光が指等によって反射され、フォトダイオード５０の受光面に入射する。このため、タッチされた位置の下方に配置されたフォトダイオード５０は、指等によって反射された光だけを受光し、位置検出回路２４はタッチされた位置を特定しやすくなる。このように、フォトダイオード５０が指等による反射光を検出しやすくするためには、遮光層６０は、少なくともバックライト光源１３の光がフォトダイオード５０に直接入射しないように十分な膜厚を有し、かつ平面視においてフォトダイオード５０よりも大きな面積を有するように形成されていなければならない。 In such a liquid crystal panel 10, the light shielding layer 60 is formed on the TFT substrate 11 below the photodiode 50. For this reason, the light from the backlight light source 13 is reflected by the light shielding layer 60 and does not enter the light receiving surface of the photodiode 50. However, when the viewer touches the surface of the CF substrate 12 with a finger or the like, the light from the backlight light source 13 transmitted through the CF substrate 12 is reflected by the finger or the like and enters the light receiving surface of the photodiode 50. For this reason, the photodiode 50 disposed below the touched position receives only the light reflected by the finger or the like, and the position detection circuit 24 can easily identify the touched position. As described above, in order for the photodiode 50 to easily detect the reflected light from a finger or the like, the light shielding layer 60 has a sufficient thickness so that at least the light from the backlight source 13 does not directly enter the photodiode 50. In addition, it must be formed to have a larger area than the photodiode 50 in plan view.
＜２．半導体装置の構成＞
　図４は、本発明の実施形態に係る半導体装置１００に含まれる、ボトムゲート型のＴＦＴ４０（以下、「ＴＦＴ４０」と略す）とフォトダイオード５０の構成を示す平面図である。なお、図４には、ガラス基板１０１上に、ＴＦＴ４０およびフォトダイオード５０が１個ずつ配置されているが、それぞれ複数個ずつ配置されていてもよい。 <2. Configuration of Semiconductor Device>
FIG. 4 is a plan view showing a configuration of a bottom gate type TFT 40 (hereinafter, abbreviated as “TFT 40”) and a photodiode 50 included in the semiconductor device 100 according to the embodiment of the present invention. In FIG. 4, one TFT 40 and one photodiode 50 are disposed on the glass substrate 101, but a plurality of TFTs 40 and a plurality of photodiodes 50 may be disposed.
　まず、ＴＦＴ４０の構成について説明する。図４に示すように、ガラス基板１０１上にゲート電極１１０が形成されている。ゲート電極１１０の端部は、ガラス基板１０１に対してほぼ垂直になるように形成されている。ゲート電極１１０の上方には、ゲート絶縁膜（図示しない）を介して、ゲート電極１１０と直交する方向に、チャネル層として機能する島状シリコン層１２０が形成されている。島状シリコン層１２０は、非晶質シリコン層にレーザアニール処理を施して結晶化した多結晶シリコン層からなる。島状シリコン層１２０の左右の端部には、ｎ型の不純物が高濃度にドープされたソース領域１２０ａとドレイン領域１２０ｂがそれぞれ形成されている。ゲート電極１１０の上方に位置し、ソース領域１２０ａとドレイン領域１２０ｂとに挟まれた領域には、チャネル層１２０ｃが形成されている。ソース領域１２０ａおよびドレイン領域１２０ｂは、層間絶縁膜（図示しない）に形成されたコンタクトホール１３５ａ、１３５ｂを介してそれぞれソース電極１４０ａおよびドレイン電極１４０ｂと電気的に接続されている。ソース電極１４０ａはソース配線（図示しない）と電気的に接続され、ドレイン電極１４０ｂは画素電極（図示しない）と電気的に接続されている。また、ゲート電極１１０の端部は、コンタクトホール１３０ｃを介してゲート接続電極１４０ｃと電気的に接続され、ゲート接続電極１４０ｃはゲート配線（図示しない）と電気的に接続されている。 First, the configuration of the TFT 40 will be described. As shown in FIG. 4, the gate electrode 110 is formed on the glass substrate 101. The end of the gate electrode 110 is formed so as to be substantially perpendicular to the glass substrate 101. Above the gate electrode 110, an island-like silicon layer 120 functioning as a channel layer is formed in a direction orthogonal to the gate electrode 110 via a gate insulating film (not shown). The island-like silicon layer 120 is composed of a polycrystalline silicon layer crystallized by applying laser annealing to an amorphous silicon layer. At the left and right ends of the island-like silicon layer 120, a source region 120a and a drain region 120b doped with n-type impurities at a high concentration are formed. A channel layer 120c is formed in a region located above the gate electrode 110 and sandwiched between the source region 120a and the drain region 120b. The source region 120a and the drain region 120b are electrically connected to the source electrode 140a and the drain electrode 140b through contact holes 135a and 135b formed in an interlayer insulating film (not shown), respectively. The source electrode 140a is electrically connected to a source wiring (not shown), and the drain electrode 140b is electrically connected to a pixel electrode (not shown). The end portion of the gate electrode 110 is electrically connected to the gate connection electrode 140c through the contact hole 130c, and the gate connection electrode 140c is electrically connected to a gate wiring (not shown).
　次に、フォトダイオード５０について説明する。ガラス基板１０１上に遮光層６０が形成されている。遮光層６０は、バックライト光源からの光を透過させないように、第１の金属層上に第２の金属層を積層した積層金属膜からなり、第１の金属層の材料および膜厚はゲート電極１１０の材料および膜厚と同じである。遮光層６０の上方に、ゲート絶縁膜を介して、少なくとも遮光層６０からはみ出さないように島状シリコン層１８０が形成されている。島状シリコン層１８０は、ＴＦＴ４０の島状シリコン層１２０と同じ工程で形成された多結晶シリコン層からなる。 Next, the photodiode 50 will be described. A light shielding layer 60 is formed on the glass substrate 101. The light shielding layer 60 is made of a laminated metal film in which a second metal layer is laminated on the first metal layer so as not to transmit light from the backlight source, and the material and thickness of the first metal layer are the gate. It is the same as the material and film thickness of the electrode 110. An island-like silicon layer 180 is formed above the light shielding layer 60 through the gate insulating film so as not to protrude from the light shielding layer 60 at least. The island-like silicon layer 180 is a polycrystalline silicon layer formed in the same process as the island-like silicon layer 120 of the TFT 40.
　島状シリコン層１８０の左右の端部には、それぞれ高濃度のｎ型不純物がドープされたｎ型領域１８０ａ、および、高濃度のｐ型不純物がドープされたｐ型領域１８０ｂが形成され、ｎ型領域１８０ａとｐ型領域１８０ｂとに挟まれた領域には真性領域１８０ｃが形成されている。ｎ型領域１８０ａおよびｐ型領域１８０ｂは、層間絶縁膜に形成されたコンタクトホール１８５ａ、１８５ｂを介してそれぞれカソード電極１９０ａおよびアノード電極１９０ｂと電気的に接続されている。このフォトダイオード５０は、量子効率が高く、高速応答が可能なラテラル型ｐｉｎ構造のダイオードであるが、ｐ型領域とｎ型領域とが直接接合されたｐｎ接合ダイオードであってもよい。なお、ラテラル型ｐｉｎ構造のダイオードのｎ型領域１８０ａ、真性領域１８０ｃ、およびｐ型領域１８０ｂをまとめて半導体層ということがある。 At the left and right ends of the island-like silicon layer 180, an n-type region 180a doped with a high-concentration n-type impurity and a p-type region 180b doped with a high-concentration p-type impurity are formed. An intrinsic region 180c is formed in a region sandwiched between the mold region 180a and the p-type region 180b. N-type region 180a and p-type region 180b are electrically connected to cathode electrode 190a and anode electrode 190b through contact holes 185a and 185b formed in the interlayer insulating film, respectively. The photodiode 50 is a lateral pin structure diode with high quantum efficiency and capable of high-speed response, but may be a pn junction diode in which a p-type region and an n-type region are directly joined. Note that the n-type region 180a, intrinsic region 180c, and p-type region 180b of a diode having a lateral pin structure may be collectively referred to as a semiconductor layer.
　図５は、図４に示す半導体装置１００の構成を示す断面図である。図５には、左から順に、図４に示すＴＦＴ４０のＡ－Ａ線に沿った断面図、ＴＦＴ４０のＢ－Ｂ線に沿った断面図、およびフォトダイオード５０のＣ－Ｃ線に沿った断面図が示されている。 FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device 100 shown in FIG. FIG. 5 shows, in order from the left, a cross-sectional view along the line AA of the TFT 40 shown in FIG. 4, a cross-sectional view along the line BB of the TFT 40, and a cross-section along the line CC of the photodiode 50. The figure is shown.
　絶縁基板であるガラス基板１０１上に、ＴＦＴ４０のゲート電極１１０とフォトダイオード５０の遮光層６０とが形成されている。ゲート電極１１０の材料は、後の製造工程における熱処理を考慮し、高融点金属であるタングステン（Ｗ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、チタン（Ｔｉ）等が好ましく、それらの好ましい膜厚は、３０～１００ｎｍである。半導体装置１００では、ゲート電極１１０はタングステンを主成分とする合金からなり、その膜厚を５０ｎｍとした。 On the glass substrate 101 which is an insulating substrate, the gate electrode 110 of the TFT 40 and the light shielding layer 60 of the photodiode 50 are formed. The material of the gate electrode 110 is preferably a refractory metal such as tungsten (W), molybdenum (Mo), tantalum (Ta), titanium (Ti), etc. in consideration of heat treatment in a later manufacturing process. Is 30 to 100 nm. In the semiconductor device 100, the gate electrode 110 is made of an alloy containing tungsten as a main component, and the film thickness is 50 nm.
　フォトダイオード５０の遮光層６０は、２層の金属層を積層した積層金属膜からなり、ガラス基板１０１上に形成される第１の金属層１１１の材料および膜厚は、ゲート電極１１０と同じである。したがって、半導体装置１００では、遮光層６０の第１の金属層１１１もタングステンを主成分とする合金からなり、その膜厚を５０ｎｍとした。第１の金属層１１１の上面に積層された第２の金属層１１３は、第１の金属層１１１よりも大きな導電率を有する材料であるアルミニウム（Ａｌ）、銅（Ｃｕ）等が好ましく、それらの好ましい膜厚は５０～２００ｎｍである。このため、本実施形態では、第２の金属層１１３はアルミニウムを主成分とする合金からなり、その膜厚を１００ｎｍとした。したがって、半導体装置１００では、ＴＦＴ４０のゲート電極１１０の膜厚は５０ｎｍであり、フォトダイオード５０の遮光層６０の膜厚は１５０ｎｍである。このように、ゲート電極１１０の膜厚を薄くした理由は後述する。また、大きな導電率を有する材料を用いて第２の金属層１１３を形成したのは以下の理由による。遮光層６０と同じ製造工程で、ＴＦＴ４０のゲート電極１１０と電気的に接続されたゲート配線ＧＬが形成される。ゲート配線ＧＬは、ゲートドライバから与えられた制御信号をゲート電極１１０に与える役割を有する。そこで、導電率の大きな材料を用いて第２の金属層１１３を形成することにより、ゲート配線ＧＬの抵抗値を小さくして、ゲート配線ＧＬによる制御信号の遅延を防止する必要があるからである。 The light shielding layer 60 of the photodiode 50 is made of a laminated metal film in which two metal layers are laminated. The material and thickness of the first metal layer 111 formed on the glass substrate 101 are the same as those of the gate electrode 110. is there. Therefore, in the semiconductor device 100, the first metal layer 111 of the light shielding layer 60 is also made of an alloy containing tungsten as a main component, and the thickness thereof is 50 nm. The second metal layer 113 laminated on the upper surface of the first metal layer 111 is preferably made of aluminum (Al), copper (Cu), or the like, which is a material having a higher conductivity than the first metal layer 111. The preferred film thickness is 50 to 200 nm. Therefore, in the present embodiment, the second metal layer 113 is made of an alloy containing aluminum as a main component, and the film thickness is 100 nm. Therefore, in the semiconductor device 100, the thickness of the gate electrode 110 of the TFT 40 is 50 nm, and the thickness of the light shielding layer 60 of the photodiode 50 is 150 nm. The reason why the thickness of the gate electrode 110 is thus reduced will be described later. The reason why the second metal layer 113 is formed using a material having a high conductivity is as follows. The gate wiring GL electrically connected to the gate electrode 110 of the TFT 40 is formed in the same manufacturing process as the light shielding layer 60. The gate wiring GL has a role of supplying a control signal supplied from the gate driver to the gate electrode 110. Therefore, it is necessary to reduce the resistance value of the gate wiring GL and prevent the delay of the control signal by the gate wiring GL by forming the second metal layer 113 using a material having high conductivity. .
　ゲート電極１１０および遮光層６０を含むガラス基板１０１の全体を覆うように、ゲート絶縁膜１２８が形成されている。ゲート絶縁膜１２８は１種類の絶縁膜で構成されていてもよく、または複数の種類の絶縁膜を積層した積層膜で構成されていてもよい。ゲート絶縁膜１２８の好ましい膜厚は５０～３００ｎｍであり、より好ましい膜厚は１００～２００ｎｍである。ゲート絶縁膜１２８には、酸化シリコン（ＳｉＯ2）、窒化シリコン（ＳｉＮｘ）、または酸窒化シリコン（ＳｉＯＮ）からなる絶縁膜が好適に用いられる。 A gate insulating film 128 is formed so as to cover the entire glass substrate 101 including the gate electrode 110 and the light shielding layer 60. The gate insulating film 128 may be configured by one type of insulating film, or may be configured by a laminated film in which a plurality of types of insulating films are stacked. A preferable film thickness of the gate insulating film 128 is 50 to 300 nm, and a more preferable film thickness is 100 to 200 nm. As the gate insulating film 128, an insulating film made of silicon oxide (SiO 2 ), silicon nitride (SiNx), or silicon oxynitride (SiON) is preferably used.
　ゲート絶縁膜１２８上には、ＴＦＴ４０のチャネル層となる島状シリコン層１２０、および、フォトダイオード５０の島状シリコン層１８０が形成されている。島状シリコン層１２０、１８０は、後述するように、非晶質シリコンにレーザ光を照射して結晶化された多結晶シリコンからなり、その好ましい膜厚は３０～１５０ｎｍであり、より好ましい膜厚は５０～１００ｎｍである。このため、半導体装置１００では、島状シリコン層１２０、１８０の膜厚をいずれも５０ｎｍとした。 On the gate insulating film 128, an island-shaped silicon layer 120 serving as a channel layer of the TFT 40 and an island-shaped silicon layer 180 of the photodiode 50 are formed. As will be described later, the island-like silicon layers 120 and 180 are made of polycrystalline silicon that is crystallized by irradiating laser light to amorphous silicon, and a preferable film thickness is 30 to 150 nm. Is 50 to 100 nm. For this reason, in the semiconductor device 100, the film thickness of the island-like silicon layers 120 and 180 are both 50 nm.
　ＴＦＴ４０の島状シリコン層１２０は、ゲート電極１１０の上方に形成されたチャネル領域１２０ｃと、チャネル領域１２０ｃの左右にそれぞれ形成された、低濃度のｎ型不純物をドープされたＬＤＤ領域１２０ｄと、ＬＤＤ領域１２０ｄの外側にそれぞれ形成された、高濃度のｎ型不純物をドープされたソース領域１２０ａおよびドレイン領域１２０ｂとを含む。 The island-like silicon layer 120 of the TFT 40 includes a channel region 120c formed above the gate electrode 110, LDD regions 120d doped with low-concentration n-type impurities, respectively, formed on the left and right sides of the channel region 120c, and LDD A source region 120a and a drain region 120b doped with a high-concentration n-type impurity are formed respectively outside the region 120d.
　ＴＦＴ４０の島状シリコン層１２０を構成する多結晶シリコンの結晶は、結晶粒径の大きな粒状結晶でもよいが、所定の方向に長く延びたラテラル結晶であることがより好ましい。ラテラル結晶の大きさは、非晶質シリコンの膜厚に依存し、半導体装置１００では長辺の長さが数μｍ、短辺の長さが０．５～１．０μｍである。これは、エキシマレーザのレーザ光を照射して結晶化した多結晶シリコンの結晶粒径０．３～０．５μｍに比べて大きい。このため、ラテラル結晶からなる島状シリコン層１２０の移動度は大きくなり、このような島状シリコン層１２０をチャネル層とするＴＦＴ４０の動作速度は速くなる。特に、ラテラル結晶の長軸方向がチャネル長方向に一致する場合には、ＴＦＴ４０の動作速度はより一層速くなる。なお、このようなラテラル結晶を成長させる方法については後述する。 The polycrystalline silicon crystal constituting the island-like silicon layer 120 of the TFT 40 may be a granular crystal having a large crystal grain size, but is more preferably a lateral crystal extending long in a predetermined direction. The size of the lateral crystal depends on the film thickness of the amorphous silicon, and in the semiconductor device 100, the length of the long side is several μm and the length of the short side is 0.5 to 1.0 μm. This is larger than the crystal grain size of 0.3 to 0.5 μm of polycrystalline silicon crystallized by irradiating the excimer laser beam. For this reason, the mobility of the island-shaped silicon layer 120 made of a lateral crystal is increased, and the operation speed of the TFT 40 using the island-shaped silicon layer 120 as a channel layer is increased. In particular, when the longitudinal direction of the lateral crystal coincides with the channel length direction, the operating speed of the TFT 40 is further increased. A method for growing such a lateral crystal will be described later.
　一方、フォトダイオード５０の島状シリコン層１８０の両端には、高濃度のｎ型不純物がドープされたｎ型領域１８０ａと、高濃度のｐ型不純物がドープされたｐ型領域１８０ｂとがそれぞれ形成され、ｎ型領域１８０ａとｐ型領域１８０ｂとに挟まれた領域には、真性領域１８０ｃが形成されている。このように、フォトダイオード５０は、ラテラル型ｐｉｎ構造のダイオードである。 On the other hand, at both ends of the island-like silicon layer 180 of the photodiode 50, an n-type region 180a doped with a high-concentration n-type impurity and a p-type region 180b doped with a high-concentration p-type impurity are formed. In addition, an intrinsic region 180c is formed in a region sandwiched between the n-type region 180a and the p-type region 180b. Thus, the photodiode 50 is a diode having a lateral pin structure.
　島状シリコン層１２０、１８０の上面には、酸化シリコンからなる保護膜１３０がそれぞれ形成されており、さらに保護膜１３０を含むガラス基板１０１の全体を覆うように、窒化シリコンからなる、第１の層間絶縁膜１３１が形成されている。第１の層間絶縁膜１３１の膜厚は、好ましくは１００～４００ｎｍである。第１の層間絶縁膜１３１上に、酸化シリコンからなる第２の層間絶縁膜１３２が形成されている。第２の層間絶縁膜１３２の膜厚は、好ましくは２００～６００ｎｍである。 A protective film 130 made of silicon oxide is formed on the upper surfaces of the island-like silicon layers 120 and 180, respectively, and further, the first glass made of silicon nitride is formed so as to cover the entire glass substrate 101 including the protective film 130. An interlayer insulating film 131 is formed. The film thickness of the first interlayer insulating film 131 is preferably 100 to 400 nm. A second interlayer insulating film 132 made of silicon oxide is formed on the first interlayer insulating film 131. The thickness of the second interlayer insulating film 132 is preferably 200 to 600 nm.
　ＴＦＴ４０では、第１および第２の層間絶縁膜１３１、１３２に開孔されたコンタクトホールを介して、ソース領域１２０ａおよびドレイン領域１２０ｂとそれぞれ電気的に接続されたソース電極１４０ａおよびドレイン電極１４０ｂが形成されている。フォトダイオード５０では、第１および第２の層間絶縁膜１３１、１３２に開孔されたコンタクトホールを介して、ｎ型領域１８０ａおよびｐ型領域１８０ｂとそれぞれ電気的に接続されたカソード電極１９０ａおよびアノード電極１９０ｂが形成されている。制御信号や映像信号等の遅延を防止するため、ソース電極１４０ａ、ドレイン電極１４０ｂ、ゲート接続電極１４０ｃ、カソード電極１９０ａ、およびアノード電極１９０ｂには、導電率の大きなアルミニウム、モリブデン等の金属が用いられる。半導体装置１００では、これらの電極材料としてアルミニウムが用いられている。 In the TFT 40, a source electrode 140a and a drain electrode 140b that are electrically connected to the source region 120a and the drain region 120b, respectively, are formed through contact holes formed in the first and second interlayer insulating films 131 and 132. Has been. In the photodiode 50, a cathode electrode 190a and an anode electrically connected to the n-type region 180a and the p-type region 180b, respectively, through contact holes opened in the first and second interlayer insulating films 131 and 132. An electrode 190b is formed. In order to prevent delay of control signals and video signals, the source electrode 140a, the drain electrode 140b, the gate connection electrode 140c, the cathode electrode 190a, and the anode electrode 190b are made of a metal having high conductivity such as aluminum or molybdenum. . In the semiconductor device 100, aluminum is used as these electrode materials.
　ＴＦＴ４０およびフォトダイオード５０を含むガラス基板１０１の全体を覆うように、感光性アクリル樹脂からなる平坦化膜１４８が形成され、平坦化膜１４８上に、ＩＴＯ（Indium Tin Oxide）等の透明金属からなる画素電極１６１が形成されている。画素電極１６１は、平坦化膜１４８に開孔されたコンタクトホールを介してＴＦＴ４０のドレイン電極１４０ｂと電気的に接続されている。一方、フォトダイオード５０では、指等による反射光の強度が小さくならないように、島状シリコン層１８０の真性領域１８０ｃの上方に第２の層間絶縁膜１３２の表面に達する凹部１６０が開口されている。画素電極１６１は、カソード電極１９０ａの上方の平坦化膜１４８の表面から、凹部１６０の内面を覆い、さらにアノード電極１９０ｂの上方の平坦化膜１４８の表面まで形成されている。さらに、ＴＦＴ４０の画素電極１６１上、ならびにフォトダイオード５０のカソード電極１９０ａおよびアノード電極１９０ｂの上方の画素電極１６１上に、クロム（Ｃｒ）等の遮光材料からなるブラックマトリクス１６２が形成されている。 A planarizing film 148 made of a photosensitive acrylic resin is formed so as to cover the entire glass substrate 101 including the TFT 40 and the photodiode 50, and is made of a transparent metal such as ITO (Indium Tin Oxide) on the planarizing film 148. A pixel electrode 161 is formed. The pixel electrode 161 is electrically connected to the drain electrode 140 b of the TFT 40 through a contact hole opened in the planarization film 148. On the other hand, in the photodiode 50, a recess 160 reaching the surface of the second interlayer insulating film 132 is opened above the intrinsic region 180c of the island-like silicon layer 180 so that the intensity of reflected light from a finger or the like does not decrease. . The pixel electrode 161 is formed from the surface of the planarization film 148 above the cathode electrode 190a to the inner surface of the recess 160 and further to the surface of the planarization film 148 above the anode electrode 190b. Further, a black matrix 162 made of a light shielding material such as chromium (Cr) is formed on the pixel electrode 161 of the TFT 40 and on the pixel electrode 161 above the cathode electrode 190 a and the anode electrode 190 b of the photodiode 50.
＜３．　半導体装置の製造方法＞
　図６および図７は、図５に示す半導体装置１００の製造工程を示す工程断面図である。なお、図６および図７では、図４に示すＡ－Ａ線に沿った断面図を省略する。図６および図７を参照しながら、半導体装置１００の製造方法を説明する。図６（Ａ）に示すように、ガラス基板１０１上に、スパッタリング法によって、タングステンを主成分とする合金からなり、膜厚５０ｎｍの第１の金属層１１１を成膜する。次に、第１の金属層１１１上に、アルミニウムを主成分とする合金からなり、膜厚１００ｎｍの第２の金属層１１３を成膜する。 <3. Manufacturing Method of Semiconductor Device>
6 and 7 are process cross-sectional views showing the manufacturing process of the semiconductor device 100 shown in FIG. 6 and 7, the cross-sectional view along the line AA shown in FIG. 4 is omitted. A method for manufacturing the semiconductor device 100 will be described with reference to FIGS. As shown in FIG. 6A, a first metal layer 111 made of an alloy containing tungsten as a main component and having a thickness of 50 nm is formed over a glass substrate 101 by a sputtering method. Next, a second metal layer 113 made of an alloy containing aluminum as a main component and having a thickness of 100 nm is formed over the first metal layer 111.
　第２の金属層１１３上に、フォトレジストを塗布してレジスト膜（図示しない）を形成し、ハーフトーンマスクを用いてレジスト膜を露光することにより、所望の形状のレジストパターン１７１ａ、１７１ｂを形成する。ハーフトーンマスクは、露光光を完全に遮光する遮光部からなるパターンだけでなく、スリット等を設けることにより所定の割合で露光光を透過させる半透過部からなるパターンも形成されている。 On the second metal layer 113, a photoresist is applied to form a resist film (not shown), and the resist film is exposed using a halftone mask to form resist patterns 171a and 171b having desired shapes. To do. In the halftone mask, not only a pattern composed of a light shielding part that completely shields exposure light but also a pattern composed of a semitransparent part that transmits the exposure light at a predetermined ratio by providing a slit or the like.
　ＴＦＴ４０のゲート配線（図示しない）およびフォトダイオード５０の遮光層６０のパターンは遮光部からなり、ゲート電極１１０のパターンは半透過部からなるハーフトーンマスクを使用する。この場合、ゲート配線および遮光層６０となるべき領域では、露光光が完全に遮光されるので、膜厚の厚いレジストパターン１７１ｂが形成される。一方、ゲート電極１１０となるべき領域では、露光光が一部透過するので、レジストパターン１７１ｂよりも薄い膜厚のレジストパターン１７１ａが形成される。 The gate wiring (not shown) of the TFT 40 and the pattern of the light shielding layer 60 of the photodiode 50 are made of a light shielding part, and the pattern of the gate electrode 110 is a halftone mask made of a semi-transmissive part. In this case, since the exposure light is completely shielded in the region to be the gate wiring and the light shielding layer 60, a thick resist pattern 171b is formed. On the other hand, in the region to be the gate electrode 110, a part of the exposure light is transmitted, so that a resist pattern 171a having a thickness smaller than that of the resist pattern 171b is formed.
　図６（Ｂ）に示すように、レジストパターン１７１ａ、１７１ｂをマスクとし、エッチングガスとして塩素（Ｃｌ2）ガスを用いたドライエッチングによって、アルミニウムを主成分とする合金からなる第２の金属層１１３をパターニングする。次に、エッチングガスとして６フッ化硫黄（ＳＦ6）ガスを用いたドライエッチングにより、タングステンを主成分とする合金からなる第１の金属層１１１をパタニーングする。この結果、フォトダイオード５０の遮光層６０およびＴＦＴ４０のゲート配線が形成されると共に、ゲート電極１１０となるべき突起部１１４が形成される。 As shown in FIG. 6B, the second metal layer 113 made of an alloy containing aluminum as a main component by dry etching using the resist patterns 171a and 171b as masks and chlorine (Cl 2 ) gas as an etching gas. Is patterned. Next, the first metal layer 111 made of an alloy containing tungsten as a main component is patterned by dry etching using sulfur hexafluoride (SF 6 ) gas as an etching gas. As a result, the light shielding layer 60 of the photodiode 50 and the gate wiring of the TFT 40 are formed, and the protrusion 114 to be the gate electrode 110 is formed.
　図６（Ｃ）に示すように、酸素（Ｏ2）ガスを用いてアッシング（ashing）を行い、突起部１１４上のレジストパターン１７１ａを除去し、第２の金属層１１３の表面を露出させる。このとき、遮光層６０上およびゲート配線上にもアッシングによって膜厚が薄くなったレジストパターン１７１ｂが残されている。 As shown in FIG. 6C, ashing is performed using oxygen (O 2 ) gas to remove the resist pattern 171a on the protrusion 114, and the surface of the second metal layer 113 is exposed. At this time, the resist pattern 171b whose thickness is reduced by ashing is also left on the light shielding layer 60 and the gate wiring.
　図６（Ｄ）に示されるように、残されたレジストパターン１７１ｂをマスクとして突起部１１４の第２の金属層１１３をウエットエッチングにより除去する。ウエットエッチングは、選択比（タングステンを主成分とする合金に対するアルミニウムを主成分とする合金のエッチング速度）の大きなエッチャントを用いて行なう。その後、レジストパターン１７１ｂを剥離する。なお、アルミニウムを主成分とする合金からなる第２の金属層１１３をウエットエッチングするために、酢酸（ＣＨ3ＣＯＯＨ）、リン酸（Ｈ3ＰＯ4）、硝酸（ＨＮＯ3）を含むエッチャントが使用される。このウエットエッチングによって、ゲート電極１１０が形成される。なお、第２の金属層１１３をドライエッチングによって除去してもよい。 As shown in FIG. 6D, the second metal layer 113 of the protrusion 114 is removed by wet etching using the remaining resist pattern 171b as a mask. Wet etching is performed using an etchant having a high selectivity (etching rate of an alloy containing aluminum as a main component relative to an alloy containing tungsten as a main component). Thereafter, the resist pattern 171b is peeled off. Note that an etchant containing acetic acid (CH 3 COOH), phosphoric acid (H 3 PO 4 ), and nitric acid (HNO 3 ) is used to wet-etch the second metal layer 113 made of an alloy containing aluminum as a main component. Is done. By this wet etching, the gate electrode 110 is formed. Note that the second metal layer 113 may be removed by dry etching.
　図６（Ｅ）に示すように、ＴＦＴ４０のゲート電極１１０およびフォトダイオード５０の遮光層６０を含む、ガラス基板１０１の全体を覆うように、モノシラン（ＳｉＨ4）ガス、アンモニア（ＮＨ3）ガス、および亜酸化窒素（Ｎ2Ｏ）ガスを原料ガスとして、プラズマ化学気相成長法（Plasma Enhanced Chemical Vapor Deposition Method）により、膜厚１００～２００ｎｍの窒化シリコン膜上に酸化シリコン膜を積層した積層膜からなるゲート絶縁膜１２８を成膜する。次に、ゲート絶縁膜１２８上に、モノシランガスと水素ガスを原料ガスとして、プラズマＣＶＤ法により、膜厚５０ｎｍの非晶質シリコン層１２１を成膜する。 As shown in FIG. 6E, monosilane (SiH 4 ) gas, ammonia (NH 3 ) gas, so as to cover the entire glass substrate 101 including the gate electrode 110 of the TFT 40 and the light shielding layer 60 of the photodiode 50. A laminated film in which a silicon oxide film is laminated on a silicon nitride film having a thickness of 100 to 200 nm by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition Method) using nitrous oxide (N 2 O) gas as a source gas A gate insulating film 128 made of is formed. Next, an amorphous silicon layer 121 having a thickness of 50 nm is formed on the gate insulating film 128 by plasma CVD using monosilane gas and hydrogen gas as source gases.
　なお、ゲート絶縁膜１２８と非晶質シリコン層１２１とはいずれも、プラズマＣＶＤ法により成膜されるので、原料ガスを切り換えることにより、それらを連続して成膜してもよい。この場合、ゲート絶縁膜１２８を成膜した後に、ゲート絶縁膜１２８の表面を大気に晒すことなく非晶質シリコン層１２１を成膜するので、ゲート絶縁膜１２８と非晶質シリコン層１２１との界面の汚染を防止でき、ＴＦＴ４０の閾値電圧の変動を抑えることができる。 Note that since both the gate insulating film 128 and the amorphous silicon layer 121 are formed by a plasma CVD method, they may be continuously formed by switching the source gas. In this case, after the gate insulating film 128 is formed, the amorphous silicon layer 121 is formed without exposing the surface of the gate insulating film 128 to the atmosphere. Contamination of the interface can be prevented, and fluctuations in the threshold voltage of the TFT 40 can be suppressed.
　次に、約４００℃の窒素雰囲気中でアニールを約１～２時間行なうことによって、非晶質シリコン層１２１に含まれる水素をあらかじめ脱離させておく。図６（Ｆ）に示すように、水素を脱離させた非晶質シリコン層１２１にレーザ光を照射することにより、非晶質シリコン層１２１を結晶化させて多結晶シリコン層１２２にする。使用されるレーザは、波長５３２ｎｍのＮｄ：ＹＶＯ4レーザといわれる連続発振レーザであり、そのレーザ出力を１１．５Ｗとした。なお、レーザ光のビーム形状は長尺形状になるように、例えば０．１×２．０ｍｍに設定され、レーザ光を非晶質シリコン層１２１の表面に平行にスキャンさせる。好ましいレーザ光のスキャン速度は、３００～５００ｍｍ／ｓｅｃである。 Next, the hydrogen contained in the amorphous silicon layer 121 is desorbed in advance by annealing in a nitrogen atmosphere at about 400 ° C. for about 1 to 2 hours. As shown in FIG. 6F, the amorphous silicon layer 121 from which hydrogen has been eliminated is irradiated with laser light to crystallize the amorphous silicon layer 121 into a polycrystalline silicon layer 122. The laser used was a continuous wave laser called Nd: YVO 4 laser with a wavelength of 532 nm, and its laser output was 11.5 W. Note that the beam shape of the laser beam is set to, for example, 0.1 × 2.0 mm so as to be a long shape, and the laser beam is scanned in parallel with the surface of the amorphous silicon layer 121. A preferable scanning speed of the laser beam is 300 to 500 mm / sec.
　レーザ光が照射された領域の非晶質シリコン層１２１は完全に融解し、しかもゲート電極１１０は、熱伝導率が１７４Ｗ／ｍ・Ｋと比較的小さなタングステンを主成分とする合金からなる第１の金属層１１１によって形成されている。非晶質シリコン層１２１で発生した熱エネルギーの一部は、熱輻射によってゲート電極１１０に与えられる。しかし、ゲート電極１１０に与えられた熱エネルギーは、さらにゲート配線に伝わりにくいので、ゲート配線で放熱されにくい。このため、非晶質シリコン層１２１は、長時間に渡り高温状態を維持し、溶融したシリコンはゆっくり冷えて固まり、レーザ光のスキャン方向が長軸となる長尺形状のラテラル結晶からなる多結晶シリコン層１２２が形成される。 The amorphous silicon layer 121 in the region irradiated with the laser light is completely melted, and the gate electrode 110 is made of a first alloy composed of a relatively small tungsten alloy having a thermal conductivity of 174 W / m · K. The metal layer 111 is formed. Part of the thermal energy generated in the amorphous silicon layer 121 is given to the gate electrode 110 by thermal radiation. However, since the heat energy given to the gate electrode 110 is more difficult to be transmitted to the gate wiring, it is difficult to dissipate heat through the gate wiring. For this reason, the amorphous silicon layer 121 maintains a high temperature state for a long time, the molten silicon slowly cools and hardens, and is a polycrystal made of a long lateral crystal whose major axis is the scanning direction of the laser beam. A silicon layer 122 is formed.
　この場合、ゲート電極１１０の膜厚は５０ｎｍと非常に薄いので、ゲート電極１１０の端部の段差による非晶質シリコン層１２１の傾斜も緩やかになっている。このため、非晶質シリコン層１２１が完全に溶融しても、溶融したシリコンはガラス基板１０１側に流れにくくなり、結晶化した多結晶シリコン層１２２はゲート電極１１０の端部で段切れしにくくなる。一方、フォトダイオード５０の遮光層６０の膜厚は１５０ｎｍと厚いので、遮光層６０を覆うように形成された非晶質シリコン層１２１の傾斜は、遮光層６０の端部で急峻になる。このため、非晶質シリコン層１２１を完全に溶融させれば、溶融したシリコンはガラス基板１０１側に流れ、結晶化した多結晶シリコン層１２２は遮光層６０の端部で段切れしやすくなる。しかし、フォトダイオード５０では、ＴＦＴ４０の場合と異なり、遮光層６０の外側の多結晶シリコン層１２２は、島状シリコン層１８０を構成しない。このため、フォトダイオード５０では、多結晶シリコン層１２２が遮光層６０の端部で段切れしても問題とはならない。 In this case, since the thickness of the gate electrode 110 is as thin as 50 nm, the inclination of the amorphous silicon layer 121 due to the step at the end of the gate electrode 110 is also gentle. For this reason, even if the amorphous silicon layer 121 is completely melted, the melted silicon is difficult to flow to the glass substrate 101 side, and the crystallized polycrystalline silicon layer 122 is difficult to be cut off at the end of the gate electrode 110. Become. On the other hand, since the thickness of the light shielding layer 60 of the photodiode 50 is as thick as 150 nm, the inclination of the amorphous silicon layer 121 formed so as to cover the light shielding layer 60 becomes steep at the end of the light shielding layer 60. Therefore, if the amorphous silicon layer 121 is completely melted, the melted silicon flows toward the glass substrate 101, and the crystallized polycrystalline silicon layer 122 is likely to be disconnected at the end of the light shielding layer 60. However, in the photodiode 50, unlike the TFT 40, the polycrystalline silicon layer 122 outside the light shielding layer 60 does not constitute the island-like silicon layer 180. Therefore, in the photodiode 50, there is no problem even if the polycrystalline silicon layer 122 is cut off at the end of the light shielding layer 60.
　図８は、連続発振レーザとエキシマレーザを用いて非晶質シリコン層を結晶化させて得られた多結晶シリコン層の移動度を示す図である。図８の横軸は照射するレーザ光のエネルギー密度を表し、縦軸はレーザアニールによって結晶化された多結晶シリコン層の移動度を表している。図８に示すように、エキシマレーザのレーザ光を照射した場合には、エネルギー密度を大きくしていくと、それに伴って多結晶シリコン層の移動度も大きくなり、エネルギー密度が所定の値になったとき、移動度は最大になる。さらにエネルギー密度を大きくすれば、移動度は逆に小さくなる。このことから、エキシマレーザを用いて非晶質シリコン層を結晶化する場合、エネルギー密度を変えれば移動度も大きく変わることがわかる。このため、レーザ光のエネルギー密度を調整して、結晶化された多結晶シリコン層の移動度を所定の値にすることは非常に難しい。また、エキシマレーザを用いて結晶化された多結晶シリコン層の結晶粒は粒状結晶になる。 FIG. 8 is a diagram showing the mobility of a polycrystalline silicon layer obtained by crystallizing an amorphous silicon layer using a continuous wave laser and an excimer laser. The horizontal axis in FIG. 8 represents the energy density of the irradiated laser light, and the vertical axis represents the mobility of the polycrystalline silicon layer crystallized by laser annealing. As shown in FIG. 8, when the excimer laser beam is irradiated, as the energy density is increased, the mobility of the polycrystalline silicon layer is increased accordingly, and the energy density becomes a predetermined value. The mobility is maximized. If the energy density is further increased, the mobility is decreased. From this, it can be seen that when the amorphous silicon layer is crystallized using an excimer laser, the mobility changes greatly if the energy density is changed. For this reason, it is very difficult to adjust the energy density of the laser beam to set the mobility of the crystallized polycrystalline silicon layer to a predetermined value. The crystal grains of the polycrystalline silicon layer crystallized using an excimer laser become granular crystals.
　一方、連続発振レーザのレーザ光のエネルギー密度を大きくしていくと、それに伴って結晶化された多結晶シリコン層の移動度も大きくなる。この多結晶シリコン層も粒状結晶になるが、エキシマレーザを用いた場合よりも結晶粒径が大きくなる。したがって、その移動度は、エキシマレーザを用いて結晶化した多結晶シリコン層の移動度よりも大きくなる。さらに、エネルギー密度を大きくすると、移動度は所定の値になり、エネルギー密度をさらに大きくしてもその値はほぼ所定の値を維持し、ほとんど変化しなくなる。エネルギー密度を変化させても移動度が所定の値からほとんど変化しない範囲では、レーザ光のエネルギー密度を調整して、結晶化された多結晶シリコン層の移動度を所定の値にすることが容易にできる。また、移動度が所定の値からほとんど変化しないエネルギー密度のレーザ光を照射して結晶化させた多結晶シリコン層の結晶粒はラテラル結晶になる。 On the other hand, when the energy density of the laser light of the continuous wave laser is increased, the mobility of the crystallized polycrystalline silicon layer is increased accordingly. Although this polycrystalline silicon layer also becomes a granular crystal, the crystal grain size becomes larger than when an excimer laser is used. Therefore, the mobility becomes larger than the mobility of the polycrystalline silicon layer crystallized using an excimer laser. Further, when the energy density is increased, the mobility becomes a predetermined value, and even if the energy density is further increased, the value maintains almost the predetermined value and hardly changes. In the range where the mobility hardly changes from the predetermined value even if the energy density is changed, the mobility of the crystallized polycrystalline silicon layer can be easily set to the predetermined value by adjusting the energy density of the laser beam. Can be. The crystal grains of the polycrystalline silicon layer crystallized by irradiation with laser light having an energy density that hardly changes from a predetermined value become lateral crystals.
　このように、連続発振レーザを使用して、エネルギー密度を所定の値よりも大きくすれば、非晶質シリコン層を容易にラテラル結晶からなる多結晶シリコン層にすることができるので、ＴＦＴの動作速度を速くすることができる。またラテラル結晶からなる多結晶シリコン層にするために必要なレーザ光のエネルギー密度の範囲は広い。このため、例えば大面積のガラス基板に非晶質シリコン層を成膜する時のように、非晶質シリコン層の膜厚がばらついた場合や、下方にゲート電極が配置されている非晶質シリコン層と配置されていない非晶質シリコン層がある場合でも、連続発振レーザを用いた場合には、それらのばらつきやゲート電極の配置の有無に関係なく、非晶質シリコン層をラテラル結晶からなる多結晶シリコン層にすることができる。なお、半導体装置１００では、連続発振レーザを用いる代わりに、塩化キセノン（ＸｅＣｌ）エキシマレーザやフッ化クリプトン（ＫｒＦ）エキシマレーザ等のエキシマレーザを使用し、非晶質シリコン層を粒状結晶からなる多結晶シリコン層にしてもよい。 In this way, if the continuous wave laser is used and the energy density is made larger than a predetermined value, the amorphous silicon layer can be easily made into a polycrystalline silicon layer made of a lateral crystal, so that the operation of the TFT Speed can be increased. Further, the range of the energy density of the laser beam necessary for forming a polycrystalline silicon layer made of a lateral crystal is wide. For this reason, for example, when the amorphous silicon layer varies in thickness, such as when an amorphous silicon layer is formed on a large-area glass substrate, or when the gate electrode is disposed below Even when there is an amorphous silicon layer that is not arranged with a silicon layer, when a continuous wave laser is used, the amorphous silicon layer is made of a lateral crystal regardless of the variation and the presence or absence of the arrangement of the gate electrode. A polycrystalline silicon layer can be formed. In the semiconductor device 100, an excimer laser such as a xenon chloride (XeCl) excimer laser or a krypton fluoride (KrF) excimer laser is used instead of the continuous wave laser, and the amorphous silicon layer is formed of a granular crystal. A crystalline silicon layer may be used.
　図７（Ｇ）に示すように、多結晶シリコン層１２２を覆うように、プラズマＣＶＤ法によって、膜厚５０～１００ｎｍの酸化シリコンからなる保護膜１３０を成膜する。次に、ＴＦＴ４０の閾値電圧を制御するため、保護膜１３０を介して、イオン注入法またはイオンドーピング法を用いて、ｎ型不純物であるリン（Ｐ）、または、ｐ型不純物であるボロン（Ｂ）を多結晶シリコン層１２２の全面にドーピングする。その後、保護膜１３０上に、フォトリソグラフィ技術を用いて、レジスト膜（図示しない）を形成する。次に、ゲート電極１１０および遮光層６０をマスクとして、ガラス基板１０１の下面側（図７（Ｇ）の下側）から露光する。この場合、ゲート電極１１０および遮光層６０は露光光を遮光するので、ゲート電極１１０および遮光層６０に対して自己整合的にレジストパターン１７２が形成される。レジストパターン１７２をマスクとして、イオン注入法またはイオンドーピング法により、保護膜１３０を介して、低濃度のリンを多結晶シリコン層１２２にドープする。この結果、多結晶シリコン層１２２のリンが注入された領域には低濃度領域１２４（ｎ-領域１２４）が形成される。その後、レジストパターン１７２を剥離する。 As shown in FIG. 7G, a protective film 130 made of silicon oxide having a thickness of 50 to 100 nm is formed by plasma CVD so as to cover the polycrystalline silicon layer 122. Next, in order to control the threshold voltage of the TFT 40, phosphorus (P) that is an n-type impurity or boron (B that is a p-type impurity) is used by using an ion implantation method or an ion doping method through the protective film 130. ) Is doped on the entire surface of the polycrystalline silicon layer 122. Thereafter, a resist film (not shown) is formed on the protective film 130 using a photolithography technique. Next, exposure is performed from the lower surface side of glass substrate 101 (lower side in FIG. 7G) using gate electrode 110 and light shielding layer 60 as a mask. In this case, since the gate electrode 110 and the light shielding layer 60 shield the exposure light, the resist pattern 172 is formed in a self-aligned manner with respect to the gate electrode 110 and the light shielding layer 60. Using the resist pattern 172 as a mask, the polycrystalline silicon layer 122 is doped with low-concentration phosphorus through the protective film 130 by ion implantation or ion doping. As a result, a low concentration region 124 (n − region 124) is formed in the region of the polysilicon layer 122 where phosphorus is implanted. Thereafter, the resist pattern 172 is peeled off.
　図７（Ｈ）に示すように、フォトリソグラフィ技術を用いて、ゲート電極１１０の上方の保護膜１３０上に、レジストパターン１７２よりも大きな形状のレジストパターン１７３を形成すると共に、フォトダイオード５０の島状シリコン層１８０の真性領域１８０ｃとなるべき領域およびｐ型領域１８０ｂとなるべき領域の上方にレジストパターン１７３を形成する。次に、レジストパターン１７３をマスクとして、イオン注入法またはイオンドーピング法を用いて、保護膜１３０を介して、高濃度のリンを多結晶シリコン層１２２にドープする。その結果、ＴＦＴ４０では、高濃度のリンがドープされた領域はｎ型高濃度領域１２５になり、ｎ型高濃度領域１２５とチャネル領域１２０ｃとに挟まれた領域はＬＤＤ領域１２０ｄになる。また、フォトダイオード５０では、多結晶シリコン層１２２の高濃度のリンがドープされた領域はｎ型高濃度領域１２５になる。 As shown in FIG. 7H, a resist pattern 173 having a shape larger than the resist pattern 172 is formed on the protective film 130 above the gate electrode 110 by using a photolithography technique, and the island of the photodiode 50 is formed. A resist pattern 173 is formed above the region to be the intrinsic region 180c and the region to be the p-type region 180b of the silicon layer 180. Next, using the resist pattern 173 as a mask, high concentration phosphorus is doped into the polycrystalline silicon layer 122 through the protective film 130 by ion implantation or ion doping. As a result, in the TFT 40, the region doped with high concentration phosphorus becomes the n-type high concentration region 125, and the region sandwiched between the n-type high concentration region 125 and the channel region 120c becomes the LDD region 120d. In the photodiode 50, the region doped with high-concentration phosphorus in the polycrystalline silicon layer 122 becomes the n-type high-concentration region 125.
　次に、図７（Ｈ）の場合と同様にして、レジストパターン（図示しない）を形成し、レジストパターンをマスクとして、イオン注入法またはイオンドーピング法を用いて、高濃度のボロンをドープすることにより、ｐチャネル型ＴＦＴ（図示しない）のｐ型高濃度領域と、フォトダイオード５０のｐ型高濃度領域１８０ｂを形成する。また、フォトダイオード５０のｎ型高濃度領域１２５とｐ型高濃度領域とに挟まれた領域は真性領域１８０ｃになる。その後、ドープされたリンおよびボロンを活性化するためにアニールを行なう。 Next, a resist pattern (not shown) is formed in the same manner as in FIG. 7H, and high-concentration boron is doped using the resist pattern as a mask by an ion implantation method or an ion doping method. Thus, a p-type high concentration region of a p-channel TFT (not shown) and a p-type high concentration region 180b of the photodiode 50 are formed. In addition, a region sandwiched between the n-type high concentration region 125 and the p-type high concentration region of the photodiode 50 becomes an intrinsic region 180c. Thereafter, annealing is performed to activate the doped phosphorus and boron.
　図７（Ｉ）に示すように、フォトリソグラフィ法を用いて、保護膜１３０上に、所望の形状のレジストパターン（図示しない）を形成する。レジストパターンをマスクにし、エッチングガスとして四フッ化炭素（ＣＦ4）を用いたドライエッチングを行なうことにより、互いに分離されたＴＦＴ４０の島状シリコン層１２０とフォトダイオード５０の島状シリコン層１８０とを形成する。これにより、ＴＦＴ４０では、島状シリコン層１２０の両端にソース領域１２０ａとドレイン領域１２０ｂとがそれぞれ形成され、フォトダイオード５０では、島状シリコン層１８０の両端にｎ型領域１８０ａとｐ型領域１８０ｂとがそれぞれ形成される。 As shown in FIG. 7I, a resist pattern (not shown) having a desired shape is formed on the protective film 130 using a photolithography method. By using the resist pattern as a mask and performing dry etching using carbon tetrafluoride (CF 4 ) as an etching gas, the island-shaped silicon layer 120 of the TFT 40 and the island-shaped silicon layer 180 of the photodiode 50 separated from each other are formed. Form. Thereby, in the TFT 40, the source region 120a and the drain region 120b are formed at both ends of the island-shaped silicon layer 120, respectively. In the photodiode 50, the n-type region 180a and the p-type region 180b are formed at both ends of the island-shaped silicon layer 180. Are formed respectively.
　次に、プラズマＣＶＤ法、減圧ＣＶＤ法、またはスパッタ法のいずれかにより、島状シリコン層１２０、１８０およびそれらの上面の保護膜１３０を覆うように、第１の層間絶縁膜１３１と第２の層間絶縁膜１３２を順に成膜する。第１の層間絶縁膜１３１は、膜厚１００～４００ｎｍの窒化シリコンからなり、第２の層間絶縁膜１３２は、膜厚２００～６００ｎｍの酸化シリコンからなる。さらに、ＴＦＴ４０およびフォトダイオード５０が形成されたガラス基板１０１を、３００～４００℃の窒素ガス雰囲気中または真空中でアニールし、第１の層間絶縁膜１３１中に含まれている水素を島状シリコン層１２０、１８０内に拡散させる。これにより、島状シリコン層に含まれる未結合手（dungling bond）は終端され、ＴＦＴ４０およびフォトダイオード５０の島状シリコン層１２０、１８０に界面準位が発生しにくくなるので、閾値電圧等の特性が改善される。 Next, the first interlayer insulating film 131 and the second insulating film 131 and the second interlayer insulating film 131 are covered by the plasma CVD method, the low pressure CVD method, or the sputtering method so as to cover the island-like silicon layers 120 and 180 and the protective film 130 on the upper surface thereof. An interlayer insulating film 132 is sequentially formed. The first interlayer insulating film 131 is made of silicon nitride having a thickness of 100 to 400 nm, and the second interlayer insulating film 132 is made of silicon oxide having a thickness of 200 to 600 nm. Further, the glass substrate 101 on which the TFT 40 and the photodiode 50 are formed is annealed in a nitrogen gas atmosphere at 300 to 400 ° C. or in a vacuum, and the hydrogen contained in the first interlayer insulating film 131 is converted into island-shaped silicon. Diffuse into layers 120, 180. As a result, dungling bonds contained in the island-like silicon layer are terminated, and interface states are less likely to be generated in the island-like silicon layers 120 and 180 of the TFT 40 and the photodiode 50. Is improved.
　次に、第１および第２の層間絶縁膜１３１、１３２に、ドライエッチングによって、ソース領域１２０ａ、ドレイン領域１２０ｂ、ｎ型領域１８０ａ、ｐ型領域１８０ｂ、およびゲート電極１１０にそれぞれ達するコンタクトホールを開孔し、スパッタリング法によって、第２の層間絶縁膜１３２を含むガラス基板１０１の全面にアルミニウム膜１４１を成膜する。次に、アルミニウム膜１４１上に、フォトリソグラフィ法によって、所望の形状のレジストパターン１７４を形成し、レジストパターン１７４をマスクとしてアルミニウム膜１４１をドライエッチングする。その結果、ソース領域１２０ａと電気的に接続されたソース電極１４０ａ、ドレイン領域１２０ｂと電気的に接続されたドレイン電極１４０ｂ、ｎ型領域１８０ａと電気的に接続されたカソード電極１９０ａ、ｐ型領域１８０ｂと電気的に接続されたアノード電極１９０ｂ、およびゲート電極１１０と電気的に接続されたゲート接続電極（図示しない）が形成される。なお、アルミニウム膜１４１をウエットエッチングしてもよい。 Next, contact holes reaching the source region 120a, the drain region 120b, the n-type region 180a, the p-type region 180b, and the gate electrode 110 are opened in the first and second interlayer insulating films 131 and 132 by dry etching. An aluminum film 141 is formed on the entire surface of the glass substrate 101 including the second interlayer insulating film 132 by sputtering. Next, a resist pattern 174 having a desired shape is formed on the aluminum film 141 by photolithography, and the aluminum film 141 is dry-etched using the resist pattern 174 as a mask. As a result, the source electrode 140a electrically connected to the source region 120a, the drain electrode 140b electrically connected to the drain region 120b, the cathode electrode 190a electrically connected to the n-type region 180a, and the p-type region 180b. An anode electrode 190b electrically connected to the gate electrode 110 and a gate connection electrode (not shown) electrically connected to the gate electrode 110 are formed. Note that the aluminum film 141 may be wet-etched.
　図７（Ｊ）に示すように、ガラス基板１０１の全面に、感光性アクリル樹脂からなる平坦化膜１４８を成膜し、平坦化膜１４８を露光・現像することによって、ドレイン電極１４０ｂに達するコンタクトホールを開孔すると共に、フォトダイオード５０の真性領域１８０ｃの上方において、第２の層間絶縁膜１３２の表面に達する凹部１６０を開口する。次に、スパッタリング法によってＩＴＯ等の透明金属膜（図示しない）を成膜する。透明金属膜をエッチングし、平坦化膜１４８に開孔されたコンタクトホールを介してドレイン電極１４０ｂの上面と電気的に接続される画素電極１６１を形成する。画素電極１６１はさらに、カソード電極１９０ａの上方の平坦化膜１４８の表面から、凹部１６０の内面を覆い、さらにアノード電極１９０ｂの上方の平坦化膜１４８の表面まで覆うように形成される。ＴＦＴ４０の画素電極１６１の表面、ならびにフォトダイオード５０のカソード電極１９０ａおよびアノード電極１９０ｂの上方の画素電極１６１の表面に、クロム等からなるブラックマトリクス１６２を形成する。このようにして、画素形成部のスイッチング素子として機能するＴＦＴ４０と、タッチセンサとして機能するフォトダイオード５０を備えた半導体装置１００が製造される。 As shown in FIG. 7J, a planarizing film 148 made of a photosensitive acrylic resin is formed on the entire surface of the glass substrate 101, and the planarizing film 148 is exposed and developed to contact the drain electrode 140b. In addition to opening the hole, a recess 160 reaching the surface of the second interlayer insulating film 132 is opened above the intrinsic region 180 c of the photodiode 50. Next, a transparent metal film (not shown) such as ITO is formed by sputtering. The transparent metal film is etched to form a pixel electrode 161 that is electrically connected to the upper surface of the drain electrode 140b through a contact hole opened in the planarization film 148. The pixel electrode 161 is further formed so as to cover the inner surface of the recess 160 from the surface of the planarization film 148 above the cathode electrode 190a and further to the surface of the planarization film 148 above the anode electrode 190b. A black matrix 162 made of chromium or the like is formed on the surface of the pixel electrode 161 of the TFT 40 and the surface of the pixel electrode 161 above the cathode electrode 190a and the anode electrode 190b of the photodiode 50. In this way, the semiconductor device 100 including the TFT 40 that functions as a switching element of the pixel formation portion and the photodiode 50 that functions as a touch sensor is manufactured.
　なお、本実施形態の半導体装置１００に含まれるＴＦＴ４０は、画素形成部のスイッチング素子として機能するＴＦＴであるとして説明したが、ソースドライバやゲートドライバ等の駆動回路を構成するＴＦＴであってもよい。 Although the TFT 40 included in the semiconductor device 100 of the present embodiment has been described as a TFT that functions as a switching element of the pixel formation portion, it may be a TFT that constitutes a drive circuit such as a source driver or a gate driver. .
＜３．効果＞
　半導体装置１００に含まれるＴＦＴ４０では、チャネル層１２０ｃを含む島状シリコン層１２０は多結晶シリコンからなる。このため、チャネル層１２０ｃの移動度は高くなり、ＴＦＴ４０を高速で動作させることができる。また、ゲート電極１１０の端部で、多結晶シリコンからなる島状シリコン層１２０の段切れを防止できるので、ＴＦＴ４０を確実に動作させることができる。フォトダイオード５０では、ＴＦＴ４０が形成されたガラス基板１０１の面と反対側のガラス基板１０１の面から入射する光を遮光層６０によって遮光することができるので、タッチセンサとして機能するフォトダイオード５０の検出感度を高くすることができる。 <3. Effect>
In the TFT 40 included in the semiconductor device 100, the island-like silicon layer 120 including the channel layer 120c is made of polycrystalline silicon. For this reason, the mobility of the channel layer 120c is increased, and the TFT 40 can be operated at high speed. Moreover, since the step of the island-like silicon layer 120 made of polycrystalline silicon can be prevented at the end of the gate electrode 110, the TFT 40 can be operated reliably. In the photodiode 50, the light incident from the surface of the glass substrate 101 opposite to the surface of the glass substrate 101 on which the TFT 40 is formed can be shielded by the light shielding layer 60, so that the detection of the photodiode 50 functioning as a touch sensor is possible. Sensitivity can be increased.
　ＴＦＴ４０のゲート電極１１０に接続されたゲート配線ＧＬは、第１の金属層１１１と同じ膜厚で、同じ材料からなる金属層上に、第２の金属層１１３と同じ膜厚で、同じ材料からなる金属層が形成された積層金属膜によって形成されているので、ゲート配線ＧＬを介してゲート電極１１０に与えられる信号の遅延を防止することができる。 The gate wiring GL connected to the gate electrode 110 of the TFT 40 has the same thickness as that of the first metal layer 111 and is formed of the same material on the metal layer made of the same material as that of the second metal layer 113. Since the metal layer is formed of the laminated metal film, delay of a signal applied to the gate electrode 110 through the gate wiring GL can be prevented.
　液晶パネル１０の表示領域２１に形成された画素形成部３１に含まれる薄膜トランジスタとして、半導体装置１００のＴＦＴ４０を用い、フォトダイオードとしてフォトダイオード５０を用いれば、ＴＦＴを高速で動作させることができると共に、フォトダイオードの検出感度を高くすることができる。このため、液晶パネル１０をタッチパネルとして使用することができる。 If the TFT 40 of the semiconductor device 100 is used as the thin film transistor included in the pixel formation portion 31 formed in the display region 21 of the liquid crystal panel 10 and the photodiode 50 is used as the photodiode, the TFT can be operated at high speed. The detection sensitivity of the photodiode can be increased. For this reason, the liquid crystal panel 10 can be used as a touch panel.
　なお、上記実施形態において、ＴＦＴ４０を第１の半導体素子、フォトダイオード５０を第２の半導体素子ともいう。また、ＴＦＴ４０のゲート電極１１０を第１の構造部または第１の層、ＴＦＴ４０の島状シリコン層１２０を多結晶シリコン層ともいう。フォトダイオード５０の遮光層６０を第２の構造部、フォトダイオード５０の第１の金属層１１１を第２の層、第２の金属層１１３を第３の層ともいう。 In the above embodiment, the TFT 40 is also referred to as a first semiconductor element, and the photodiode 50 is also referred to as a second semiconductor element. The gate electrode 110 of the TFT 40 is also referred to as a first structure portion or a first layer, and the island-like silicon layer 120 of the TFT 40 is also referred to as a polycrystalline silicon layer. The light shielding layer 60 of the photodiode 50 is also referred to as a second structure portion, the first metal layer 111 of the photodiode 50 is also referred to as a second layer, and the second metal layer 113 is also referred to as a third layer.
＜４．変形例＞
＜４．１　第１の変形例＞
　非晶質シリコン層を完全に溶融させて多結晶シリコン層を形成するときに、非晶質シリコン層がゲート電極の端部で段切れしないようにするために、図５に示す半導体装置１００のようにゲート電極１１０の膜厚を薄くする代わりに、ゲート電極の端部の形状をテーパ状にしてもよい。図９は、本発明の第１の変形例に係る、ゲート電極２１０の端部の形状がテーパ状であるＴＦＴ４１を備えた半導体装置２００の構成を示す断面図である。図９に示す半導体層２００の構成要素のうち、図５に示す半導体装置１００の構成要素と同じ構成要素については、同じ参照符号を付してその説明を省略する。 <4. Modification>
<4.1 First Modification>
In order to prevent the amorphous silicon layer from being disconnected at the end of the gate electrode when the amorphous silicon layer is completely melted to form the polycrystalline silicon layer, the semiconductor device 100 shown in FIG. Thus, instead of reducing the thickness of the gate electrode 110, the shape of the end of the gate electrode may be tapered. FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device 200 including a TFT 41 having a tapered end portion of the gate electrode 210 according to the first modification of the present invention. Among the constituent elements of the semiconductor layer 200 shown in FIG. 9, the same constituent elements as those of the semiconductor device 100 shown in FIG.
　図９に示すように、ゲート電極２１０の端部の形状はテーパ状になっている。ゲート電極２１０を覆うように形成された非晶質シリコン層の傾斜は、ゲート電極２１０の端部で緩やかになる。非晶質シリコン層にレーザ光を照射して、非晶質シリコン層を完全に溶融させても、溶融したシリコンはガラス基板１０１側に流れにくくなる。このため、溶融したシリコンが固化した多結晶シリコン層からなる島状シリコン層１２０は、ゲート電極２１０の端部で段切れしにくくなる。なお、ゲート電極２１０の端部の形状をテーパ状にするとき、同時に遮光層２６０を構成する第１の金属層２１１の端部もテーパ状になる。しかし、島状シリコン層１８０は遮光層２６０上に形成されるので、上述のように遮光層２６０の端部で多結晶シリコン層が段切れしても問題は生じない。このため、遮光層２６０の端部の形状はテーパ状でなくてもよい。本明細書では、図５に示すゲート電極１１０のように、その端部がガラス基板１０１に対してほぼ垂直である場合だけでなく、図９に示すゲート電極２１０のように、その端部がガラス基板１０１に対して所定の角度を有するテーパ状の場合も、ガラス基板１０１の表面とゲート電極２１０の表面との高低差を段差という。 As shown in FIG. 9, the shape of the end of the gate electrode 210 is tapered. The inclination of the amorphous silicon layer formed so as to cover the gate electrode 210 becomes gentle at the end of the gate electrode 210. Even if the amorphous silicon layer is irradiated with laser light to completely melt the amorphous silicon layer, the melted silicon hardly flows to the glass substrate 101 side. For this reason, the island-like silicon layer 120 made of a polycrystalline silicon layer obtained by solidifying molten silicon is difficult to be disconnected at the end of the gate electrode 210. Note that when the shape of the end portion of the gate electrode 210 is tapered, the end portion of the first metal layer 211 constituting the light shielding layer 260 is also tapered. However, since the island-like silicon layer 180 is formed on the light shielding layer 260, there is no problem even if the polycrystalline silicon layer is disconnected at the end of the light shielding layer 260 as described above. For this reason, the shape of the edge part of the light shielding layer 260 may not be a taper shape. In this specification, not only when the end portion is substantially perpendicular to the glass substrate 101 as in the gate electrode 110 shown in FIG. 5, but also at the end portion as in the gate electrode 210 shown in FIG. 9. Also in the case of a tapered shape having a predetermined angle with respect to the glass substrate 101, a difference in height between the surface of the glass substrate 101 and the surface of the gate electrode 210 is referred to as a step.
　半導体装置２００では、ゲート電極２１０の端部に形成されたテーパがガラス基板１０１となす好ましい角度は、１０～５０度である。テーパの角度が５０度よりも大きい場合には、溶融したシリコンが流れやすくなるので、段切れが発生しやすくなる。一方、テーパの角度が１０度よりも小さい場合には、溶融したシリコンは流れにくくなるが、テーパの加工が難しくなる。 In the semiconductor device 200, a preferable angle between the taper formed at the end of the gate electrode 210 and the glass substrate 101 is 10 to 50 degrees. When the taper angle is larger than 50 degrees, melted silicon tends to flow, so that disconnection is likely to occur. On the other hand, when the taper angle is smaller than 10 degrees, the molten silicon is difficult to flow, but the taper is difficult to process.
　次に、ゲート電極２１０の端部の形状をテーパ状にする方法について説明する。図６（Ｂ）に示す工程において、レジストパターン１７１ａをマスクとして、アルミニウムを主成分とする合金からなる第２の金属層１１３をドライエッチングによってパターニングする。次に、タングステンを主成分とする合金からなる第１の金属層１１１を、ウエットエッチングによってパターニングする。ウエットエッチングには、フッ硝酸、フッ化水素酸（ＨＦ）、過酸化水素（Ｈ2Ｏ2）等を主成分とするエッチャントを使用する。この場合、第１の金属層１１１のウエットエッチングは、第２の金属層１１３の下面端部を起点として下方側および側面側に等方的に進む。その結果、第２の金属層１１３が第１の金属層１１１に対してオーバハング状態になり、第１の金属層１１１は、側面の形状がテーパ状の第１の金属層２１１になる。さらに、図６（Ｃ）に示す工程と同様にして、ゲート電極１１５となるべき突起部１１４上のレジストパターン１７１ａをアッシングによって除去し、第２の金属層１１３の表面を露出させる。そして、アルミニウムを主成分とする合金からなる第２の金属層１１３をウエットエッチングにより除去する、その結果、第１の金属層２１１のみからなるゲート電極２１０が形成され、ゲート電極２１０の側面はテーパ状になる。 Next, a method for forming the end portion of the gate electrode 210 into a tapered shape will be described. In the step shown in FIG. 6B, the second metal layer 113 made of an alloy containing aluminum as a main component is patterned by dry etching using the resist pattern 171a as a mask. Next, the first metal layer 111 made of an alloy containing tungsten as a main component is patterned by wet etching. In the wet etching, an etchant mainly containing hydrofluoric acid, hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ), or the like is used. In this case, the wet etching of the first metal layer 111 isotropically proceeds to the lower side and the side surface starting from the lower surface end of the second metal layer 113. As a result, the second metal layer 113 is in an overhanging state with respect to the first metal layer 111, and the first metal layer 111 becomes the first metal layer 211 whose side surface is tapered. Further, in the same manner as in the step shown in FIG. 6C, the resist pattern 171a on the projecting portion 114 to be the gate electrode 115 is removed by ashing to expose the surface of the second metal layer 113. Then, the second metal layer 113 made of an alloy containing aluminum as a main component is removed by wet etching. As a result, the gate electrode 210 made only of the first metal layer 211 is formed, and the side surface of the gate electrode 210 is tapered. It becomes a shape.
　なお、ゲート電極２１０の膜厚が薄い場合、その端部の形状をテーパ状にしなくても、上述のようにゲート電極２１０の端部での島状シリコン層１２０の段切れを防止できる。しかし、ゲート電極２１０の膜厚を薄くするだけでなく、さらにその端部の形状をテーパ状にすれば、島状シリコン層１２０の段切れをより一層防止できる。 Note that when the gate electrode 210 is thin, the island-like silicon layer 120 can be prevented from being cut off at the end of the gate electrode 210 as described above, even if the end is not tapered. However, if the gate electrode 210 is not only thinned, but also its end is tapered, the island-like silicon layer 120 can be further prevented from being disconnected.
＜４．２　第２の変形例＞
　図４に示す半導体装置１００では、フォトダイオード５０の遮光層６０を、タングステンを主成分とする合金からなる第１の金属層１１１上に、アルミニウムを主成分とする合金からなる第２の金属層１１３を積層した積層金属膜をパターニングして形成した。しかし、ＴＦＴ４０のゲート電極１１０と同じ材料からなり、膜厚も等しい第１の金属層１１１を含む、３層以上の金属層を積層した積層金属膜をパターニングして遮光層を形成してもよい。この場合、遮光層の膜厚をより厚くできるので、フォトダイオードに直接入射するバックライト光源からの光をより完全に遮光し、本来検出すべき指等によって反射されたバックライト光源からの光の検出感度をより高くすることができる。 <4.2 Second Modification>
In the semiconductor device 100 shown in FIG. 4, the light shielding layer 60 of the photodiode 50 is formed on the first metal layer 111 made of an alloy containing tungsten as a main component and the second metal layer made of an alloy containing aluminum as a main component. The laminated metal film on which 113 was laminated was formed by patterning. However, the light shielding layer may be formed by patterning a laminated metal film made of the same material as the gate electrode 110 of the TFT 40 and including the first metal layer 111 having the same film thickness and laminated with three or more metal layers. . In this case, since the thickness of the light shielding layer can be increased, the light from the backlight light source directly incident on the photodiode is more completely shielded, and the light from the backlight light source reflected by the finger or the like to be detected originally is reflected. The detection sensitivity can be further increased.
　また、フォトダイオードの遮光層を、タングステンを主成分とする合金のみからなる金属層によって形成してもよい。この場合、遮光層としての役割を十分果たすことができるように、金属層の膜厚を例えば１５０～３００ｎｍと、少なくとも上述の実施形態の第１の金属層１１１と第２の金属層１１３の膜厚を合わせた程度の膜厚にする必要がある。この場合、２種類の金属層を成膜する代わりに、１種類の金属層の膜厚を調整して成膜するだけでよいので、成膜工程を簡略化できる。 Further, the light shielding layer of the photodiode may be formed of a metal layer made of only an alloy containing tungsten as a main component. In this case, the film thickness of the metal layer is, for example, 150 to 300 nm, and at least the first metal layer 111 and the second metal layer 113 of the above-described embodiment so that the role as the light shielding layer can be sufficiently achieved. It is necessary to make the film thickness to the extent of the combined thickness. In this case, instead of forming two types of metal layers, it is only necessary to adjust the film thickness of one type of metal layer to form a film, so that the film forming process can be simplified.
　また、ＴＦＴのゲート電極の膜厚を薄くするために、厚く形成した金属層のうちゲート電極になるべき領域の膜厚をエッチングによって薄くする必要がある。しかし、ドライエッチング後の金属層の表面を滑らかにすることは難しく、表面に凹凸が形成されやすい。金属層の表面に凹凸があると、レーザアニールによって結晶化された多結晶シリコン層の結晶粒径が金属層の凹凸のためにばらつきやすくなるという問題がある。そこで、ウエットエッチングによって、ゲート電極となるべき突起部の金属層の膜厚を薄くすることが好ましい。なお、タングステンを主成分とする合金からなる金属層のウエットエッチングには、フッ硝酸、フッ化水素酸、過酸化水素等を主成分とするエッチャントが用いられる。 Also, in order to reduce the thickness of the gate electrode of the TFT, it is necessary to reduce the thickness of the region to be the gate electrode in the thick metal layer by etching. However, it is difficult to smooth the surface of the metal layer after dry etching, and irregularities are easily formed on the surface. If the surface of the metal layer is uneven, there is a problem that the crystal grain size of the polycrystalline silicon layer crystallized by laser annealing tends to vary due to the unevenness of the metal layer. Therefore, it is preferable to reduce the thickness of the metal layer of the protruding portion to be the gate electrode by wet etching. Note that an etchant mainly containing hydrofluoric acid, hydrofluoric acid, hydrogen peroxide, or the like is used for wet etching of a metal layer made of an alloy containing tungsten as a main component.
＜４．３　第３の変形例＞
　図５に示す半導体装置１００では、ＴＦＴ４０のゲート電極１１０はガラス基板１０１上にのみ形成されていた。しかし、ＴＦＴ４０の代わりに、島状シリコン層１２０の下方と上方にゲート電極を有する、ダブルゲート型ＴＦＴを形成してもよい。図１０は、本発明の第３の変形例に係る、ダブルゲート型ＴＦＴ４２を含む半導体装置３００の構成を示す断面図である。図１０に示す半導体装置３００の構成要素のうち、図５に示す半導体装置１００の構成要素と同じ構成要素については、同じ参照符号を付してその説明を省略する。 <4.3 Third Modification>
In the semiconductor device 100 shown in FIG. 5, the gate electrode 110 of the TFT 40 is formed only on the glass substrate 101. However, instead of the TFT 40, a double gate TFT having gate electrodes below and above the island-like silicon layer 120 may be formed. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device 300 including a double gate TFT 42 according to a third modification of the present invention. Among the constituent elements of the semiconductor device 300 shown in FIG. 10, the same constituent elements as those of the semiconductor device 100 shown in FIG.
　図１０に示すように、ダブルゲート型ＴＦＴ４２では、図５に示す半導体装置１００のＴＦＴ４０と同様に、第１のゲート電極４１０がガラス基板１０１上に形成されているだけでなく、さらに第２のゲート電極４１５がチャネル領域１２０ｃと対向する、第２の層間絶縁膜１３２上に形成されている。このようなダブルゲート型ＴＦＴ４２では、第２のゲート電極４１５に印加する電圧を所定の電圧に固定することによって、バックゲート効果を生じさせることができるので、閾値電圧を安定化させることができる。また、第２のゲート電極４１５に印加する電圧を変えることによって、閾値電圧を変えることができる。この場合、半導体装置３００の製造プロセスを変更することなく、第２のゲート電極４１５に印加する電圧を変更するだけで閾値電圧を容易に変えることができる。 As shown in FIG. 10, in the double gate TFT 42, the first gate electrode 410 is not only formed on the glass substrate 101, but also the second gate, as in the TFT 40 of the semiconductor device 100 shown in FIG. A gate electrode 415 is formed on the second interlayer insulating film 132 facing the channel region 120c. In such a double gate TFT 42, the voltage applied to the second gate electrode 415 is fixed to a predetermined voltage, so that the back gate effect can be generated, and the threshold voltage can be stabilized. Further, the threshold voltage can be changed by changing the voltage applied to the second gate electrode 415. In this case, the threshold voltage can be easily changed only by changing the voltage applied to the second gate electrode 415 without changing the manufacturing process of the semiconductor device 300.
　ダブルゲート型ＴＦＴ４２の第２のゲート電極４１５は、ソース電極１４０ａやドレイン電極１４０ｂを形成するために成膜されたアルミニウム膜等の金属膜をパターニングすることによって、ソース電極１４０ａやドレイン電極１４０ｂと同時に形成される。このため、上述の実施形態の製造方法において、図７（Ｉ）で説明したソース電極１４０ａ、ドレイン電極１４０ｂ等をパターニングするためのマスクの代わりに、別のマスクを使用するだけでよく、製造工程を新たに追加する必要はない。 The second gate electrode 415 of the double-gate TFT 42 is patterned simultaneously with the source electrode 140a and the drain electrode 140b by patterning a metal film such as an aluminum film formed to form the source electrode 140a and the drain electrode 140b. It is formed. For this reason, in the manufacturing method of the above-described embodiment, it is only necessary to use another mask instead of the mask for patterning the source electrode 140a, the drain electrode 140b and the like described in FIG. There is no need to add a new.
＜４．４　第４の変形例＞
　図１では、フォトダイオード５０を画素形成部ごとに配置し、タッチセンサとして利用している。しかし、フォトダイオードを、ＴＦＴ基板１１の額縁領域に配置し、外光の強度に合わせてバックライト光源１３の輝度を制御するアンビエントライトセンサとして使用してもよい。図１１は、本発明の第４の変形例に係る、アンビエントライトセンサとして機能するフォトダイオード２５を備えた液晶パネル８０の構成を示す斜視図である。図１１に示す液晶パネル８０の構成要素のうち、図１に示す液晶パネル１０の構成要素と同じ構成要素には、同一の参照符号を付してその説明を省略する。 <4.4 Fourth Modification>
In FIG. 1, a photodiode 50 is arranged for each pixel formation portion and used as a touch sensor. However, a photodiode may be disposed in the frame region of the TFT substrate 11 and used as an ambient light sensor that controls the luminance of the backlight light source 13 in accordance with the intensity of external light. FIG. 11 is a perspective view showing a configuration of a liquid crystal panel 80 including a photodiode 25 that functions as an ambient light sensor according to a fourth modification of the present invention. Among the components of the liquid crystal panel 80 shown in FIG. 11, the same components as those of the liquid crystal panel 10 shown in FIG.
　図１１に示すように、液晶パネル８０では、フォトダイオード２５はＴＦＴ基板１１の額縁領域に設けられ、フォトダイオード２５に隣接してバックライト制御回路２６が設けられている。バックライト制御回路２６は、フォトダイオード２５の出力に基づき、バックライト光源１３の光の強度を調節するので、外光の強度に応じて映像の輝度を調整することができる。なお、本明細書ではタッチセンサとアンビエントセンサをまとめて光センサといい、さらにタッチセンサを第１の光センサ、アンビエントセンサを第２の光センサという。 As shown in FIG. 11, in the liquid crystal panel 80, the photodiode 25 is provided in the frame region of the TFT substrate 11, and the backlight control circuit 26 is provided adjacent to the photodiode 25. Since the backlight control circuit 26 adjusts the intensity of the light from the backlight source 13 based on the output of the photodiode 25, the brightness of the image can be adjusted according to the intensity of the external light. In this specification, the touch sensor and the ambient sensor are collectively referred to as an optical sensor, the touch sensor is referred to as a first optical sensor, and the ambient sensor is referred to as a second optical sensor.
＜４．５　第５の変形例＞
　図４に示す半導体装置１００では、ボトムゲート型ＴＦＴ４０と共にガラス基板１０１に形成されるのは、遮光層６０を備えたフォトダイオード５０であるとして説明した。しかし、ボトムゲート型ＴＦＴ４０と共に形成される半導体素子は、信号の遅延を防止するために、配線抵抗の低い配線層を有するＴＦＴであってもよい。この場合、遮光層６０と同様に、第１の金属層と、第１の金属層よりも大きな導電率を有する第２の金属層を積層した積層金属膜を用いて配線層を形成する。 <4.5 Fifth Modification>
In the semiconductor device 100 shown in FIG. 4, it has been described that the photodiode 50 including the light shielding layer 60 is formed on the glass substrate 101 together with the bottom gate TFT 40. However, the semiconductor element formed together with the bottom gate TFT 40 may be a TFT having a wiring layer with low wiring resistance in order to prevent signal delay. In this case, similarly to the light shielding layer 60, the wiring layer is formed using a laminated metal film in which a first metal layer and a second metal layer having a higher conductivity than the first metal layer are laminated.
＜４．６　第６の変形例＞
　上記説明では、多結晶シリコンからなる島状シリコン層１２０は、金属などの導電性材料からなるゲート電極１１０の端部の段差を覆うように形成されている。しかし、島状シリコン層１２０は、絶縁材料からなる構造部の端部の段差を覆うように形成されていてもよい。 <4.6 Sixth Modification>
In the above description, the island-like silicon layer 120 made of polycrystalline silicon is formed so as to cover the step at the end of the gate electrode 110 made of a conductive material such as metal. However, the island-like silicon layer 120 may be formed so as to cover the step at the end of the structure portion made of an insulating material.
　また、図４に示す半導体装置１００を、アクティブマトリクス型液晶表示装置のＴＦＴ基板１１に適用する場合について説明したが、アクティブマトリクス型有機ＥＬ（Electro-Luminescence）表示装置のＴＦＴ基板にも適用することができる。 Further, the case where the semiconductor device 100 shown in FIG. 4 is applied to the TFT substrate 11 of the active matrix liquid crystal display device has been described. However, the semiconductor device 100 is also applied to the TFT substrate of an active matrix organic EL (Electro-Luminescence) display device. Can do.
　本発明は、タッチパネル機能を有するアクティブマトリクス型の液晶表示装置や、アンビエントセンサによってバックライト光源の光の強度を調節する液晶表示装置などの表示装置に適している。 The present invention is suitable for display devices such as an active matrix type liquid crystal display device having a touch panel function and a liquid crystal display device in which the intensity of light from a backlight light source is adjusted by an ambient sensor.
　１０…配線構造
　１１…ＴＦＴ基板
　２２…ゲートドライバ
　２３…ソースドライバ
　２５…フォトダイオード（アンビエントセンサ）
　２６…バックライト制御回路
　３１…画素形成部
　４０、４１…ボトムゲート型薄膜トランジスタ
　４２…ダブルゲート型薄膜トランジスタ
　５０、５１…フォトダイオード（タッチセンサ）
　６０…遮光層
　１００、２００、３００…半導体装置
　１０１…ガラス基板（絶縁基板）
　１１０、２１０、４１０、４１５…ゲート電極
　１１１、２１１…第１の金属層
　１１３…第２の金属層
　１２０…（ＴＦＴの）島状シリコン層
　１８０…（フォトダイオードの）島状シリコン層 DESCRIPTION OF SYMBOLS 10 ... Wiring structure 11 ... TFT substrate 22 ... Gate driver 23 ... Source driver 25 ... Photodiode (ambient sensor)
DESCRIPTION OF SYMBOLS 26 ... Backlight control circuit 31 ... Pixel formation part 40, 41 ... Bottom gate type thin film transistor 42 ... Double gate type thin film transistor 50, 51 ... Photodiode (touch sensor)
60 ... Light shielding layer 100, 200, 300 ... Semiconductor device 101 ... Glass substrate (insulating substrate)
110, 210, 410, 415 ... gate electrodes 111, 211 ... first metal layer 113 ... second metal layer 120 ... island-like silicon layer (of TFT) 180 ... island-like silicon layer (of photodiode)

Claims (13)

  1. 　少なくとも第１の半導体素子と前記第１の半導体素子とは異なる種類の第２の半導体素子とが同一の絶縁基板上に形成された半導体装置であって、
    　前記第１の半導体素子は、
    　　段差を有し、第１の層からなる第１の構造部と、
    　　前記第１の構造部の少なくとも前記段差を覆うように形成された多結晶半導体層とを備え、
    　前記第２の半導体素子は、
    　　前記第１の層と同じ材料からなる第２の層を含み、前記第１の構造部よりも厚い第２の構造部を備え、
    　前記第１の構造部の段差は、前記多結晶半導体層を段切れさせることなく形成可能な段差であることを特徴とする、半導体装置。     A semiconductor device in which at least a first semiconductor element and a second semiconductor element of a different type from the first semiconductor element are formed on the same insulating substrate,
    The first semiconductor element is:
    A first structure having a step and comprising a first layer;
    A polycrystalline semiconductor layer formed to cover at least the step of the first structure portion,
    The second semiconductor element is:
    Including a second layer made of the same material as the first layer, and comprising a second structure part thicker than the first structure part,
    The step of the first structure portion is a step that can be formed without breaking the polycrystalline semiconductor layer.
  2. 　少なくとも前記第１の構造部の段差の形状はテーパ状であることを特徴とする、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein at least the shape of the step of the first structure portion is tapered.
  3. 　前記第１の半導体素子はボトムゲート型薄膜トランジスタであり、
    　　前記第１の構造部は前記ボトムゲート型薄膜トランジスタのゲート電極であり、
    　　前記多結晶半導体層は前記ボトムゲート型薄膜トランジスタのチャネル層であり、
    　前記第２の半導体素子は、前記絶縁基板の前記ボトムゲート型薄膜トランジスタが形成された第１の面側から入射する光を受光する光センサであり、
    　　前記第２の構造部は、前記絶縁基板において、前記第１の面と対向する第２の面側から前記光センサに入射する光を遮光する遮光層であることを特徴とする、請求項１に記載の半導体装置。     The first semiconductor element is a bottom-gate thin film transistor;
    The first structure portion is a gate electrode of the bottom-gate thin film transistor;
    The polycrystalline semiconductor layer is a channel layer of the bottom-gate thin film transistor;
    The second semiconductor element is an optical sensor that receives light incident from a first surface side of the insulating substrate on which the bottom-gate thin film transistor is formed,
    The said 2nd structure part is a light shielding layer which light-shields the light which injects into the said optical sensor from the 2nd surface side facing the said 1st surface in the said insulating substrate, The said 1st structure is characterized by the above-mentioned. A semiconductor device according to 1.
  4. 　前記遮光層は前記第２の層のみからなり、
    　前記第２の層の膜厚は前記ゲート電極の膜厚よりも厚いことを特徴とする、請求項３に記載の半導体装置。     The light shielding layer consists only of the second layer,
    The semiconductor device according to claim 3, wherein a film thickness of the second layer is larger than a film thickness of the gate electrode.
  5. 　前記遮光層は前記第２の層を含む複数の層からなり、
    　前記第２の層の膜厚は前記ゲート電極の膜厚と等しいことを特徴とする、請求項３に記載の半導体装置。     The light shielding layer is composed of a plurality of layers including the second layer,
    The semiconductor device according to claim 3, wherein a film thickness of the second layer is equal to a film thickness of the gate electrode.
  6. 　前記チャネル層は、長軸の方向がチャネル長の方向に形成されたラテラル結晶を含む多結晶半導体層であることを特徴とする、請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the channel layer is a polycrystalline semiconductor layer including a lateral crystal whose major axis direction is formed in the channel length direction.
  7. 　前記光センサは、ラテラル型ｐｉｎ構造のフォトダイオードであることを特徴とする、請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the optical sensor is a photodiode having a lateral pin structure.
  8. 　前記薄膜トランジスタのゲート電極に接続された配線をさらに含み、
    　前記配線は、前記第１の層の上面に積層された、前記第１の層よりも導電率の大きな材料からなる第３の層をさらに含むことを特徴とする、請求項３に記載の半導体装置。     Further comprising a wiring connected to the gate electrode of the thin film transistor,
    4. The semiconductor according to claim 3, wherein the wiring further includes a third layer made of a material having a higher conductivity than the first layer, which is stacked on an upper surface of the first layer. apparatus.
  9. 　請求項３に記載の半導体装置をそれぞれが含む複数の画素形成部を絶縁基板上に備えた表示装置であって、
    　前記複数の画素形成部のそれぞれは、
    　　画素電極と、
    　　オフ状態からオン状態に切り換わることによって電圧を前画素電極に印加する薄膜トランジスタと、
    　　前記画素形成部内に入射する光を受光する第１の光センサとを備え、
    　前記薄膜トランジスタおよび前記第１の光センサは、それぞれ第１の半導体素子および第２の半導体素子であることを特徴とする、表示装置。     A display device comprising a plurality of pixel formation portions each including the semiconductor device according to claim 3 on an insulating substrate,
    Each of the plurality of pixel formation portions includes
    A pixel electrode;
    A thin film transistor that applies a voltage to the previous pixel electrode by switching from an off state to an on state; and
    A first photosensor that receives light incident on the pixel formation portion,
    The display device, wherein the thin film transistor and the first photosensor are a first semiconductor element and a second semiconductor element, respectively.
  10. 　前記画素形成部を駆動する駆動回路をさらに含み、
    　前記駆動回路は前記第１の半導体素子によって構成されていることを特徴とする、請求項９に記載の表示装置。     A driving circuit for driving the pixel forming unit;
    The display device according to claim 9, wherein the drive circuit is configured by the first semiconductor element.
  11. 　バックライト光源と、
    　前記複数の画素形成部が形成された表示領域の外側に配置され、外光の強度を検出する第２の光センサと、
    　前記第２の光センサの出力に基づいて前記バックライト光源の輝度を制御するバックライト制御回路とをさらに含み、
    　前記第２の光センサは前記第２の半導体素子であることを特徴とする、請求項９に記載の表示装置。     A backlight light source;
    A second optical sensor that is disposed outside a display area in which the plurality of pixel forming portions are formed and detects the intensity of external light;
    A backlight control circuit that controls the luminance of the backlight light source based on the output of the second photosensor;
    The display device according to claim 9, wherein the second photosensor is the second semiconductor element.
  12. 　ボトムゲート型薄膜トランジスタと、遮光層を有する光センサとが同一の絶縁基板上に形成された半導体装置の製造方法であって、
    　前記絶縁基板上に第１の導電層を成膜する工程と、
    　前記第１の導電層上に第２の導電層を成膜する工程と、
    　ハーフトーンマスクを用いて露光することにより、前記第２の導電層上において、ゲート電極となるべき領域に第１のレジストパターンを形成し、遮光層となるべき領域に、前記第１のレジストパターンよりも厚い膜厚の第２のレジストパターンを形成する工程と、
    　前記第１および第２のレジストパターンをマスクとして、前記第２導電層、前記第１の導電層の順にエッチングして前記遮光層を形成する工程と、
    　前記第１および第２のレジストパターンの膜厚を同時に薄くすることによって、前記第１のレジストパターンで覆われていた第２の導電層の表面を露出させる工程と、
    　表面を露出させた前記第２の導電層を除去して、前記ゲート電極を形成する工程とを備えることを特徴とする、半導体装置の製造方法。     A method for manufacturing a semiconductor device in which a bottom-gate thin film transistor and an optical sensor having a light shielding layer are formed on the same insulating substrate,
    Forming a first conductive layer on the insulating substrate;
    Forming a second conductive layer on the first conductive layer;
    By exposing using a halftone mask, a first resist pattern is formed in a region to be a gate electrode on the second conductive layer, and the first resist pattern is formed in a region to be a light shielding layer. Forming a thicker second resist pattern; and
    Etching the second conductive layer and the first conductive layer in this order using the first and second resist patterns as a mask to form the light shielding layer;
    Exposing the surface of the second conductive layer covered with the first resist pattern by simultaneously reducing the thickness of the first and second resist patterns;
    And removing the second conductive layer whose surface is exposed to form the gate electrode. A method for manufacturing a semiconductor device, comprising:
  13. 　前記ゲート電極および前記遮光層を覆うように非晶質半導体層を形成する工程と、
    　前記非晶質半導体層に連続発振レーザのレーザ光を照射して溶融させた後に固化させて、多結晶半導体層を形成する工程と、
    　前記多結晶半導体層をパターニングすることにより、前記ゲート電極を覆う前記薄膜トランジスタのチャネル層を形成すると同時に、前記光センサの半導体層を前記遮光層の上方に形成する工程とをさらに含むことを特徴とする、請求項１２に記載の半導体装置の製造方法。     Forming an amorphous semiconductor layer so as to cover the gate electrode and the light shielding layer;
    A step of forming a polycrystalline semiconductor layer by solidifying the amorphous semiconductor layer after irradiating the amorphous semiconductor layer with laser light of a continuous wave laser; and
    Forming a channel layer of the thin film transistor covering the gate electrode by patterning the polycrystalline semiconductor layer, and simultaneously forming a semiconductor layer of the photosensor above the light shielding layer. A method of manufacturing a semiconductor device according to claim 12.
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