WO2011033072A2 - High-efficiency amorphous silicon photovoltaic devices - Google Patents

Abstract

A method for manufacturing an amorphous silicon p-i-n solar cell is disclosed. The cell comprises an anti-reflection coating and doped LPCVD ZnO front and back contacts, wherein the doped LPCVD ZnO front and back contacts are polycrystalline films constituted of large grains whose extremities appear at the growing surface as pyramids. The method comprises: depositing said front contact by means of LPCVD; depositing the silicon layers of said p-i-n solar cell by means of plasma enhanced chemical vapor deposition; depositing said back contact by means of LPCVD; providing said anti-reflection coating. The amorphous silicon p-i-n solar cell can achieve a stabilized efficiency of 10.09%.

Description

HIGH-EFFICIENCY AMORPHOUS SILICON PHOTOVOLTAIC DEVICES

FIELD OF THE INVENTION

The present invention relates to silicon-based thin-film solar cells and modules and to their manufacture. It relates to improvements in the manufacturing process for thin-film, silicon-based solar cells or modules. More specifically the invention relates to amorphous thin-film solar cells and their manufacture.

BACKGROUND ART

Photovoltaic devices, photoelectric conversion devices or solar cells are devices which convert light, especially sunlight into direct current (DC) electrical power. For low-cost mass production thin film solar cells are being of interest since they allow using glass, glass ceramics or other rigid or flexible substrates as a base material (substrate) instead of crystalline or polycrystalline silicon. The solar cell structure, i. e. the layer sequence responsible for or capable of the photovoltaic effect is being deposited in thin layers. This deposition may take place under atmospheric or vacuum conditions. Deposition techniques are widely known in the art, such as PVD, CVD, PECVD, APCVD,... all being used in semiconductor technology.

The conversion efficiency of a solar cell is the common measure for the performance of a solar cell and is being determined by the ratio of the output power density (= product of open-circuit voltage V_oc, fill-factor FF and current-density J_sc) - to the input power density.

A thin-film solar cell generally includes a first electrode, one or more semiconductor thin-film p-i-n or n-i-p junctions, and a second electrode, which are successively stacked on a substrate. Each p-i-n junction or thin-film photoelectric conversion unit includes an intrinsic or i-type layer sandwiched between a positively doped or p-type layer and a negatively doped or n-type layer. The intrinsic semiconductor layer occupies the most part of the thickness of the thin-film p-i-n junction. Photoelectric conversion occurs primarily in this i-type layer; hence it is also called active or absorber layer . Depending on the crystallinity of the i-type layer solar cells or photoelectric (conversion) devices are characterized as amorphous (a-Si) or microcrystalline ^c-Si) solar cells, independent of the kind of crystallinity of the adjacent p and n-layers. Microcrystalline layers are being understood, as common in the art, as layers comprising at least a Raman crystallinity of 15% of microcrystalline crystallites in an amorphous matrix.

The doped layers in a p-i-n junction are also often referred to as window layers. Since the light absorbed by the doped p/n layers is lost for the active layer, highly transparent window layers are desired to obtain high current-densities (J_sc) . Furthermore the window layers are instrumental in establishing the electric field in the semiconductor junction constituting the solar cell, which helps collecting the photo-generated charge carriers and obtain high V_oc and FF values. Besides this, the contact between the front transparent conductive oxide (TCO) and the window layer should be ohmic with a low resistivity, in order to obtain good FF values. In the art window layers of microcrystalline silicon have been preferred over amorphous window layers due to their better optical properties (less absorption) .

Prior Art Fig. 9 shows a basic, simple photovoltaic cell 40 comprising a transparent substrate 41, e. g. glass with a layer of a transparent conductive oxide (TCO) 42 deposited thereon. This layer is also called front contact and acts as first electrode for the photovoltaic element. The combination of substrate 41 and front contact 42 is also known as superstrate. The next layer 43 acts as the active photovoltaic layer and comprises three "sub-layers" forming a p-i-n junction. Said layer 43 comprises hydrogenated microcrystalline, nanocrystalline or amorphous silicon or a combination thereof. Sub-layer 44 (adjacent to TCO front contact 42) is positively doped, the adjacent sub-layer 45 is intrinsic, and the final sub-layer 46 is negatively doped. In an alternative embodiment the layer sequence p-i-n as described can be inverted to n-i-p, then layer 44 is identified as n-layer, layer 45 again as intrinsic, layer 46 as p-layer.

Finally, the cell includes a rear contact layer 47 (also called back contact) which may be made of zinc oxide, tin oxide or ITO and a reflective layer 48. Alternatively a metallic back contact may be realized, which can combine the physical properties of back reflector 48 and back contact 47. For illustrative purposes, arrows indicate impinging light.

It is generally understood that when light, for example, solar radiation, impinges on a photoelectric device electron-hole pairs are generated in the i-layer. The holes from the generated pair are directed towards the p-region and the electrons towards the n- region. The contacts are generally directly or indirectly in contact with the p- and n-regions . Current will flow through an external circuit connecting these contacts as long as light continues to generate electron-hole pairs.

I . GENERAL

HIGH-EFFICIENCY AMORPHOUS SILICON DEVICES ON LPCVD-ZNO TCO

PREPARED IN INDUSTRIAL KAI-M R&D REACTOR

This -general- portion of the present patent application is

-substantially- taken from US Provisional application Serial

No. 61/244,236 filed September 21, 2009 with the U.S. Patent and Trademark Office. In the following is presented a study on the optimal i-layer thickness for high efficiency amorphous silicon p-i-n solar cells deposited on doped LPCVD-ZnO. The optimization activities have led to excellent stabilized efficiencies at

remarkably low amorphous i-layer thicknesses. A light-soaked single-junction a-Si:H cell with record efficiency of 10.09% (on 1 cm²) was independently confirmed by NREL. In a table, results of measurements done on the same devices at Oerlikon Solar-Lab

Neuchatel and NREL laboratories reveal very low deviations between both characterizations. The processes developed for a-Si:H cells were applied to the preparation of mini-modules (10 x 10 cm²) .

Measurements on these light-soaked mini-modules at ESTI

laboratories of JRC have confirmed a module aperture efficiency of 9.2%.

Details concerning certain aspects of the invention can be taken from the sections II to IV following further below.

1.1 INTRODUCTION

On the path towards achieving grid parity, thin film solar modules based on amorphous silicon and icromorph tandem technologies offer a significant potential for manufacturing costs reduction. For both technologies the silicon films can be deposited in single-chamber Plasma Enhanced Chemical Vapor Deposition (PECVD) reactors like the Oerlikon Solar KAI system. Previous studies have proven that the KAI reactor can produce high-quality amorphous silicon p-i-n cells when a special p-i interface treatment [1, 2] is introduced.

Both, the manufacturing costs and the light-soaking stability of the modules can be beneficially influenced by appropriately reducing the a-Si:H absorber layer thickness. For this purpose, rough TCOs were used for enhancing the light-trapping within the device. Increased light-scattering within the TCO results in a several-fold path of light in the cell, and hence permits using a thinner absorber layer. Moreover, the light-scattering properties of the front TCO are even more important for Micromorph tandem devices due to the lower optical absorption of c-Si:H compared to a-Si:H.

TCO film properties, such as high transmission, high conductivity, excellent light-scattering capabilities (visible and near-infrared range) , and a surface morphology suited for the homogeneous growth of the thin films are mandatory for high efficient silicon thin film devices. Boron-doped zinc oxide fabricated by Low Pressure Chemical Vapor Deposition (LPCVD) has been proven to produce excellent thin- film silicon solar cells due to its outstanding light-scattering capability [3] . LPCVD-ZnO is also a low cost TCO when produced on a mass production scale. For these reasons Oerlikon Solar has decided to develop processes and production equipment for the large-area deposition of 1.4 m² LPCVD-ZnO layers [4].

This patent application presents results achieved on single-junction a-Si:H cells and mini-modules having all LPCVD-ZnO front and back electrodes . 1 . 2 EXPERIMENTAL

The presented p-i-n a-Si:H solar cells were deposited in a R&D single-chamber KAI-M system (52 x 41 cm² substrate size) . An in-situ plasma process was used to clean the KAI plasmabox reactor after each cell run.

Previous studies demonstrated that an excellent quality amorphous silicon i-layer (at 3.35 A/s) could be deposited by using an

excitation frequency of 40.68 MHz [5, 6, 7]. In this new study, the i-layer deposition rate was of 1.75 A/s. Each cell and mini-module has the in-house prepared LPCVD-ZnO as front and back contacts, the latter in combination with a white reflector (WR) [8] . The deposition parameters of the ZnO layers were optimized to obtain efficient light-scattering, high transparency and conductivity. As glass superstrate we used Schott Borofloat 33 with a thickness of 1mm. The optical characteristics of the LPCVD- ZnO layers were measured with Perkin Elmer lambda 950 spectrometer equipped with an integrating sphere.

For careful characterization, all the cells were structured by laser-patterning to a well-defined area of 1cm². Mini-modules of

10 x 10cm² dimension were realized by applying laser scribing for the monolithic series connection of the segments.

The I (V) characteristics of the cells were measured under AM 1.5 illumination (Wacom WXS-155S-L2 double-source simulator) at 25°C. The I (V) characteristics of record cells and mini-modules were independently measured by the National Renewable Laboratory (NREL) , Golden (USA) and ESTI laboratories of JRC, Ispra (Italy),

respectively. Light-soaking experiments were carried out under the following conditions: one sun light intensity (MW powered sulfur lamp), 50°C, during lOOOh and in open-circuit voltage. Samples under light- soaking test are placed on a cooling platform in order to maintain the temperatures at 50 °C. The I_sc-value of an amorphous p-i-n mini- module (10 x 10cm²) that was previously measured by the ESTI

laboratories of JRC, was used as reference for setting the light intensity on the samples' platform to a value of 1000W/m².

Furthermore, light uniformity was determined to be better than ± 5%.

The cooling platform was covered by a thermo-conductive pad, so that a good thermal contact to the samples under test can be ensured. To determine the temperatures of each zone on the platform, a-Si:H cell samples (5 x 5cm²) with a PtlOO sensor pasted on top of it were used. Between the sensor and the cell a thermo-conductive paste was employed to guarantee a good thermal contact. A few samples also included a sensor at the bottom, on the back side (shadow side) . It was experimentally found that the temperature difference between the two sensors (top and bottom) is within 1°C. The cooling platform was finally sorted in different zones depending on the measured

temperature. An ideal area with 50 °C ± 2°C was identified and used for the light-soaking experiments described in this work. After placing the samples (considered in the present work) on an ideal zone of the light-soaking platform, a PtlOO sensor was pasted on them, and the temperature was again controlled. Then the light- soaking experiment was started. To check that the conditions are maintained during the experiment, the light intensity and the temperature are controlled different times. In particular these parameters are carefully verified at the start in the middle and at the end of the light-soaking. A similar careful procedure for checking the temperature is used during the light-soaking

experiments of mini-modules. Again it was found a variation of ± 2°C around the standard value of 50 °C. I .3 RESULTS

1.3.1 LPCVD-ZNO AS FRONT TCO

The ZnO layers presented in this work (namely type-A and type-B) were modified compared to the layers used in a previous work presented at the EU PVSEC [7] . In particular, the Haze factor at

600nm was reduced from 20% to 12% for type-A, whereas for ZnO type-B it was strongly increased up to 70%. However, for the mini-module preparation only the ZnO type-A was employed so far. Both types of ZnO are polycrystalline films constituted of large grains whose extremities appear at the growing surface as pyramids (see Fig. 1) . This as-grown rough surface texture, diffuse the light, as

illustrated by the diffuse transmittance plotted Fig. 2. This effect yields to efficient light-scattering into the silicon device [9] . A known drawback for the utilization of high Haze LPCVD-ZnO as front contact is that the optimization of thin-film silicon devices is more delicate and difficult. But, the high J_sc-value potential that can provide these type of ZnO layers, justify that front ZnO type-B was also included in our study.

1.3.2 AMORPHOUS SILICON CELLS

Fig. 3 and 4 present results of an amorphous i-layer thickness series formerly obtained by the Oerlikon Solar-Lab Neuchatel in 2008 [7] and a new series of 2009, respectively. It is important to indicate a few changes applied in the preparation of 2009 cells: the deposition rate of the i-layer was reduced from 3.35A/s to 1.75A/s, new methods to increase the short-circuit current density were used (no anti-reflection, AR, coating) , and the ZnO front contact Haze was slightly reduced.

Optical properties of Ιμπι thick a-Si:H layers deposited at 3.35A/s and 1.75A/s were measured at the Institute of Physics, Academy of Sciences of the Czech Republic in Prague. Note that, the reduction of the i-layer deposition rate was not accompanied by a modification of the optical properties, as usually expected from the sole modification of the silane dilution. Both considered i-layers have an optical bandgap (Tauc's) of 1.73eV [5]. This is an important feature for achieving a-Si:H cells with a high short-circuit current density, as desired in the design of high efficiency (after light- soaking) Micromorph devices.

The main observation that can be seen by comparing Fig. 3 and 4 is a remarkable increase of the J_sc-value. This is the result of an intensive investigation on the minimization of the light intensity losses in the 400-800 nm wavelength range. Note that the increase in the J_sc-value was obtained without a decrease of the cell FF-value and V_oc-value. Another observation is a slight increase of the initial and stable open-circuit voltage (V_oc-value) for the new developed process. Looking only at Fig. 4 it can be concluded that the maximal efficiency as a function of the i-layer thickness is probably not yet reached; thinner layers as 180 nm will be further investigated.

The fundamental learning from this study is that using a LPCVD-ZnO front and back contact for a-Si:H single-junction solar cells, can provide very high stable <J_sc-value (16mA/cm²) in combination with good V_oc-value and FF-value even with a thin i-layer (180nm) .

Excellent light-trapping, thin p-i-n layers and high quality i-layer are key factors for achieving high efficiency devices.

Having gained experience in preparing high performance cells with thin i-layers the next step was to investigate devices with a commercial anti-reflection (AR) coating of the air glass-substrate interface. Moreover, we developed an in-house broad band AR.

Concerning the experiments on cells with AR a new type of LPCVD-ZnO was also tested (ZnO type-B, with Haze at 600nm of 70 %) . Whereas for cells prepared on type-A ZnO an i-layer thickness of 180 nm was chosen, for cells on type-B an absorber layer at 250 nm was

selected. On ZnO type-B we measured a record light-soaked cell efficiency of 10.03%, see Fig. 5. The record cell of Fig. 5 was sent to NREL, Golden, CO (USA) and the result of their independent characterization is presented in Fig. 6. The remarkably high stabilized efficiency of 10.09 % was confirmed. For the first time an amorphous silicon single-junction cell reached efficiency beyond the 10% barrier. To the authors' knowledge the cell represented in Fig. 6 represents the new world record for amorphous silicon p-i-n cells. Compared to the previous record (η = 9.47% obtained by IMT, Neuchatel [9, 10]) we obtained a significant improvement of 0.6% absolute.

This champion cell demonstrates that OC Oerlikon LPCVD-ZnO (front and back contact) combined with amorphous silicon deposited in the single-chamber KAI™ reactor are a very mature and highly efficient technology .

In Fig. 7 the absolute EQE of the cell as in Fig. 6 is calculated by the QE measurement of NREL normalized to the AMI .5 short-circuit current density of 17.284mA/cm² (from I (V) characteristics of NREL). To note is that the absolute EQE characteristics is remarkable high throughout the range of absorption of amorphous silicon. This result was attained after an intensive optimization of all layers and interfaces forming the cell. In particular, the excellent light- scattering potential of our LPCVD-ZnO, the high quality and standard band gap i-layer (deposited in the KAI reactor) are significant factors for obtaining such high absolute EQEs .

In Table 1, a review of different record cells prepared in the R&D Solar-Lab Neuchatel is presented. In particular, it is a comparison between the I (V) cell parameters as measured first at Oerlikon Solar-Lab Neuchatel and then shortly afterwards (within 9 days) at NREL. It is worth noting that it is possible to achieve very high efficiencies (above 10 %) with both types of analyzed ZnO (namely type-A and -B) : see cells 3497, 3473 and 3470 of Table 1.

As Table 1 shows our own AMI .5 I-V characterization is in excellent agreement with the NREL measurements . We want to mention that our

AMI .5 calibration is based on ESTI (Ispra) which seems to match very well with NREL. The strongest deviation one can notice is in the determination of the cell area for samples 3297 and 3470. This last fact results in a change of the determined efficiency, as seen in Table 1. V_oc FF Eff. Area

Sample AR Isc [mA] [mV] [%] [%] [cm²]

ZnO type-B, p-i (250nm) -n cell

3328 Oerlikon Com. 18. 070 878 65. 68 9.93 1 05

3328 NREL Com. 18. 110 875.6 65. 91 9.94 1 051

3497 Oerlikon Oerl . 18. 040 879 66. 39 10.03 1 05

3497 NREL Oerl. 18. 098 876.7 66. 58 10.09 1 047

ZnO type-A, p-i (180nm) -n cell

3473 Oerlikon Oerl. 17. 310 885 68. 61 10.01 1 05

3473 NREL Oerl. 17. 480 883.8 68. 33 10.06 1 049

3297 Oerlikon No 16. 680 881 67. 65 9.47 1 05

3297 NREL No 16. 708 878.2 67. 57 9.55 1 038

3470 Oerlikon Com. 17. 290 882 68. 15 9.90 1 05

3470 NREL Com. 17. 360 885.6 67. 85 10.06 1 036

Table 1: Review of record cells prepared and measured by Oerlikon Solar-Lab Neuchatel and independently characterized by NREL. All cells were deposited in a R&D KAI-M PECVD system, having a LPCVD-ZnO front and back contact, and being light-soaked for lOOOh under one sun at 50°C in open-circuit voltage conditions. Whereas cells 3328 and 3470 have commercial AR coating, on cells 3497 and 3473 our in- house AR (Oerl.) was applied. 1.3.3 AMORPHOUS SILICON MINI-MODULES

Findings from experiments on a cell size of 1cm² were transferred to optimize mini-modules on LPCVD-ZnO. For the mini-modules, the more mature technology on ZnO type-A was chosen. Three thicknesses of the i-layer were considered: 180, 215 and 250nm. After light-soaking (conditions as described in section 2) , the most efficient mini- modules were sent to ESTI laboratories of JRC in Ispra for

independent characterization (the best result is shown in Fig. 8) . The module aperture area was as well determined by ESTI. A

stabilized module aperture efficiency of 9.2% was certified (light- soaking done at Oerlikon Solar-Lab, see section 2) . When record cells results (Table 1: NREL) are compared to the record mini-module (Fig. 8: ESTI), a lost in efficiency of 0.86% (absolute) is

calculated. This value is reasonable and, hence, our record cells results are further confirmed. 1.4 SUMMARY AND CONCLUSIONS

The efforts in optimization of the i-layer thickness of amorphous silicon p-i-n solar cells have shown that high J_sc-values and efficiency levels can be obtained with thin i-layers (180nm) , when appropriately doped LPCVD-ZnO electrodes are used.

The high quality of the silicon layers deposited in the KAI system and the excellent properties of the in-house doped LPCVD-ZnO have proven to be very important in achieving high efficiency levels. In- house ZnO presents high transmission, high conductivity, excellent light-scattering capabilities and a surface morphology suited for the growth of high quality a-Si:H thin films. A record stabilized cell efficiency of 10,09% on 1cm² could be attained (independently confirmed by NREL) . This result presents to our knowledge the highest confirmed stabilized cell efficiency for a-Si:H single-junction solar cells. Compared to the previous champion cell also confirmed by NREL (n = 9.47% J. Meier et al., IMT, Neuchatel [9, 10]) we obtained here a significant absolute improvement in η of 0.62%. Additionally, two others cells presented an efficiency of 10.06% (NREL).

The processes developed for cells were transferred to the

preparation of mini-modules, 10 x 10cm². Measurements at ESTI laboratories of JRC in Ispra on these light-soaked mini-modules showed an aperture area efficiency of 9,2%. This high stabilized module efficiency is in alignment with the NREL cell efficiency measurements .

We point out that the mini-module results prove that the record cell can be up-scaled to modules of high performances. In a next step, Oerlikon Solar will focus on the up-scaling towards industrial substrates size of 1.4m².

The results show the great potential of Oerlikon Solar's technology for manufacturing high performance amorphous silicon and Micromorph tandem modules. II. Surface Treatment for Improvement of Electrical Properties

METHOD FOR MANUFACTURING A PHOTOVOLTAIC DEVICE WITH IMPROVED PERFORMANCE

This portion of the present patent application is -substantially- taken from US Provisional application Serial No. 61/243,646 filed September 18, 2009 with the U.S. Patent and Trademark Office and relates to improvements in the manufacturing process for thin-film, silicon-based solar cells or modules. More specifically it relates to a manufacturing process for the so called window layer in a thin film silicon solar cell and a layer structure for such thin film silicon solar cell. In particular it relates to a surface treatment for the electrode layer in a solar cell structure, said electrode layer comprising a transparent conductive oxide (TCO) .

11.1. DEFICIENCIES IN THE ART

The window (p/n-type) layers are generally made of amorphous or microcrystalline silicon (also called nanocrystalline) or any mixture thereof and their alloys with oxygen, carbon, germanium, and the like. Since the p/n-type layers are highly defective (disordered) the photogenerated electron-hole pairs recombine with a high probability; thus they do not contribute to the photocurrent of the device but do cause absorption losses. The thickness of the doped layers should for this reason be minimized in order to reduce these optical losses. However, when the doped layer thickness is reduced too much, the values of the fill-factor and the open-circuit voltage drop significantly.

11.2. SUMMARY

It is suggested herein, that prior to the growth of a window layer for a thin film silicon layer stack, a short surface treatment shall be performed resulting in a very thin, continuous or discontinuous nucleation layer or TCO surface preparation respectively. It has shown that such treatment improves the electrical properties of the later cell. II.3. DETAILED DESCRIPTION

Generally, again with reference to Fig. 9, a thin film photovoltaic device photovoltaic cell 40 comprises a substrate 41, preferably a transparent vitreous substrate, usually with a thickness of 0.4mm to 5mm, preferably 2mm to 4mm, an electrically conductive oxide 42 as contact on the substrate 41, one or more semiconductor layers 43-46, which generate an electric charge separation upon exposure to light, and a second electrically conductive contact 47. This surface treatment presented herein comprises providing a substrate 41 with a TCO contact layer 42 thereon, providing a plasma of SiH, H₂ and optionally a doping gas (e. g. trimethylboron, diborane, ...) in a gas phase concentration between 0 to 80%; preferably 0 to 20% of the concentration used for deposition of the subsequent sub layer 44 = p-doped window layer.

In the following example, said surface treatment implemented with parameters as in Table 2, prior to the p-layer, increases the efficiency of the solar cell by 2.09% (Table 3), half of this gain being achieved in the current-density (see EQE in Fig. 10) .

Table 2:

Table 3:

Jsc QE Voc FF Efficiency

(mA/cm²) (mV) (%) (%>

Standard <p> 16.81 903.03 70.67 10.73

Surface treatment + <p> 16.98 911.00 70.80 10.95

Relative gain (%) 1.02 0.88 0.18 2.09 Example for standard p-layer, here composed of 2 steps (upper part of Table 2) :

1. p μο-εί:Η - depositing a p-layer with conditions suitable for

microcrystalline silicon material

2. p a-SiC:H - depositing a p-doped layer of an alloy of amorphous silicon and carbon.

Ά proposed silicon layer stack with a surface treatment comprises 3 steps (lower part of Table 2) :

1. Surface treatment: Short exposure (5 seconds) of the TCO layer 42 to a plasma with p ic conditions without doping gas. The plasma conditions are chosen to be the same as in subsequent step 2, but without any dopant gas .

2. p yc-Si:H - Depositing a p-layer under conditions for

microcrystalline material for 65 seconds

3. p a-SiC:H - Depositing a p-doped layer of an alloy of amorphous silicon and carbon

Table 3 shows absolute values of single junction amorphous solar cells with Standard p' and inventive 'surface treatment + standard p-layer' and the relative gains.

The example described in Table 2 shall demonstrate results, but shall not be limiting. The processing temperature can be varied between 150 and 280°C without compromising the gist of the proposal. A frequency between 13.56 MHz and 82 MHz (harmonics of 13.56 MHz) can be successfully employed. For the deposition processes the ratios between SiH , H₂ and dopants (if any) CH , TMB, PH₃ are relevant and can be easily derived from Table 2. The Power applied to the process chamber will influence the desired deposition rate but will also influence the crystallinity of the layer and its stability. Since the cells in this example had the size of 1 cm², the respective power density per cm² can be easily derived from Table 2. The inventive process shall be understood as process for depositing a doped silicon layer on a TCO surface comprising a first plasma treatment process step performed under a first set of process parameters followed by a second plasma deposition process step with essentially the same (first) set of process parameters but including a dopant gas or precursor. For instance, the ρ-μο layer is deposited with a Silane concentration (SiH₄/H₂) between 0.1% and 10%, preferably between 1% and 5% with a dopant concentration (dopant/Silane) between 0.01% to 1%, preferably between 0.05% and 0.5% with a power density of 10 mW/cm² to lW/cm², preferably between 50 and 300 mW/cm2 with a pressure between 0.5 and 12 mbar. The time fraction of the first in relation to duration of first plus second process step shall be between 5 and 20% and/or, in absolute values, between 3 and 15 seconds, preferably between 5 and 10 seconds. The above parameters are typical for a KAI- PECVD reactor operated at 40 MHZ with an electrode surface of approx. 3000 cm².

This manufacturing process can be upscaled in a KAI 1200 or similar industrial reactor as commercially available from Oerlikon Solar. The TCO (ZnO) layer can be deposited on a system known as TCO 1200, also from Oerlikon Solar.

The inventive method can be applied in a beneficial manner on all kinds of thin film silicon photovoltaic layer stacks, where a doped window layer has to be deposited on a TCO front contact. The silicon photovoltaic layer stack may be single junction amorphous, tandem junction micromorph, tandem junction amorphous or alike.

III. DART - Diffusive Anti-Reflective Treatment

METHOD FOR MANUFACTURING A PHOTOVOLTAIC DEVICE BY MEANS OF IMPROVEMENTS TO THE CARRIER SUBSTRATE This portion of the present patent application is -substantially- taken from US Provisional application Serial No. 61/243,689 filed September 18, 2009 with the U.S. Patent and Trademark Office and relates to improvements in the manufacturing process for thin-film, silicon-based solar cells or modules. More specifically it relates to a treatment process for the substrate or superstrate of a thin film silicon solar cell. III.l. DEFICIENCIES IN THE ART

It is a continuous effort in the art to improve cell efficiency and at the same time reduce manufacturing cost. This balance is difficult to keep.

In order to improve a photovoltaic (PV) device's electrical conversion efficiency, as much as possible of the impinging light shall be able to be absorbed within the active silicon layers. This is achieved by 1) minimizing reflectance losses and 2) introducing light-scattering optical interfaces in the vicinity of the photovoltaic active silicon layers.

The first optical interface producing light intensity losses in the superstrate p-i-n configuration is the air/glass interface 49 (Fig. 9) . In order to prevent the typical 4% losses due to reflection of light at this interface, two main technologies are known: antireflection thin film coatings (ARC) or antireflection etching (chemical, plasma or mechanical) .

In order to obtain light-scattering at optical interfaces, commonly rough interfaces are being used, mostly the TCO/Si interfaces, which are located in Fig. 9 between references 42 (front contact) and 44 and 46 and 47 (back contact) . However, strong light-scattering requires very rough TCOs which render subsequent dense silicon growth and laser patterning of the device much more difficult.

Therefore, it is tempting to introduce rough air/glass and/or rough glass/TCO interfaces by using textured glasses. However, the use of initially textured glasses is expensive and creates problems with the essential processing step of "laser patterning".

Typically, thin-film silicon solar cells pin deposited on flat AR- coated glasses exhibit an increased photocurrent of 3 to 4% which contributes directly to increased cell efficiency. However, the cost for a commercially available dielectric AR-coating in the visible- near IR range (broadband) is quite high. Therefore, AR-coated glasses are used specifically for high-efficiency (record) cell fabrication.

The second known technology for the production of antireflection glasses, namely antireflection etching, has not been used until now in the fabrication of thin-film solar cells, to the authors' knowledge. This is amazing, since further etching of the glass can additionally result in light-scattering at the first air/glass interface. However, this effect has probably not been exploited due to the additional difficulty for laser structuring of the cells deposited on initially textured glasses. Indeed, the patterning laser beam entering the device from the glass-side experiences this light-scattering effect as well, and hence, the focused intensity needed for defined material ablation is partially lost. This makes laser scribing of cells and modules much more difficult on light- scattering glasses. As monolithic series connection is a key element of thin film silicon photovoltaics , compared to conventional wafer based technology, no much attention has so far been paid to the application of light-scattering glass substrates. Therefore, a "post-cell glass treatment" is proposed which allows to decouple the introduction of 1) optical anti-reflection and 2) light scattering at the air/glass interface. It is thus possible to tailor a Diffusive Anti-Reflective Treatment (DART) to various thin-film solar cell configurations, depending on the amount of optical diffusion wanted for maximal device performances.

111 . 2 . SUMMARY

It is suggested, to structure or texture the air/glass interface 49 after full cell or module preparation. The glass is exposed to an etching treatment that does not destroy the solar cell (or fully laser patterned module) fabricated on the other (averted) side. This etching DART treatment preferably is being performed by RIE (Reactive Ion Etching) plasma etching but is not limited to this process. Microwave plasma etching, mechanical or chemical glass etching can be used as well, depending on the glass composition. An etching DART treatment for 5-15 minutes under conditions described below has shown to provide for antireflective effects, an inventive treatment up to 2 hrs will additionally provide for increased light scattering properties.

111 . 3 . DETAILED DESCRIPTION

It has been found that a plasma treatment in a RIE reactor with a mixture of 0₂ and SF₆ (gas flux ratio of SF₆:0₂ = 5:1, pressure 30mTorr, power 600-1000W, preferably longer than 5 min) is appropriate for etching Schott Borofloat 33 glass.

In order to avoid damaging of the cell stack, protective measures need to be taken. As known in the art the silicon layer stack 43 and the rear contact layer 47 (cf. Fig. 9) and sometimes reflective layer 48 are being deposited by vacuum or near vacuum process steps such as PECVD, LPCVD, PVD. If the DART process shall be used at this stage of the manufacturing process, the sensitive layer stack has to be protected from the effects of the frontside etching process. This can be done e. g. by temporary mechanical means, such as a carrier arrangement with a clamping frame, whereat the frame provides for sealing means that allow to exposing only those portions of the front side of substrate 41 that need to be DART processed. Alternatively a removable adhesive film or a removable paint can be used. The inventors have found that surprisingly the well-known white paint reflector (feature 48) is also a sufficient protection against the exposure of the etching step. Since the diffuse white paint reflector has to be applied in a later step of the module assembly process anyway, essentially no additional means are necessary. Fore very extended DART treatment the white paint may change its properties, because of the heat generated by the treatment or/and the chemical gasses employed in the DART treatment. Hence, for long treatments and/or treatments which can generate a heating up of the sample, it is preferably to process the DART before the white paint application or to provide for sufficient cooling in order to avoid detrimental effects.

Figure 11 shows the measured total reflection coefficient of a series of glass/TCO/a-Si : H pin/TCO structures. At near-specular light incidence, there are 7-6% reflection losses at the air/plain glass (Schott Boroflaot33) interface. The total reflection is decreased to RtotARcgiass^¾3% by using a typical commercial (Schott) broad-band AR-coating in the range 400-650 nm. This corresponds to a decreased reflection R_totfiatgiass-RtotARcgiass^=:4% . An inventive Diffusive Anti-Reflection Treatment (DART) of at least 15 min allows obtaining similar R_tot as the expensive AR-coating. The corresponding gain in the light intensity entering the device is completely transferred in a relative gain of 3.5-4% in the photocurrent (J_sc) of the thin film device . It can be noted in Figure 11 that the AR-coating reflection losses exhibit some wavelength-dependency (interference fringes) in the range between 400-650nm, which is different from the flat glass configuration. This is due to the fact that the ARC effect relies on interferences within dielectric thin-film stacks. However, the amplitude of the fringes is visibly decreased for the DART glasses.

This is experimental evidence that some optical diffusion effect must occur at the air/DART interface. This is seen by observation of the treated glass surface morphology whose roughness and morphology evolves with etching times (see Figure 11) . Therefore, the DART treatment can be tailored to produce anti-reflection effect only (short treatment time) or anti-reflection + light-scattering effects (longer glass treatment time) .

Figures 12 and 13 show a scanning electron micrograph of the treated surface of a Schott Borofloat33 glass etched with varying times (RIE reactor with a mixture of 0₂ and SF₆ (glass flux ratio SF₆/0₂ = 1.67), pressure 5 mTorr and discharge power of 1000W) Fig. 12: 5 minutes plasma treatment, Fig. 13: 120 min plasma treatment.

Figure 14 shows the External Quantum Efficiency EQE curve measured for a tandem micromorph cell without (no AR, lower curves) and with DART treatment (120 min, upper curves) . A gain in J_sc superior to the expected 4% in the top a-Si:H cell and in the microcrystalline bottom cell indicates a contribution to increased light-trapping from the DART treatment .

This is an advantage, by which the absorption of incoming light in the silicon layers can be further maximized. Therefore, the diffuse component of the DART can be tailored to the front TCO optical scattering characteristics and to the device thickness (tandem- or single-junction) . For example, if the DART of the glass increases the light-scattering of long-wavelength light (>700nm) , then the microcrystalline bottom cell can be kept thinner for current matching with the top cell.

This effect can be obtained with longer etching times of the glass. It allows for an increased light-scattering in the long wavelength range, a property difficult to obtain from the as-grown textured ZnO developed for a-Si:H cells.

Typically, the optimum etching process of the glass for a micromorph solar cell deposited on a rather flat ZnO is longer, as it is needed to have increased light -scattering for the microcrystalline silicon bottom cell. The optimum etching time will depend as-well on the presence of an intermediate reflector within the tandem micromorph. Finally, it has been observed that special combination of DART with a Micromorph solar cell is not limited to an increased J_sc, but can lead as well to an increased V_oc and FF.

All these examples indicate that DART allows an optimized tailoring for maximum efficiency of almost any combination of TCO/a-Si : H/ c- Si:H/TCO layer thicknesses combinations.

The application of the above-proposed, which has been used for very high efficiency test cells, can also be applied to industrial thin- film a-Si:H silicon modules, if its cost is not prohibitive compared to an expected 3.5-4% module power increase. The angular dependency of the reflection coefficient is very small; i.e. the reflection losses are reduced even for light incidence angles far from near- specular. Thus, not only higher efficiencies can be achieved by DART, but as well the yearly energy production (kWh/kW_p) of modules in real outdoor applications will be positively affected due to the weak angular dependency of the DART characteristics. Known Broadband AR-thin film coatings can also be optimized for minimal angular dependency, but this is an additional, constraining requirement for the optimization of such a coating.

This has the potential for an increased micromorph tandem solar cell efficiency and an enhanced light-trapping capability for a further reduction of the Si absorber (until now, 10% gain in photocurrent of the bottom cell, in some cases increased Voc and FF) by optimal combination of front glass /TCO / Si/TCO device system. It is being understood, that the values given above are depending on many parameters and that a general recipe cannot easily be given. The exposure time to an inventive DART treatment depends on the capabilities of the etching machine, the type of glass (thickness, chemical composition) , the used front and back contact (in particular their Haze factor) , the technology (aSi or Micromorph) , for each technology the absorber layer thickness used for the cell, use or not of a intermediate reflector, and - last but not least whether only a antireflective effect shall be attained (short etching) or a diffusion PLUS antireflection (long etching time) . The man skilled in the art, will, following the basic teaching above, adopt the necessary changes to comparable process environments.

IV. Controlled and Accelerated Oxidation before Back Contact TCO Deposition

METHOD FOR MANUFACTURING THIN FILM SILICON PHOTOVOLTAIC DEVICE BY MEANS OF A FAST OXYDIZING TREATMENT TO IMPROVE YIELD AND ELECTRICAL

PERFORMANCE

This portion of the present patent application is -substantially- taken from US Provisional application Serial No. 61/243,628 filed September 18, 2009 with the U.S. Patent and Trademark Office and relates to a method of fabricating thin film solar cells. It focuses on a treatment allowing to reducing the leakage current of such thin film solar cells. In particular it relates to an oxidizing surface treatment of a thin film silicon layer or multilayer structure forming part of a thin film solar cell by oxidation of the surface of the last deposited silicon.

For evaluation of the yield, the open-circuit voltage V_oc of the cells is measured (after back contact deposition and cell patterning) under a low light intensity (intensity lower than 10% of AMI.5). Under these measurement conditions, cells exhibiting an open-circuit voltage lower than 600mV are considered as (partially) shunted and will exhibit poor electrical performances under AMI .5 full illumination. Figure 15 shows the standard AMI .5 I (V) curves of three contacted test cells exhibiting a low-illumination Voc below 600 mV (i.e. so-called partially shunted) and the I (V) curve of one test cell of the same pin PECVD run oxidized before back contact deposition (i.e. passivated device according to what has been propsed above) .

There are several possible origins to shunts in thin-film silicon solar cells. For example, particles on the front contact are highly detrimental for high yield. But if particles are the cause of the shunted behaviour of the device, their effect can be cancelled notably by using an intrinsically started back contact as described in publication WO 2009/077605.

Another cause of low yield and poor electrical performances in thin- film silicon solar cells is the presence of low-density, low-quality silicon material observed in devices fabricated on rough substrates, see Figure 16. The detrimental effect of such defective zones in thin-film silicon deposited on very rough substrates has been described in Sakai et al, J. of Non-Cryst. Solids 115 (1989) p.198- 200 for a-Si:H cells and in M. Python et al . Solar Energy Materials and Solar Cells 93, Issue 10 (2009) p.1714-1720 for microcrystalline silicon solar cells.

Figure 16 shows a Transmission electron micrograph of a cross- section of a a-Si:H pin solar cell deposited by PECVD on a rough glass/TCO superstrate (bottom of the micrograph) . The circled zone shows the presence of low-density, porous silicon material. The TEM micrograph is the projected view of a 2D "leaking boundary" present in the 3D layer stack. Such boundaries are observed over recessed areas of the substrate. Such low density material deteriorates the overall device electrical performances and is thus suspected to be highly electronically defective.

It is known that high yield is difficult to obtain for very thin pin devices (i-layer thickness below 200 nm, p-layer thickness below 10 nm) or on pin devices deposited on highly textured front contacts (very rough TCOs or glass/TCO superstrates with surfaces possessing acute recessing angles) . In these cases, cells are partially or totally shunted if the back contact is directly deposited after PECVD n-layer deposition. However, we have observed that storage of the incomplete device (i.e. after n-layer PECVD deposition and before back contact deposition) in air during a period of a few days increases the yield and the conversion efficiency of the (later) complete device.

These defective boundaries have been identified as current leaking boundaries. These low density defective material zones can either occur during layer growth within the PECVD reactor or during layer unloading (from deposition temperature (~ 200 °C) to ambient temperatures) out of the PECVD reactor (weak points for mechanical stress relaxation) . Their detrimental impact on the device electrical properties is to increase the dark leakage current proportionally to their linear density as measured in cross-section views (for microcrystalline silicon: ref. Martin Python et al . Solar Energy Materials and Solar Cells Volume 93, Issue 10, October 2009, Pages 1714-1720) , according to the equivalent electrical circuit sketched in Figure 17. Figure 17 shows a simple equivalent electrical circuit for a thin-film silicon solar cell on a rough substrate exhibiting leaking boundaries. These leaking boundaries are sketched as a second diode in this representation with a "high dark current J diode2".

Figure 18 shows the effect of the leaking boundaries density (called "cracks" in this example) on the dark current density J₀₂ of microcrystalline silicon solar cells. From M. Python, PhD dissertation, Institute of Microtechnology, University of Neuchatel, 2009. Original Caption: Relationship between the J₀₂ and the crack density, for p-i-n configuration, estimated by TEM micrographs, in co-deposited mc-Si:H cells on varying substrates. Low J₀₂ and low crack-density is observed in high efficiency solar cells.

For given PECVD deposition conditions, the linear density of defective boundaries as observed in a section view depends on the superstrate morphology; and for a given superstrate morphology, PECVD deposition conditions can be found which decrease the density of these defective, leaking boundaries. What is described below allows to deactivate these leaking boundaries in such a way as to notably improve the device electrical properties and the yield. IV.1. DEFICIENCIES IN THE ART

The effect of storage in air after the n-layer deposition for increased yield occurs very slowly. About 10 hours of storage in air are needed for high yield on rather flat, standard front contacts, whereas one week storage is needed for high yield on highly textured TCOs or for critical, thin pin devices.

IV.2. SUMMARY

It is suggested, to provide for a controlled and accelerated oxidation of the silicon layer stack of a thin film solar cell before deposition of a back contact TCO.

In a first embodiment a respective silicon surface is exposed to an atmosphere enriched with H₂0 and/or 30% H₂0₂ for about 1 hour, preferably 1-2 hours at a temperature of 100°C. Increasing the temperature will allow to reduce exposure time. In a second embodiment the silicon surface shall be exposed to ozone at room temperature for about 1 hour. In a variation of this embodiment temperature is set to about 100°C to accelerate the oxidation process with ozone. An exposition to this environment between 5 to 15 minutes has been found to be effective. In a further variation the surrounding pressure has been set to 0.5mbar for 15 minutes. Higher ozone concentration allows further reducing the treatment duration. In a third embodiment a soft oxidizing plasma (e.g.: C₂F₆, C0₂, 0₂, SF₆) after the n-layer deposition is being used. Preferably, the soft oxygen plasma (power 100 (on 3000 cm² electrode area) , temperature 200 °C) shall be applied for a few seconds, preferably longer than 10s. A treatment more than one minute has been found not to be beneficial. Changing the effective power and substrate temperature will allow to vary the exposure time without leaving the scope of the proposition.

IV.3. DETAILED DESCRIPTION

What is described described herein refers to treatments after the n- layer deposition, but before application of a back contact, which are faster than the air-storage process and allowing to obtain sufficient yield even for thin pin devices (1/3 thinner p-layers, i- layer thickness<200nm) or for standard thickness pin (i-layer thickness >200nm) deposited on very rough superstrates (e.g. ZnO R S>100nm) . After the oxidation treatment, the electrical performances of the device are improved (mostly open-circuit voltage and Fill-Factor, as seen in Figure 15) These treatments comprise a combination of oxidizing chemical agents with temperature and pressure that allows for an oxidation process occurring otherwise very slowly during ambient air exposure. Evidently, in a respective embodiment all these treatments could also be plasma assisted.

Herein, the oxidation reaction is understood as in classical chemistry i.e. as a typical redox reaction in which there is a transfer of electron from one substance to another. The oxidizing agent is here the substance which accepts electrons. Thus the oxidizing agent is not limited to oxygen. For example fluorine, sulphur, chlorine, nitrogen etc.. are chemical oxidizing agents of silicon, even if some of them are not preferentially used because of their detrimental effect as doping elements in silicon.

Several possibilities to speed up the oxidation process have been investigated. The typical faster treatments need less than one hour, preferably less or equal to 5 minutes.

For these embodiments, standard state of the art a-Si:H pin layer stacks (i-layer thickness 240 nm, initial efficiency >11%) have been used. Several oxidation procedures have been evaluated.

After n-layer deposition, it has been observed that

1) Exposure of the pin device to humid air ("Becher" glass containing deionised H₂0 or H₂0₂, with a concentration of 30%) at 100°C in an oven during 1 hr , preferably 2 hrs allows to increase the yield on critical TCOs from 0 to approx. 80 % and the treated cells exhibit good I (V) characteristics. 2) Exposure of the pin device to ozone (0₃) obtained from air provided by a commercially available ozone generator during lhr or more at room temperature (and 1 atm) in an oven allows to obtain high yield and good I (V) characteristics on highly textured TCO. A temperature increase up to 100°C accelerates the oxidation process with ozone. There are combinations of temperature and exposure times which give an optimum yield depending on the front TCO roughness/texture: Ozone treatment in an oven at 100°C during 5 min on a standard ZnO (called "flat" in the caption of Figure 19) improves notably the yield, whereas a treatment of preferably 15min is needed for high yield on a highly textured ZnO (called "rough" in caption of Figure 16) . Longer exposure times may not be so efficient. Exposure to 0₃ during 15 min with sample temperature of 100°C or more and vacuum of 0.5 mbar (such as in the ZnO-LPCVD equipment, before back contact deposition) is another possibility for ozone oxidation in-between n- layer and back contact deposition. Oxidation times even shorter than 5min are possible by using a higher ozone concentration in the oxidation chamber (for example by using pure Oxygen for ozone generation) .

3) An alternative to ozone exposure is to apply a soft oxidizing plasma (e.g.: C₂F₆, C0₂, 0₂, SF₆) after the n-layer deposition. Preferably, in a commercial PECVD system like a Oerlikon Solar KAI a soft oxygen plasma (power 300 mW/cm2, temperature 200 °C) during a few seconds, (preferably longer than 10s) results in high yield on critical TCO and improved cell performances on standard ZnO.

Figure 19 shows the effect of ozone exposure time on the yield of pin devices with two different TCO front types. Some improvement occurs already after 5min, the preferred duration is around 15 min.

The proposed fast oxidation process gives an increased conversion efficiency of cells fabricated on standard TCOs . Moreover, it allows to use a larger variety of front TCO/glass combinations in particular those with increased roughness and increased light scattering properties.

Very thin (i-layer thickness lower than lOOnm) a-Si:H pin's with good I (V) characteristics can be successfully realized and finally can be implemented in a-Si:H pin-pin tandem cells, which opens a new potential for stabilized high efficiency a-Si:H based cells and rough TCOs.

Such oxidizing treatments could be as well be applied for deactivation of leaking boundaries in microcrystalline single junction cells and in micromorph cells. V. Brief Description of the Drawings

Above, the invention has been described in detail by means of examples and the included drawings. The figures show:

Figure 1: Scanning Electron Microscope (SEM) micrographs of the surface of LPCVD-ZnO type-A.

Figure 2: Total transmittance (upper graph, measured without index matching liquid) and diffuse transmittance (lower graph) of

LPCVD-ZnO type-A, deposited on glass (Schott Borofloat 33 with a thickness of 1mm) .

Figure 3: 2008 results; V_oc, J_sc, FF-values and efficiency as a function of the i-layer thickness in the initial and light-soaked state [7] . LPCVD-ZnO is used as front TCO (Haze at 600nm is 20%) . The i-layer thickness is varied form 180 to 400nm, and the

deposition rate is 3.35A/s. For an improved statistics, 4 to 7 cells are considered (for each thickness) . Figure 4: 2009 results; V_oc, J_sc, FF-values and efficiency as a function of the i-layer thickness in the initial and light-soaked state. LPCVD-ZnO type-A is used as front TCO (Haze at 600nm is 12%) . The i-layer is varied form 180 to 350 nm, and the deposition rate is 1.75A/s. For an improved statistics, 4 to 7 cells are considered (for each thickness) .

Figure 5: Record single-junction a-Si:H light-soaked cell prepared and measured by Oerlikon Solar-Lab Neuchatel . Figure 6: I (V) of the record stabilized efficiency (10.09 %) obtained for a-Si:H single-junction solar cell (NREL confirmation) . The cell was deposited in a R&D KAI™-M system (52 x 41cm² substrate size) . The used superstrate is a 1mm Schott Borofloat 33 glass on which LPCVD-ZnO with high Haze factor (ZnO type-B) was deposited. On this cell our in-house AR was applied.

Figure 7: Absolute External Quantum Efficiency (abs EQE) deduced from the relative QE of NREL and the short-circuit current density under AMI .5 measured at NREL for the record cell 3497. This cell of 250nm i-layer thickness was previously light-soaked in open-circuit voltage conditions . Figure 8: I (V) curves of the best p-i(180 nm) -n a-Si:H (light- soaked) lOxlOcm² mini-module on LPCVD-ZnO, measured by ESTI

laboratories of JRC in Ispra.

Figure 9: A basic, simple photovoltaic cell.

Figure 10: External Quantum Efficiency (EQE) data.

Figure 11: Measured total reflection coefficient of a series of glass/TCO/a-Si:H pin/TCO structures.

Figure 12: Scanning electron micrograph of the treated surface of a Schott Borofloat33 glass, etched (5 minutes plasma treatment) .

Figure 13: Scanning electron micrograph of the treated surface of a Schott Borofloat33 glass, etched (120 minutes plasma treatment) .

Figure 14: External Quantum Efficiency (EQE) curve measured for a tandem micromorph cell without (no AR, lower curves) and with DART treatment (120 min, upper curves) .

Figure 15: Standard AMI .5 I (V) curves of three contacted test cells.

Figure 16: Transmission electron micrograph of a cross-section of a a-Si:H pin solar cell deposited by PECVD.

Figure 17: Sketch of a simple equivalent electrical circuit for a thin-film silicon solar cell on a rough substrate exhibiting leaking boundaries . Figure 18 shows the effect of the leaking boundaries density on the dark current density J₀2 of macrocrystalline silicon solar cells. Figure 19 shows the effect of ozone exposure time on the yield of pin devices with two different TCO front types.

The above-described embodiments are meant as examples and shall not confine the invention.

VI . REFERENCES

[1] U. Kroll et al . , Thin Solid Films 451-452 (2004), pp. 525-530.

[2] U. Kroll et al . , Proc 19th EU PVSEC (Paris 2004), paper 3A0.8.1.

[3] J. Meier, J. Spitznagel, U. Kroll, C. Bucher,

S. Fay, T. Moriarty, A. Shah, Thin Solid Films 451-452 (2004) p.

518.

[4] O. Kluth et al, Proc 20th EU PVSEC (Barcelona 2005), paper

3DV.3.38.

[5] U. Kroll et al . , Proc. 23rd EU PVSEC (Milan 2007), paper

3C0.1.2, p.1795-1800.

[6] S. Benagli et al . , Proc. 21st EU PVSEC (Dresden 2006), paper

3DV.3.42, p.1719-1723.

[7] S. Benagli et al . , Proc. 24th EU PVSEC (Valencia 2008), paper

3AV.2.23, p. 2414-2418.

[8] J. Meier et al, Proc 19th EU PVSEC (Paris 2004), paper 3BP.1.2 .

[9] J. Meier et al . , Proc. 3rd CPEC (Osaka 2003) session S2.

[10] M. A. Green, Keith Emery, Yoshihiro Hishikawa and Wilhelm Warta,

Progress in Photovoltaics : Research and Applications 2009;

17:320-326.

Claims

PATENT CLAIMS

1. Method for manufacturing an amorphous silicon p-i-n solar cell, said cell comprising an anti-reflection coating and doped LPCVD ZnO front and back contacts, wherein the doped LPCVD ZnO front and back contacts are polycrystalline films constituted of large grains whose extremities appear at the growing surface as pyramids, said method comprising

— depositing said front contact by means of LPCVD;

— depositing the silicon layers of said p-i-n solar cell by means of plasma enhanced chemical vapor deposition;

— depositing said back contact by means of LPCVD;

— providing said anti-reflection coating.

2. The method according to claim 1, wherein at least one of the following applies:

— the method comprises using as a superstrate a 1 mm Schott

Borofloat 33 glass on which LPCVD-ZnO with Haze factor of 70 % at 600 nm was deposited;

— the cell has a stabilized cell efficiency beyond the 10%

barrier, in particular a stabilized cell efficiency of 10.09%;

— the method comprises depositing the silicon films in a single- chamber Plasma Enhanced Chemical Vapor Deposition reactor, in particular in an Oerlikon Solar KAI system; — the method comprises combining said back contact with a white reflector;

— the method comprises depositing the i-layer at a deposition rate of 1.75 A/s; — the i-layer having an optical bandgap of 1.73 eV;

— the i-layer having a thickness of 250 nm;

— the method comprises structuring the cell by laser-patterning.

3. The method according to claim 1 or claim 2, the amorphous silicon p-i-n cell comprising a substrate/ p-i-n junction

configuration having a glass/air interface having antireflection ability due to said anti-reflection coating, the method comprising providing a glass- substrate/p-i-n- junction configuration with a glass/air interface and then DART-etching the glass surface for said air/glass interface to provide for said antireflection (AR) and for a desired light scattering ability (D) .

4. The method of claim 3, wherein etching is performed during a first time span to provide for antireflection abilty (AR) and performing said etching additionally during a second time span selected to additionally (AR+D) provide for an increased amount of light scattering.

5. The method of claim 3 or 4, comprising at least one of the following features:

— the glass-substrate/p-i-n- junction configuration includes a first electrode, one semiconductor thin-film p-i-n or n-i-p junction, and a second electrode, which are successively stacked on the substrate, in particular said LPCVD ZnO front contact, said said silicon layers and said LPCVD ZnO back contact

successively stacked on the substrate;

— the glass-substrate/p-i-n junction configuration includes a

transparent substrate of glass with a layer of a transparent conductive oxide deposited thereon, in particular with said LPCVD ZnO front contact layer deposited thereon;

— Antireflex and scattering ability is established by etching after providing said glass- substrate/p-i-n- junction configuration.

6. The method of one of claims 4 and 5, further comprising the step of performing laser patterning through said glass/air interface only before performing said etching during said second time span.

7. The method of one of claims 3 to 6, wherein said etching is performed by Reactive Ion Etching.

8. The method of one of claims 3 to 8, comprising the step of protecting said p-i-n junction configuration, and in particular said silicon layers, from said etching said glass surface by

— temporary mechanical means, preferably a carrier arrangement with a clamping frame wherein the frame provides for sealing means that allow to exposing only said glass surface that needs to be etched; or by

—a removable adhesive film or a removable paint, preferably white reflector paint.

9. The method according to one of the preceding claims, wherein the amorphous silicon p-i-n solar cell comprises:

— a substrate and

— a first electrode, in particular said LPCVD ZnO front contact, one semiconductor thin-film p-i-n or n-i-p junction, in particular said silicon layers, and a second electrode, in particular said LPCVD ZnO back contact, successively stacked on said substrate;

wherein the method comprises

— Providing said substrate and said first electrode and said at least one junction stacked on said substrate,

— Subjecting the surface of said junction to a controlled oxidation so as to deactivate leaking boundaries through said at least one junction, Applying directly or indirectly above said surface having been subjected to said oxidation said second electrode.

10. The method of claim 9, wherein said amorphous silicon p-i-n solar cell has at least one of the following features:

— Is a thin-film solar cell,

— Is a thin-film silicon solar cell,

— Said surface is a surface of the last deposited thin film silicon layer,

— Said substrate is transparent, preferably of glass, in particular of Schott Borofloat 33 glass,

— Said first electrode comprises or is of a transparent conductive oxide deposited on said substrate, in particular is said doped LPCVD ZnO front contact,

— Said at least one junction comprises hydrogenated microcrystalline or amorphous silicon or a combination thereof,

— The thickness of the i-layer of said junction is below 200nm and the thickness of the p layer is below lOnm and the junction is preferably a p-i-n junction,

—Said surface is the surface of an n-layer, preferably PECVD deposited,

— Said second electrode is deposited at a temperature of about

200°C,

— Said first electrode comprises or is of a transparent conductive oxide deposited on said substrate and is preferably textured on its surface whereupon said at least one junction is applied, said conductive oxide preferably being ZnO textured to a roughness of more than lOOnm RMS.

11. The method of claim 9 or 10, wherein said surface

— is exposed to an atmosphere enriched with H₂0 and/or 30% H₂0₂ preferably for 1 h to 2 h at a temperature of 100°C, or

— is exposed to ozone at room temperature for about 1 hour, or

— is exposed to ozone at a temperature of about 100 °C, preferably for 5 min. to 15 min, or

— is exposed to ozone at a pressure of 0.5 mbar for 15 min, or — is exposed to an oxidizing plasma preferably in a C₂F₆, C0₂, 0₂ or

SF₆ containing atmosphere, preferably at a power of 300 mW/cm² electrode area, and preferably at a temperature of 200°C, preferably longer than 10 s but not longer than one minute, said surface being preferably the surface of an n-layer.

12. The method of one of claims 9 to 11, wherein said oxidation is performed with an oxidizing agent which accepts electrons being at least one of oxygen, fluorine, sulphur, chlorine, nitrogen.

13. The method of one of claims 9 to 12, wherein said exposure is performed for at most 5 min.

14. The method according to one of the preceding claims, wherein the amorphous silicon p-i-n solar cell comprises:

— a substrate,

— upon said substrate a first electrode layer comprising a transparent, conductive oxide, in particular said LPCVD ZnO front contact,

— upon said first electrode layer, stacked layers comprising a positively doped semiconductor layer, an intrinsic semiconductor layer and a negatively doped semiconductor layer as well as a second electrode layer, in particular wherein these stacked semiconductor layers are said silicon layers of said p-i-n solar cell and said second electrode layer in particular is said LPCVD ZnO back contact,

said method comprising the steps of

— providing said substrate,

— depositing upon said substrate said first electrode layer comprising said transparent, conductive oxide and having a surface,

— treating said surface by a first vacuum treatment process during a first time span,

— depositing upon said surface treated by said first vacuum

treatment process one of said positively and of said negatively doped layers by a second vacuum process performed during a second time span in a process atmosphere comprising a gaseous dopant, — performing said first vacuum treatment process in a process atmosphere comprising a gaseous dopant with a different amount than comprised in said atmosphere of said second vacuum process but otherwise performing said first vacuum treatment process equally to said second vacuum process and selecting said first time span shorter than said second time span.

15. The method of claim 14, comprising performing said first vacuum treatment process as a vacuum plasma treatment process in an atmosphere containing SiH and H₂ and a gaseous dopant in a concentration between 0% and 80% of the concentration of a gaseous dopant present in the atmosphere of said second vacuum process, preferably between 0% and 20%, thereby preferably depositing by said second vacuum process said positively doped semiconductor layer.

16. The method of claim 14, wherein said second vacuum process is a vacuum plasma process.

17. The method of claim 14, wherein said first time span is selected to be between 5% and 20% of the sum of the first and second time spans, and wherein preferably said second vacuum process is a vacuum plasma process, and there is valid at least one of:

— said one doped semiconductor layer deposited by said second vacuum process is said positively doped semiconductor layer,

— said one doped semiconductor layer is deposited in an atmosphere comprising a SiH₄ to H₂ concentration of 0.1% to 10%, preferably of 1% to 5%,

— said one doped semiconductor layer is deposited in an atmosphere comprising SiH₄ and the dopant to SiH₄ concentration in said atmosphere is 0.1% to 10%, preferably 0.05% to 0.5%,

— said one doped semiconductor layer is deposited at a power density of 10 mW/cm² to 1 W/cm² preferably between 50 mW/cm² and 300 mW/cm²,

— said one doped semiconductor layer is deposited at a total

pressure of 0.5 mbar to 12 mbar,

— said one doped semiconductor layer is deposited at a process temperature between 1500° C and 2800° C, — said one doped semiconductor layer is deposited with an Rf power at a frequency of 13.56 MHz to 82 MHz.

18. Amorphous silicon p-i-n solar cell, comprising an anti- reflection coating, a p-i-n junction of silicon layers, and doped LPCVD ZnO front and back contacts, wherein the doped LPCVD ZnO front and back contacts are polycrystalline films constituted of large grains whose extremities appear at the growing surface as pyramids.

19. The amorphous silicon p-i-n solar cell according to claim 18, wherein at least one of the following applies:

— the amorphous silicon p-i-n solar cell comprises as a

superstrate a 1 mm Schott Borofloat 33 glass on which LPCVD-ZnO with Haze factor of 70 % at 600 ran was deposited; — the cell has a stabilized cell efficiency the 10% barrier, in particular a stabilized cell efficiency of 10.09 %;

— the silicon films are deposited in a single-chamber Plasma

Enhanced Chemical Vapor Deposition reactor, in particular in a Oerlikon Solar KAI system; — said back contact is combined with a white reflector;

— the i-layer is deposited at a deposition rate of 1.75 A/s;

— the i-layer has an optical bandgap of 1.73 eV;

— the i-layer has a thickness of 250 nm;

— the cell is structured by laser-patterning.