WO2011032879A2 - Method for manufacturing a thin-film, silicon-based solar cell - Google Patents

Method for manufacturing a thin-film, silicon-based solar cell Download PDF

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WO2011032879A2
WO2011032879A2 PCT/EP2010/063208 EP2010063208W WO2011032879A2 WO 2011032879 A2 WO2011032879 A2 WO 2011032879A2 EP 2010063208 W EP2010063208 W EP 2010063208W WO 2011032879 A2 WO2011032879 A2 WO 2011032879A2
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vacuum
layer
semiconductor layer
atmosphere
doped semiconductor
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French (fr)
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WO2011032879A3 (en
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Julien Bailat
Evelyne Vallat-Sauvain
Daniel Borrello
Stefano Benagli
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Oerlikon Solar Ag, Truebbach
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Priority to CN2010800415724A priority Critical patent/CN102844891A/en
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Publication of WO2011032879A3 publication Critical patent/WO2011032879A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
    • H01L31/1824—Special manufacturing methods for microcrystalline Si, uc-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/545—Microcrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to improvements in the manufacturing process for thin-film, silicon-based solar cells or modules. More specifically the invention relates to a manufacturing process for the so called window layer in a thin film silicon solar cell and a layer structure for such thin film silicon solar cell. In particular the present invention relates to a surface treatment for the electrode layer in a solar cell structure, said electrode layer comprising a transparent conductive oxide (TCO) .
  • TCO transparent conductive oxide
  • Photovoltaic devices, photoelectric conversion devices or solar cells are devices which convert light, especially sunlight into direct current (DC) electrical power.
  • DC direct current
  • thin film solar cells are being of interest since they allow using glass, glass ceramics or other rigid or flexible substrates as a base material (substrate) instead of crystalline or polycrystalline silicon.
  • the solar cell structure i. e. the layer sequence responsible for or capable of the photovoltaic effect is being deposited in thin layers. This deposition may take place under atmospheric or vacuum conditions. Deposition techniques are widely known in the art, such as PVD, CVD, PECVD, APCVD,... all being used in semiconductor technology.
  • a thin-film solar cell generally includes a first electrode, one or more semiconductor thin-film p-i-n or n-i-p junctions, and a second electrode, which are successively stacked on a substrate.
  • Each p-i-n junction or thin-film photoelectric conversion unit includes an intrinsic or i-type layer sandwiched between a positively doped or p- type layer and a negatively doped or n-type layer.
  • the intrinsic semiconductor layer occupies the most part of the thickness of the thin-film p-i-n junction. Photoelectric conversion occurs primarily in this i-type layer; hence it is also called active or absorber layer.
  • a-Si amorphous
  • yc-Si microcrystalline
  • the doped layers in a p-i-n junction are also often referred to as window layers. Since the light absorbed by the doped p/n layers is lost for the active layer, highly transparent window layers are desired to obtain high current-densities (J sc ) .
  • the window layers are instrumental in establishing the electric field in the semiconductor junction constituting the solar cell, which helps collecting the photo-generated charge carriers and obtain high V oc and FF values.
  • the contact between the front transparent conductive oxide (TCO) and the window layer should be ohmic with a low resistivity, in order to obtain good FF values.
  • Prior Art Fig. 1 shows a basic, simple photovoltaic cell 40 comprising a transparent substrate 41, e. g. glass with a layer of a transparent conductive oxide (TCO) 42 deposited thereon.
  • TCO transparent conductive oxide
  • This layer is also called front contact and acts as first electrode for the photo- voltaic element.
  • the next layer 43 acts as the active photovoltaic layer and comprises three "sub-layers" forming a p-i-n junction.
  • Said layer 43 comprises hydrogenated microcrystalline (also called nanocrystalline) or amorphous silicon or a combination thereof.
  • Sublayer 44 (adjacent to TCO front contact 42) is positively doped, the adjacent sub-layer 45 is intrinsic, and the final sub-layer 46 is negatively doped.
  • the layer sequence p- i-n as described can be inverted to n-i-p, then layer 44 is identified as n-layer, layer 45 again as intrinsic, layer 46 as p-layer.
  • the cell includes a rear contact layer 47 (also called back contact) which may be made of zinc oxide, tin oxide or ITO and a re- flective layer 48.
  • a metallic back contact may be realized, which can combine the physical properties of back reflector 48 and back contact 47.
  • arrows indicate impinging light. It is generally understood that when light, for example, solar radiation, impinges on a photoelectric device electron-hole pairs are generated in the i-layer.
  • the holes from the generated pair are directed towards the p-region and the electrons towards the n-region.
  • the contacts are generally directly or indirectly in contact with the p- and n-regions. Current will flow through an external circuit connecting these contacts as long as light continues to generate electron-hole pairs.
  • the window (p/n-type) layers are generally made of amorphous or microcrystalline silicon (also called nanocrystalline) or any mixture thereof and their alloys with oxygen, carbon, germanium, and the like. Since the p/n-type layers are highly defective (disor- dered) the photogenerated electron-hole pairs recombine with a high probability; thus they do not contribute to the photocurrent of the device but do cause absorption losses. The thickness of the doped layers should for this reason be minimized in order to reduce these optical losses. However, when the doped layer thickness is reduced too much, the values of the fill-factor and the open-circuit voltage drop significantly.
  • a short surface treatment shall be performed resulting in a very thin, continuous or discontinuous nucleation layer or TCO surface preparation respectively. It has shown that such treatment improves the electrical properties of the later cell.
  • the present invention is directed on a method of manufacturing a thin-film, silicon-based solar cell, comprising:
  • a first electrode layer comprising a transparent, conductive oxide
  • the first electrode layer comprising the transparent, conductive oxide and having a surface
  • first vacuum treatment process one of the positively and of said negatively doped semiconductor layers by a second vacuum process performed during a second time span in a process atmosphere comprising a gaseous dopant
  • the method according to the present invention comprises performing the first vacuum treatment process as a vacuum plasma treatment process in an atmosphere containing SiH 4 and H 2 and a gaseous dopant in a concentration between 0% and 80% of the concentration of a gaseous dopant present in the atmosphere of the second vacuum process, preferably between 0% and 20%, thereby preferably depositing by the second vacuum process the positively doped semiconductor layer.
  • the first first vacuum treatment process is a vacuum plasma treatment process in an atmosphere containing SiH 4 and H 2 the same prevails for the second vacuum process.
  • the method according to the present invention comprises depositing by the second vacuum process a positively doped semiconductor layer of hydrogenated silicon, thereby performing the second vacuum process for microcrystal- line material deposition and performing the first vacuum treatment process in an atmosphere without gaseous dopant and preferably depositing on the positively doped semiconductor layer of hydrogenated silicon an amorphous, positively doped layer of an alloy of silicon and carbon in a process atmosphere comprising hydrogenated silicon carbide wherein further preferably said second vacuum process is a vacuum plasma process - and thus also the first vacuum treatment process.
  • the second vacuum process (and thus also the first vacuum treatment process) is a vacuum plasma process.
  • the first time span is selected to be between 5% and 20% of the sum of the first and of the second time spans and wherein preferably the second vacuum process is a vacuum plasma process and there is valid at least one of:
  • the one doped layer deposited by said second vacuum process is the positively doped semiconductor layer
  • the one doped semiconductor layer is deposited in an atmosphere comprising a SiH 4 to H 2 concentration of 0.1% to 10%, preferably of 1% to 5%;
  • the one doped semiconductor layer is deposited in an atmosphere comprising SiH 4 and the dopant to SiH 4 concentra- tion in the atmosphere is 0.1% to 10%, preferably 0.05% to 0.5%;
  • the one doped semiconductor layer is deposited at a power density of lOmW/cm 2 to IW/cm 2 ' preferably between 50 mW/cm 2 and 300 mW/ cm 2 ;
  • the one doped semiconductor layer is deposited at a total pressure of 0.5 mbar to 12 mbar;
  • the one doped semiconductor layer is deposited at a process temperature between 150° C and 280° C;
  • the one doped semiconductor layer is deposited with an Rf power at a frequency of 13.56 MHz to 82 MHz.
  • a thin film photovoltaic device photovoltaic cell 40 comprises a substrate 41, preferably a transparent vitreous substrate, usually with a thickness of 0.4mm to 5mm, preferably 2mm to 4mm, an electrically conductive oxide 42 as contact on the substrate 41, one or more semiconductor layers 43-46, which generate an electric charge separation upon exposure to light, and a second electrically conductive contact 47.
  • a doping gas e. g. trimethylboron, diborane, 10.1.
  • said surface treatment implemented with parameters as in Table 1, prior to the p-layer, increases the efficiency of the solar cell by 2.09% (Table 3), half of this gain being achieved in the current-density (see EQE in Fig. 4) .
  • a silicon layer stack according to the invention with a surface treatment comprises 3 steps (lower part of Table 1) :
  • Table 2 shows absolute values of single junction amorphous solar cells with standard p' and inventive ⁇ surface treatment + standard p-layer' and the relative gains.
  • the processing temperature can be varied between 150 and 280 °C without compromising the gist of the invention.
  • a frequency between 13.56 MHz and 82 MHz (harmonics of 13.56 MHz) can be successfully employed.
  • the ratios between SiH 4 , H 2 and dopants (if any) CH 4 , TMB, PH 3 are relevant and can be easily derived from Table 1.
  • the Power applied to the process chamber will influence the desired deposition rate but will also influence the crystallinity of the layer and its stability. Since the cells in this example had the size of 1 cm 2 , the respective power density per cm 2 can be easily derived from Table 1.
  • the inventive process shall be understood as process for depositing a doped silicon layer on a TCO surface comprising a first plasma treatment process step performed under a first set of process parameters followed by a second plasma deposition process step with essentially the same (first) set of process parameters but including a dopant gas or precursor.
  • the ⁇ - ⁇ layer is deposited with a Silane concentration (SiH/H 2 ) between 0.1% and 10%, preferably between 1% and 5% with a dopant concentration (dopant/Silane) between 0.01% to 1%, preferably between 0.05% and 0.5% with a power density of 10 mW/cm 2 to lW/cm 2 , preferably between 50 and 300 mW/cm2 with a pressure between 0.5 and 12 mbar.
  • the time fraction of the first in relation to duration of first plus second process step shall be between 5 and 20% and/or, in absolute values, between 3 and 15 seconds, preferably between 5 and 10 seconds.
  • the above parameters are typical for a KAI-M PECVD reactor operated at 40 MHZ with an electrode surface of approx. 3000 cm 2 .
  • This manufacturing process can be upscaled in a KAI 1200 or similar industrial reactor as commercially available from Oerlikon Solar.
  • the TCO (ZnO) layer can be deposited on a system known as TCO 1200, also from Oerlikon Solar.
  • the inventive method can be applied in a beneficial manner on all kinds of thin film silicon photovoltaic layer stacks, where a doped window layer has to be deposited on a TCO front contact.
  • the silicon photovoltaic layer stack may be single junction amorphous, tandem junction micromorph, tandem junction amorphous or alike.

Abstract

In a method of manufacturing thin-film, silicon-based solar cells there is provided a substrate and deposited thereupon a first electrode layer of transparent, conductive oxide. During a first time span the surface of the transparent, conductive oxide layer is treated. Afterwards there is deposited upon the treated surface a doped layer during a second time span. The treatment of the transparent, conductive oxide surface is performed in an atmosphere which comprises a gaseous dopant with a different amount than comprised in the atmosphere for depositing the doped layer. Beside of this difference, the process for performing the treatment of the surface of the transparent, conductive oxide is equal to the process for depositing the doped layer. Nevertheless, the first time span is substantially shorter than the time span for depositing the doped layer.

Description

METHOD FOR MANUFACTURING A THIN-FILM, SILICON-BASED SOLAR CELL FIELD OF THE INVENTION
The present invention relates to improvements in the manufacturing process for thin-film, silicon-based solar cells or modules. More specifically the invention relates to a manufacturing process for the so called window layer in a thin film silicon solar cell and a layer structure for such thin film silicon solar cell. In particular the present invention relates to a surface treatment for the electrode layer in a solar cell structure, said electrode layer comprising a transparent conductive oxide (TCO) .
BACKGROUND ART
Photovoltaic devices, photoelectric conversion devices or solar cells are devices which convert light, especially sunlight into direct current (DC) electrical power. For low-cost mass production thin film solar cells are being of interest since they allow using glass, glass ceramics or other rigid or flexible substrates as a base material (substrate) instead of crystalline or polycrystalline silicon. The solar cell structure, i. e. the layer sequence responsible for or capable of the photovoltaic effect is being deposited in thin layers. This deposition may take place under atmospheric or vacuum conditions. Deposition techniques are widely known in the art, such as PVD, CVD, PECVD, APCVD,... all being used in semiconductor technology.
The conversion efficiency of a solar cell is the common measure for the performance of a solar cell and is being determined by the ratio of the output power density (= product of open-circuit voltage Voc, fill-factor FF and current-density Jsc) - to the input power density of 1000W/m2.
A thin-film solar cell generally includes a first electrode, one or more semiconductor thin-film p-i-n or n-i-p junctions, and a second electrode, which are successively stacked on a substrate. Each p-i-n junction or thin-film photoelectric conversion unit includes an intrinsic or i-type layer sandwiched between a positively doped or p- type layer and a negatively doped or n-type layer. The intrinsic semiconductor layer occupies the most part of the thickness of the thin-film p-i-n junction. Photoelectric conversion occurs primarily in this i-type layer; hence it is also called active or absorber layer.
Depending on the crystallinity of the i-type layer solar cells or photoelectric (conversion) devices are characterized as amorphous (a-Si) or microcrystalline (yc-Si) solar cells, independent of the kind of crystallinity of the adjacent p and n-layers . Microcrystalline layers are being understood, as layers comprising at least a Raman crystallinity of 15% of microcrystalline crystallites in an amorphous matrix. The doped layers in a p-i-n junction are also often referred to as window layers. Since the light absorbed by the doped p/n layers is lost for the active layer, highly transparent window layers are desired to obtain high current-densities (Jsc) . Furthermore the window layers are instrumental in establishing the electric field in the semiconductor junction constituting the solar cell, which helps collecting the photo-generated charge carriers and obtain high Voc and FF values. Besides this, the contact between the front transparent conductive oxide (TCO) and the window layer should be ohmic with a low resistivity, in order to obtain good FF values.
Prior Art Fig. 1 shows a basic, simple photovoltaic cell 40 comprising a transparent substrate 41, e. g. glass with a layer of a transparent conductive oxide (TCO) 42 deposited thereon. This layer is also called front contact and acts as first electrode for the photo- voltaic element. The next layer 43 acts as the active photovoltaic layer and comprises three "sub-layers" forming a p-i-n junction. Said layer 43 comprises hydrogenated microcrystalline (also called nanocrystalline) or amorphous silicon or a combination thereof. Sublayer 44 (adjacent to TCO front contact 42) is positively doped, the adjacent sub-layer 45 is intrinsic, and the final sub-layer 46 is negatively doped. In an alternative embodiment the layer sequence p- i-n as described can be inverted to n-i-p, then layer 44 is identified as n-layer, layer 45 again as intrinsic, layer 46 as p-layer. Finally, the cell includes a rear contact layer 47 (also called back contact) which may be made of zinc oxide, tin oxide or ITO and a re- flective layer 48. Alternatively a metallic back contact may be realized, which can combine the physical properties of back reflector 48 and back contact 47. For illustrative purposes, arrows indicate impinging light. It is generally understood that when light, for example, solar radiation, impinges on a photoelectric device electron-hole pairs are generated in the i-layer. The holes from the generated pair are directed towards the p-region and the electrons towards the n-region. The contacts are generally directly or indirectly in contact with the p- and n-regions. Current will flow through an external circuit connecting these contacts as long as light continues to generate electron-hole pairs.
DEFICIENCIES IN THE ART
The window (p/n-type) layers are generally made of amorphous or microcrystalline silicon (also called nanocrystalline) or any mixture thereof and their alloys with oxygen, carbon, germanium, and the like. Since the p/n-type layers are highly defective (disor- dered) the photogenerated electron-hole pairs recombine with a high probability; thus they do not contribute to the photocurrent of the device but do cause absorption losses. The thickness of the doped layers should for this reason be minimized in order to reduce these optical losses. However, when the doped layer thickness is reduced too much, the values of the fill-factor and the open-circuit voltage drop significantly.
SUMMARY OF THE INVENTION According to the invention it is suggested, prior to the growth of a window layer for a thin film silicon layer stack, a short surface treatment shall be performed resulting in a very thin, continuous or discontinuous nucleation layer or TCO surface preparation respectively. It has shown that such treatment improves the electrical properties of the later cell. Thus the present invention is directed on a method of manufacturing a thin-film, silicon-based solar cell, comprising:
• a substrate,
• upon the substrate a first electrode layer comprising a transparent, conductive oxide,
• upon the first electrode layer, stacked layers com- prising a positively doped semiconductor layer, an intrinsic semiconductor layer and a negatively doped semiconductor layer as well as a second electrode layer,
whereby the method comprises the steps of
· providing the substrate,
• depositing upon the substrate the first electrode layer comprising the transparent, conductive oxide and having a surface,
• treating the addressed surface by a first vacuum treat- ment process during a first time span,
• depositing upon the addressed surface treated by the
first vacuum treatment process one of the positively and of said negatively doped semiconductor layers by a second vacuum process performed during a second time span in a process atmosphere comprising a gaseous dopant,
• performing the first vacuum treatment process in a process atmosphere comprising a gaseous dopant with a different amount than comprised in the atmosphere of the second vacuum process but otherwise performing the first vacuum treatment process equally to the second vacuum process and selecting the first time span shorter than the second time span. In one embodiment the method according to the present invention comprises performing the first vacuum treatment process as a vacuum plasma treatment process in an atmosphere containing SiH4 and H2 and a gaseous dopant in a concentration between 0% and 80% of the concentration of a gaseous dopant present in the atmosphere of the second vacuum process, preferably between 0% and 20%, thereby preferably depositing by the second vacuum process the positively doped semiconductor layer. As the first first vacuum treatment process is a vacuum plasma treatment process in an atmosphere containing SiH4 and H2 the same prevails for the second vacuum process.
In one embodiment the method according to the present invention comprises depositing by the second vacuum process a positively doped semiconductor layer of hydrogenated silicon, thereby performing the second vacuum process for microcrystal- line material deposition and performing the first vacuum treatment process in an atmosphere without gaseous dopant and preferably depositing on the positively doped semiconductor layer of hydrogenated silicon an amorphous, positively doped layer of an alloy of silicon and carbon in a process atmosphere comprising hydrogenated silicon carbide wherein further preferably said second vacuum process is a vacuum plasma process - and thus also the first vacuum treatment process.
In one embodiment of the method according to the invention, the second vacuum process (and thus also the first vacuum treatment process) is a vacuum plasma process. In one embodiment of the method according to the present invention there prevails: the first time span is selected to be between 5% and 20% of the sum of the first and of the second time spans and wherein preferably the second vacuum process is a vacuum plasma process and there is valid at least one of:
• the one doped layer deposited by said second vacuum process is the positively doped semiconductor layer;
· the one doped semiconductor layer is deposited in an atmosphere comprising a SiH4 to H2 concentration of 0.1% to 10%, preferably of 1% to 5%;
• the one doped semiconductor layer is deposited in an atmosphere comprising SiH4 and the dopant to SiH4 concentra- tion in the atmosphere is 0.1% to 10%, preferably 0.05% to 0.5%;
• the one doped semiconductor layer is deposited at a power density of lOmW/cm2 to IW/cm2' preferably between 50 mW/cm2 and 300 mW/ cm2;
· the one doped semiconductor layer is deposited at a total pressure of 0.5 mbar to 12 mbar;
• the one doped semiconductor layer is deposited at a process temperature between 150° C and 280° C;
• the one doped semiconductor layer is deposited with an Rf power at a frequency of 13.56 MHz to 82 MHz.
DETAILED DESCRIPTION OF THE INVENTION
Generally, again with reference to Fig. 1, a thin film photovoltaic device photovoltaic cell 40 comprises a substrate 41, preferably a transparent vitreous substrate, usually with a thickness of 0.4mm to 5mm, preferably 2mm to 4mm, an electrically conductive oxide 42 as contact on the substrate 41, one or more semiconductor layers 43-46, which generate an electric charge separation upon exposure to light, and a second electrically conductive contact 47.
This surface treatment according to the invention comprises providing a substrate 41 with a TCO contact layer 42 thereon, providing a plasma of SiH4, H2 and optionally a doping gas (e. g. trimethylboron, diborane, ...) in a gas phase concentration between 0 to 80%; preferably 0 to 20% of the concentration used for deposition of the subsequent sub layer 44 = p-doped window layer. In the following example, said surface treatment implemented with parameters as in Table 1, prior to the p-layer, increases the efficiency of the solar cell by 2.09% (Table 3), half of this gain being achieved in the current-density (see EQE in Fig. 4) . Example for standard p-layer, here composed of 2 steps (upper part of Table 1) :
1. p μο-εί: H - depositing a p-layer with conditions suitable for
microcrystalline silicon material
2. p a-SiC:H - depositing a p-doped layer of an alloy of amorphous silicon and carbon.
A silicon layer stack according to the invention with a surface treatment comprises 3 steps (lower part of Table 1) :
1. Surface treatment: Short exposure (5 seconds) of the TCO layer 42 to a plasma with p μο conditions without doping gas. The plasma conditions are chosen to be the same as in subsequent step 2, but without any dopant gas .
2. p μσ-3ί:Η - Depositing a p-layer under conditions for microcrystalline material for 65 seconds
3. p a-SiC:H - Depositing a p-doped layer of an alloy of amorphous silicon and carbon
Figure imgf000009_0001
Table 1
Table 2 shows absolute values of single junction amorphous solar cells with standard p' and inventive ^surface treatment + standard p-layer' and the relative gains.
Figure imgf000010_0001
Table 2
The example described in Table 2 as well as fig. 2 shall demonstrate results, but shall not be limiting. The processing temperature can be varied between 150 and 280 °C without compromising the gist of the invention. A frequency between 13.56 MHz and 82 MHz (harmonics of 13.56 MHz) can be successfully employed. For the deposition processes the ratios between SiH4, H2 and dopants (if any) CH4, TMB, PH3 are relevant and can be easily derived from Table 1. The Power applied to the process chamber will influence the desired deposition rate but will also influence the crystallinity of the layer and its stability. Since the cells in this example had the size of 1 cm2, the respective power density per cm2 can be easily derived from Table 1.
The inventive process shall be understood as process for depositing a doped silicon layer on a TCO surface comprising a first plasma treatment process step performed under a first set of process parameters followed by a second plasma deposition process step with essentially the same (first) set of process parameters but including a dopant gas or precursor. For instance, the ρ-μσ layer is deposited with a Silane concentration (SiH/H2) between 0.1% and 10%, preferably between 1% and 5% with a dopant concentration (dopant/Silane) between 0.01% to 1%, preferably between 0.05% and 0.5% with a power density of 10 mW/cm2 to lW/cm2, preferably between 50 and 300 mW/cm2 with a pressure between 0.5 and 12 mbar. The time fraction of the first in relation to duration of first plus second process step shall be between 5 and 20% and/or, in absolute values, between 3 and 15 seconds, preferably between 5 and 10 seconds. The above parameters are typical for a KAI-M PECVD reactor operated at 40 MHZ with an electrode surface of approx. 3000 cm2.
This manufacturing process can be upscaled in a KAI 1200 or similar industrial reactor as commercially available from Oerlikon Solar. The TCO (ZnO) layer can be deposited on a system known as TCO 1200, also from Oerlikon Solar.
The inventive method can be applied in a beneficial manner on all kinds of thin film silicon photovoltaic layer stacks, where a doped window layer has to be deposited on a TCO front contact. The silicon photovoltaic layer stack may be single junction amorphous, tandem junction micromorph, tandem junction amorphous or alike.

Claims

Claims :
1. A method of manufacturing a thin-film, silicon-based solar cell, comprising:
• a substrate,
• upon said substrate a first electrode layer comprising a transparent, conductive oxide,
• upon said first electrode layer, stacked layers comprising a positively doped semiconductor layer, an intrinsic semiconductor layer and a negatively doped semiconductor layer as well as a second electrode layer,
said method comprising the steps of
• providing said substrate,
• depositing upon said substrate said first electrode
layer comprising said transparent, conductive oxide and having a surface,
• treating said surface by a first vacuum treatment process during a first time span,
• depositing upon said surface treated by said first vacuum treatment process one of said positively and of said negatively doped layers by a second vacuum process performed during a second time span in a process atmosphere comprising a gaseous dopant,
• performing said first vacuum treatment process in a process atmosphere comprising a gaseous dopant with a different amount than comprised in said atmosphere of said second vacuum process but otherwise performing said first vacuum treatment process equally to said second vacuum process and selecting said first time span shorter than said second time span.
2. The method of claim 1 comprising performing said first vacuum treatment process as a vacuum plasma treatment process in an atmosphere containing SiH4 and H2 and a gaseous dopant in a concentration between 0% and 80% of the concentration of a gaseous dopant present in the atmosphere of said second vacuum process, preferably between 0% and 20%, thereby preferably depositing by said second vacuum process said positively doped semiconductor layer.
3. The method of claim 1 comprising depositing by said second vacuum process as said one layer a positively doped layer of microcrystalline hydrogenated silicon, thereby performing said second vacuum process suitable for microcrystalline material deposition and performing said first vacuum treatment process in an atmosphere without gaseous dopant and preferably depositing on said positively doped layer of hydrogenated microcrystalline silicon an amorphous, positively doped layer of an alloy of silicon and carbon in a process atmosphere comprising hydrogenated silicon carbide, wherein further preferably said second vacuum process is a vacuum plasma process.
4. The method of claim 1, wherein said second vacuum process is a vacuum plasma process.
5. The method of claim 1, wherein said first time span is selected to be between 5% and 20% of the sum of the first and second time spans and wherein preferably
said second vacuum process is a vacuum plasma process and there is valid at least one of:
• said one doped semiconductor layer deposited by said second vacuum process is said positively doped semiconductor layer, said one doped semiconductor layer is deposited in an atmosphere comprising a SiH4 to ¾ concentration of 0.1% to 10%, preferably of 1% to 5%,
said one doped semiconductor layer is deposited in an atmosphere comprising SiH4 and the dopant to SiH4 concentration in said atmosphere is 0.1% to 10%, preferably 0.05% to 0.5%,
said one doped semiconductor layer is deposited at a power density of 10mW/cm2 to lW/cm2, preferably between 50 mW/cm2 and 300 m / cm2,
said one doped semiconductor layer is deposited at a total pressure of 0.5 mbar to 12 mbar,
said one doped semiconductor layer is deposited at a process temperature between 150° C and 280° C,
said one doped semiconductor layer is deposited with an Rf power at a frequency of 13.56 MHz to 82 MHz.
PCT/EP2010/063208 2009-09-18 2010-09-09 Method for manufacturing a thin-film, silicon-based solar cell WO2011032879A2 (en)

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