TW201126741A - Method for manufacturing a thin-film, silicon-based solar cell - Google Patents

Method for manufacturing a thin-film, silicon-based solar cell Download PDF

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TW201126741A
TW201126741A TW099131357A TW99131357A TW201126741A TW 201126741 A TW201126741 A TW 201126741A TW 099131357 A TW099131357 A TW 099131357A TW 99131357 A TW99131357 A TW 99131357A TW 201126741 A TW201126741 A TW 201126741A
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layer
vacuum
deposited
doped semiconductor
doped
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TW099131357A
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Julien Bailat
Evelyne Vallat-Sauvain
Daniel Borrello
Stefano Benagli
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Oerlikon Solar Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
    • H01L31/1824—Special manufacturing methods for microcrystalline Si, uc-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/545—Microcrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

In a method of manufacturing thin-film, silicon-based solar cells there is provided a substrate and deposited thereupon a first electrode layer of transparent, conductive oxide. During a first time span the surface of the transparent, conductive oxide layer is treated. Afterwards there is deposited upon the treated surface a doped layer during a second time span. The treatment of the trans-parent, conductive oxide surface is performed in an atmosphere which comprises a gaseous dopant with a different amount than comprised in the atmosphere for depositing the doped layer. Beside of this difference, the process for performing the treatment of the surface of the transparent, conductive oxide is equal to the process for depositing the doped layer. Nevertheless, the first time span is substantially shorter than the time span for depositing the doped layer.

Description

201126741 六、發明說明： 【發明所屬之技術領域】 本發明係關於改善製造薄膜矽系太陽能電池或模組之 製程。該發明更明確地關於在薄膜太陽能電池及一對如薄 膜矽系太陽能電池之層結構中，被稱作窗層之製造過程。 本發明更特別的關於在一太陽能電池結構中，對該電極層 之表面處理，該電極層包含一透明導電氧化物（TCO)。 【先前技術】 光電伏裝置、光電裝換裝置或太陽能電池係轉換光， 特別是將太陽光轉爲直流（DC)電能之裝置。對大量生產 低成本薄膜太陽能電池產生興趣是因其可允許使用玻璃、 玻璃陶瓷或其他堅硬或可彎曲基板做爲一基底材料（基 板）’以代替晶矽或多晶矽。該太陽能電池結構，即負責或 可起光電伏作用之該連續層沉積在薄層。在氣體環境或真 空條件下這沉積可發生。在本技藝中廣爲人知的沉積技術 諸如PVD、CVD、PECVD、APCVD，…全都使用在半導體 技術中。201126741 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a process for improving the manufacture of a thin film tantalum solar cell or module. The invention is more specifically directed to a manufacturing process referred to as a window layer in a layered structure of a thin film solar cell and a pair of thin film tantalum solar cells. More particularly, the invention relates to the surface treatment of a layer of a solar cell comprising a transparent conductive oxide (TCO). [Prior Art] A photovoltaic device, an optoelectronic device, or a solar cell converts light, particularly a device that converts sunlight into direct current (DC) power. There is an interest in mass production of low cost thin film solar cells because they allow the use of glass, glass ceramic or other hard or flexible substrates as a substrate material (substrate) to replace wafer or polysilicon. The solar cell structure, i.e., the continuous layer responsible for or capable of photovoltaic, is deposited in a thin layer. This deposition can occur under gaseous or vacuum conditions. Deposition techniques well known in the art such as PVD, CVD, PECVD, APCVD, ... are all used in semiconductor technology.

太陽能電池之轉換效率係對太陽能電池性能之共通量 測’且其藉該外部功率密度（=開路電壓 V。。，塡充因子FF 及電流密度Jse之積）與l〇0〇W/m2之該內部功率密度之比- 來判定。 薄膜太陽能電池一般包含一第一電極、一個以上半導 體薄膜Ρ“-η或n-i-p接面，及一第二電極，其等連續的堆 疊在一基板上。每一 p-i-n接面或薄膜光電轉換單元包含夾 201126741 在一正摻雜或p型層及一負摻雜或η型層之間的本質或i-型層。該本質半導體層佔該薄膜p-i-n接面之大部分厚度。 光電轉換主要發生在這i型層中；因此其亦稱爲主動或吸 收層。 不管相鄰P及η層之結晶性種類爲何，依該i型層太 陽能電池或光電（轉換）裝置之結晶性，定成如非晶體（a-Si) 或微晶體Uc-Si)太陽能電池之特徵。據瞭解，微晶體層係 在一非晶矩陣中包含至少1 5 %微晶晶體性之拉曼結晶度。 p-i-n接面中的摻雜層也經常稱爲窗層。由於該摻雜 P/η層所吸收的光會因主動層而消失，因此，極度透明的窗 層宜得到高電流密度（Jse)。而且，窗層有助於形成電場在 構成太陽能電池之半導體接面，該電場協助收集該產生光 的電荷載子及得到高V。。及FF値。除此之外，前透明導電 氧化物（TCO)與窗層間應爲歐姆接觸，其爲得到好FF値， 具有低阻抗。 習知技術之第1圖顯示一基本、簡單光電伏電池40， 該光電伏電池40包含一透明基板41，其例如爲玻璃，於 其上有一層沉積TCO 42。該層亦稱爲前接點，並且作爲用 於光電伏兀件之第一電極。該次層43作爲主動光電伏層使 用，並包含形成p-i-n接面之三“子層”。該層43包含微晶（亦 稱奈米晶）氫化矽或非晶矽或其組合。子層44(鄰近TCO前 接點42)係正摻雜，該鄰近次層45係本質，及該最後次層 46係負摻雜。在替代實施例中，該層連續p-i-n如所述轉 爲n-i-p，接著，層44被定義爲η層，層45再度爲本質， 201126741 2包含可由氧化鋅、氧化錫或銦 I觸層47 (亦稱背接點），以及反 -金屬背接觸，其能結合被反射 性。爲說明，箭頭指出照射光。 之光照射在一光電伏裝置時， [自所產生的一對電洞被導向ρ :域。一般該接觸會直接或間接 :連續以產生電子電洞對，電流 電路。 係由非晶或微晶矽（也叫奈米晶） 氧、碳、鍺等之合金製成。因 該產生光的電子電洞對高機率 置之光電流，而會造成吸收損 應最小化，以減少這些光學的 度過度減少時.，塡充因子之値 層46爲p層。最後，該電沖 錫氧化物（ITO)製成之背後S 射層48。替代地，可實現一 面48及背接觸47之物理特 咸知，當例如太陽輻射 在i層產生電子電洞對。萍 區域，而該電子被導向η區 的接觸Ρ或η區域。只要光 %·β 即流經連接這些接點之外部 [本技藝中之缺點] 該窗 （ρ/η型）層一般 或其等之任何混合物及其含 ρ/η型層缺陷極大（混亂的）， 重新組合；因此其無助於裝 失。因此，該摻雜層之厚度 損耗。然而，當該摻雜層厚 ❹ 及該開路電壓大幅降低。 【發明内容】 根據所提議之該發明， 長前，進行短暫的表面處理 不連續晶核層或TCO表面$ 的電池之電特性。因此，本 在用於薄膜矽堆積層之窗層成 ，這分別造成非常薄，連續或 備。其顯示此種處理改善之後 發明係有關製造一薄膜矽系太 陽能電池之方法，其包括： 一基板； 201126741 一第一電極層，其於該基板上包含一透明導電氧化物； 堆疊層，其於該第一電極層上包含一正摻雜半導體 層、一本質半導體層及一負摻雜半導體層及第二電極層； 俾該方法包含以下步驟： 提供該基板； 沉積該第一電極層於該基板上，該第一電極層包含該 透明導電氧化物以及具有一表面； 於第一時間段期間，藉第一真空處理製程處理該定址 (addressed)表面； 藉由於第二時間段期間在包含氣態摻雜物之製程氣體 環境中進行之第二真空處理製程，沉積該正摻雜層及該負 摻雜層之一於第一真空處理製程所處理之定址表面上； 在包含氣態摻雜物之處理氣體環境中進行該第一真空 製程，該氣態摻雜物與在該第二真空製程之該氣體環境所 包含者之量不同，惟另外以相同於該第二真空製程的方式 進行該第一真空製程，及選擇比該第二時間段還短的該第 一時間段。 在一實施例中，根據本發明之方法中包括在一包含 SiH4及H2以及氣態摻雜物之氣體環境中，進行如真空電漿 處理製程的該第一真空製程，該氣態摻雜物濃度介乎存在 於該第二真空製程的氣體環境之氣態摻雜物濃度的0%到 80%之間，較佳是介於0%到20%之間，藉此，藉由該第二 真空製程較佳地沉積該正摻雜半導體層。該第一真空處理 製程係一真空電漿處理製程，在一包含SiH4及H2之氣體 201126741 環境中也同樣適用於該第二真空製程。 在一實施例中，根據本發明之方法包括藉該第二真空 處理製程沉積一氫化矽之正摻雜半導體層，藉此爲微晶材 料沉積進行該第二真空製程，及在一無含氣態摻雜物之氣 體環境中進行該第一真空製程，及較佳地沉積在非晶氫化 矽之該正摻雜層半導體層上，在一製程氣體環境包含氫化 碳化矽中，正摻雜層係一矽及碳之合金，其中更佳地該第 二真空製程係一真空電漿製程以及也是該第一真空製程。 在一實施例中，根據本發明之方法之該第二真空製程 (以及也是該第一真空製程）係一真空電漿製程。 在一實施例中，在根據本發明之方法更適用：該第一 時間段係選擇成介於該第一及第二時間段之和的5 %到20% 之間，及其中較佳地該第二真空製程係該真空電漿製程， 及下列者之至少一者是有效的： 藉該第二真空製程所沉積的該一層摻雜半導體層係該 正摻雜半導體層；. 該一層摻雜半導體層係在氣體環境中沉積，該氣體環 境包含濃度0.1%至10%，較佳爲1%及5%之 SiH4對H2 之濃度； 該一層摻雜半導體層係在包含SiH4的氣體環境中沉 積，及在該氣體環境該摻雜物對SiH4的濃度係0.1%到 1 0 %，較佳爲 0 · 0 5 % 到 0.5 % ; 該一層摻雜半導體層係爲在功率密度爲l〇m W/cm2到 lW/cm2沉積，更好是介於50mW/cm2到300 mW/cm2之間’· 201126741 該一層摻雜半導體層係在0.5mbar到12mbar之間的總 壓力沉積； 該一層摻雜半導體層係在介於150。(：到280。(：之間的 製程溫度沉積； 及該一層摻雜半導體層係以頻率爲13.56MHz到 82MHz的Rf功率沉積。 【貫施方式】 一般’再參考第1圖，一薄膜光電伏裝置光電伏電池 40包含一基板41，較佳爲透明玻璃的基板，通常具有一 0.4mm至5mm的厚度，較佳爲2mm至4mm，一電性導電 氧化物42作爲接點在一基板41，一個以上的半導體層 43-46曝露在光中，該等半導體層會產生價電子分離，及一 第二電性的導電接點47。 根據本發明，該表面處理包含提供在其中具有一TCO 接觸層42之一基板41，提供一SiH4、h2之電漿及任意地 一摻雜.氣體(例如，三甲基硼，乙硼烷…）在氣體階段濃度介 在0至8 0 % ;較佳地使用濃度爲〇至2 〇 %，爲該之後次層 44 =摻雜P的窗層之沉積。 在以下例子，該表面處理設備具有如表1所列參數， 該P層之前，增加2.09% (表3)該太陽能電池之效率，在 該電流密度（見第4圖的EQE)達到此增益的—半。 例如標準的p層’此結合兩步驟（表1之上部）： 1 . p pc-Si:H-沉積一對微晶矽材料具有適當的條件p層。 2· p a-SiC:H-沉積一非晶矽及碳之合金之p參雜層。 201126741 一矽層根據本發明堆疊具有一表面處理包含3步驟 (表1之下部）： 1. 表面處理：該TCO層42之短暫曝露（5秒）在一具ρ μο 條件無摻雜氣體的電漿中，該電漿條件係選擇相同 於之後步驟2，但無任何摻雜氣體。 2. ρ μο-Si :Η-在爲微晶材料的條件下，沉積一 ρ層65秒。 3. p a-SiC: Η-沉積一非晶矽及碳之合金之ρ參雜層。 201126741The conversion efficiency of the solar cell is a common measure of the performance of the solar cell' and it is by the external power density (=open circuit voltage V., the product of the charge factor FF and the current density Jse) and l〇0〇W/m2 The ratio of the internal power density - is determined. The thin film solar cell generally comprises a first electrode, more than one semiconductor film Ρ "-η or nip junction, and a second electrode, which are successively stacked on a substrate. Each pin junction or thin film photoelectric conversion unit comprises Clip 201126741 is an intrinsic or i-type layer between a positively doped or p-type layer and a negatively doped or n-type layer. The intrinsic semiconductor layer occupies most of the thickness of the pin junction of the film. In the i-type layer; therefore, it is also referred to as an active or absorbing layer. Regardless of the crystallinity of the adjacent P and η layers, depending on the crystallinity of the i-type solar cell or photoelectric (conversion) device, Characterization of a crystalline (a-Si) or microcrystalline Uc-Si solar cell. It is understood that the microcrystalline layer contains at least 15% microcrystalline crystallinity of Raman crystallinity in an amorphous matrix. The doped layer in the layer is also often referred to as the window layer. Since the light absorbed by the doped P/n layer disappears due to the active layer, the extremely transparent window layer should preferably have a high current density (Jse). Layer helps to form an electric field in the formation of a solar cell The conductor junction, the electric field assists in collecting the photogenerated charge carriers and obtains high V. and FF. In addition, the front transparent conductive oxide (TCO) and the window layer should be ohmic contact, which is good. FF 値, with low impedance. Figure 1 of the prior art shows a basic, simple photovoltaic cell 40 comprising a transparent substrate 41, such as glass, having a layer of deposited TCO 42 thereon. The layer is also referred to as the front contact and serves as the first electrode for the photovoltaic element. The secondary layer 43 is used as an active photovoltaic layer and includes three "sublayers" that form a pin junction. The layer 43 contains micro Crystal (also known as nanocrystal) hydrogenated tantalum or amorphous tantalum or a combination thereof. Sublayer 44 (adjacent to TCO front junction 42) is positively doped, the adjacent sublayer 45 is essential, and the last sublayer 46 is negative Doping. In an alternative embodiment, the continuous pin of the layer is converted to nip as described, then layer 44 is defined as the η layer, layer 45 is again the essence, and 201126741 2 contains the contact layer of zinc oxide, tin oxide or indium. 47 (also known as the back contact point), and the anti-metal back contact, which can be combined with the reverse For the sake of explanation, the arrow indicates the illuminating light. When the light is irradiated on a photovoltaic device, [a pair of holes generated from the ρ: domain are generated. Generally, the contact will be directly or indirectly: continuous to generate an electron hole pair. , current circuit. It is made of amorphous or microcrystalline germanium (also known as nanocrystal) oxygen, carbon, germanium, etc. Because the electron hole that generates light has a high probability of setting the photocurrent, it will cause absorption. The damage should be minimized to reduce the excessive reduction of these optical degrees. The layer 46 of the enthalpy factor is the p layer. Finally, the etched tin oxide (ITO) is formed behind the S-emitter layer 48. Alternatively, The physical characteristics of the side 48 and the back contact 47 can be realized, for example, when solar radiation produces an electron hole pair in the i layer. The area is the area where the electrons are directed to the contact Ρ or η area of the η region. As long as the light %·β flows through the outside of these joints [disadvantages in the art], the window (ρ/η type) layer generally or any mixture thereof and its ρ/η type layer defects are extremely confusing ), regrouping; therefore it does not help to replace the loss. Therefore, the thickness of the doped layer is lost. However, when the doping layer is thick and the open circuit voltage is greatly reduced. SUMMARY OF THE INVENTION According to the proposed invention, the electrical properties of the battery of the discontinuous crystal nucleation layer or the TCO surface $ are temporarily surface treated for a short period of time. Therefore, it is used in the window layer for the film 矽 accumulation layer, which respectively causes very thin, continuous or ready. The invention relates to a method for manufacturing a thin film tantalum solar cell, comprising: a substrate; 201126741 a first electrode layer comprising a transparent conductive oxide on the substrate; The first electrode layer includes a positively doped semiconductor layer, an intrinsic semiconductor layer, and a negatively doped semiconductor layer and a second electrode layer. The method includes the steps of: providing the substrate; depositing the first electrode layer on the On the substrate, the first electrode layer comprises the transparent conductive oxide and has a surface; during the first time period, the addressed surface is processed by a first vacuum processing process; by containing a gaseous state during the second time period a second vacuum processing process performed in the process gas environment of the dopant, depositing one of the positive doped layer and the negative doped layer on the addressed surface processed by the first vacuum processing process; and including the gaseous dopant Performing the first vacuum process in a processing gas environment, the gaseous dopant being different from the amount of the gas environment included in the second vacuum process, Further the first vacuum process performed in a manner identical to that of the second vacuum process, selective and shorter than the second period of the first period. In one embodiment, the method according to the present invention includes performing a first vacuum process such as a vacuum plasma processing process in a gas atmosphere comprising SiH4 and H2 and a gaseous dopant, the gaseous dopant concentration Between 0% and 80%, preferably between 0% and 20%, of the gaseous dopant concentration in the gaseous environment of the second vacuum process, whereby the second vacuum process is compared The positively doped semiconductor layer is preferably deposited. The first vacuum processing process is a vacuum plasma processing process that is equally applicable to the second vacuum process in a gas containing SiH4 and H2 201126741. In one embodiment, the method according to the present invention includes depositing a positively doped semiconductor layer of ruthenium hydride by the second vacuum process, thereby performing the second vacuum process for deposition of the microcrystalline material, and in a gas-free state Performing the first vacuum process in a gas environment of the dopant, and preferably depositing on the positive doped layer semiconductor layer of the amorphous hydrogen hydride, in a process gas atmosphere comprising ruthenium carbide, a positive doped layer And a carbon alloy, wherein the second vacuum process is more preferably a vacuum plasma process and also the first vacuum process. In one embodiment, the second vacuum process (and also the first vacuum process) in accordance with the method of the present invention is a vacuum plasma process. In an embodiment, the method according to the invention is more suitable: the first time period is selected to be between 5% and 20% of the sum of the first and second time periods, and preferably the The second vacuum process is the vacuum plasma process, and at least one of the following is effective: the layer of doped semiconductor deposited by the second vacuum process is the doped semiconductor layer; The semiconductor layer is deposited in a gaseous environment comprising a concentration of SiH4 to H2 at a concentration of 0.1% to 10%, preferably 1% and 5%; the layer of doped semiconductor layer is deposited in a gas atmosphere containing SiH4 And in the gaseous environment, the concentration of the dopant to SiH4 is 0.1% to 10%, preferably 0. 05% to 0.5%; the layer of doped semiconductor layer is at a power density of l〇m W /cm2 to lW/cm2 deposition, more preferably between 50mW/cm2 and 300mW/cm2'· 201126741 The total doped semiconductor layer is deposited between 0.5 mbar and 12 mbar; this layer of doped semiconductor The layer is between 150. (: to 280. (: process temperature deposition between; and the layer of doped semiconductor layer is deposited with Rf power at a frequency of 13.56 MHz to 82 MHz. [General application method] Generally, refer to Figure 1, a thin film photovoltaic The photovoltaic device photovoltaic cell 40 comprises a substrate 41, preferably a transparent glass substrate, typically having a thickness of from 0.4 mm to 5 mm, preferably from 2 mm to 4 mm, and an electrically conductive oxide 42 as a contact on a substrate 41. One or more semiconductor layers 43-46 are exposed to light, the semiconductor layers will produce valence electron separation, and a second electrically conductive contact 47. According to the present invention, the surface treatment includes providing a TCO therein The substrate 41 of the contact layer 42 provides a plasma of SiH4, h2 and optionally a doping gas (for example, trimethylboron, diborane...) at a gas phase concentration of 0 to 80%; preferably The concentration used is 〇 to 2 〇%, which is the deposition of the subsequent sub-layer 44 = doped P window layer. In the following example, the surface treatment equipment has the parameters listed in Table 1, before the P layer, an increase of 2.09% (Table 3) The efficiency of the solar cell at the current density See EQE in Figure 4) to achieve this gain - half. For example the standard p-layer 'this combines two steps (top of Table 1): 1. p pc-Si: H-deposit a pair of microcrystalline germanium materials with appropriate Condition p layer. 2· p a-SiC: H-deposited p-doped layer of amorphous germanium and carbon alloy. 201126741 A stack of layers according to the invention having a surface treatment comprising 3 steps (lower part of Table 1): 1. Surface Treatment: The TCO layer 42 is briefly exposed (5 seconds) in a plasma of ρ μο conditional undoped gas, which is selected to be the same as the subsequent step 2, but without any dopant gas. 2. ρ μο-Si : Η - Under the condition of microcrystalline material, a ρ layer is deposited for 65 seconds. 3. p a-SiC: Η-deposited ρ-doped layer of amorphous bismuth and carbon alloy.

時間 o 溫度 (°C) 200 200 200 1- 1 200 j 200 頻率 (MHz) 40.68 40.68 40.68 1- 40.68 1 40.68 壓力 (mbar) (N 〇 <N <N 〇 功率 400 o 1 I 400 1 1 400 o ch4 (seem) o Os o o Os tmb/h2 (seem) m m 00 〇 cn 00 κη Μ (seem) 1800 〇〇 Os 1800 1800 00 as SiH4 (seem) cs VO fS VO CN ppc-Si:H p a-SiC:H 表面處理 ppc-Si:H p a-SiC:H 201126741 表2顯示具’標準p’及發明’表面處理+標準p層’及該 相對增益的單接面非晶太陽能電池之絕對値。Time o Temperature (°C) 200 200 200 1- 1 200 j 200 Frequency (MHz) 40.68 40.68 40.68 1- 40.68 1 40.68 Pressure (mbar) (N 〇<N <N 〇 power 400 o 1 I 400 1 1 400 o ch4 (seem) o Os oo Os tmb/h2 (seem) mm 00 〇cn 00 κη Μ (seem) 1800 〇〇Os 1800 1800 00 as SiH4 (seem) cs VO fS VO CN ppc-Si:H p a -SiC:H Surface treatment ppc-Si:H p a-SiC:H 201126741 Table 2 shows the absolute of single-junction amorphous solar cells with 'standard p' and invention 'surface treatment + standard p-layer' and the relative gain value.

Jsc QE Voc FF 效率 (mA/cm2) (mV) (%) (%) 標準P 16.81 903.03 70.67 10.73 表面處理+<p> 16.98 911.00 70.80 10.95 相對增益（％) 1.02 0.88 0.18 2.09 表2 表2及第2圖所述該例子顯示結果，但不限於此。該 製程溫度可介於150及2 8 0°C間各溫度無包含其發明之要 旨。一頻率介於13.56 MHz及82 MHz(13.56 MHz之諧波） 順利地被使用。對該沉積製程比率介於SiH4、H2及摻雜物 (若任何）有關CH4、TMB、PH3間，及能從表1容易地得 Q 到。該功率施加該製程腔體將影響所述沉積率，但也將影 響該層之結晶性及其穩定性。因在此例中該等電池有1 cm2 之尺寸，每cm2該個別的功率密度能從表1容易地描述。 據了解，該發明製程應爲一對沉積一摻雜砂層在一 TCO表面上之製程，其包含在一第一製程參數之設定下進 行一第一電漿處理製程步驟，以及接在其後的第二電漿沉 積製程步驟，該第二電漿沉積製程步驟具有實質上相同（第 一）製程摻數之設定，但包含一摻雜氣體或前驅物。例如， 該ρ-μ(；層係具有一·砂院濃度（SiH4/H2)介於0.1%及10%間 -12- 201126741 沉積，較佳地在具有一摻雜物濃度（摻雜物/矽烷）介於 0 · 0 1 %及1 %間中，該矽烷濃度介於1 %及5 %間；較佳地在 一具功率密度爲l〇mW/cm2至lW/cm2中，該摻雜物濃度介 於0.05%及0.5%間；較佳地在具一壓力介於0.5及12mbr 間，該功率密度介於50 mW/cm2及300 mW/cm2中。關於 第一及第一脈衝之持續時間，第二製程步驟之該時間分數 應爲5及2 0 %及/或，在絕對値，介於3及1 5秒，較佳地 介於5及10秒。該上述參數係典型的對—KAI-M PECVD U 反應爐在40MHZ具一近似3000cm2之電極表面中被操作。 此製造製程從歐瑞康太陽能公司（〇erlikon Solar)的 ΚΑΙ 12 00或相似的工業反應器作爲可用於商業的，能被完 整應用。該TCO(ZnO)層可沉積在~以TCO 1200著稱，亦 來自的歐瑞康太陽能公司（Oerlikon Solar)之系統上。 本發明方法可應用在各種薄膜矽系光電伏堆積層上， 其中摻雜窗層應被沉積在一 TC0前接點上。該矽光電伏堆 積層可爲非晶單接面、微型態雙頭接面、非晶雙頭接面等 〇 〇 【圖式簡單說明】 第1圖係表示一薄膜光電伏裝置之示意剖面圖； 第2圖係具有標準P層（虛線）及根據本發明處理的諸 P層（實線）之單一接通非晶太陽能電池之依波長而定的絕 對値。 【主要元件符號說明】 4〇 光電伏單元 -13- 201126741 4 1 透 明 基 板 42 TCO 43 下 層 44 次 層 45 鄰 近 次 層 46 最 後 次 層 47 背 後 接 觸層 48 反 射 層Jsc QE Voc FF Efficiency (mA/cm2) (mV) (%) (%) Standard P 16.81 903.03 70.67 10.73 Surface treatment + <p> 16.98 911.00 70.80 10.95 Relative gain (%) 1.02 0.88 0.18 2.09 Table 2 Table 2 and The example shown in Fig. 2 shows the result, but is not limited thereto. The process temperature can be between 150 and 280 ° C. The temperature does not include the purpose of the invention. A frequency between 13.56 MHz and 82 MHz (harmonic of 13.56 MHz) was used successfully. The deposition process ratio is between SiH4, H2 and dopants (if any) between CH4, TMB, PH3, and can be easily obtained from Table 1. The application of this power to the process chamber will affect the deposition rate, but will also affect the crystallinity of the layer and its stability. Since the cells have a size of 1 cm2 in this example, the individual power densities per cm2 can be easily described from Table 1. It is understood that the process of the invention should be a pair of processes for depositing a doped sand layer on a TCO surface, comprising performing a first plasma processing process step at a setting of a first process parameter, and following A second plasma deposition process step, the second plasma deposition process step having substantially the same (first) process dosing setting but comprising a dopant gas or precursor. For example, the ρ-μ(; layer has a sand concentration (SiH4/H2) between 0.1% and 10% -12-201126741 deposition, preferably with a dopant concentration (dopant/矽 )) is between 0 · 0 1 % and 1%, the decane concentration is between 1% and 5%; preferably in a power density of l〇mW/cm2 to lW/cm2, the doping The concentration of the substance is between 0.05% and 0.5%; preferably between a pressure of between 0.5 and 12 mbr, the power density is between 50 mW/cm2 and 300 mW/cm2. Regarding the duration of the first and first pulses The time, the time fraction of the second process step should be 5 and 20% and/or, in absolute 値, between 3 and 15 seconds, preferably between 5 and 10 seconds. The above parameters are typical pairs. - KAI-M PECVD U reactor is operated at 40 MHZ with an electrode surface of approximately 3000 cm2. This manufacturing process is commercially available from ΚΑΙerlikon Solar's ΚΑΙ 12 00 or similar industrial reactor. It is fully applied. The TCO (ZnO) layer can be deposited on the system of TCO 1200, also from the system of Oerlikon Solar. It can be applied to various film lanthanum photovoltaic stacks, wherein the doped window layer should be deposited on a TC0 front contact. The 矽 photovoltaic stack can be amorphous single junction, microstate double junction , amorphous double-ended junction, etc. [Simplified description of the drawings] Fig. 1 is a schematic sectional view showing a thin film photovoltaic device; Fig. 2 is a standard P layer (dashed line) and P processed according to the present invention The layer (solid line) is connected to the absolute wavelength of the amorphous solar cell according to the wavelength. [Main component symbol description] 4〇 Photovoltaic cell-13- 201126741 4 1 Transparent substrate 42 TCO 43 Lower layer 44 Sublayer 45 Adjacent Secondary layer 46 last layer 47 back contact layer 48 reflective layer

-14--14-

Claims (1)

201126741 七、申請專利範圍： 1. 一種製造薄膜矽系太陽能電池之方法，該太陽能電池包 含： 一基板； 一第一電極層，於該基板上，且包含一透明導電氧化 物； 堆疊層，於該第一電極層上，且包含一正摻雜半導體 層，一本質半導體層及負摻雜層以及第二電極層； 〇 該方法包含以下步驟： 提供上述基板； 沉積該第一電極層於該基.板上，該第一電極層包含該 透明導電氧化物，並具有一表面； 於第一時間段期間藉由一第一真空處理製程處理該 表面； 藉由在一包含氣態摻雜物製程氣體環境，於第二時間 段期間所執行的第二真空製程，於藉由該第一真空處理 0 製程所處理的該表面上，沉積該正摻雜及該負摻雜層之 一者； 在包含氣態摻雜物之處理氣體環境中進行該第一真 空製程，該氣態摻雜物具有與在該第二真空製程之該氣 體環境所包含者不同之量，否則以相同於第該第二真空 製程的方式執行該第一真空製程，及選擇比該第二時間 段還短的該第一時間段。 2. 如申請專利範圍第1項之方法，其包含在一包含SiH4及 -15- 201126741 h2以及氣態摻雜物之氣體環境中，執行如真空電獎 製程的該第一真空製程，該氣態摻雜物濃度介於存 該第二真空製程的氣體環境之氣態摻雜物濃度的 80%之間，較佳是介於0%到20%之間，藉此藉由該 真空製程較佳地沉積該正摻雜半導體層。 3. 如申請專利範圍第1項之方法，其包含藉由該第二 製程沉積一微晶氫化矽之正摻雜層作爲該一層，藉 行適合微晶材料沉積的該第二真空製程’及在無包 態摻雜物之氣體環境中執行該第一真空處理製程， 包含氫化碳化矽之製程氣體環境中’沉積一碳矽合 非晶正摻雜層於微晶氫化矽’其中較佳地該第二真 程是真空電漿製程。 4. 如申請專利範圍第1項之方法，其中該第二真空製 一真空電漿製程。 5 .如申請專利範圍第1項之方法，其中第一時間段係 成介於該第-及第二時間段之和的5%到2〇%之間’ 中較佳地該第二真空製程係該真空電漿製程’及下 之至少一者是有效的： 藉該第二真空製程所沉積的該一層摻雜半導體 該正摻雜半導體層； 該一層摻雜半導體層係在氣體環境中沉積’該氣 境包含濃度0.1%至10%’較佳爲1%及5%之SlH4: 之濃度； 該一層摻雜半導體層係在包含siH4的氣體環境 處理 在於 〇 %到 第二 真空 此執 含氣 及在 金之 空製 程是 選擇 及其 列者 層係 體環 對h2 中沉 -16 - 201126741 積’及在該氣體環境誃換 見β摻雜物對SiH4的濃度係0.1%到 10°/。，較佳爲 0.05%到 0.5% ; 該一層摻雜半導體層係爲在功率密度爲l〇mW/cm2 到lW/cm2沉積，更好是介於50 mW/cm2到300 mW/cm2 之間； 該一層摻雜半導體層係在〇.5mbar到12mbar之間的 總壓力沉積； 該一層摻雜半導體層係在介於150°C到280°C之間的 製程溫度沉積； 及該一層摻雜半導體層係以頻率爲13·56ΜΗζ到 8 2MHz的Rf功率沉積。 0 -17-201126741 VII. Patent application scope: 1. A method for manufacturing a thin film tantalum solar cell, the solar cell comprising: a substrate; a first electrode layer on the substrate and comprising a transparent conductive oxide; The first electrode layer includes a positively doped semiconductor layer, an intrinsic semiconductor layer and a negative doped layer and a second electrode layer; and the method comprises the steps of: providing the substrate; depositing the first electrode layer The first electrode layer comprises the transparent conductive oxide and has a surface; the surface is processed by a first vacuum processing process during the first period; by a process comprising a gaseous dopant a gas environment, a second vacuum process performed during the second time period, depositing one of the positive doping and the negative doping layer on the surface processed by the first vacuum processing 0 process; The first vacuum process is performed in a process gas atmosphere containing a gaseous dopant, and the gaseous dopant has a gas environment included in the second vacuum process Different amounts, otherwise the first vacuum process in the same manner to the first of the second vacuum process, and selecting the first time is shorter than the period of the second time period. 2. The method of claim 1, wherein the first vacuum process, such as a vacuum credit process, is performed in a gas atmosphere comprising SiH4 and -15-201126741 h2 and a gaseous dopant, the gaseous state doping The impurity concentration is between 80%, preferably between 0% and 20%, of the gaseous dopant concentration of the gaseous environment in which the second vacuum process is performed, whereby the vacuum process is preferably deposited. The positively doped semiconductor layer. 3. The method of claim 1, comprising the step of depositing a positively doped layer of microcrystalline hydrogenated ruthenium as the layer by the second process, by the second vacuum process suitable for deposition of the microcrystalline material and Performing the first vacuum processing process in a gas atmosphere without a clad dopant, in which a carbon monoxide-doped amorphous positive doped layer is deposited in a process gas atmosphere comprising hydrogenated niobium carbide. The second real process is a vacuum plasma process. 4. The method of claim 1, wherein the second vacuum is a vacuum plasma process. 5. The method of claim 1, wherein the first time period is between 5% and 2% of the sum of the first and second time periods, preferably the second vacuum process At least one of the vacuum plasma process and the lower one is effective: the layer of doped semiconductor deposited by the second vacuum process is positively doped semiconductor layer; the layer of doped semiconductor layer is deposited in a gaseous environment 'The atmosphere comprises a concentration of 0.1% to 10%, preferably 1% and 5% of the concentration of SlH4:; the layer of doped semiconductor layer is treated in a gas environment containing siH4 in the range of 〇% to the second vacuum. The gas and the process in the gold space are selected and their column layer is in the pair of h2 in the sink-16 - 201126741 product ' and in the gas environment, the beta dopant to SiH4 concentration is 0.1% to 10 ° / . Preferably, the layer of doped semiconductor layer is deposited at a power density of from 10 mW/cm 2 to 1 W/cm 2 , more preferably from 50 mW/cm 2 to 300 mW/cm 2 ; The one layer of doped semiconductor layer is deposited at a total pressure between mbar5 mbar and 12 mbar; the layer of doped semiconductor layer is deposited at a process temperature between 150 ° C and 280 ° C; and the layer of doped semiconductor The layer is deposited at Rf power at a frequency of 13.56 ΜΗζ to 8 2 MHz. 0 -17-
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