CN102782881A - High-efficiency amorphous silicon photovoltaic devices - Google Patents

High-efficiency amorphous silicon photovoltaic devices Download PDF

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Publication number
CN102782881A
CN102782881A CN2010800415739A CN201080041573A CN102782881A CN 102782881 A CN102782881 A CN 102782881A CN 2010800415739 A CN2010800415739 A CN 2010800415739A CN 201080041573 A CN201080041573 A CN 201080041573A CN 102782881 A CN102782881 A CN 102782881A
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layer
glass
substrate
silicon
lpcvd
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D·博雷洛
E·瓦拉特-绍瓦因
J·拜拉特
U·克罗尔
J·迈尔
S·贝纳格利
M·马梅洛
G·蒙特杜罗
J·赫策尔
J·施泰因豪泽
C·卢西
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TEL Solar AG
TEL Solar Services AG
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Oerlikon Solar IP AG
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Abstract

A method for manufacturing an amorphous silicon p-i-n solar cell is disclosed. The cell comprises an anti-reflection coating and doped LPCVD ZnO front and back contacts, wherein the doped LPCVD ZnO front and back contacts are polycrystalline films constituted of large grains whose extremities appear at the growing surface as pyramids. The method comprises: depositing said front contact by means of LPCVD; depositing the silicon layers of said p-i-n solar cell by means of plasma enhanced chemical vapor deposition; depositing said back contact by means of LPCVD; and providing said anti-reflection coating. The amorphous silicon p-i-n solar cell can achieve a stabilized efficiency of 10.09%.

Description

The high efficiency amorphous silicon photovoltaic device
Technical field
The present invention relates to thin-film solar cells and module and manufacturing thereof based on silicon.The present invention relates to film, based on the improvement of the manufacturing process of the solar cell of silicon or module.More specifically, the present invention relates to noncrystal membrane solar cell and manufacturing thereof.
Continue in the affiliated technical field for improving battery efficiency and reducing the manufacturing cost this respect simultaneously and drop into mental and physical efforts.This balance is difficult to keep.
In order to improve the photoelectric transformation efficiency of photovoltaic (PV) device, should in active silicon layer, absorb maximum incident lights as far as possible.This is through 1) minimize reflected specific loss and 2) introducing light scattering optical interface reaches near this photovoltaic active silicon layer.
First optical interface that in this cover plate p-i-n structure, produces light intensity losses is air/glass interface 49 (Fig. 9).For fear of because typical 4% loss that this light reflection is at the interface caused, known have two kinds of major techniques: anti-reflection film coating (ARC) or antireflection etching (chemistry, plasma or machinery).
In order to obtain light scattering at optical interface, use coarse interface usually, major part is the TCO/Si interface, in Fig. 9 is to be positioned between reference point 42 (positive contact) and 44 and 46 and 47 (back side contacts).Yet strong light scattering needs very coarse TCO, and this makes follow-up intensive silicon growth and this device of laser patterning become difficult more.
Therefore, want that the glass (textured glasses) that has texture through use introduces coarse air/glass and/or coarse glass/TCO interface.Yet it is quite expensive using the glass that initially has texture, and in basic " laser patterning " processing step, can have problems.
Typically, be deposited on smooth thin film silicon solar cell pin on glass and can show 3 to 4% photoelectric current and increase, thereby the battery efficiency that increases is directly contributed through the AR coating.Yet the cost of the dielectric AR-coating in commercial obtainable visible light-near infrared ray (visible-near IR) scope (broadband) is quite high.Therefore, be used in particular for the manufacturing of high efficiency (record-breaking) battery through the glass of AR coating.
With regard to author itself know that the second kind of known technology (that is antireflection etching) that is used to produce anti-reflective glass is not used in the manufacturing of thin-film solar cells till now yet.This lets the people surprised very much, because further this glass of etching can cause light scattering at this first air/glass interface place extraly.Yet, be built with extra degree of difficulty owing to carry out laser, so this effect maybe be still untapped for the battery that is deposited on the glass that initially has texture.Really, the patterning laser beam that gets into this device from glass side can experience this light scattering effect equally, and therefore, is used for limited material (material ablation) the required concentrated intensity (focused intensity) that comes off and has the part loss.This makes and more is difficult in light scattering laser grooving and scribing battery on glass and module.When monolithic is connected in series when being the key element of thin film silicon photovoltaic,, up to the present too many concern is not thrown in the application of light scattering glass substrate as yet compared to the technology based on wafer of routine.
Therefore, propose a kind of " glass treatment behind the battery (post-cell glass treatment) ", it allows the following introducing 1 of decoupling zero) optical anti and 2) in the light scattering at this air/glass interface place.Therefore, depend on the optical diffuser amount that the maximum device performance is wanted, possibly make diffusion anti-reflex treated (Diffusive Anti-Reflective Treatment; DART) be applicable to various film solar battery structures.
III.2. general introduction
The present invention's suggestion makes up or this air/glass interface 49 of veining after the preparation of completed cell or module.This glass exposure is in the etch processes of the solar cell that can not damage manufacturing on another (avoiding) side (perhaps complete module through laser patterning).This etching DART handles preferred through the execution of RIE (reactive ion etching) plasma etching, but is not limited to this kind technology.Can use microwave plasma etching, machinery or chemical glass etching equally, depend on glass ingredient.The etching DART that under following condition, carried out 5 to 15 minutes handles to have illustrated the antireflection effect is provided, and the processing up to 2 hours of the present invention will provide the light scattering characteristic of increase extraly.
III.3 describes in detail
Find, in the reactive ion etching reactor with O 2With SF 6(gas flow ratio is SF to the Cement Composite Treated by Plasma that mixture carries out 6: O 2=5: 1, pressure 30mTorr, power 600 preferably, were longer than 5 minutes to 1000W) be suitable for etching Schott Borofloat 33 glass.
For fear of the infringement cell stacks, need take safeguard measure.As as known in the art, this silicon layer pile up 43 with this back side contact layer 47 (referring to Fig. 9) and sometimes reflector 48 be to deposit through vacuum or near the processing step (like PECVD, LPCVD, PVD) of vacuum.If this DART technology should be used in this stage of this manufacturing process, then must protect the layer of this sensitivity to pile up, in order to avoid receive the influence of front side etch technology.This can achieve the above object through for example temporary transient mechanical device (as the carrier with clamping framework is installed), and wherein, this framework provides sealing device, and it allows only to expose substrate 41 front sides, and those need the part through the DART processing.Replacedly, can use removable adhesive film or removable coating.The inventor finds that surprisingly well-known whitewash reflector (characteristic 48) also is enough protections, in order to avoid the exposure of etching step.Owing in any case this diffusion whitewash reflector all must be applied in this module packaging technology step after a while, so means that basically need not be extra.For DART handled very widely, because the heat that this processing produced or this DART handle the chemical gas that is adopted, this whitewash can change its characteristic.Therefore, for long processing and/or can heat for the processing of this sample, preferably before whitewash applies, carry out DART, perhaps provide enough cooling to avoid adverse effect.
Figure 11 illustrates the total reflectance through measuring of a series of glass/TCO/a-Si:H pin/TCO structure.Near the light incident of minute surface the time, 7 to 6% reflection loss is arranged at the interface at this air/usual glass (Schott Boroflaot33).Can make total reflection be reduced to R through typical commerce (Schott) the wideband A R-coating of the scope of application in 400 to 650 nanometer range TotARCglass≈ 3%.This is corresponding to the reflection R that reduces Totflatglass-R TotARCglass=%.Diffusion anti-reflex treated (DART) of the present invention at least 15 minutes allows to obtain and the expensive similar R of AR-coating TotThe correspondence gain that gets into the luminous intensity of this device is converted into the photoelectric current (J of this thin-film device fully SC) 3.5 to 4% relative gain of aspect.
It may be noted that in Figure 11 this AR-coating reflection loss shows some wavelength-dependences (wavelength-dependency) (interference fringe) in the scope of 400 to 650 nanometers, it is different from smooth glass structure.This is because this ARC effect relies on is the interference in dielectric film piles up.Yet for DART glass, the amplitude of striped (fringe) can reduce with finding out.
This is that some optical diffuser effect must occur in this air/DART experimental evidence at the interface.Can see above-mentioned phenomenon through observing treated glass surface form (its roughness and form are along with the etching number of times develops) (seeing Figure 11).Therefore, this DART handles applicable to only producing antireflection effect (of short duration processing time) or antireflection+light scattering effect (long glass treatment time).
Figure 12 and Figure 13 illustrate the scanning electron micrograph (scanning electron micrograph) of the treated surface of Schott Borofloat 33, and this Schott Borofloat 33 carries out etchedly (having O with the change time 2With SF 6The reactive ion etching reactor of mixture (glass flow rate compares SF 6/ O 2=1.67), the discharge power of pressure 5mTorr and 1000W).Figure 12: 5 minutes Cement Composite Treated by Plasma, Figure 13: 120 minutes Cement Composite Treated by Plasma.
Figure 14 illustrates not to have (no AR, lower curve) and is having measured external quantum efficiency EQE curve under the situation of DART processing (120 minutes, higher curve) series connection amorphous/crystallite stack of cells.In the a-Si:H battery of this top with this microcrystal bottom battery in J SCThe contribution of catching for the light that increases is handled in 4% expression that gain is superior to expecting from this DART.
This is an advantage, through can further maximizing absorption of incident light in this silicon layer like this.Therefore, the diffusion composition of this DART can be applicable to this front TCO optical scattering characteristic, and is applicable to this thickness of detector (tandem junction or unijunction).For example, if the DART of this glass has increased the light scattering of long wavelength light (>700 nanometer), then this microcrystal bottom battery is able to keep thinner, is used for carrying out currents match with this top battery.
Capable of using long etching period of this glass is obtained this effect.This effect is taken into account the light scattering in long wavelength's scope of increase, and this is a kind of being difficult to be used for the character that the ZnO with texture that is grown of a-Si:H battery obtains from research and development.
Typically, longer to the optimal etch technology of the glass that is used to be deposited on the amorphous/crystallite stacked solar cells on the quite smooth ZnO, because it must have the light scattering of the increase that is used for the microcrystal silicon bottom battery.The optimal etch time will depend on that also this series connection amorphous/crystallite piles up the existence of interior middle reflector.At last, the special combination of having observed DART and amorphous/crystallite stacked solar cells is not the J that is defined in increase SC, also can cause the V that increases OCWith FF.
All these examples are all pointed out the modification that the DART permission is optimized to the maximal efficiency work of almost any combination of TCO/a-Si:H/ μ c-Si:H/TCO layer thickness combination.
Above-mentioned application (being used for very high efficiency test battery) if its cost is not too high compared to the modular power increase of desired 3.5-4%, then also can be applicable to industrial film a-Si:H silicon module.(angular dependency) is very little for the angle dependence of this reflection coefficient; That is, even for away from for the angle of light degree of minute surface, reflection loss also reduces.Therefore, not only higher efficient can be obtained through DART, annual production of energy (yearly energy the production) (kWh/kW of the module in the actual outdoor use P) also can receive positive influence because of the faint angle dependence of DART characteristic.Known wideband A R-film coating also can be to minimizing the angle dependence and optimised, but this is extra, the restrictive needs that are used to optimize this type coating.
Optimum organization through face glass/TCO/Si/TCO device system; This application has the potentiality that increase amorphous/crystallite piles up series-connected solar cells efficient and strengthens the light capturing ability; Be used for further reducing this Si absorber (till now; In the gain that has 10% aspect the photoelectric current of this bottom battery, there is the V that increases in some cases OCWith FF).Should be appreciated that, above institute's specified value be to depend on many parameters and can't given easily general formula (recipe).The open-assembly time that DART of the present invention handles depend on the ability of this etching machine, the type of glass (thickness, chemical composition), employed front contact with the back side (especially, its haze factor), technology (aSi or amorphous/crystallite pile up), for the use that is used for the absorber layers thickness of this battery, middle reflector in the various technology whether and-last but be not least importantly whether should only obtain antireflection effect (short etch) perhaps should obtain diffusion and add antireflection (length etching period).Those skilled in the art will follow above-mentioned basic teaching and take necessary change for analogous process environments.
IV. contact warp control and the oxidation before of TCO deposition overleaf through quickening
Be used for through the thin film silicon photovoltaic device of oxidation processes manufacturing fast to improve the method for productive rate and electric property
It is No.61/243 that this part of present patent application is taken from the sequence number of submitting to United States Patent (USP) trademark office on September 18th, 2009 in fact, 628 U.S. Provisional Application, and it relates to the method for making thin-film solar cells.This part stresses that permission reduces the processing of the leakage current of this based thin film solar cell.Especially, the present patent application surface that relates to membrane silicon layer or the silicon through the last deposition of the oxidation oxidized surface of sandwich construction that forms the part of thin-film solar cells is handled.
In order to assess productive rate, (intensity be lower than AM1.5 10%) is measured the open circuit voltage V of (contact deposition overleaf with cell patternization after) battery under low luminous intensity OCUnder these measuring conditions, show the battery that is lower than the 600mV open circuit voltage and be regarded as (part) shunting (shunted) and under the full illumination of AM1.5, will show bad electric property.Figure 15 illustrates and shows the low-light (level) V that is lower than 600mV (that is so-called part shunting) OCStandard A M1.5 I (V) curve and I (V) curve of a test battery of identical pin PECVD batch of oxidation before the contact deposition (that is, according to passivation device that foregoing proposed) overleaf of three engaged test batteries.
Several possible reasons are arranged in thin film silicon solar cell, to shunt.For example, the particle in this front contact is quite disadvantageous for high yield.If but particle is the reason of the branch Flow Behavior of this device, then capable of usingly come significantly to eliminate its influence from intrinsic initial back side contact (described in open source literature WO 2009/077605).
The Another reason of low-yield and bad electric property is to be manufactured in to observe in the device on the coarse substrate and has low-density, low quality silicon materials in the thin film silicon solar cell, and is shown in figure 16.The J.of Non-Cryst.Solids 115 (1989) that the adverse effect that is deposited on this type of defective zone in the thin film silicon on the very coarse substrate has been described in people such as Sakai is people's such as (to the a-Si:H battery) and M.Python Solar Energy Materials and Solar Cells 93 p.198-200, and Issue 10 (2009) is p.1714-1720 in (to the microcrystal silicon solar cell).
Figure 16 illustrates the projection electron micrograph that is deposited on the section of the a-Si:H pin solar cell on coarse glass/TCO cover plate (bottom of this micrograph) through PECVD.This encircled illustrates and has low-density and porose silicon materials.This TEM micrograph is to appear at the perspective view that the 2D of 3D layer in piling up " leaks border (leaking boundary) ".This kind border is that the recess at this substrate is observed.This type of low density material reduces this integral device electric property, and therefore infers and be the height electronic defects.
As everyone knows; (the i-layer thickness is less than 200 nanometers for extremely thin pin device; The p-layer thickness is less than 10 nanometers) or be deposited on pin device in the front contact of tool height texture (very coarse TCO or have the glass/TCO cover plate on the surface that has sharp-pointed depression angle), obtain high yield difficulty considerably.In these cases, if directly this back side contact of deposition after PECVD n-layer deposition, then battery can part or overall shunting.
Yet we have observed in air, preserving uncompleted device (that is, after n-layer PECVD deposition and before the contact deposition overleaf) during several days time period has increased the productive rate and the conversion efficiency of the device of (after a while) completion.
These defective borders have been identified as electric current and have leaked the border.These low-density and defective material zone can betide (auto-deposition temperature (~200 ℃) is to ambient temperature) (relaxing for mechanical stress is weakness) during layer removal during the layer growth in this PECVD reactor or in this PECVD reactor outside.According to the equivalent electric circuit that Figure 17 illustrated; Its adverse effect for the device electrical characteristics is and increases dark leakage current pro rata (for microcrystal silicon: with reference to people's such as Martin Python Solar Energy Materials and Solar Cells Volume 93 like its measured in profile linear density; Issue 10; October2009, Pages 1714-1720).Figure 17 illustrates the simple equivalent circuit that shows the thin film silicon solar cell on the coarse substrate that leaks the border.These leak the border is to have " high dark current J Diode2" diagram in to illustrate be second diode.
Figure 18 illustrates and leaks the dark current density J of boundary density for microcrystalline silicon solar cell 02Influence (in this example, be called " collapse (crack) ").Take from M.Python; PhD dissertation; Institute of Microtechnology, University of
Figure BPA00001522653800171
2009.Original header: Relationship between the J 02And the crack density, for p-i-n configuration, estimated by TEM micrographs, in co-deposited mc-Si:H cells on varying substrates.In high efficiency solar cell, observe low J 02With low collapse density.
For given PECVD sedimentary condition, depend on the cover plate form like the linear density on viewed defective border in the profile; And, can find the PECVD sedimentary condition of the density that reduces these defective leakage borders for given cover plate form.Below described conditions permit deactivate (deactivate) these leak borders, can improve this device electrical characteristics and productive rate significantly in this way.
The shortcoming of IV.1 prior art
The effect of after being used for increasing the n-layer deposition of productive rate, preserving at air takes place very slowly.For front quite smooth, standard contacts; Must be stored in the air about 10 hours in order to obtain high yield; And, must preserve a week in order to obtain high yield for TCO or for key, thin pin device with height texture.
IV.2. general introduction
The present invention suggestion before deposition back side contact TCO, provide that the silicon layer of thin-film solar cells piles up through control and oxidation through quickening.
In first embodiment, individual other silicon face is exposed to and is rich in H 20 and/or 30%H 2O 2Atmosphere in reach about 1 hour, preferably, assigned 1 to 2 hour 100 ℃ temperature.Improving temperature will allow to reduce open-assembly time.In a second embodiment, this silicon face should at room temperature be exposed to and reach about 1 hour in the ozone.In the variant of present embodiment, temperature is set in about 100 ℃, with the oxidation technology of acceleration with ozone.Be found to, being exposed to this kind environment, to assign 5 to 15 minutes be effective.In further variant, ambient pressure has been set at 0.5mbar and has reached 15 minutes.Higher ozone concentration allow further to reduce this processing the duration.In the 3rd embodiment, after this n-layer deposition, (for example: C use soft oxidation plasma (soft oxidizing plasma) 2F 6, CO 2, O 2, SF 6).Preferably, (power 100W is (at 3000cm should to apply this soft oxidation plasma 2Electrode area on), 200 ℃ of temperature) reach the several seconds, preferably surpassed for 10 seconds.Have been found that the processing that surpasses a minute does not have benefit.Change that effective power will allow to change open-assembly time with substrate temperature and the category that can not depart from this proposition.
IV.3. describe in detail
Here described relate to after n-layer deposition and applying back side contact processing before; Even if this processing than air-preservation technology faster and to being deposited on very coarse cover plate (for example: the thin pin device ZnO RMS>100 nanometers) (1/3 thinner p layer thickness, i-layer thickness<200 nanometers) or the pin (i-layer thickness>200 nanometers) of standard thickness also allow to obtain enough productive rates.After this oxidation processes, the electric property of this device is enhanced (shown in figure 15, as mainly to be open circuit voltage and fill factor, curve factor).These processing comprise the combination of oxidation chemistry agent (oxidizing chemical agent) and temperature and pressure, and it allows to make oxidation technology otherwise very slowly take place between the gas exposure period around.Significantly, in corresponding embodiment, all these handle also auxiliary (the plasma assisted) of plasma.
In this article, oxidation reaction is understood that traditional chemical, is typical redox reaction (rebox reaction), and wherein, electronics is from a kind of substance transfer to another kind of material.Here, oxidant is a material of accepting electronics.Therefore, this oxidant is not to be defined in oxygen.For example, even if make in them some not by preferential use because fluorine, sulphur, chlorine, nitrogen etc. have adverse effect as the doped chemical in the silicon, but fluorine, sulphur, chlorine, nitrogen etc. still can be the chemical oxidizing agent of silicon.
Worked out the possible method of several accelerated oxidation technologies.Typically processing faster need be less than 1 hour, preferably is less than or equals 5 minutes.
For these embodiment, adopted the a-Si:H pin layer of the current techniques of standard to pile up (i-layer thickness 240 nanometers, starting efficiency>11%).Several oxidizing processs have been assessed.
After n-layer deposition, observe
1) the pin device is exposed to malaria (the deionization H that contains concentration 30% in stove under 100 ℃ 2O or H 2O 2" Becher " glass) in reach 1 hour, preferably 2 hours, it was about 80% allow to make that the productive rate of crucial TCO increases to from 0, and this treated battery shows good I (V) characteristic.
2) the pin device is exposed to the resulting ozone (O of the air that provides from commercial obtainable ozone generation device in stove under room temperature (and 1 atm) 3) in reach 1 hour or more of a specified duration, allow on the TCO that highly has texture, to obtain high yield and good I (V) characteristic.Temperature increase to 100 ℃ has been quickened the oxidation technology with ozone.There is the combination of temperature and open-assembly time; It is the productive rate that provides optimization according to positive TCO roughness/texture: in stove, with 100 ℃ standard ZnO (being called " smooth " in the explanatory note of Figure 19) is continued ozone treatment and can significantly improve productive rate in 5 minutes; But for the ZnO that highly has texture (being called " coarse " in the explanatory note of Figure 16), reaching high yield needs preferably 15 minutes processing.Long open-assembly time maybe be really not so efficient.Be exposed to O with 100 ℃ or higher sample temperature and the vacuum of 0.5mbar 3In continue 15 minutes (as in ZnO-LPCVD equipment, before the contact deposition overleaf) be to be used for n-layer deposition contact the ozone oxidation between depositing with the back side another kind possibility.Through in oxidation chamber, utilizing higher ozone concentration (for example: utilize pure oxygen to be used for ozone generating), can make oxidization time even less than 5 minutes.
3) alternative of ozone exposure is after n-layer deposition, (for example: C to apply soft oxidation plasma 2F 6, CO 2, O 2, SF 6).Preferably, in the PECVD system of commercial similar Oerlikon Solar KAI, continue soft oxygen plasma (the power 300mW/cm of several seconds (preferably above 10 seconds) 2, 200 ℃ of temperature) can cause at the battery performance that obtains high yield on the TCO of key and on standard ZnO, be improved.
Figure 19 illustrates the influence of ozone exposure time for the pin device yield with two kinds of positive types of different TCO.After 5 minutes, a little improvement will occur, the preferred duration is about 15 minutes.
The quick oxidation technology that is proposed provides the conversion efficiency of the increase that is manufactured in the battery on the standard TCO.In addition, allow to use various positive TCO/ glass combination, especially have the positive TCO/ glass of light scattering characteristic of roughness and the increase of increase.
Can successfully realize extremely thin (thickness of i-layer is less than 100 nanometers) and a-Si:H pin with good I (V) characteristic; And finally may be implemented in a-Si:H pin-pin series-connected cell, opened new potentiality based on battery and the coarse TCO of a-Si:H for the stability and high efficiency rate.
Also can use this type of oxidation processes and be used for deactivating the leakage border in crystallite single junction cell and the amorphous/crystallite stack of cells.
Background technology
Photovoltaic device, electrooptical device or solar cell are convert light, particularly sunlight are converted into the device of direct current (DC) electric energy.Produce low cost is a large amount of, thin-film solar cells is interesting, and this is because of it allows to use glass, glass ceramics or other rigidity or flexible base, board as base material (substrate), to replace crystal silicon or polysilicon.This solar battery structure, promptly responsible this sequence of layer that maybe can play photovoltaic effect is deposited in the thin layer.This deposition can occur under atmosphere or the vacuum condition.Deposition technique such as PVD, CVD, PECVD, APCVD... are known in this area, and these all are used in the semiconductor technology.
The conversion efficiency of solar cell is that the common of solar cell properties measured, and it is by output power density (=open circuit voltage V Oc, fill factor, curve factor FF and current density, J ScLong-pending) with recently the confirming of input power density.
Thin-film solar cells generally comprises first electrode, one or more semiconductive thin film p-i-n or n-i-p knot, and second electrode, and their sequence stacks are on substrate.Each p-i-n knot or film photoelectric converting unit comprise be clipped in just mix p type layer and negative mixes or n type layer between intrinsic-OR i-type layer.This intrinsic semiconductor layer accounts for most thickness of this film p-i-n knot.Opto-electronic conversion mainly occurs in this i type layer; Therefore it also is called active or absorber layers.
According to the crystallinity of this i type layer solar cell, or photoelectricity (conversion) device is characterized as being amorphous (a-Si) or crystallite (μ c-Si) solar cell, and no matter the crystallinity kind of adjacent p and n layer why.As common in the art, microcrystalline coating is considered to be in the crystalline layer of the Raman that comprises at least 15% microcrystallization degree in the noncrystal substrate.
Doped layer in the p-i-n knot also often is called the window layer.Because the light that this doping p/n layer is absorbed can be because of the active layer loss, therefore, the expectation of the window layer of highly transparent obtains high current density (J Sc).And the window layer helps in the semiconductor junction that constitutes solar cell, to set up electric field, and this electric field assists to collect the electric charge carrier of light generation and obtain high V OcAnd FF value.Except that this, contacting between preceding transparent conductive oxide (TCO) and the window layer should be ohm, and it has low-resistivity, so that obtained the FF value.In the art, because the preferred optical characteristic (absorbing less) of the window layer of microcrystal silicon makes that the window layer of microcrystal silicon is more favored than amorphous window layer.
Fig. 9 of prior art illustrates basically, simple photovoltaic cell 40, and this photovoltaic cell 40 comprises transparency carrier 41, and it for example is a glass, deposits layer of transparent conductive oxide (TCO) 42 above that.This layer also is called positive contact, and as first electrode that is used for photovoltaic element.Substrate 41 contacts 42 combination and also is known as cover plate (superstrate) with positive.Following one deck 43 is as active photovoltaic layer, and comprises three " sublayers " that form the p-i-n knot.This layer 43 comprises microcrystalline hydrogenated silicon, nanocrystalline silicon or amorphous silicon or its combination.Just mix in sublayer 44 (the positive contact 42 of contiguous TCO), this vicinity sublayer 45 is intrinsics, and this last sublayer 46 is negative doping.In alternate embodiment, can be reversed to n-i-p like described this sequence of layer p-i-n, so, layer 44 is identified as the n layer, and layer 45 be intrinsic once again, and layers 46 is the p layer.
At last, this battery comprises the behind contact layer 47 (also claiming back of the body contact) that can be processed by zinc oxide, tin oxide or indium tin oxide (ITO), and reflector 48.Alternatively, can realize the metal backing contact, it can combine the physical characteristic of back reflection body 48 and back of the body contact 47.Be explanation, arrow is pointed out incident light.
Usually understand, when the light of for example solar radiation is incident on the photovoltaic device, in the i layer, produce electron hole pair.Right hole from being produced is directed to the p zone, and this electronics is directed to the n zone.General this contact contacts p or n zone directly or indirectly.As long as light continues to produce electron hole pair, electric current will be flowed through and connected the external circuit of these contacts.
I. general
High efficiency amorphous silicon device on the prepared LPCVD-ZnO TCO of industrial KAI-M R&D reactor
It is No.61/244 that the general part of this of present patent application comes down to take from the sequence number of submitting to United States Patent (USP) trademark office on September 21st, 2009,236 U.S. Provisional Application.Research for the optimum i-layer thickness of the high efficiency amorphous silicon p-i-n solar cell on the LPCVD-ZnO that is deposited on doping is hereinafter proposed.The action of this kind optimum is issued to excellent and stable efficient in the situation of obviously very thin amorphous i-layer thickness.Has 10.09% record-breaking efficient (record efficiency) (at 1cm 2On) the unijunction a-Si:H battery that soaks into of light be by NREL independently confirm.In table, the measurement result that Oerlikon Solar-Lab
Figure BPA00001522653800021
and NREL laboratory are done for identity unit shows extremely low deviation between two specific characters.The technology of being researched and developed for the a-Si:H battery is to be applied to prepare mini module (10x10cm 2).In the ESTI laboratory of JRC, 9.2% module aperture efficient has been confirmed in the measurement of these light being soaked into mini module.
Can further understand the details of some aspect of the present invention from joint II to IV hereinafter.
I.1 introduce
On the direction of reaching the same valency of civil power (grid parity), pile up the thin-film solar module that (micromorph) serial connection technology is the basis with amorphous silicon and amorphous/crystallite and have very big potentiality for the reduction manufacturing cost.For two kinds of technology, silicon thin film can be deposited in single chamber plasma enhanced chemical vapor deposition (PECVD) reactor (similar Oerlikon Solar KAI system).Previous research is verified when introducing special p-i interface processing [1,2], and this KAI reactor can produce high-quality amorphous silicon p-i-n battery.
Simultaneously, through suitably reducing this a-Si:H absorber layers thickness, the manufacturing cost and the light that can influence these modules valuably soak into stability.For this purpose, adopt coarse TCO to catch with the light of strengthening in this device.The light scattering that is increased in this TCO causes in this battery several-light path (several-fold path of light) of folding, and therefore allow to adopt the absorber layers of thinner thickness.In addition, because the optical absorption of μ c-Si:H is poor than the optical absorption of a-Si:H, so for amorphous/crystallite piles up the series connection device, the light scattering characteristic of this front TCO even even more important.
TCO film characteristics (like the light scattering ability (visible light and near infra red region) of high transmission, high conductivity, excellence) and suitable the film evenly configuration of surface of growth are that high efficiency silicon thin film device is necessary.The zinc oxide of the doped with boron through low-pressure chemical vapor deposition (LPCVD) manufacturing is verified because therefore its outstanding light scattering ability can produce excellent thin film silicon solar cell [3].When with the volume production large-scale production, LPCVD-ZnO also is TCO cheaply.For these reasons, Oerlikon Solar has determined research and development to be used for large tracts of land deposition 1.4m 2The technology and the production equipment [4] of LPCVD-ZnO layer.
Present patent application is presented on unijunction a-Si:H battery and has the result who is reached on the mini module of all LPCVD-ZnO fronts and backplate.
I.2 experiment
The p-i-n a-Si:H solar cell deposition that is proposed is (52x41cm in the single chamber KAI-M of R&D system 2Substrate size).At each battery batch (run) afterwards, use in-situ plasma technology to clear up this KAI plasma case reactor.
Previous research proof can utilize the stimulating frequency of 40.68MHz to come the excellent amorphous silicon i-layer (with
Figure BPA00001522653800031
) [5 of deposition quality; 6,7].In this new research, the deposition rate of this i-layer is
Figure BPA00001522653800041
Each battery contacts with the back side as positive with the LPCVD-ZnO that mini module all has inner preparation, and the latter combines white reflection body (WR) [8].The deposition parameter of ZnO layer is optimised, to obtain efficient light scattering, the high grade of transparency and conductivity.We adopt the Schott Borofloat 33 of thickness 1mm as glass cover-plate.The optical characteristics utilization of LPCVD-ZnO layer is equipped with Perkin Elmer lambda 950 spectrometers of integrating sphere (integrating sphere) and measures.
For careful characterization, all batteries all are to be configured to by 1 square centimeter area of good definition through laser patterning.The mini module that is of a size of the 10x10 square centimeter through the monolithic for each section be connected in series (monolithic series connection) apply laser grooving and scribing (laser scribing) and realize.
The I of battery (V) characteristic is measured under 25 ℃ and AM 1.5 irradiance (Wacom WXS-155S-L2 double source simulator).I (V) characteristic of record-breaking battery (record cell) and mini module is that ESTI laboratory, the Ispra (Italy) by this National Renewable Laboratory (NREL), Golden (USA) and JRC measures respectively independently.
It is to carry out under the following condition that light soaks into test: a sunlight intensity (power reaches the sulphur lamp of MW), 50 ℃, during the 1000h and under open circuit voltage.For with temperature maintenance in 50 ℃, light soak into the test under sample be placed on the chill station.Previous I by the measured mini module of amorphous p-i-n (10 * 10 square centimeters) in the ESTI laboratory of this JRC SCValue is used for the luminous intensity on this example platform is set to 1000W/m as a reference 2Value.Moreover, the light uniformity be confirmed as be superior to ± 5%.
This chill station is covered by the heat conduction pad, makes it possible to guarantee the good thermo-contact with the sample of tested person.In order to confirm each regional temperature on this platform, be employed in the a-Si:H battery sample (5x5 square centimeter) that its top is pasted with the Pt100 transducer.Between this transducer and this battery, adopt the heat conduction paster to guarantee good thermo-contact.On bottom (rear side (shadow side)), some samples also comprise transducer.Find that through test the temperature difference between two transducers (top and bottom) is in 1 ℃.Finally, look measured temperature and decide, this chill station is classified in different zones.Ideal zone with 50 ℃ ± 2 ℃ is identified, and is used for the described light of this work and soaks into test.
Sample (this work is considered) is being placed in after this light soaks on the ideal zone of platform, the Pt100 transducer attaches on it, and controls this temperature once again.Then begin to carry out light and soak into test.Remain unchanged in order to check, in different time control luminous intensity and temperature in this duration of test condition.Particularly, the initial segment that soaks at this light, interlude and latter end are carefully verified these parameters.Light in mini module soaks into duration of test, is used to check the similarly careful program of this temperature.Moreover finding has near 50 ℃ standard value ± 2 ℃ variation.
I.3 result
I.3.1 LPCVD-ZnO is as positive TCO
Compared to previous in the work [7] that EU PVSEC is proposed employed layer, the ZnO layer that this work proposed (that is, type A and type B) is modified.Particularly, for type A, be reduced to 12% in the haze factor (haze factor) of 600 nanometers from 20%, but for the ZnO type B, haze factor increases up to 70% suddenly then.Yet up to the present, only ZnO type A is used to prepare mini module.Two types ZnO is all the polycrystalline film that is made up of large-scale shot-like particle, and the end of this large-scale shot-like particle comes across the growing surface (see figure 1) as the pyramid that kind.This type of is along with such this light of diffusion of the rough surface texture of growth diffuse transmissivity as shown in Figure 2.This effect causes light scattering entering this silicon device [9] effectively.
About using high mist degree LPCVD-ZnO to be that as the known disadvantage of front contact the optimization of thin film silicon device is more meticulous and difficult.But, can provide these types the ZnO layer, can prove the high J of this front ZnO type B ScThe value potentiality also are contained among our research.
I.3.2 amorphous silicon battery
Fig. 3 and Fig. 4 illustrate respectively before by Oerlikon Solar-Lab
Figure BPA00001522653800051
[7] resulting amorphous i-layer thickness series in 2008 and 2009 annual earnings to new range.Importantly, point out to be applied to some changes in the cell preparation in 2009: the deposition rate of this i-layer is that employing increases the new method (no antireflection, AR, coating) of this short-circuit current density and reduces the positive contact of this ZnO mist degree slightly from
Figure BPA00001522653800052
is reduced to
Figure BPA00001522653800053
.
To
Figure BPA00001522653800054
and The deposition thickness of 1 micron and a-Si: H layer of the optical properties is located in Prague, Czech Academy of Sciences Institute of Physics measurements.Notice that the deposition rate that reduces this i-layer is as revising the modification that the desired that kind of silane dilution is attended by optical characteristics usually separately.Consider that simultaneously the i-layer has 1.73 electron-volts optical band gap (Tauc ' s) [5].For reaching the a-Si:H battery with high short-circuit current density, this is an important characteristic, piles up in the design of device desired as high efficiency (after light soaks into) amorphous/crystallite.
Mainly viewed with Fig. 4 through comparison diagram 3 is this J ScThe obvious increase of value.This is the result for the minimized intensive research of the light intensity losses in 400 to 800 nanometer wavelength range.Notice J SCThe increase of value is not reduce this battery FF value and V OCObtain under the situation of value.Another is observed to be the initial and stable open circuit voltage (V of the technology of new research and development OCValue) slight increase.Only with reference to Fig. 4, the maximal efficiency that deducibility goes out as the function of this i-layer thickness possibly not reach as yet; With further studying thinner layer, like 180 nanometers.
From this research study to basic principle be that positive the contact with the back side of LPCVD-ZnO is used for the a-Si:H unijunction solar cell, even very high stable J also can be provided to approach i-layer (180 nanometer) SCValue (16mA/cm 2) and good V OCValue and FF value.Excellent light seizure, thin p-i-n layer and high-quality i-layer are the key factors that reaches the high efficiency device.
Had preparation to have the experience of the heavy-duty battery of thin i-layer, next step is a device of studying antireflection (AR) coating of the commerce with air glass-substrate interface.In addition, we have developed inner wideband A R.
Consider the test of carrying out for the battery with AR, also the LPCVD-ZnO to newtype tests (the ZnO type B has 70% mist degree in 600 nanometers).Yet, with regard to prepared cell on the type A ZnO, select the i-layer of thickness 180 nanometers, and with regard to type B ZnO goes up prepared cell, the absorber layers of selected 250 nanometers.As shown in Figure 5, on type B ZnO, we measure 10.03% record-breaking light and soak into battery efficiency.
The record-breaking battery of Fig. 5 is sent to NREL, Golden, and CO (USA), and the result of its independent characteristic is illustrated among Fig. 6.Confirm to have 10.09% suitable height and stable efficient.The amorphous silicon single junction cell reaches the efficient that stops above 10% for the first time.Know that with regard to the author battery shown in Fig. 6 is represented the New World record of amorphous silicon p-i-n battery.Compared to previous record (η=9.47%; By IMT;
Figure BPA00001522653800061
resultant [9; 10]), we have obtained 0.6% absolute significant the improvement.
Such champion's battery has proved that OC Oerlikon LPCVD-ZnO (front contacts with the back side) combines to be deposited on single chamber KAI TMAmorphous silicon in the reactor is very ripe and has high efficiency technology.
In Fig. 7, the absolute EQE of battery as shown in Figure 6 is through being standardized into 17.284mA/cm 2The QE measurement of the NREL of AM 1.5 short-circuit current densities of (from I (V) characteristic of NREL) is calculated.Notice that in the absorption region of amorphous silicon, absolute EQE characteristic is all very high throughout.This result obtains after all layers that form this battery are carried out intensive optimization with the interface.Especially, the excellent light scattering potentiality of our LPCVD-ZnO, high-quality and standard bandgap i-layer (being deposited in this KAI reactor) are the key factors that is used to obtain so high absolute EQE.
In table 1, the review of different record-breaking battery prepared among the R&D Solar-Lab
Figure BPA00001522653800071
is shown.Particularly, table 1 be at first measure at Oerlikon Solar-Lab
Figure BPA00001522653800072
and (in 9 days) comparison between I (V) battery parameter that NREL measures after a while.It should be noted that the efficient (surpassing 10%) that can reach very high: the battery 3497,3473 and 3470 of seeing table 1 with two types ZnO (that is, type A and type B) through analyzing.
As shown in table 1, our AM1.5I-V characteristic is quite consistent with the measurement of NREL.As if we want that the AM1.5 that is stressed that us proofreaies and correct based on ESTI (Ispra), and this ESTI (Ispra) quite matees with NREL.The obvious deviation that we can notice is in the confirming of the cell area of sample 3297 and 3470.As shown in table 1, this final fact can cause determined efficient to change.
Figure BPA00001522653800073
Table 1: look back prepared and measure and by the record-breaking battery of NREL institute independent present characteristic by Oerlikon Solar-Lab
Figure BPA00001522653800074
.All batteries all are deposited in R&DKAI-M PECVD system, have that LPCVD-ZnO is positive to be contacted with the back side, and light soaks into and reaches 1000 hours under open circuit voltage conditions, 50 ℃, one times sun light intensity.And battery 3328 and 3470 has under the situation of commercial AR coating, on battery 3497 and 3473, applies our inside AR (Oerl.).
I.3.3 the mini module of amorphous silicon
Experiment is resulting on 1 square centimeter the battery finds by conversion to optimize the mini module on the LPCVD-ZnO being of a size of.For mini module, be chosen on the ZnO type A more mature technique.180,215, and 250 nanometers consider following three kinds of i-layer thicknesses:.Soak into (as the described condition of the 2nd joint) at light afterwards, the ESTI laboratory that the mini module of full blast is sent to the JRC of Ispra characterizes (optimum is illustrated in Fig. 8) to be used for autonomous behavior.Module aperture area (module aperture area) is to be determined by ESTI equally.9.2% stable module aperture efficiency be confirmed (, soaking into) at Oerlikon Solar-Lab completion light like the description of the 2nd joint institute.When record-breaking battery result (table 1:NREL) and record-breaking mini module (among Fig. 8: when ESTI) comparing, the efficiency losses (absolute) of calculating 0.86%.This value is reasonably, and therefore our record-breaking battery result further obtains confirming.
I.4 summarize and conclusion
When using the LPCVD-ZnO electrode that is suitably mixed, the achievement that the i-layer thickness of amorphous silicon p-i-n solar cell is optimized has illustrated thin i-layer capable of using (180 nanometer) and has obtained high J SCValue and level of efficiency.
The excellent specific property of high-quality silicon layer that in this KAI system, deposits and the LPCVD-ZnO that should inside mixes has turned out to be and has reached extremely important aspect the high efficiency level.Inner ZnO shows high transmission, high conductivity, the light scattering ability of excellence and the configuration of surface of suitable growing high-quality a-Si:H film.
On 1 square centimeter, can reach 10.09% record-breaking stable cell efficient (confirming) by NREL institute is independent.This result provides our knowledge for the highest stabilizing battery efficiency of a-Si:H unijunction solar cell through confirming.Compared to previous equally by champion's battery that NREL confirmed (people such as η=9.47%J.Meier; IMT;
Figure BPA00001522653800081
[9; 10]), we have obtained 0.62% obviously absolute the improvement on η.In addition, two other battery shows 10.06% efficient (NREL).
The preparation (10x10 square centimeter) of technology through being converted to mini module of developing for battery.The ESTI laboratory of the JRC of Ispra illustrates 9.2% aperture area efficient to the measurement that these light soak into mini module.The module efficiency of high stable is measured consistent with this NREL battery efficiency like this.
We point out that the result of mini module proves that record-breaking battery can be promoted to the high-performance module.In the next stage, Oerlikon Solar will be absorbed in to be promoted to and be of a size of 1.4 square metres industrial substrate.
The technology that the result illustrates Oerlikon Solar is used to make the high potential that high-performance amorphous silicon and amorphous/crystallite pile up serial module structure.
II. be used to improve the surface treatment of electrical characteristics
Be used to make method with the photovoltaic device that improves performance
It is No.61/243 that this part of present patent application is taken from the sequence number of submitting to United States Patent (USP) trademark office on September 18th, 2009 in fact, 646 U.S. Provisional Application, and it relates to improving and is used for based on the thin-film solar cells of silicon or the manufacturing process of module.More detailed, present patent application relates to and is used at thin film silicon solar cell and is used for the manufacturing process of so-called window layer of the layer structure of such thin film silicon solar cell.Present patent application relates more particularly to the surface treatment to the electrode layer in solar battery structure, and this electrode layer comprises transparent conductive oxide (TCO).
The shortcoming of II.1 prior art
This window (p/n type) layer generally is to process by amorphous or microcrystal silicon (also being nanocrystal) or its any mixture and with the alloy of oxygen, carbon, germanium etc.Because of p/n type layer is (chaotic) that very big defective is arranged, the electron hole that this light produces is compound with high probability; Therefore it is helpless to the photoelectric current of device, and can cause absorption loss.Therefore, the thickness of this doped layer should minimize, to reduce the loss of these optics.Yet when this doped layer thickness excessively reduced, the value of fill factor, curve factor and this open circuit voltage significantly reduced.
The II.2 general introduction
Suggestion in this manual before being used for window layer that membrane silicon layer piles up and growing up, should be carried out of short duration surface treatment, and this causes extremely thin respectively, continuous or discontinuous nucleating layer or TCO surface preparation.It illustrates the electrical characteristics that this kind processing has improved battery after a while.
II.3 describes in detail
Generally, again with reference to figure 9, film photovoltaic device photovoltaic cell 40 comprises substrate 41, is preferably the substrate of clear glass, has the thickness of 0.4mm to 5mm usually, is preferably 2mm to 4mm; The conductive oxide 42 of conduct contact on substrate 41; One or more semiconductor layer 43-46 are being exposed to the light time, and this semiconductor layer produces separation of charge; And the second conduction contact 47.
This surface treatment that this paper proposes comprises provides the substrate 41 that has TCO contact layer 42 above that; SiH is provided 4, H 2Plasma and randomly provide phase concentrations between the concentration that is used to deposit follow-up sublayer 44=p doping window layer 0 to 80% between, the impurity gas between 0 to 20% (for example, trimethyl borine, diborane ...) preferably.
In following example, before the P layer, with this surface treatment of implementing like the parameter in the table 2 efficient of this solar cell has been increased by 2.09% (table 3) and reached the half the of this gain (seeing the EQE of Figure 10) aspect the current density.
Table 2
SiH 4 H 2 TMB/H 2 CH 4 Power Pressure Frequency Temperature Time
(sccm) (sccm) (sccm) (sccm) (W) (mbar) (MHz) (℃) (s)
pμc-Si:H 62 1800 3.3 0 400 2 40.68 200 70
p?a-SiC:H 50 98 58 95 40 0.5 40.68 200 35
Surface treatment 62 1800 0 0 400 2 40.68 200 5
pμc-Si:H 62 1800 3.3 0 400 2 40.68 200 65
p?a-SiC:H 50 98 58 95 40 0.5 40.68 200 35
Table 3
Jsc?QE Voc FF Efficient
(mA/cm 2) (mV) (%) (%)
Standard < p > 16.81 903.03 70.67 10.73
Surface treatment+< p > 16.98 911.00 70.80 10.95
Relative gain (%) 1.02 0.88 0.18 2.09
For the example of standard p layer, form by two steps (top of table 2) here:
1.p μ c-Si:H-is to be suitable for the condition deposition p layer of microcrystal silicon material.
2.p the p doped layer of the alloy of a-SiC:H-deposition of amorphous silicon and carbon.
The silicon layer that is proposed piles up, and its surface treatment comprises 3 steps (bottom of table 2):
1. surface treatment: with these tco layer 42 of short duration exposing to the open air (5 seconds) in plasma with p μ c condition, and non-impurity-doped gas, it is identical with subsequent step 2 that this plasma condition is selected as, but do not have any impurity gas.
2.p μ c-Si:H-is being used under the condition of micro crystal material, deposition p layer 65 seconds.
3.p the p doped layer of the alloy of a-SiC:H-deposition of amorphous silicon and carbon.
Table 3 illustrates absolute value and this relative gain of the unijunction amorphous solar cell with " standard p " and " surface treatment+standard p layer " of the present invention.
Said this example of table 2 will be showed the result, but not be restrictive.This treatment temperature can change between 150 and 280 ℃, and this does not comprise the main idea of motion.Frequency between 13.56MHz and 82MHz (harmonic wave of 13.56MHz) can successfully be used.To this depositing operation, SiH 4, H 2With alloy (if having) CH 4, TMB, PH 3Between ratio be correlated with and can easily obtain from table 2.The power that is applied in this process cavity will influence the deposition rate of expectation, but also will influence the crystallinity and the stability thereof of this layer.Because of this battery in this example has 1cm 2Size, every cm 2Corresponding power density can easily obtain from table 2.
To understand; This invented technology should be the technology that is used for dopant deposition silicon layer on the TCO surface; It is included in the first plasma-treating technology step of carrying out under first group of technological parameter; And being connected on the second plasma deposition process step thereafter, this second plasma deposition process step has the technology of identical in fact (first) group and mixes number, but comprises impurity gas or predecessor.For example, this p-μ c layer deposits with following condition: silane concentration (SiH 4/ H 2) between 0.1% and 10%, preferably between 1% and 5%, concentration of dopant (alloy/silane) is between 0.01% to 1%, preferably between 0.05% and 0.5%, power density is 10mW/cm 2To 1W/cm 2, preferably between 50mW/cm 2With 300mW/cm 2Between, pressure between 0.5 and 12mbr between.With respect to first add the duration of second processing step the shared time score of first processing step should be between 5% and 20%, and/or, in absolute value, between 3 and 15 seconds, preferably between 5 and 10 seconds.This above-mentioned parameter for operation under 40MHZ, have an approximate 3000cm 2The KAI-M PECVD reactor of electrode surface be typical.
This manufacturing process can get a promotion commercial KAI 1200 that obtains or the similar industrial reactor from Oerlikon Solar.This TCO (ZnO) layer can deposit on also from system Oerlikon Solar, that be called TCO 1200.
The inventive method can useful mode be applied in all types of thin film silicon photovoltaic layers piles up, and the window layer that wherein mixes should be deposited in the positive contact of TCO.This silicon photovoltaic layer pile up can be the unijunction amorphous, that tandem junction amorphous/crystallite piles up, tandem junction amorphous etc.
The anti-reflex treated of III.DART-diffusion
Be used for making the method for photovoltaic device through improving carrier substrate
It is No.61/243 that this part of present patent application is taken from the sequence number of submitting to United States Patent (USP) trademark office on September 18th, 2009 in fact, 689 U.S. Provisional Application, and it relates to improving and is used for based on the thin-film solar cells of silicon or the manufacturing process of module.More detailed, present patent application relates to the substrate that is used for thin film silicon solar cell or the treatment process of cover plate (superstrate).
The shortcoming of III.1 prior art
Description of drawings
As stated, the present invention is described in detail through example and the accompanying drawing that is comprised.These illustrate:
Fig. 1: scanning electron microscopy (SEM) micrograph on the surface of LPCVD-ZnO type A.
Fig. 2: the total transmittance (last figure does not have index matching fluid body (index matching liquid) through measuring) and diffuse transmissivity (figure) that are deposited on the LPCVD-ZnO type A on the glass (the Schott Borofloat 33 of thickness 1mm).
Fig. 3: result in 2008; As the V that soaks into the function of the i-layer thickness in the state at initial and light Oc, J Sc, FF value and efficient [7].LPCVD-ZnO is as positive TCO (mist degree in 600 nanometers is 20%).This i-layer thickness is changed to 400 nanometers from 180; And deposition rate is for for the statistics of improving, and considers 4 to 7 batteries (for every kind of thickness).
Fig. 4: result in 2009; As the V that soaks into the function of the i-layer thickness in the state at initial and light Oc, J Sc, FF value and efficient.LPCVD-ZnO type A is as positive TCO (mist degree in 600 nanometers is 12%).This i-layer is changed to 350 nanometers from 180; And deposition rate is
Figure BPA00001522653800202
for for the statistics of improving, and considers 4 to 7 batteries (for every kind of thickness).
Fig. 5: record-breaking unijunction a-Si:H light prepared by Oerlikon Solar-Lab and that measure soaks into battery.
Fig. 6: for the I (V) of a-Si:H unijunction solar cell (NREL affirmation) resulting record-breaking stabilization efficiency (10.09%).This cell deposition is in R&D KAI TMIn-M the system (52x41 square centimeter substrate size).Employed cover plate is Schott Borofloat 33 glass of 1mm, deposits the LPCVD-ZnO (ZnO type B) with high haze factor above that.On this battery, apply our inner AR.
Fig. 7: derive from NREL gets short-circuit current density under relative QE and the AM1.5 to record-breaking battery 3497 measured NREL absolute external quantum efficiency (abs EQE).The battery of this 250 nanometer i-layer thickness before under open circuit voltage conditions light soak into.
I (V) curve of last best p-i (180 the nanometer)-mini module of n a-Si:H (light soaks into) 10x10 square centimeter of Fig. 8: LPCVD-ZnO is by measured the obtaining in ESTI laboratory of the JRC of Ispra.
Fig. 9: basic, simple photovoltaic cell.
Figure 10: external quantum efficiency (EQE) data.
Figure 11: the total reflectance through measuring of a series of glass/TCO/a-Si:H pin/TCO structure.
Figure 12: through the scanning electron microscopy of the treated surface of Schott Borofloat 33 glass of etching (5 minutes Cement Composite Treated by Plasma).
Figure 13: through the scanning electron microscopy of the treated surface of Schott Borofloat 33 glass of etching (120 minutes Cement Composite Treated by Plasma).
Figure 14: for not having (no AR, downside curve) and measured external electrical efficient (EQE) curve of series connection amorphous/crystallite stack of cells with DART processing (120 minutes, the upside curve).
Figure 15: the standard A M1.5I of three engaged test batteries (V) curve.
Figure 16: the transmission electron microscopy figure of the section through the a-Si:H pin solar cell that PECVD deposited.
Figure 17: the simple equivalent circuit of coarse substrate upper film silicon solar cell illustrates and leaks the border.
Figure 18 illustrates and leaks the dark current J of boundary density to microcrystalline silicon solar cell 02Influence.
Figure 19 illustrates the influence of ozone exposure time to pin device yield with the positive types of two kinds of different TCO.
The foregoing description is as an example, and should not limit the present invention.
[list of references]
[1]U.Kroll?et?al.,Thin?Solid?Films?451-452(2004),pp.525-530.
[2]U.Kroll?et?al.,Proc?19th?EU?PVSEC(Paris?2004),paper3AO.8.1.
[3]J.Meier,J.Spitznagel,U.Kroll,C.Bucher,S.Fay,T.Moriarty,A.Shah,Thin?Solid?Films?451-452(2004)p.518.
[4]O.Kluth?et?al,Proc?20th?EU?PVSEC(Barcelona?2005),paper3DV.3.38.
[5]U.Kroll?et?al.,Proc.23rd?EU?PVSEC(Milan?2007),paper3CO.1.2,p.1795-1800.
[6]S.Benagli?et?al.,Proc.21st?EU?PVSEC(Dresden?2006),paper3DV.3.42,p.1719-1723.
[7]S.Benagli?et?al.,Proc.24th?EU?PVSEC(Valencia?2008),paper3AV.2.23,p.2414-2418.
[8]J.Meier?et?al,Proc?19th?EU?PVSEC(Paris?2004),paper3BP.1.2.
[9]J.Meier?et?al.,Proc.3rd?WCPEC(Osaka?2003)session?S2.
[10]M.A.Green,Keith?Emery,Yoshihiro?Hishikawa?and?Wilhelm?Warta,Progress?in?PhotoVoltaics:Research?and?Applications?2009;17:320-326.

Claims (19)

1. method that is used to make amorphous silicon p-i-n solar cell; Said battery comprises that the LPCVD ZnO front of ARC and doping contacts with the back side; Wherein, The positive contact with the back side of the LPCVD ZnO of said doping is the polycrystalline film that is made up of large-scale shot-like particle, and the end of said large-scale shot-like particle is rendered as pyramid at growing surface, and said method comprises:
-through the said positive contact of LPCVD deposition;
-deposit the silicon layer of said p-i-n solar cell through plasma enhanced chemical vapor deposition;
-deposit the contact of the said back side through LPCVD;
-said ARC is provided.
2. at least one in the method for claim 1, wherein following is suitable for:
-said method comprises Schott Borofloat 33 glass that use 1mm as cover plate, has the LPCVD-ZnO of 70% haze factor in 600 nanometers in said Schott Borofloat 33 deposition on glass;
-said battery has stable cell efficient, especially 10.09% the stable cell efficient that stops above 10%;
-said method is included in the said silicon fiml of deposition in the single chamber pecvd reactor, especially in Oerlikon Solar KAI system;
-said method comprises contact of the said back side and the combination of white reflection body;
The said i layer of deposition rate deposit that-said method is included in
Figure FPA00001522653700011
;
-said i layer has the optical band gap of 1.73eV;
-said i layer has the thickness of 250 nanometers;
-said method comprises through laser patterning and makes up said battery.
3. like claim 1 or the described method of claim 2; Said amorphous silicon p-i-n battery comprises the substrate/p-i-n junction structure with glass/air interface; Said glass/air interface is owing to said ARC has the antireflection ability; Said method comprises provides the glass substrate/p-i-n junction structure with glass/air interface, and follows the said glass surface of the said air/glass interface of DART etching, so that the light scattering ability (D) of said antireflection (AR) and expectation to be provided.
4. method as claimed in claim 3 wherein, is carried out etching so that antireflection ability (AR) to be provided in the interim very first time, and (AR+D) provides the amount of light scatter of increase with extraly during the second selected time interval, carrying out said etching extraly.
5. like claim 3 or the described method of claim 4, comprise at least one in the following characteristic:
-said glass substrate/p-i-n junction structure comprises first electrode, semiconductive thin film p-i-n or the n-i-p knot and second electrode; It sequentially is stacked on the said substrate, is stacked on the said substrate the positive contact of especially said LPCVD ZnO, said silicon layer and said LPCVD ZnO back side engagement sequence;
-said glass substrate/p-i-n junction structure comprises transparent glass substrate, and said transparent glass substrate has deposition including transparent conducting oxide layer on it, especially has deposition said LPCVD ZnO front contact layer on it;
-after said glass substrate/p-i-n junction structure is provided, set up antireflection and scattering power through etching.
6. like the described method of one of claim 4 and claim 5, further may further comprise the steps: only before carrying out said etching during said second time interval, see through the step that said glass/air interface is carried out laser patterning.
7. like the described method of one of claim 3 to claim 6, wherein, carry out said etching through reactive ion etching.
8. like the described method of one of claim 3 to claim 8, comprise through following and protect said p-i-n junction structure that especially said silicon layer avoids it to receive the step of the influence of the said glass surface of said etching:
-temporary transient mechanical device, the carrier that preferably has the clamping framework is installed, and wherein, said framework provides sealing device, and it allows only to expose the etched said glass surface of needs; Perhaps pass through
-removable adhesive film or removable coating, preferably, white reflection body coating.
9. like one of aforementioned claim described method, wherein, said amorphous silicon p-i-n solar cell comprises:
-substrate; And
-the first electrode, the positive contact of especially said LPCVD ZnO, semiconductive thin film p-i-n or n-i-p knot, the especially said silicon layer and second electrode, the contact of the especially said LPCVD ZnO back side, it sequentially is stacked on the said substrate;
Wherein, said method comprises:
-said substrate is provided and is stacked in said first electrode and said at least one knot on the said substrate;
-make the surface of said knot stand controlled oxidation, deactivate the leakage border so that see through said at least one knot;
-said second electrode directly or is indirectly put on the said surface of standing said oxidation.
10. method as claimed in claim 9, wherein, said amorphous silicon p-i-n solar cell has at least one in the following characteristic:
-be thin-film solar cells;
-be thin film silicon solar cell;
-said surface is the surface of the membrane silicon layer that is deposited at last;
-said substrate is transparent, is preferably glass, especially Schott Borofloat 33 glass;
-said first electrode comprises or is deposited on the transparent conductive oxide on the said substrate, the positive contact of the LPCVD ZnO of especially said doping;
-said at least one knot comprises microcrystal silicon or amorphous silicon or both combinations of hydrogenation;
The thickness of the i layer of-said knot is less than 200 nanometers, and the thickness of said p layer is less than 10 nanometers, and said knot p-i-n knot preferably;
-said surface is the surface of n layer, preferably deposits through PECVD;
-said second electrode deposits under about 200 ℃ temperature;
-said first electrode comprise or said substrate on the transparent conductive oxide that deposited; And preferably has texture on its surface; Said at least one knot is applied on the surface of said first electrode, and said conductive oxide preferably has the ZnO of roughness greater than the texture of 100 nanometer RMS.
11. like claim 9 or the described method of claim 10, wherein, said surface
-be exposed to and be rich in H 2O and/or 30%H 2O 2Atmosphere in, preferably, under 100 ℃ temperature 1 to 2 hour; Perhaps
-at room temperature be exposed in the ozone about 1 hour; Perhaps
-under about 100 ℃ temperature, be exposed in the ozone, preferably, 5 to 15 minutes; Perhaps
-under the pressure of 0.5mbar, be exposed in the ozone 15 minutes; Perhaps
-be exposed under the oxidation plasma, preferably, be exposed to and contain C 2F 6, CO 2, O 2Or SF 6Atmosphere in, preferably, at 300mW/cm 2Under the power of electrode area, and preferably, under 200 ℃ temperature, preferably, surpass 10 seconds but be no more than one minute,
Said surface is the surface of n layer preferably.
12. like the described method of one of claim 9 to claim 11, wherein, utilize the oxidant of accepting electronics to carry out said oxidation, said oxidant is at least one in oxygen, fluorine, sulphur, chlorine, the nitrogen.
13. like the described method of one of claim 9 to claim 12, wherein, said exposure is performed maximum 5 minutes.
14. like one of aforementioned claim described method, wherein, said amorphous silicon p-i-n solar cell comprises:
-substrate;
-first electrode layer on said substrate comprises transparent conductive oxide, especially, and the positive contact of said LPCVD ZnO;
-stack layer on said first electrode layer; Comprise the semiconductor layer that is just mixing, the semiconductor layer and the negative semiconductor layer and the second electrode lay that mixes of intrinsic; Especially, wherein, these Stacket semiconductor layers are said silicon layers of said p-i-n solar cell; And the particularly said LPCVD ZnO of said the second electrode lay back side contact
Said method comprising the steps of:
-said substrate is provided;
-said first electrode layer of deposition on said substrate, said first electrode layer comprises said transparent conductive oxide and has the surface;
-in the interim very first time, handle said surface through first vacuum processing technique;
-through during second time interval, second vacuum technology of in the processing atmosphere that comprises the gaseous state alloy, carrying out on the said surface of handling through said first vacuum processing technique, deposits in said positive doped layer and the said negative doped layer;
-said first vacuum processing technique of execution in the processing atmosphere that comprises the gaseous state alloy; This gaseous state alloy is different with the amount that in the said atmosphere of said second vacuum technology, comprises; But carry out said first vacuum processing technique identical in others, and select the said very first time interval shorter than said second time interval with said second vacuum technology.
15. method as claimed in claim 14, it is included in and comprises SiH 4And H 2And in the atmosphere of gaseous state alloy; Carry out said first vacuum processing technique as vacuum plasma treatment technology; The gaseous state concentration of dopant of this gaseous state concentration of dopant in the atmosphere that is present in said second vacuum technology 0% to 80% between; Preferably between 0% to 20%, thus, preferably deposit said positive doping semiconductor layer by said second vacuum technology.
16. method as claimed in claim 14, wherein, said second vacuum technology is the vacuum plasma body technology.
17. method as claimed in claim 14; The wherein said very first time be selected at interval between this first and second time interval and 5% to 20% between; And wherein preferably said second vacuum technology is the vacuum plasma body technology, and following be effective one of at least:
-said the doping semiconductor layer that deposited by said second vacuum technology is said positive doping semiconductor layer;
-said doping semiconductor layer is to comprise SiH 4To H 2Concentration be 0.1% to 10%, be preferably and deposit in 1% to 5% the atmosphere;
-said doping semiconductor layer is to comprise SiH 4Atmosphere in deposit, and in said atmosphere this alloy to SiH 4Concentration be 0.1% to 10%, be preferably 0.05% to 0.5%;
-said doping semiconductor layer is to be 10mW/cm in power density 2To 1W/cm 2, preferably between 50mW/cm 2With 300mW/cm 2Between the deposition;
-said doping semiconductor layer is to the total pressure deposit of 12mbar at 0.5mbar;
-said doping semiconductor layer is in the technological temperature deposit between 1500 ℃ to 2800 ℃;
-said doping semiconductor layer is is 13.56MHz with the frequency to the Rf power deposition of 82MHz.
18. amorphous silicon p-i-n solar cell; The p-i-n that comprises ARC, silicon layer ties, reaches the LPCVD ZnO front of mixing and contacts with the back side; Wherein, The positive contact with the back side of the LPCVDZnO of said doping is the polycrystalline film that is made up of large-scale shot-like particle, and the end of said large-scale shot-like particle is rendered as pyramid at growing surface.
19. amorphous silicon p-i-n solar cell as claimed in claim 18, wherein, at least one in following is suitable for:
-Schott Borofloat 33 glass that said amorphous silicon p-i-n solar cell comprises 1mm are as cover plate, have the LPCVD-ZnO of 70% haze factor in 600 nanometers in said Schott Borofloat 33 deposition on glass;
-said battery has stable cell efficient, especially 10.09% the stable cell efficient that stops above 10%;
-said silicon fiml is deposited in the single chamber pecvd reactor, especially in Oerlikon Solar KAI system;
-said back side contact and the combination of white reflection body;
-said i layer deposits with the deposition rate of
Figure FPA00001522653700061
;
-said i layer has the optical band gap of 1.73eV;
-said i layer has the thickness of 250 nanometers;
-said battery makes up through laser patterning.
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