WO2011018835A1 - Semiconductor drive device and power conversion device - Google Patents

Semiconductor drive device and power conversion device Download PDF

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Publication number
WO2011018835A1
WO2011018835A1 PCT/JP2009/064136 JP2009064136W WO2011018835A1 WO 2011018835 A1 WO2011018835 A1 WO 2011018835A1 JP 2009064136 W JP2009064136 W JP 2009064136W WO 2011018835 A1 WO2011018835 A1 WO 2011018835A1
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Prior art keywords
voltage
unit
pulse
output
drive
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PCT/JP2009/064136
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French (fr)
Japanese (ja)
Inventor
順一 坂野
正剛 行武
高志 平尾
恭彦 河野
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株式会社日立製作所
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Priority to JP2011526652A priority Critical patent/JP5462880B2/en
Priority to PCT/JP2009/064136 priority patent/WO2011018835A1/en
Publication of WO2011018835A1 publication Critical patent/WO2011018835A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit

Definitions

  • Power converters are used everywhere, including transportation such as high-speed railways, power generation facilities such as wind power generation, and other factories and construction sites.
  • a semiconductor driving device for a power semiconductor used in a power conversion device such as an inverter
  • an insulated communication circuit that performs communication while ensuring insulation is provided between the upper control circuit and the power semiconductor.
  • there is a method of communicating via an insulation transformer using magnetic coupling see, for example, Patent Document 1).
  • An object of the present invention is to ensure high reliability against noise and defects in a circuit (to be robust), and to use a small power semiconductor drive device and a high reliability and small size using the semiconductor drive device.
  • the object is to provide a high-performance power converter.
  • a semiconductor drive device is a semiconductor drive device that controls the on / off operation of a semiconductor switching element.
  • a command signal driving unit that generates a continuous pulse voltage signal
  • an insulated communication unit that transmits a continuous pulse voltage signal generated by the command signal driving unit using a transformer, and a continuous signal transmitted through the insulating communication unit.
  • an output unit that generates and outputs a drive voltage for driving the semiconductor switching element to be turned on so as to fill a gap between pulses constituting the continuous pulse based on a voltage signal of the pulse.
  • a power conversion device including a semiconductor switching element and a semiconductor drive device that drives and controls the semiconductor switching element.
  • the semiconductor drive device includes the semiconductor switching device.
  • an instruction signal driving unit that generates a voltage signal of a continuous pulse that commands the ON driving, and an insulation that transmits a voltage signal of the continuous pulse generated by the command signal driving unit by a transformer
  • a driving voltage for turning on the semiconductor switching element is generated so as to fill a gap between the pulses constituting the continuous pulse.
  • an output unit for outputting the output.
  • FIG. 1 It is a figure which shows the structure of the power converter device using the semiconductor drive device which concerns on the 1st Embodiment of this invention. It is a figure which shows the voltage waveform in each point which comprises a semiconductor drive device. It is a figure which shows the specific structural example of a semiconductor drive device. It is a figure which shows the voltage waveform in each point which comprises a semiconductor drive device. It is a figure which shows the structural example which further improved the noise tolerance of the determination part. It is a figure which shows the circuit structure of a voltage adjustment circuit. It is a figure which shows the circuit structure of a voltage adjustment circuit. It is a figure which shows the structure of a voltage adjustment circuit. It is a figure which shows the structure of the power converter device using the semiconductor drive device which concerns on the 2nd Embodiment of this invention.
  • FIG. 1 is a diagram showing a configuration of a power conversion device 100 using a semiconductor drive device 10 according to an embodiment of the present invention.
  • the power conversion device 100 includes a semiconductor drive device 10, an IGBT (Insulated Gate Bipolar Transistor) semiconductor switching element Q ⁇ b> 1 whose gate voltage is controlled by the output of the semiconductor drive device 10, a load 4, and a power supply And 5.
  • IGBT Insulated Gate Bipolar Transistor
  • the semiconductor drive device 10 includes a command signal drive unit 1 that receives a drive command IN to which a command signal is input, an insulated communication unit 2 that receives an output of the command signal drive unit 1, and an output of the insulated communication unit 2. And an output unit 3 as an input.
  • the command signal drive unit 1 includes a continuous pulse generation unit 6 and a drive unit 7.
  • the output unit 3 includes a determination unit 8 and an output pulse generation unit 9.
  • FIG. 2 is a diagram illustrating a voltage waveform at each point constituting the semiconductor drive device 10.
  • the command signal drive unit 1 is configured so that the continuous pulse generator 6 generates a continuous pulse voltage Va having a predetermined period corresponding to the ON period of the drive command IN (command signal ON shown in FIG. 2; hereinafter referred to as command signal ON). 1 (see point A shown in FIG. 1, see FIG. 2), and the drive unit 7 applies a pulse voltage to the insulating communication unit 2 in accordance with the pulse voltage Va.
  • the insulating communication unit 2 uses an insulating transformer (pulse transformer), and a pulse voltage from the driving unit 7 is applied between the transmission side (input side) terminals of the insulating transformer.
  • the determination unit 8 outputs a pulse voltage Vb corresponding to the pulse voltage between the reception side (output side) terminals of the insulation transformer of the insulation communication unit 2 (see point B shown in FIG. 1, see FIG. 2).
  • the pulse voltage Vb to which the output pulse generator 9 is input one pulse of a drive voltage Vout having a constant width longer than the cycle of the pulse voltage Va is output. This drive voltage Vout turns on the gate of the semiconductor switching element Q1. Further, when a plurality of pulse voltages Vb are input, the output unit 3 adds the pulse width of the drive voltage Vout based on the plurality of pulse voltages Vb.
  • the drive voltage (Vout) for turning on the gate of the semiconductor switching element Q1 is output from the output pulse generator 9 during the period in which the pulse voltage Va of a predetermined cycle is output from the continuous pulse generator 6 (See FIG. 2).
  • the semiconductor drive device 10 turns on the gate of the semiconductor switching element Q1 in accordance with the period during which the command signal ON is input to the drive command IN.
  • the semiconductor switching element Q1 when the semiconductor switching element Q1 is turned on, the potential of the on command output side GND 21 rises to about the voltage VB of the power supply 5 with respect to the drive command side GND 20. This potential difference is applied to the insulating communication unit 2.
  • the accuracy of the pulse width of the voltage for turning on the gate of the semiconductor switching element Q1 is increased, that is, the pulse width of the drive command IN and the drive voltage Vout. Need to match well. For this purpose, it is desirable to shorten the pulse width for outputting one pulse by the output pulse generator 9 and to increase the number of pulses per time.
  • the actual design is designed with a sufficient noise margin, but even if unexpected noise enters the circuit of the apparatus, the semiconductor switching element Q1 corresponding to the noise generation period is used. Although a gate-on voltage is generated, a malfunction is not maintained as in the case of using a conventional latch circuit, so that although the gate is turned on only for a short time, the normal operation can be restored by the disappearance of noise.
  • the gate of the semiconductor switching element Q1 has an input capacitance and also functions as a low-pass filter, if the pulse width at the time of outputting one pulse of the output pulse generator 9 is set sufficiently short, the semiconductor switching element Q1 The gate voltage (drive voltage Vout) is not increased to the threshold voltage, and the gate is prevented from being turned on accidentally.
  • the power conversion device 100 can be connected to the reception side (output side) of the insulation communication unit 2 even when a problem such as disconnection of wiring in the circuit from the drive command IN of the semiconductor drive device 10 to the insulation communication unit 2 occurs. Since no pulse voltage is generated, the gate of the semiconductor switching element Q1 is maintained in an off state so as not to cause a problem in the circuit.
  • FIG. 3 is a diagram illustrating a specific configuration example of the semiconductor drive device 10.
  • the continuous pulse generator 6A includes an AND circuit 22 and generates a continuous pulse by taking a logical product of a command signal (IN) and a clock signal (CLK) supplied from inside or outside.
  • I command signal
  • CLK clock signal
  • the drive unit 7 applies the pulse voltage (point D) having a predetermined width tp generated by the driver 26 in the rising edge pulse generation circuit 24 to one terminal of the winding on the drive command side of the insulation transformer 12.
  • the driver 27 applies the pulse voltage (point E) having a predetermined width tp generated by the falling edge pulse generation circuit 25 to the other terminal of the winding on the drive command side of the insulating transformer 12.
  • the drive command side GND 20 is connected to the driver 26 and the driver 27.
  • the driver controller 17 of the drive unit 7 issues a command to set the output stage of the drive circuit 19 to high impedance during a period in which the drive circuit 19 does not transmit the pulse voltage compared to a period in which the pulse voltage is transmitted. Specifically, the driver controller 17 turns off the output stages of the drivers 26 and 27 included in the drive circuit 19 while the drive circuit 19 does not transmit a pulse voltage.
  • the voltage Vs is applied between the drive command side (transmission side) terminals of the isolation transformer 12 and the voltage Vt is applied between the on command output side (reception side) terminals of the isolation transformer 12. Is output.
  • the inter-terminal voltage Vs and inter-terminal voltage Vt at this time are shown in FIG.
  • the determination unit 8 that determines whether the inter-terminal voltage Vt of the isolation transformer 12 is positive or negative, it is possible to remove common-mode noise caused by the parasitic capacitances (C1, C2) of the transformer shown in FIG. This is because the potential difference Vh between the on command output side GND 21 and the drive command side GND 20 generated when the semiconductor switching element Q1 is turned on and off in the power conversion device 100 of FIG. 1 is changed by the voltage change dVh / dt.
  • the voltage adjustment circuit 203 has an input side connected to the terminal of the isolation transformer 12 to which one end of the receiving resistor 29 is connected, and an output side connected to the ⁇ input terminal of the comparator 31.
  • the voltage adjustment circuit 204 has an input side connected to the terminal of the isolation transformer 12 to which one end of the receiving resistor 28 is connected, and an output side connected to the + input terminal of the comparator 31.
  • the voltage adjustment circuits 201 and 203 are circuits that adjust the reference voltage level in the determination of the + input terminals of the comparators 30 and 31.
  • FIG. 6 shows a circuit configuration of the voltage adjustment circuits 201 and 203, and includes a diode 211, a resistor (Rad1) 213, and a resistor (Rad2) 214.
  • the input voltage becomes a DC voltage Vdc by the diode 211.
  • the determination reference level rises almost in proportion to this voltage rise.
  • the command signal drive unit 1A includes a continuous pulse generation unit 6, a drive unit 7 including an edge trigger pulse generation circuit 15 and a drive circuit 19, and a reception-compatible drive command unit 73.
  • the output unit 3A includes a determination unit 8, an output pulse generation unit 9, and a transmission-accepted reception signal processing unit 76.
  • the status output unit 66 includes an output pulse generation unit 78, a transmission-compatible received signal processing unit 79, and a determination unit 80.
  • the determination unit 80 uses an input side (transmission side) terminal of the insulation transformer 12 of the insulation communication unit 2 as an input.
  • the state signal drive unit 67 includes a drive unit 82 including a drive circuit 81a and an edge trigger pulse generation circuit 81b, a continuous pulse generation unit 83, a state determination unit 84, and a reception-compatible drive command unit 85.
  • the state determination unit 84 receives the voltage between the gate and the emitter of the semiconductor switching element Q1.
  • the output of the drive circuit 81 a is input to the output side (reception side) terminal of the isolation transformer 12 of the isolation communication unit 2.
  • the reception-compatible drive command unit 85 of the state signal drive unit 67 issues a command to set the output stage of the drive circuit 81a to high impedance in a period in which the drive circuit 81a does not transmit a pulse compared to a period in which the pulse is transmitted. Specifically, the reception-compatible drive command unit 85 turns off the output stage of the drive circuit 81a while the drive circuit 81a does not transmit a pulse.
  • the reception-compatible drive command unit 73 of the command signal drive unit 1A issues a command to set the output stage of the drive circuit 19 to high impedance in a period in which the drive circuit 19 does not transmit the pulse voltage compared to a period in which the pulse voltage is transmitted. put out. Specifically, the reception-capable drive command unit 73 turns off the output stage of the drive circuit 19 during a period in which the drive circuit 19 does not transmit a pulse.
  • the output impedance of the drive circuit 19 in the command signal drive unit 1A is the reception resistance (reception resistors 28 and 29 shown in FIG.
  • the insulating communication unit 2 receives a continuous pulse voltage that turns on the gate of the semiconductor switching element Q1, the equivalent impedance on the receiving side is increased, and less current from the drive circuit 19 is obtained. Transmission is possible, and the drive circuit 19 can be reduced in size and loss.
  • a pulse from the state signal driving unit 67 (state signal P determined that the gate of the semiconductor switching element Q1 is turned on) is a command signal (semiconductor switching) as indicated by the inter-terminal voltage Vt on the output side of the isolation transformer 12.
  • the output is delayed by time td so that it does not overlap with the command signal.
  • a pulse (state signal P) is transmitted at the frequency of the clock signal (tck2) generated by the continuous pulse generator 83 of the state signal driver 67 (See FIG. 9).
  • the continuous pulse generator 6 of the command signal driver 61 generates and transmits a pulse at the frequency of the clock signal (tck1) (see FIG. 9).
  • tdon is a delay time for turning on the gate of the semiconductor switching element Q1
  • tdoff is a delay time for turning off the gate of the semiconductor switching element Q1. It is.
  • the determination unit 80 receives a pulse voltage corresponding to the pulse voltage Vs between the transmission side (input side) terminals of the isolation transformer 12, and the output pulse generation unit 78 is based on the input pulse voltage.
  • An edge trigger on-state detection signal having a pulse width tw longer than 1 ⁇ 2 of the period tck1 (tck2) of the clock signal (CLK) is output to the host device (not shown) through the input terminal STATE.
  • FIG. 10 is a diagram illustrating a configuration example of the semiconductor drive device 10 b using the full-wave rectifier circuit 44.
  • FIG. 11 is a diagram showing voltage waveforms at respective points constituting the semiconductor drive device 10b.
  • the semiconductor drive device 10b has the same basic configuration, and includes a command signal drive unit 41, an insulation communication unit 42, and an output unit 43.
  • the output unit 43 is provided with a full-wave rectifier circuit 44 instead of the determination unit.
  • the differential voltage Vc at the output side terminal of the insulating transformer 53 is rectified by the full-wave rectifier circuit 44, so that the differential voltage Vd (point H in FIG. 10). ) Can be easily obtained (see FIG. 11), and the determination / output pulse generation circuit 46 can be simplified. Further, if the transmission signal from the command signal drive unit 41 is transmitted as a continuous rectangular wave, the semiconductor switching is performed when the output (differential voltage) Vd voltage level of the filter circuit 45 is high (predetermined threshold level). An output that turns on the gate of the element Q1 may be used, and the determination / output pulse generation circuit 46 can be simplified.
  • the clock signal (CLK) shown in FIG. 11 is simplified to illustrate the relationship between the differential voltage Vc and the differential voltage Vd.
  • the clock signal (CLK) shown in FIGS. ) And the same period tck.
  • FIG. 12 is a diagram illustrating another configuration example of the insulated communication unit 2A.
  • the insulating communication unit 2A has two insulating transformers 92 and 94 connected in series.
  • a GND 96 is connected via a capacitor 98 to the insulation transformer 92 side of the connection point where the insulation transformer 92 and the insulation transformer 94 are connected in series, and a GND 97 is connected via the capacitor 99 to the insulation transformer 94 side of the connection point.
  • a voltage difference is generated between GND 96 and GND 97, capacitors 98 and 99 are applied even if imbalance occurs between the parasitic capacitance 93 of the insulating transformer 92 and the parasitic capacitance 95 of the insulating transformer 94.
  • the voltage is shared equally.
  • the voltage applied to each isolation transformer can be kept low even if the isolation transformers are connected in series, and a miniaturized isolation communication unit can be configured.
  • the capacitors 98 and 99 have a small capacitance from the viewpoint of noise resistance, and it is sufficient that the unbalance of the parasitic capacitances 93 and 95 can be adjusted. It is. As a result, the semiconductor drive device can be reduced in size.
  • FIG. 13 is a diagram illustrating a configuration example of the power conversion device 200 using the semiconductor drive devices 109, 114, 119, 120, 121, and 122.
  • Each of the semiconductor drive devices 109, 114, 119, 120, 121, and 122 corresponds to the semiconductor drive device 10a.
  • This application example includes semiconductor drive devices 109, 114, 119, 120, 121, and 122 that drive semiconductor switching elements Q11, Q12, Q13, Q14, Q15, and Q16 that receive a command from the higher-order logic circuit 101.
  • This is a three-phase inverter type power converter 200 that drives a certain motor 123.
  • the higher-order logic circuit 101 is configured using, for example, a microcomputer, and includes an ON command calculation circuit 102 and continuous pulse generation units 103 and 104.
  • the on command calculation circuit 102 sends the on / off command signal (IN) of the semiconductor switching elements (Q11, Q12, Q13, Q14, Q15, Q16) and the clock signal (CLK) to the continuous pulse generators 103, 104. Supply.
  • a command signal (IN) for turning on the gate of the semiconductor switching element is referred to as a command signal on (IN).
  • the higher-order logic circuit 101 includes a continuous pulse generator (not shown) corresponding to each of the semiconductor driving devices 119, 120, 121, and 122, and each continuous pulse generator (not shown) is a protection circuit (not shown). ) To the respective semiconductor drive devices (119, 120, 121, 122).
  • the semiconductor drive device 109 includes a drive unit 110, an insulation communication unit 111, an output unit 112, a state output unit 113, and a state signal drive unit 130.
  • the drive unit 110 corresponds to the drive unit 7
  • the insulated communication unit 111 corresponds to the insulated communication unit 2
  • the output unit 112 corresponds to the output unit 3A.
  • the state output unit 113 corresponds to the state output unit 66
  • the state signal drive unit 130 corresponds to the state signal drive unit 67.
  • the driving unit 110 applies a pulse voltage to the insulating communication unit 111 in accordance with a continuous pulse supplied via the protection circuit 107.
  • the insulation communication unit 111 is configured by an insulation transformer, and a pulse voltage from the drive unit 110 is applied between the transmission side (input side) terminals of the insulation transformer, and a pulse is generated between the reception side (output side) terminals of the insulation transformer. The voltage is output to the output unit 112.
  • the output unit 112 outputs a drive voltage having a certain width to the gate of the semiconductor switching element Q11 based on the input pulse voltage. This drive voltage turns on the gate of the semiconductor switching element Q11.
  • the state signal driving unit 130 determines the ON state of the semiconductor switching element Q11 and transmits a state signal to the reception side of the insulated communication unit 111.
  • the state output unit 113 outputs a state signal received on the transmission side of the insulated communication unit 111 to the drive unit 115 of the semiconductor drive device 114.
  • the semiconductor drive device 114 can detect the on / off state of the semiconductor switching element Q11 when a state signal is input to the drive unit 115.
  • the semiconductor drive device 114 includes a drive unit 115, an insulation communication unit 116, an output unit 117, a state output unit 118, and a state signal drive unit 131.
  • the drive unit 115 corresponds to the drive unit 7
  • the insulated communication unit 116 corresponds to the insulated communication unit 2
  • the output unit 117 serves as the output unit 3A.
  • the state output unit 118 corresponds to the state output unit 66
  • the state signal drive unit 131 corresponds to the state signal drive unit 67.
  • the driving unit 115 applies a pulse voltage to the insulating communication unit 116 in accordance with a continuous pulse supplied via the protection circuit 106.
  • the insulation communication unit 116 is configured by an insulation transformer, and a pulse voltage from the drive unit 115 is applied between the transmission side (input side) terminals of the insulation transformer, and a pulse is generated between the reception side (output side) terminals of the insulation transformer. The voltage is output to the output unit 117.
  • the output unit 117 outputs a drive voltage having a certain width to the gate of the semiconductor switching element Q12 based on the input pulse voltage. This drive voltage turns on the gate of the semiconductor switching element Q12.
  • the state signal driver 131 determines the ON state of the semiconductor switching element Q12 and transmits a state signal to the reception side of the insulated communication unit 116.
  • the state output unit 118 outputs a state signal received on the transmission side of the insulating communication unit 116 to the drive unit 110 of the semiconductor drive device 109.
  • the semiconductor drive device 109 can detect the on / off state of the semiconductor switching element Q12 when a state signal is input to the drive unit 110.
  • the semiconductor switching element Q11 is turned on and off via the state signal driving unit 130, the insulating communication unit 111, and the state output unit 113 of the semiconductor driving device 109 that drives the semiconductor switching element Q11. It is transmitted to the drive unit 115 of the semiconductor drive device 114 of the element Q12.
  • the semiconductor switching element Q12 is turned on and off via the state signal driving unit 131, the insulating communication unit 116, and the state output unit 118 of the semiconductor driving device 114 that drives the semiconductor switching element Q12. Is transmitted to the drive unit 110 of the semiconductor drive device 109.
  • the on / off states of the paired semiconductor switching elements (Q11, Q12) received by bidirectional communication are shared between the upper and lower arms that form a pair of the inverters (semiconductor driving devices 109, 114).
  • the pair arm is on, control is performed so that the own arm is not turned on.
  • the semiconductor drive devices 119 and 120 and the semiconductor drive devices 121 and 122 are controlled as a pair of arms similarly to the semiconductor drive devices 109 and 114 described above.
  • the power conversion device 200 may synchronize the continuous pulse between the semiconductor driving devices with the clock signal from the higher-order logic circuit 101 in order to increase the time accuracy of the ON period.
  • the output may be synchronized.
  • the protection circuit the power conversion device 200 can be a highly accurate and reliable device.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

Provided is a small-size and high-performance semiconductor drive device for electric power which can assure a high reliability against a noise or trouble in a circuit.  Provided is also a small-size power conversion device having a high reliability realized by using the semiconductor drive device. In an instruction signal drive unit (1), a continuous pulse generation unit (6) generates a continuous pulse voltage (Va) of a predetermined cycle corresponding to the ON period of a drive instruction IN, and a drive unit (7) applies a pulse voltage to the transmission side of an insulating communication unit (2) in accordance with the pulse voltage (Va).  In an output unit (3), a determination unit (8) outputs a pulse voltage (Vb) in accordance with the pulse voltage generated at the reception side of the insulating communication unit (2), and an output pulse generation unit (9) outputs one pulse of a drive voltage (Vout) having a constant width longer than the period of the pulse voltage (Va) in accordance with the inputted pulse voltage (Vb).  The drive voltage (Vout) turns ON the gate of a semiconductor switching element (Q1).

Description

半導体駆動装置と電力変換装置Semiconductor drive device and power conversion device
　本発明は、電力用半導体を駆動する半導体駆動装置と、この半導体駆動装置を用いた電力変換装置に関する。 The present invention relates to a semiconductor drive device for driving a power semiconductor and a power conversion device using the semiconductor drive device.
　高速鉄道などの交通手段、風力発電などの発電設備、その他工場や工事現場など、あらゆるところで電力変換装置が使用されている。インバータをはじめとする電力変換装置で用いられる電力用半導体の半導体駆動装置では、上位制御回路と電力用半導体との間の絶縁をとった上で制御信号を伝送する必要がある。このため、上位制御回路と電力用半導体との間に絶縁を確保しながら通信する絶縁通信回路を設けている。このような絶縁通信回路においては、磁気結合を用いた絶縁トランスを介して通信する方法がある（例えば、特許文献１参照）。 Power converters are used everywhere, including transportation such as high-speed railways, power generation facilities such as wind power generation, and other factories and construction sites. In a semiconductor driving device for a power semiconductor used in a power conversion device such as an inverter, it is necessary to transmit a control signal after taking insulation between the host control circuit and the power semiconductor. For this reason, an insulated communication circuit that performs communication while ensuring insulation is provided between the upper control circuit and the power semiconductor. In such an insulation communication circuit, there is a method of communicating via an insulation transformer using magnetic coupling (see, for example, Patent Document 1).
　特許文献１では、送信する信号パルスの立上り若しくは立下りを検出し、これに同期した比較的幅の短いパルスを生成し、このパルスを絶縁トランスの送信側の端子に入力する。その結果として絶縁トランスの受信側に発生するパルス電圧を判定し、判定したパルス電圧に応じて受信側の状態をフリップフロップにより保持させるものである。この方法では、絶縁トランスには比較的短い時間幅の電圧が印加されるため絶縁トランスに流れる電流が少なく、絶縁トランスで問題となる磁気飽和がしにくいという特徴がある。 In Patent Document 1, rising or falling of a signal pulse to be transmitted is detected, a pulse having a relatively short width is generated in synchronization with this, and this pulse is input to a terminal on the transmission side of an insulating transformer. As a result, the pulse voltage generated on the reception side of the insulation transformer is determined, and the state on the reception side is held by a flip-flop according to the determined pulse voltage. This method is characterized in that since a voltage having a relatively short time width is applied to the insulating transformer, the current flowing through the insulating transformer is small, and magnetic saturation, which is a problem with the insulating transformer, is difficult to occur.
　この方法の場合には、パルスにて送信した後に受信した信号をフリップフロップ等のラッチ回路で保持するため、回路内にノイズが入った場合に誤った状態を保持してしまうという懸念がある。こうした回路をインバータに用いた場合、インバータの上アームと下アームのそれぞれの半導体駆動装置（電力用）の駆動回路において、通常は一方がオン状態の時、他方はオフ状態となる。 In this method, since a signal received after being transmitted in a pulse is held by a latch circuit such as a flip-flop, there is a concern that an erroneous state is held when noise enters the circuit. When such a circuit is used for an inverter, in the drive circuits of the semiconductor drive devices (for electric power) of the upper arm and the lower arm of the inverter, normally, when one is on, the other is off.
　しかし、先に述べたような回路の誤動作を保持してしまうと、新たな制御信号が生じるまでオフすべきアームがオン状態を保持し、上下のアームがともにオン状態となり、主電源からの貫通電流が発生して半導体駆動装置に損傷を与える危険性がある。
　これに対して、ラッチ回路で信号を保持しない方法も開示されている（例えば、特許文献２参照）。特許文献２の方法では、スイッチング電源の絶縁トランスへの印加電圧の周波数を２種類にし、その周波数の高低を判定して信号を送信している。 However, if a malfunction of the circuit as described above is maintained, the arm to be turned off will remain on until a new control signal is generated, and the upper and lower arms will both be turned on, and the main power supply will not penetrate. There is a risk of current being generated and damaging the semiconductor drive device.
On the other hand, a method in which a signal is not held by a latch circuit is also disclosed (for example, see Patent Document 2). In the method of Patent Document 2, the frequency of the voltage applied to the insulating transformer of the switching power supply is set to two types, and the signal is transmitted by determining the level of the frequency.
国際公開第２００４／１００４７３号パンフレットInternational Publication No. 2004/100473 Pamphlet 特開２００９－２７４５５号公報JP 2009-27455 A
　しかしながら、特許文献２の方法ではラッチ回路を必ずしも持つ必要はないが、例えば回路基板の劣化で配線が切れる等の回路内の不具合が発生した場合、新たな制御信号が生じるまでオフすべきアームがオン状態を保持し、上下のアームがともにオン状態となり、主電源からの貫通電流が発生して半導体駆動装置に損傷を与えるという問題があった。さらに、より小型化した半導体駆動装置と電力変換装置が望まれていた。 However, in the method of Patent Document 2, it is not always necessary to have a latch circuit. However, when a malfunction in the circuit occurs, for example, the wiring is cut due to deterioration of the circuit board, an arm to be turned off until a new control signal is generated. There is a problem that the on-state is maintained and the upper and lower arms are both turned on, and a through current is generated from the main power source to damage the semiconductor drive device. Furthermore, a more miniaturized semiconductor drive device and power conversion device have been desired.
　本発明の目的は、回路内のノイズや不具合に対する高信頼性を確保し（ロバストなものとし）、且つ小型な電力用の半導体駆動装置と、該半導体駆動装置を用いて信頼性が高く小型で高性能な電力変換装置を提供することにある。 An object of the present invention is to ensure high reliability against noise and defects in a circuit (to be robust), and to use a small power semiconductor drive device and a high reliability and small size using the semiconductor drive device. The object is to provide a high-performance power converter.
　前記課題を解決するために、本発明の半導体駆動装置は、半導体スイッチング素子のオン、オフを駆動制御する半導体駆動装置において、前記半導体スイッチング素子のオン駆動を指令する期間中、該オン駆動を指令する連続パルスの電圧信号を生成する指令信号駆動部と、前記指令信号駆動部で生成される連続パルスの電圧信号をトランスにより伝送する絶縁通信部と、前記絶縁通信部を介して伝送される連続パルスの電圧信号に基づいて、前記連続パルスを構成するパルス間のすき間を埋めるように前記半導体スイッチング素子をオン駆動する駆動電圧を生成して出力する出力部とを備えることを特徴とする。 In order to solve the above-described problem, a semiconductor drive device according to the present invention is a semiconductor drive device that controls the on / off operation of a semiconductor switching element. A command signal driving unit that generates a continuous pulse voltage signal, an insulated communication unit that transmits a continuous pulse voltage signal generated by the command signal driving unit using a transformer, and a continuous signal transmitted through the insulating communication unit. And an output unit that generates and outputs a drive voltage for driving the semiconductor switching element to be turned on so as to fill a gap between pulses constituting the continuous pulse based on a voltage signal of the pulse.
　また、本発明の電力変換装置は、半導体スイッチング素子と、該半導体スイッチング素子のオン、オフを駆動制御する半導体駆動装置とを備えた電力変換装置であって、前記半導体駆動装置が、前記半導体スイッチング素子のオン駆動を指令する期間中、該オン駆動を指令する連続パルスの電圧信号を生成する指令信号駆動部と、前記指令信号駆動部で生成される連続パルスの電圧信号をトランスにより伝送する絶縁通信部と、前記絶縁通信部を介して伝送される連続パルスの電圧信号に基づいて、前記連続パルスを構成するパルス間のすき間を埋めるように前記半導体スイッチング素子をオン駆動する駆動電圧を生成して出力する出力部とを備えることを特徴とする。 According to another aspect of the present invention, there is provided a power conversion device including a semiconductor switching element and a semiconductor drive device that drives and controls the semiconductor switching element. The semiconductor drive device includes the semiconductor switching device. In a period for commanding ON driving of the element, an instruction signal driving unit that generates a voltage signal of a continuous pulse that commands the ON driving, and an insulation that transmits a voltage signal of the continuous pulse generated by the command signal driving unit by a transformer Based on the voltage signal of the continuous pulse transmitted through the communication unit and the insulated communication unit, a driving voltage for turning on the semiconductor switching element is generated so as to fill a gap between the pulses constituting the continuous pulse. And an output unit for outputting the output.
　本発明によれば、回路内のノイズや不具合に対する高信頼性を確保し、且つ小型な電力用の半導体駆動装置と、該半導体駆動装置を用いて信頼性が高く小型で高性能な電力変換装置を提供することができる。 Advantageous Effects of Invention According to the present invention, high reliability against noise and defects in a circuit is ensured, and a small power semiconductor drive device, and a highly reliable, small, and high performance power conversion device using the semiconductor drive device. Can be provided.
本発明の第１の実施形態に係る半導体駆動装置を用いた電力変換装置の構成を示す図である。It is a figure which shows the structure of the power converter device using the semiconductor drive device which concerns on the 1st Embodiment of this invention. 半導体駆動装置を構成する各点における電圧波形を示す図である。It is a figure which shows the voltage waveform in each point which comprises a semiconductor drive device. 半導体駆動装置の具体的な構成例を示す図である。It is a figure which shows the specific structural example of a semiconductor drive device. 半導体駆動装置を構成する各点における電圧波形を示す図である。It is a figure which shows the voltage waveform in each point which comprises a semiconductor drive device. 判定部のノイズ耐量をさらに向上させた構成例を示す図である。It is a figure which shows the structural example which further improved the noise tolerance of the determination part. 電圧調整回路の回路構成を示す図である。It is a figure which shows the circuit structure of a voltage adjustment circuit. 電圧調整回路の回路構成を示す図である。It is a figure which shows the circuit structure of a voltage adjustment circuit. 本発明の第２の実施形態に係る半導体駆動装置用いた電力変換装置の構成を示す図である。It is a figure which shows the structure of the power converter device using the semiconductor drive device which concerns on the 2nd Embodiment of this invention. 半導体駆動装置を構成する各点における電圧波形を示す図である。It is a figure which shows the voltage waveform in each point which comprises a semiconductor drive device. 本発明の第３の実施形態に係る全波整流回路を用いた半導体駆動装置の構成例を示す図である。It is a figure which shows the structural example of the semiconductor drive device using the full wave rectifier circuit which concerns on the 3rd Embodiment of this invention. 半導体駆動装置を構成する各点における電圧波形を示す図である。It is a figure which shows the voltage waveform in each point which comprises a semiconductor drive device. 絶縁通信部の他の構成例を示す図である。It is a figure which shows the other structural example of an insulated communication part. 本発明の第４の実施形態に係る半導体駆動装置を用いた電力変換装置の構成例を示す図である。It is a figure which shows the structural example of the power converter device using the semiconductor drive device which concerns on the 4th Embodiment of this invention.
≪第１の実施形態≫
　以下に、本発明の第１の実施形態に係る半導体駆動装置と電力変換装置について図を参照しながら詳細に説明する。
　図１は、本発明の実施形態に係る半導体駆動装置１０を用いた電力変換装置１００の構成を示す図である。
　電力変換装置１００は、半導体駆動装置１０と、半導体駆動装置１０の出力によりゲート電圧が制御されるＩＧＢＴ（Insulated Gate Bipolar Transistor:絶縁ゲートハイポーラトランジスタ）の半導体スイッチング素子Ｑ１と、負荷４と、電源５とを備えている。 << First Embodiment >>
Hereinafter, a semiconductor drive device and a power conversion device according to a first embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a power conversion device 100 using a semiconductor drive device 10 according to an embodiment of the present invention.
The power conversion device 100 includes a semiconductor drive device 10, an IGBT (Insulated Gate Bipolar Transistor) semiconductor switching element Q <b> 1 whose gate voltage is controlled by the output of the semiconductor drive device 10, a load 4, and a power supply And 5.
　半導体駆動装置１０は、指令信号が入力される駆動指令ＩＮを入力とする指令信号駆動部１と、指令信号駆動部１の出力を入力とする絶縁通信部２と、絶縁通信部２の出力を入力とする出力部３とを備える。
　指令信号駆動部１は、連続パルス生成部６と駆動部７とを備える。
　出力部３は、判定部８と出力パルス生成部９とを備える。 The semiconductor drive device 10 includes a command signal drive unit 1 that receives a drive command IN to which a command signal is input, an insulated communication unit 2 that receives an output of the command signal drive unit 1, and an output of the insulated communication unit 2. And an output unit 3 as an input.
The command signal drive unit 1 includes a continuous pulse generation unit 6 and a drive unit 7.
The output unit 3 includes a determination unit 8 and an output pulse generation unit 9.
　次に、このような構成において動作を説明する。
　図２は、半導体駆動装置１０を構成する各点における電圧波形を示す図である。
　指令信号駆動部１は、連続パルス生成部６が駆動指令ＩＮのオン期間（図２に示す指令信号のオン：以下、指令信号オンと表記する）に応じた所定周期の連続するパルス電圧Ｖａを生成し（図１に示すＡ点、図２参照）、駆動部７がパルス電圧Ｖａに応じて絶縁通信部２にパルス電圧を印加する。 Next, the operation in such a configuration will be described.
FIG. 2 is a diagram illustrating a voltage waveform at each point constituting the semiconductor drive device 10.
The command signal drive unit 1 is configured so that the continuous pulse generator 6 generates a continuous pulse voltage Va having a predetermined period corresponding to the ON period of the drive command IN (command signal ON shown in FIG. 2; hereinafter referred to as command signal ON). 1 (see point A shown in FIG. 1, see FIG. 2), and the drive unit 7 applies a pulse voltage to the insulating communication unit 2 in accordance with the pulse voltage Va.
　この絶縁通信部２は絶縁型のトランス（パルストランス）が用いられ、該絶縁トランスの送信側（入力側）端子間に駆動部７からのパルス電圧が印加される。
　出力部３においては、判定部８が絶縁通信部２の該絶縁トランスの受信側（出力側）端子間のパルス電圧に応じたパルス電圧Ｖｂを出力し（図１に示すＢ点、図２参照）、出力パルス生成部９が入力されるパルス電圧Ｖｂに基づいてパルス電圧Ｖａの周期よりも長い一定幅の駆動電圧Ｖoutを１パルス出力する。この駆動電圧Ｖoutは、半導体スイッチング素子Ｑ１のゲートをオンにする。さらに複数のパルス電圧Ｖｂが入力された場合、出力部３は、複数のパルス電圧Ｖｂに基づいて駆動電圧Ｖoutのパルス幅を加算する。 The insulating communication unit 2 uses an insulating transformer (pulse transformer), and a pulse voltage from the driving unit 7 is applied between the transmission side (input side) terminals of the insulating transformer.
In the output unit 3, the determination unit 8 outputs a pulse voltage Vb corresponding to the pulse voltage between the reception side (output side) terminals of the insulation transformer of the insulation communication unit 2 (see point B shown in FIG. 1, see FIG. 2). ) Based on the pulse voltage Vb to which the output pulse generator 9 is input, one pulse of a drive voltage Vout having a constant width longer than the cycle of the pulse voltage Va is output. This drive voltage Vout turns on the gate of the semiconductor switching element Q1. Further, when a plurality of pulse voltages Vb are input, the output unit 3 adds the pulse width of the drive voltage Vout based on the plurality of pulse voltages Vb.
　このような構成により、連続パルス生成部６から所定周期のパルス電圧Ｖａが出力される期間、出力パルス生成部９から半導体スイッチング素子Ｑ１のゲートをオンにする駆動電圧（Ｖout）が出力される（図２参照）。
　前記したように半導体駆動装置１０は、駆動指令ＩＮに指令信号オンが入力された期間に応じて半導体スイッチング素子Ｑ１のゲートをオンにする。 With such a configuration, the drive voltage (Vout) for turning on the gate of the semiconductor switching element Q1 is output from the output pulse generator 9 during the period in which the pulse voltage Va of a predetermined cycle is output from the continuous pulse generator 6 ( (See FIG. 2).
As described above, the semiconductor drive device 10 turns on the gate of the semiconductor switching element Q1 in accordance with the period during which the command signal ON is input to the drive command IN.
　図１に示す電力変換装置１００の場合、半導体スイッチング素子Ｑ１がオンされるとオン指令出力側ＧＮＤ２１の電位は、駆動指令側ＧＮＤ２０に対して電源５の電圧ＶＢの電圧程度まで上昇する。この電位差は絶縁通信部２に印加される。ここで、電力変換装置１００の制御の精度を向上させるには、半導体スイッチング素子Ｑ１のゲートをオンにする電圧のパルス幅の精度を高くすること、すなわち、駆動指令ＩＮと駆動電圧Ｖoutのパルス幅がよく一致していることが必要である。そのためには、出力パルス生成部９で１パルス出力するパルス幅を短くすることと、時間当たりのパルスの数を多くすることが望ましい。 In the case of the power conversion device 100 shown in FIG. 1, when the semiconductor switching element Q1 is turned on, the potential of the on command output side GND 21 rises to about the voltage VB of the power supply 5 with respect to the drive command side GND 20. This potential difference is applied to the insulating communication unit 2. Here, in order to improve the control accuracy of the power conversion device 100, the accuracy of the pulse width of the voltage for turning on the gate of the semiconductor switching element Q1 is increased, that is, the pulse width of the drive command IN and the drive voltage Vout. Need to match well. For this purpose, it is desirable to shorten the pulse width for outputting one pulse by the output pulse generator 9 and to increase the number of pulses per time.
　また、電力変換装置１００において、実際の設計では十分にノイズマージンを持たせて設計するが、仮に想定外のノイズが装置の回路に進入した場合でも、ノイズ発生期間に応じた半導体スイッチング素子Ｑ１のゲートオン電圧が生じるものの、従来のラッチ回路を用いた場合のように誤作動を保持しないため、短時間だけゲートオンするもののノイズの消滅により正常動作への復旧が可能である。 In the power converter 100, the actual design is designed with a sufficient noise margin, but even if unexpected noise enters the circuit of the apparatus, the semiconductor switching element Q1 corresponding to the noise generation period is used. Although a gate-on voltage is generated, a malfunction is not maintained as in the case of using a conventional latch circuit, so that although the gate is turned on only for a short time, the normal operation can be restored by the disappearance of noise.
　さらに、半導体スイッチング素子Ｑ１のゲートは、入力容量を持って低域通過フィルタとしても機能するため、出力パルス生成部９の１パルス出力時のパルス幅を十分短く設定すれば、半導体スイッチング素子Ｑ１のゲート電圧（駆動電圧Ｖout）のしきい電圧まで上昇せず誤ってゲートがオンになることを防いでいる。
　また、電力変換装置１００は、半導体駆動装置１０の駆動指令ＩＮから絶縁通信部２までの回路内で配線が断線するといった不具合が生じた場合でも、絶縁通信部２の受信側（出力側）にパルス電圧が生じないので、半導体スイッチング素子Ｑ１のゲートがオフ状態を保持して回路内で不具合を生じさせないようにしている。 Further, since the gate of the semiconductor switching element Q1 has an input capacitance and also functions as a low-pass filter, if the pulse width at the time of outputting one pulse of the output pulse generator 9 is set sufficiently short, the semiconductor switching element Q1 The gate voltage (drive voltage Vout) is not increased to the threshold voltage, and the gate is prevented from being turned on accidentally.
In addition, the power conversion device 100 can be connected to the reception side (output side) of the insulation communication unit 2 even when a problem such as disconnection of wiring in the circuit from the drive command IN of the semiconductor drive device 10 to the insulation communication unit 2 occurs. Since no pulse voltage is generated, the gate of the semiconductor switching element Q1 is maintained in an off state so as not to cause a problem in the circuit.
　図３は、半導体駆動装置１０の具体的な構成例を示す図である。なお、図１に示した半導体駆動装置１０と同一箇所には同一符号を付して説明を省略する。
　連続パルス生成部６Ａは、アンド回路２２で構成され、内部もしくは外部から供給される指令信号（ＩＮ）とクロック信号（ＣＬＫ）の論理積をとり連続パルスを生成する。以下、内部から供給されるものとして説明する。 FIG. 3 is a diagram illustrating a specific configuration example of the semiconductor drive device 10. The same parts as those of the semiconductor drive device 10 shown in FIG.
The continuous pulse generator 6A includes an AND circuit 22 and generates a continuous pulse by taking a logical product of a command signal (IN) and a clock signal (CLK) supplied from inside or outside. Hereinafter, description will be made assuming that the supply is from the inside.
　駆動部７は、立上りエッジパルス発生回路２４と立下りエッジパルス発生回路２５とを有するエッジトリガパルス発生回路１５，ドライバコントローラ１７，ドライバ２６とドライバ２７とを有する駆動回路１９を備える。
　絶縁通信部２は、絶縁型のパルストランスである絶縁トランス１２で構成される。
　判定部８は、受信抵抗２８，２９と、コンパレータ３０，３１と、ナンド回路３２とを備える。 The drive unit 7 includes an edge trigger pulse generation circuit 15 having a rising edge pulse generation circuit 24 and a falling edge pulse generation circuit 25, a driver controller 17, a drive circuit 19 having a driver 26 and a driver 27.
The insulating communication unit 2 includes an insulating transformer 12 that is an insulating pulse transformer.
The determination unit 8 includes reception resistors 28 and 29, comparators 30 and 31, and a NAND circuit 32.
　出力パルス生成部９は、エッジトリガパルス発生回路３４，ドライバ３５を備える。
　なお、絶縁通信部２を構成する絶縁トランス１２の指令信号駆動部１に接続される巻き線側（図３上の左側）が駆動指令側（送信側）となり、絶縁トランス１２の出力部３に接続される巻き線側（図３上の右側）がオン指令出力側（受信側）となる。 The output pulse generation unit 9 includes an edge trigger pulse generation circuit 34 and a driver 35.
The winding side (left side in FIG. 3) connected to the command signal drive unit 1 of the insulation transformer 12 constituting the insulation communication unit 2 is the drive command side (transmission side), and the output unit 3 of the insulation transformer 12 The winding side to be connected (the right side in FIG. 3) is the ON command output side (reception side).
　次に、このような構成において動作を説明する。
　図４は、図３に示す半導体駆動装置１０を構成する各点における電圧波形を示す図である。
　図３において、連続パルス生成部６Ａは、内部から駆動指令（ＩＮ）に供給する指令信号オンと、内部から供給する周期tckのクロック信号（ＣＬＫ）との論理積をアンド回路２２でとって連続パルス（ＩＮ×ＣＬＫ）を生成する（図４参照）。 Next, the operation in such a configuration will be described.
FIG. 4 is a diagram showing voltage waveforms at points constituting the semiconductor drive device 10 shown in FIG.
In FIG. 3, the continuous pulse generator 6 </ b> A continuously obtains a logical product of the command signal ON supplied to the drive command (IN) from the inside and the clock signal (CLK) of the cycle tck supplied from the inside by the AND circuit 22. A pulse (IN × CLK) is generated (see FIG. 4).
　駆動部７は、アンド回路２２で生成された連続パルス（ＩＮ×ＣＬＫ）を入力とする。また、アンド回路２２には、駆動指令側ＧＮＤ２０が接続される。駆動部７は、エッジトリガパルス発生回路１５において、立上りエッジパルス発生回路２４が入力される連続パルス（ＩＮ×ＣＬＫ）の立上りエッジから所定の幅tpのパルス電圧（Ｄ点：図４参照）を生成し、立下りエッジパルス発生回路２５が入力される連続パルス（ＩＮ×ＣＬＫ）の立下りエッジから所定の幅tpのパルス電圧（Ｅ点：図４参照）を生成する。パルス電圧（Ｄ点）は、図３に示す立上りエッジパルス発生回路２４のＤ点の出力を示し、パルス電圧（Ｅ点）は、図３に示す立下りエッジパルス発生回路２５のＥ点の出力を示す。また、立上りエッジパルス発生回路２４，立下りエッジパルス発生回路２５には、駆動指令側ＧＮＤ２０が接続される。 The driving unit 7 receives the continuous pulse (IN × CLK) generated by the AND circuit 22 as an input. Further, the drive command side GND 20 is connected to the AND circuit 22. In the edge trigger pulse generation circuit 15, the drive unit 7 applies a pulse voltage having a predetermined width tp from the rising edge of the continuous pulse (IN × CLK) to which the rising edge pulse generation circuit 24 is input (D point: see FIG. 4). The pulse voltage (point E: see FIG. 4) having a predetermined width tp is generated from the falling edge of the continuous pulse (IN × CLK) to be generated and input to the falling edge pulse generation circuit 25. The pulse voltage (point D) indicates the output at point D of the rising edge pulse generation circuit 24 shown in FIG. 3, and the pulse voltage (point E) indicates the output at point E of the falling edge pulse generation circuit 25 shown in FIG. Indicates. The drive command side GND 20 is connected to the rising edge pulse generation circuit 24 and the falling edge pulse generation circuit 25.
　続いて駆動部７は、駆動回路１９において、ドライバ２６が立上りエッジパルス発生回路２４で生成した所定幅tpのパルス電圧（Ｄ点）を絶縁トランス１２の駆動指令側の巻き線の一方の端子に印加し、ドライバ２７が立下りエッジパルス発生回路２５で生成した所定幅tpのパルス電圧（Ｅ点）を絶縁トランス１２の駆動指令側の巻き線の他方の端子に印加する。また、ドライバ２６，ドライバ２７には、駆動指令側ＧＮＤ２０が接続される。 Subsequently, in the drive circuit 19, the drive unit 7 applies the pulse voltage (point D) having a predetermined width tp generated by the driver 26 in the rising edge pulse generation circuit 24 to one terminal of the winding on the drive command side of the insulation transformer 12. Then, the driver 27 applies the pulse voltage (point E) having a predetermined width tp generated by the falling edge pulse generation circuit 25 to the other terminal of the winding on the drive command side of the insulating transformer 12. In addition, the drive command side GND 20 is connected to the driver 26 and the driver 27.
　なお、駆動部７のドライバコントローラ１７は、駆動回路１９がパルス電圧を送信しない期間に、パルス電圧を送信する期間に比べ駆動回路１９の出力段をハイインピーダンスとする指令を出す。具体的にドライバコントローラ１７は、駆動回路１９でパルス電圧を送信しない期間、駆動回路１９が有するドライバ２６，２７の出力段をオフにする。
　この結果、図３に示すように、絶縁トランス１２の駆動指令側（送信側）の端子間に電圧Ｖｓが印加され、絶縁トランス１２のオン指令出力側（受信側）の端子間に電圧Ｖｔが出力される。このときの端子間電圧Ｖｓと端子間電圧Ｖｔを図４に示す。 Note that the driver controller 17 of the drive unit 7 issues a command to set the output stage of the drive circuit 19 to high impedance during a period in which the drive circuit 19 does not transmit the pulse voltage compared to a period in which the pulse voltage is transmitted. Specifically, the driver controller 17 turns off the output stages of the drivers 26 and 27 included in the drive circuit 19 while the drive circuit 19 does not transmit a pulse voltage.
As a result, as shown in FIG. 3, the voltage Vs is applied between the drive command side (transmission side) terminals of the isolation transformer 12 and the voltage Vt is applied between the on command output side (reception side) terminals of the isolation transformer 12. Is output. The inter-terminal voltage Vs and inter-terminal voltage Vt at this time are shown in FIG.
　出力部３の判定部８には、絶縁トランス１２のオン指令出力側の巻き線の端子間電圧Ｖｔが入力される。
　判定部８において、絶縁トランス１２のオン指令出力側の巻き線の端子間に受信抵抗２８，２９が直列に接続され、受信抵抗２８と受信抵抗２９との間にオン指令出力側ＧＮＤ２１が接続される。 The inter-terminal voltage Vt of the winding on the ON command output side of the insulation transformer 12 is input to the determination unit 8 of the output unit 3.
In the determination unit 8, the receiving resistors 28 and 29 are connected in series between the terminals of the winding on the ON command output side of the isolation transformer 12, and the ON command output side GND 21 is connected between the receiving resistor 28 and the receiving resistor 29. The
　コンパレータ３０，３１は、絶縁トランス１２のオン指令出力部側の巻き線の端子間に接続される。その際、コンパレータ３０の－入力端子と＋入力端子と、コンパレータ３１の－入力端子と＋入力端子とが、絶縁トランス１２の端子間に互いに異なるようにそれぞれ接続され、絶縁トランス１２の端子間電圧Ｖｔの正、負を判定する。また、コンパレータ３０，３１には、オン指令出力側ＧＮＤ２１が接続される。
　ナンド回路３２は、コンパレータ３０の出力とコンパレータ３１の出力とを入力とし、クロック信号（ＣＬＫ）と駆動指令（ＩＮ）に入力された指令信号オンの論理積（ＩＮ×ＣＬＫ：図４参照）のエッジに対応した連続パルス電圧（図４参照）を出力する（図３のＦ点）。また、ナンド回路３２には、オン指令出力側ＧＮＤ２１が接続される。 The comparators 30 and 31 are connected between terminals of the winding on the on command output unit side of the insulating transformer 12. At that time, the −input terminal and the + input terminal of the comparator 30 and the −input terminal and the + input terminal of the comparator 31 are respectively connected to be different from each other between the terminals of the isolation transformer 12. Determine whether Vt is positive or negative. Further, the ON command output side GND 21 is connected to the comparators 30 and 31.
The NAND circuit 32 receives the output of the comparator 30 and the output of the comparator 31 as input, and is a logical product (IN × CLK: see FIG. 4) of the command signal ON input to the clock signal (CLK) and the drive command (IN). A continuous pulse voltage (see FIG. 4) corresponding to the edge is output (point F in FIG. 3). The NAND circuit 32 is connected to the ON command output side GND 21.
　出力パルス生成部９において、エッジトリガパルス発生回路３４は、連続パルス電圧（Ｆ点）の入力に対し、クロック信号（ＣＬＫ）の周期tckの１／２より長いパルス幅ｔｗのエッジトリガのパルスを発生する。ドライバ３５は、エッジトリガパルス発生回路３４からのパルス幅ｔｗのパルスに応じて駆動電圧Ｖｏｕｔを出力する（図４参照）。また、ドライバ３５には、オン指令出力側ＧＮＤ２１が接続される。
　このように、エッジトリガパルス回路３４が再トリガすることで、パルス幅ｔｗのパルス電圧が連続して発生する期間では、半導体スイッチング素子Ｑ１のゲートをなめらかにオンにする駆動電圧Ｖｏｕｔが出力される（図４参照）。 In the output pulse generation unit 9, the edge trigger pulse generation circuit 34 generates an edge trigger pulse having a pulse width tw longer than ½ of the cycle tck of the clock signal (CLK) in response to the input of the continuous pulse voltage (point F). appear. The driver 35 outputs the drive voltage Vout according to the pulse having the pulse width tw from the edge trigger pulse generation circuit 34 (see FIG. 4). The driver 35 is connected to the on command output side GND 21.
As described above, when the edge trigger pulse circuit 34 retriggers, the drive voltage Vout for smoothly turning on the gate of the semiconductor switching element Q1 is output during a period in which the pulse voltage having the pulse width tw is continuously generated. (See FIG. 4).
　この第１の実施形態によれば、駆動部７が立上りエッジと立下りエッジからパルス電圧を生成することにより、つまり、図４のＶｓ，Ｖｔに示すようにパルス電圧の極性を交互に変えることで電流の向きが変わり、これにより絶縁トランス１２がリセットされ、磁気飽和を避けることができる。さらに、出力パルス生成部９は、パルス幅ｔｗをクロック信号ＣＬＫの周期tckの１／２近くまで短くできるので、半導体スイッチング素子Ｑ１のゲートをオンにするパルス電圧（駆動電圧）のパルス幅の精度を高めることが可能となる。 According to the first embodiment, the drive unit 7 generates the pulse voltage from the rising edge and the falling edge, that is, the polarity of the pulse voltage is alternately changed as indicated by Vs and Vt in FIG. This changes the direction of the current, thereby resetting the isolation transformer 12 and avoiding magnetic saturation. Further, since the output pulse generation unit 9 can shorten the pulse width tw to nearly ½ of the period tck of the clock signal CLK, the accuracy of the pulse width of the pulse voltage (drive voltage) that turns on the gate of the semiconductor switching element Q1. Can be increased.
　さらに、絶縁トランス１２の端子間電圧Ｖｔの正、負を判定する判定部８を用いることで、図３に示すトランスの寄生容量（Ｃ１，Ｃ２）に起因する同相ノイズの除去が可能となる。これは、前記した図１の電力変換装置１００で半導体スイッチング素子Ｑ１をオン、オフした際に発生するオン指令出力側ＧＮＤ２１と駆動指令側ＧＮＤ２０との間の電位差Ｖｈの電圧変化ｄＶｈ／ｄｔによる変移電流と、受信抵抗２８の積のＣ１×（ｄＶｈ／ｄｔ）×Ｒ（受信抵抗２８）のノイズと、受信抵抗２９の積のＣ２×（ｄＶｈ／ｄｔ）×Ｒ（受信抵抗２９）のノイズとが同相モードで判定部８に入力されるが、差動判定することで同相のノイズが除去されるためである。この結果、ノイズ耐量を向上させることができる。 Furthermore, by using the determination unit 8 that determines whether the inter-terminal voltage Vt of the isolation transformer 12 is positive or negative, it is possible to remove common-mode noise caused by the parasitic capacitances (C1, C2) of the transformer shown in FIG. This is because the potential difference Vh between the on command output side GND 21 and the drive command side GND 20 generated when the semiconductor switching element Q1 is turned on and off in the power conversion device 100 of FIG. 1 is changed by the voltage change dVh / dt. C1 × (dVh / dt) × R (reception resistor 28) noise of the product of the reception resistor 28, and C2 × (dVh / dt) × R (reception resistor 29) noise of the product of the reception resistor 29 Is input to the determination unit 8 in the in-phase mode, and the in-phase noise is removed by performing the differential determination. As a result, noise tolerance can be improved.
　図５は、ノイズ耐量をさらに向上させた判定部８Ａの構成例を示す図である。図３に示した判定部８と同一箇所には同一符号を付して説明を省略する。判定部８Ａは、絶縁トランス１２の受信側の両端子とコンパレータ（３０，３１）の入力端子との間に電圧調整回路２０１，２０２，２０３，２０４を設けたものである。
　電圧調整回路２０１は、入力側が受信抵抗２８の一端が接続されている絶縁トランス１２の端子に接続され、出力側がコンパレータ３０の－入力端子に接続されている。
　電圧調整回路２０２は、入力側が受信抵抗２９の一端が接続されている絶縁トランス１２の端子に接続され、出力側がコンパレータ３０の＋入力端子に接続されている。 FIG. 5 is a diagram illustrating a configuration example of the determination unit 8A in which the noise tolerance is further improved. The same parts as those of the determination unit 8 shown in FIG. The determination unit 8A is provided with voltage adjustment circuits 201, 202, 203, and 204 between both receiving terminals of the isolation transformer 12 and the input terminals of the comparators (30, 31).
The voltage adjustment circuit 201 has an input side connected to a terminal of the isolation transformer 12 to which one end of the receiving resistor 28 is connected, and an output side connected to the − input terminal of the comparator 30.
The voltage adjustment circuit 202 has an input side connected to the terminal of the isolation transformer 12 to which one end of the receiving resistor 29 is connected, and an output side connected to the + input terminal of the comparator 30.
　電圧調整回路２０３は、入力側が受信抵抗２９の一端が接続されている絶縁トランス１２の端子に接続され、出力側がコンパレータ３１の－入力端子に接続されている。
　電圧調整回路２０４は、入力側が受信抵抗２８の一端が接続されている絶縁トランス１２の端子に接続され、出力側がコンパレータ３１の＋入力端子に接続されている。
　電圧調整回路２０１，２０３は、コンパレータ３０，３１の＋入力端子の判定における基準電圧レベルを調整する回路である。 The voltage adjustment circuit 203 has an input side connected to the terminal of the isolation transformer 12 to which one end of the receiving resistor 29 is connected, and an output side connected to the − input terminal of the comparator 31.
The voltage adjustment circuit 204 has an input side connected to the terminal of the isolation transformer 12 to which one end of the receiving resistor 28 is connected, and an output side connected to the + input terminal of the comparator 31.
The voltage adjustment circuits 201 and 203 are circuits that adjust the reference voltage level in the determination of the + input terminals of the comparators 30 and 31.
　図６は、電圧調整回路２０１，２０３の回路構成を示すもので、ダイオード２１１，抵抗（Ｒａｄ１）２１３，抵抗（Ｒａｄ２）２１４を備える。入力電圧はダイオード２１１により直流電圧Ｖｄｃとなる。この直流電圧Ｖｄｃを抵抗分圧した電圧Ｖａｄ０＝Ｒａｄ２／（Ｒａｄ１＋Ｒａｄ２）×Ｖｄｃとなるまで出力電圧はＶａｄ０となり、これが基準レベルとなる（基準信号）。入力電圧がさらに上昇すると、この電圧上昇にほぼ比例して判定の基準レベルが上昇する。 FIG. 6 shows a circuit configuration of the voltage adjustment circuits 201 and 203, and includes a diode 211, a resistor (Rad1) 213, and a resistor (Rad2) 214. The input voltage becomes a DC voltage Vdc by the diode 211. The output voltage becomes Vad0 until the voltage Vad0 = Rad2 / (Rad1 + Rad2) × Vdc obtained by resistance-dividing the DC voltage Vdc, and this becomes the reference level (reference signal). When the input voltage further rises, the determination reference level rises almost in proportion to this voltage rise.
　図７は、電圧調整回路２０２，２０４の回路構成を示すもので、ダイオード２１５，抵抗（Ｒａｄ３）２１６，抵抗（Ｒａｄ４）２１７を備える。電圧調整回路２０２，２０４が備える抵抗２１６，２１７は、図６に示す電圧調整回路２０１，２０３が備える抵抗と抵抗値が異なるものである。
　電圧調整回路２０２，２０４は、コンパレータ３０，３１の－入力端子に印加される判定すべき電圧信号（判定信号）のレベルを調整する。 FIG. 7 shows a circuit configuration of the voltage adjustment circuits 202 and 204, and includes a diode 215, a resistor (Rad 3) 216, and a resistor (Rad 4) 217. The resistors 216 and 217 included in the voltage adjustment circuits 202 and 204 are different in resistance value from the resistors included in the voltage adjustment circuits 201 and 203 shown in FIG.
The voltage adjustment circuits 202 and 204 adjust the level of the voltage signal (determination signal) to be determined that is applied to the negative input terminals of the comparators 30 and 31.
　図５に示す判定部８Ａのコンパレータ３０，３１の－入力端子側が＋入力端子側より高い電圧となり、出力が「ロー」となった場合に、そのエッジから連続のパルス電圧を生成する場合を想定すると、電圧調整回路２０２，２０４は、直流電圧Ｖｈｇを抵抗分圧した出力電圧Ｖｅｈが電圧調整回路２０１，２０３の出力電圧Ｖａｄより低く設定される。
　すなわち、絶縁トランス１２の一方の出力端子に接続される基準レベルの電圧を調整する電圧調整回路(第１の基準電圧調整回路)２０１の出力電圧（基準電圧）Ｖｅｈは、判定レベルの電圧を調整する電圧調整回路（第２の判定電圧調整回路）２０２の出力電圧（判定電圧）Ｖａｄより低く設定され、絶縁トランス１２の他方の出力端子に接続される基準レベルの電圧を調整する電圧調整回路(第２の基準電圧調整回路)２０３の出力電圧（基準電圧）Ｖｅｈは、判定レベルの電圧を調整する電圧調整回路（第１の判定電圧調整回路）２０４の出力電圧（判定電圧）Ｖａｄより低く設定される。 Assume that a continuous pulse voltage is generated from the edge when the negative input side of the comparators 30 and 31 of the determination unit 8A shown in FIG. 5 is higher than the positive input terminal side and the output becomes “low”. Then, the voltage adjustment circuits 202 and 204 are set so that the output voltage Veh obtained by resistance-dividing the DC voltage Vhg is lower than the output voltage Vad of the voltage adjustment circuits 201 and 203.
That is, the output voltage (reference voltage) Veh of the voltage adjustment circuit (first reference voltage adjustment circuit) 201 that adjusts the reference level voltage connected to one output terminal of the isolation transformer 12 adjusts the determination level voltage. A voltage adjustment circuit that adjusts a reference level voltage that is set lower than the output voltage (determination voltage) Vad of the voltage adjustment circuit (second determination voltage adjustment circuit) 202 that is connected to the other output terminal of the isolation transformer 12 ( The output voltage (reference voltage) Veh of the second reference voltage adjustment circuit 203 is set lower than the output voltage (determination voltage) Vad of the voltage adjustment circuit (first determination voltage adjustment circuit) 204 that adjusts the voltage of the determination level. Is done.
　このような構成により、電圧調整回路（２０１，２０２，２０３，２０４）の基準信号側の入力と判定信号側の入力に同一の電圧が印加された場合、必ず、判定信号側の電圧調整回路（２０２，２０４）の出力電圧を低くできる。このため、絶縁トランス１２における入力端子と出力端子との間の寄生容量の差（Ｃ１、Ｃ２）、さらに受信抵抗２８，２９のばらつきにより判定部８Ａの平衡性が失われて同相ノイズが差動ノイズに変換された場合でも、判定信号側の電圧調整回路（２０２，２０４）の出力電圧を低くすることでノイズによる誤動作を回避することが可能となる。 With such a configuration, when the same voltage is applied to the reference signal side input and the determination signal side input of the voltage adjustment circuit (201, 202, 203, 204), the determination signal side voltage adjustment circuit ( 202, 204) can be lowered. For this reason, the balance of the determination unit 8A is lost due to the difference in parasitic capacitance (C1, C2) between the input terminal and the output terminal in the isolation transformer 12 and the variation of the receiving resistors 28, 29, and the common-mode noise becomes differential. Even when converted to noise, it is possible to avoid malfunction due to noise by lowering the output voltage of the voltage adjustment circuit (202, 204) on the determination signal side.
≪第２の実施形態≫
　次に、第２の実施形態に係る半導体駆動装置と電力変換装置について説明する。
　図８は、本発明の第２の実施形態に係る半導体駆動装置１０ａと、半導体駆動装置１０ａを用いた電力変換装置１００ａの構成を示す図である。なお、図３に示した半導体駆動装置１０と同一箇所には同一符号を付して説明を省略する。また、図１に示した電力変換装置１００と同一箇所には同一符号を付して説明を省略する。 << Second Embodiment >>
Next, a semiconductor drive device and a power conversion device according to the second embodiment will be described.
FIG. 8 is a diagram showing a configuration of a semiconductor drive device 10a according to the second embodiment of the present invention and a power conversion device 100a using the semiconductor drive device 10a. The same parts as those of the semiconductor drive device 10 shown in FIG. Moreover, the same code | symbol is attached | subjected to the same location as the power converter device 100 shown in FIG. 1, and description is abbreviate | omitted.
　半導体駆動装置１０ａは、図３に示した半導体駆動装置１０に状態信号駆動部６７，状態出力部６６，受信対応駆動指令部７３，送信対応受信信号処理部７６を設けたものである。状態信号駆動部６７は半導体スイッチング素子Ｑ１のオン状態を判定して状態信号を送信するものであり、その送信された状態信号を受信して半導体スイッチング素子Ｑ１のオン状態のオン状態検知信号を出力するものが状態出力部６６である。すなわち、半導体駆動装置１０ａと電力変換装置１００ａは、駆動指令ＩＮからの指令信号オンの送信と、半導体スイッチング素子Ｑ１の状態信号の送信とを絶縁トランス１２を介して双方向に通信する構成である。
　なお、半導体駆動装置１０ａは、マイクロコンピュータなどの上位機器（図示しない）から駆動指令ＩＮに指令信号オンが入力される構成となっている。 The semiconductor drive device 10a is obtained by providing the semiconductor drive device 10 shown in FIG. 3 with a state signal drive unit 67, a state output unit 66, a reception-compatible drive command unit 73, and a transmission-compatible reception signal processing unit 76. The state signal driving unit 67 determines the ON state of the semiconductor switching element Q1 and transmits a state signal. The state signal driving unit 67 receives the transmitted state signal and outputs an ON state detection signal of the ON state of the semiconductor switching element Q1. What is to be performed is a state output unit 66. That is, the semiconductor drive device 10a and the power conversion device 100a are configured to bidirectionally communicate the transmission of the command signal ON from the drive command IN and the transmission of the state signal of the semiconductor switching element Q1 via the isolation transformer 12. .
The semiconductor drive device 10a is configured such that a command signal ON is input to the drive command IN from a host device (not shown) such as a microcomputer.
　指令信号駆動部１Ａは、連続パルス生成部６，エッジトリガパルス発生回路１５と駆動回路１９とを備える駆動部７，受信対応駆動指令部７３を備える。
　出力部３Ａは、判定部８，出力パルス生成部９，送信対応受信信号処理部７６を備える。
　状態出力部６６は、出力パルス生成部７８，送信対応受信信号処理部７９，判定部８０を備える。判定部８０は、絶縁通信部２の絶縁トランス１２の入力側（送信側）の端子を入力とする。 The command signal drive unit 1A includes a continuous pulse generation unit 6, a drive unit 7 including an edge trigger pulse generation circuit 15 and a drive circuit 19, and a reception-compatible drive command unit 73.
The output unit 3A includes a determination unit 8, an output pulse generation unit 9, and a transmission-accepted reception signal processing unit 76.
The status output unit 66 includes an output pulse generation unit 78, a transmission-compatible received signal processing unit 79, and a determination unit 80. The determination unit 80 uses an input side (transmission side) terminal of the insulation transformer 12 of the insulation communication unit 2 as an input.
　状態信号駆動部６７は、駆動回路８１ａとエッジトリガパルス発生回路８１ｂとを備える駆動部８２，連続パルス生成部８３，状態判定部８４，受信対応駆動指令部８５を備える。状態判定部８４は、半導体スイッチング素子Ｑ１のゲート－エミッタ間の電圧を入力とする。駆動回路８１ａの出力は、絶縁通信部２の絶縁トランス１２の出力側（受信側）の端子に入力される。 The state signal drive unit 67 includes a drive unit 82 including a drive circuit 81a and an edge trigger pulse generation circuit 81b, a continuous pulse generation unit 83, a state determination unit 84, and a reception-compatible drive command unit 85. The state determination unit 84 receives the voltage between the gate and the emitter of the semiconductor switching element Q1. The output of the drive circuit 81 a is input to the output side (reception side) terminal of the isolation transformer 12 of the isolation communication unit 2.
　次に、このような構成において動作を説明する。
　図９は、半導体駆動装置１０ａを構成する各点における電圧波形を示す図である。
　まず、状態信号駆動部６７において、状態判定部８４が半導体スイッチング素子Ｑ１のゲートがオンであると判定した際、連続パルス生成部８３，エッジトリガパルス発生回路８１ｂを介して駆動回路８１ａが連続パルス（第２の連続パルス）を絶縁通信部２の絶縁トランス１２の出力側に出力（送信）する。 Next, the operation in such a configuration will be described.
FIG. 9 is a diagram showing voltage waveforms at each point constituting the semiconductor drive device 10a.
First, in the state signal drive unit 67, when the state determination unit 84 determines that the gate of the semiconductor switching element Q1 is ON, the drive circuit 81a is continuously pulsed via the continuous pulse generation unit 83 and the edge trigger pulse generation circuit 81b. (Second continuous pulse) is output (transmitted) to the output side of the insulating transformer 12 of the insulating communication unit 2.
　状態出力部６６において、判定部８０が前記送信された連続パルスを絶縁トランス１２の入力側で受信し、出力パルス生成部７８が1つのパルスに対してパルス幅ｔｗのパルスを再トリガして発生し、半導体スイッチング素子Ｑ１がオン状態であるとするオン状態検知信号を入力端子ＳＴＡＴＥを介して上位機器（図示しない）へ出力する。
　上位機器（図示しない）は、オン状態検知信号が入力端子ＳＴＡＴＥに入力されることにより、半導体スイッチング素子Ｑ１のオン，オフ状態を検知することができる。 In the status output unit 66, the determination unit 80 receives the transmitted continuous pulse at the input side of the isolation transformer 12, and the output pulse generation unit 78 re-triggers a pulse with a pulse width tw for one pulse and generates it. Then, an on-state detection signal indicating that the semiconductor switching element Q1 is in the on-state is output to the host device (not shown) via the input terminal STATE.
The host device (not shown) can detect the on / off state of the semiconductor switching element Q1 by inputting the on state detection signal to the input terminal STATE.
　また、状態信号駆動部６７の受信対応駆動指令部８５は、駆動回路８１ａがパルスを送信しない期間に、パルスを送信する期間に比べ駆動回路８１ａの出力段をハイインピーダンスとする指令を出す。具体的に受信対応駆動指令部８５は、駆動回路８１ａがパルスを送信しない期間、駆動回路８１ａの出力段をオフにする。 Further, the reception-compatible drive command unit 85 of the state signal drive unit 67 issues a command to set the output stage of the drive circuit 81a to high impedance in a period in which the drive circuit 81a does not transmit a pulse compared to a period in which the pulse is transmitted. Specifically, the reception-compatible drive command unit 85 turns off the output stage of the drive circuit 81a while the drive circuit 81a does not transmit a pulse.
　同様に、指令信号駆動部１Ａの受信対応駆動指令部７３は、駆動回路１９がパルス電圧を送信しない期間に、パルス電圧を送信する期間に比べ駆動回路１９の出力段をハイインピーダンスとする指令を出す。具体的に受信対応駆動指令部７３は、駆動回路１９がパルスを送信しない期間、駆動回路１９の出力段をオフにする。この場合、指令信号駆動部１Ａにおける駆動回路１９の出力インピーダンスは、パルス電圧を送信しない期間は判定部８の受信抵抗（図３に示す受信抵抗２８，２９）Ｒとなるが、パルス電圧（Ｄ点、Ｅ点）を送信する期間は並列に駆動回路１９の出力段の抵抗ＲＤが入るため抵抗の値が下がる（図８と図９を参照）。 Similarly, the reception-compatible drive command unit 73 of the command signal drive unit 1A issues a command to set the output stage of the drive circuit 19 to high impedance in a period in which the drive circuit 19 does not transmit the pulse voltage compared to a period in which the pulse voltage is transmitted. put out. Specifically, the reception-capable drive command unit 73 turns off the output stage of the drive circuit 19 during a period in which the drive circuit 19 does not transmit a pulse. In this case, the output impedance of the drive circuit 19 in the command signal drive unit 1A is the reception resistance ( reception resistors 28 and 29 shown in FIG. 3) R of the determination unit 8 during a period in which no pulse voltage is transmitted, but the pulse voltage (D During the transmission period of point (E), the resistance value RD of the output stage of the drive circuit 19 is inserted in parallel, so that the resistance value decreases (see FIGS. 8 and 9).
　このような構成により、絶縁通信部２が半導体スイッチング素子Ｑ１のゲートをオン状態とする連続するパルス電圧を受信するとき受信側の等価的なインピーダンスが高くなり、より少ない駆動回路１９からの電流で送信を可能とし、駆動回路１９の小型化と低損失化を図ることができる。 With this configuration, when the insulating communication unit 2 receives a continuous pulse voltage that turns on the gate of the semiconductor switching element Q1, the equivalent impedance on the receiving side is increased, and less current from the drive circuit 19 is obtained. Transmission is possible, and the drive circuit 19 can be reduced in size and loss.
　状態信号駆動部６７からのパルス（半導体スイッチング素子Ｑ１のゲートをオン状態と判定した状態信号Ｐ）の送信は、絶縁トランス１２の出力側の端子間電圧Ｖｔに示すように、指令信号（半導体スイッチング素子Ｑ１のゲートをオン状態にする送信信号Ｓ）に同期し、時間ｔｄだけ遅れて出力することで指令信号と重ならないようにしている。また、送信信号Ｓが発生していない期間は、同期する信号が無いため、状態信号駆動部６７の連続パルス生成部８３で生成するクロック信号（tck2）の周波数でパルス（状態信号Ｐ）を送信する（図９参照）。なお、指令信号駆動部６１の連続パルス生成部６は、クロック信号（tck1）の周波数でパルスを生成して送信する（図９参照）。 Transmission of a pulse from the state signal driving unit 67 (state signal P determined that the gate of the semiconductor switching element Q1 is turned on) is a command signal (semiconductor switching) as indicated by the inter-terminal voltage Vt on the output side of the isolation transformer 12. In synchronization with the transmission signal S) that turns on the gate of the element Q1, the output is delayed by time td so that it does not overlap with the command signal. Further, since there is no signal to synchronize during the period when the transmission signal S is not generated, a pulse (state signal P) is transmitted at the frequency of the clock signal (tck2) generated by the continuous pulse generator 83 of the state signal driver 67 (See FIG. 9). The continuous pulse generator 6 of the command signal driver 61 generates and transmits a pulse at the frequency of the clock signal (tck1) (see FIG. 9).
　また、半導体スイッチング素子Ｑ１から出力されるオン状態検知信号（図９参照）において、tdonは半導体スイッチング素子Ｑ１のゲートのターンオンの遅延時間であり、tdoffは半導体スイッチング素子Ｑ１のゲートのターンオフの遅延時間である。
　状態出力部６６においては、判定部８０が絶縁トランス１２の送信側（入力側）端子間のパルス電圧Ｖｓに応じたパルス電圧を受信し、出力パルス生成部７８が入力されるパルス電圧に基づいてクロック信号（ＣＬＫ）の周期tck１（tck２）の１／２より長いパルス幅ｔｗのエッジトリガのオン状態検知信号を入力端子ＳＴＡＴＥを介して上位機器（図示しない）に１パルス出力する。 In the ON state detection signal (see FIG. 9) output from the semiconductor switching element Q1, tdon is a delay time for turning on the gate of the semiconductor switching element Q1, and tdoff is a delay time for turning off the gate of the semiconductor switching element Q1. It is.
In the state output unit 66, the determination unit 80 receives a pulse voltage corresponding to the pulse voltage Vs between the transmission side (input side) terminals of the isolation transformer 12, and the output pulse generation unit 78 is based on the input pulse voltage. An edge trigger on-state detection signal having a pulse width tw longer than ½ of the period tck1 (tck2) of the clock signal (CLK) is output to the host device (not shown) through the input terminal STATE.
　出力部３Ａの送信対応受信信号処理部７６は、駆動回路８１ａのパルス送信期間に信号をマスクして受信しない期間とする。このような構成により、出力部３Ａは、状態信号を受信信号と誤判定せず信頼性の高い信号の伝送が可能となる。
　同様に、状態出力部６６の送信対応受信信号処理部７９は、駆動回路１９のパルス送信期間に信号をマスクして受信しない期間とする。このような構成により、状態出力部６６は、状態信号と指令信号とを誤判定せず信頼性の高い信号の伝送が可能となる。 The transmission corresponding received signal processing unit 76 of the output unit 3A masks the signal during the pulse transmission period of the drive circuit 81a so as not to receive it. With this configuration, the output unit 3A can transmit a highly reliable signal without erroneously determining the status signal as a received signal.
Similarly, the transmission corresponding received signal processing unit 79 of the status output unit 66 masks the signal during the pulse transmission period of the drive circuit 19 and sets it as a period during which no signal is received. With such a configuration, the status output unit 66 can transmit a highly reliable signal without erroneously determining the status signal and the command signal.
　なお、連続パルス生成部６で生成される連続パルスを第１の連続パルスとした場合、連続パルス生成部８３で生成される連続パルスは第２の連続パルスとなる。
　この第２の実施形態によれば、上位機器（図示しない）から供給される指令信号オンの送信と、半導体スイッチング素子Ｑ１のオン状態検知信号の送信とを絶縁トランスを介して双方向に通信する構成により、該上位機器（図示しない）は、供給した指令信号オンに応じて制御されるスイッチング素子Ｑ１のオン、オフ状態を検知することができる。 When the continuous pulse generated by the continuous pulse generator 6 is the first continuous pulse, the continuous pulse generated by the continuous pulse generator 83 is the second continuous pulse.
According to the second embodiment, the transmission of the command signal ON supplied from the host device (not shown) and the transmission of the ON state detection signal of the semiconductor switching element Q1 are bidirectionally communicated via the insulating transformer. According to the configuration, the host device (not shown) can detect the on / off state of the switching element Q1 that is controlled in response to the supplied command signal being on.
≪第３の実施形態≫
　次に、第３の実施形態に係る半導体駆動装置について説明する。
　図１０は、全波整流回路４４を用いた半導体駆動装置１０ｂの構成例を示す図である。図１１は、半導体駆動装置１０ｂを構成する各点における電圧波形を示す図である。
　半導体駆動装置１０ｂは、基本構成は変わらず、指令信号駆動部４１，絶縁通信部４２，出力部４３を備えている。本構成例では、出力部４３に、判定部に代わる全波整流回路４４を設けている。 << Third Embodiment >>
Next, a semiconductor drive device according to a third embodiment will be described.
FIG. 10 is a diagram illustrating a configuration example of the semiconductor drive device 10 b using the full-wave rectifier circuit 44. FIG. 11 is a diagram showing voltage waveforms at respective points constituting the semiconductor drive device 10b.
The semiconductor drive device 10b has the same basic configuration, and includes a command signal drive unit 41, an insulation communication unit 42, and an output unit 43. In the present configuration example, the output unit 43 is provided with a full-wave rectifier circuit 44 instead of the determination unit.
　指令信号駆動部４１は、駆動論理回路５１と駆動回路５２を備える。
　絶縁通信部４２は、絶縁トランス５３で構成される。
　出力部４３は、全波整流回路４４，フィルタ回路４５，判定・出力パルス生成回路４６，ドライバ４７を備える。
　本構成例の半導体駆動装置１０ｂにおいては、指令信号オンの時、駆動論理回路５１と駆動回路５２を備える指令信号駆動部４１から送信される連続のパルス電圧が絶縁トランス５３の入力側端子間に印加され、絶縁トランス５３の出力側端子間（図１０のＧ点）に差電圧Ｖｃが出力（生成）される（図１１参照）。 The command signal drive unit 41 includes a drive logic circuit 51 and a drive circuit 52.
The insulating communication unit 42 includes an insulating transformer 53.
The output unit 43 includes a full-wave rectifier circuit 44, a filter circuit 45, a determination / output pulse generation circuit 46, and a driver 47.
In the semiconductor drive device 10b of this configuration example, when the command signal is on, the continuous pulse voltage transmitted from the command signal drive unit 41 including the drive logic circuit 51 and the drive circuit 52 is transmitted between the input side terminals of the insulation transformer 53. The differential voltage Vc is output (generated) between the output-side terminals of the insulating transformer 53 (point G in FIG. 10) (see FIG. 11).
　出力部４３は、全波整流回路４４で差電圧Ｖｃを整流し、整流した電圧がある一定以上の値の期間、半導体スイッチング素子のゲートをオンとする指令を出力（駆動電圧Ｖｏｕｔ）する。なお、フィルタ回路４５は、全波整流回路４４で整流した際のノイズを除くために設けられている。 The output unit 43 rectifies the difference voltage Vc by the full-wave rectifier circuit 44, and outputs a command to turn on the gate of the semiconductor switching element (drive voltage Vout) for a period of a certain value or more. The filter circuit 45 is provided to remove noise when rectified by the full-wave rectifier circuit 44.
　前記第３の実施形態によれば、半導体駆動装置１０ｂでは、絶縁トランス５３の出力側端子の差電圧Ｖｃを全波整流回路４４で整流しているので差動の電圧Ｖｄ（図１０のＨ点）が容易に得られ（図１１参照）、判定・出力パルス生成回路４６を簡素化できる。
　また、指令信号駆動部４１からの送信信号を連続の矩形波で送信すれば、フィルタ回路４５の出力（差動の電圧）Ｖｄの電圧レベルが高い場合（所定のしきい値レベル）に半導体スイッチング素子Ｑ１のゲートをオンとする出力にすればよく、判定・出力パルス生成回路４６を簡素化することができる。 According to the third embodiment, in the semiconductor drive device 10b, the differential voltage Vc at the output side terminal of the insulating transformer 53 is rectified by the full-wave rectifier circuit 44, so that the differential voltage Vd (point H in FIG. 10). ) Can be easily obtained (see FIG. 11), and the determination / output pulse generation circuit 46 can be simplified.
Further, if the transmission signal from the command signal drive unit 41 is transmitted as a continuous rectangular wave, the semiconductor switching is performed when the output (differential voltage) Vd voltage level of the filter circuit 45 is high (predetermined threshold level). An output that turns on the gate of the element Q1 may be used, and the determination / output pulse generation circuit 46 can be simplified.
　なお、図１１に示したクロック信号（ＣＬＫ）は、差電圧Ｖｃと差動の電圧Ｖｄの関係を説明するため図示を簡素化しているもので、図４、図９で示したクロック信号（ＣＬＫ）と同様の周期tckである。 The clock signal (CLK) shown in FIG. 11 is simplified to illustrate the relationship between the differential voltage Vc and the differential voltage Vd. The clock signal (CLK) shown in FIGS. ) And the same period tck.
　図１２は、絶縁通信部２Ａの他の構成例を示す図である。絶縁通信部２Ａは、２つの絶縁トランス９２，９４が直列に接続される。絶縁トランス９２と絶縁トランス９４とが直列接続されている接続点の絶縁トランス９２側にコンデンサ９８を介してＧＮＤ９６が接続され、接続点の絶縁トランス９４側にコンデンサ９９を介してＧＮＤ９７が接続されている。ＧＮＤ９６とＧＮＤ９７の間に電圧差が生じた場合に、絶縁トランス９２の寄生容量９３と絶縁トランス９４の寄生容量９５とにアンバランスが生じてもコンデンサ９８，９９が接続されているので印加される電圧が均等に分担される。 FIG. 12 is a diagram illustrating another configuration example of the insulated communication unit 2A. The insulating communication unit 2A has two insulating transformers 92 and 94 connected in series. A GND 96 is connected via a capacitor 98 to the insulation transformer 92 side of the connection point where the insulation transformer 92 and the insulation transformer 94 are connected in series, and a GND 97 is connected via the capacitor 99 to the insulation transformer 94 side of the connection point. Yes. When a voltage difference is generated between GND 96 and GND 97, capacitors 98 and 99 are applied even if imbalance occurs between the parasitic capacitance 93 of the insulating transformer 92 and the parasitic capacitance 95 of the insulating transformer 94. The voltage is shared equally.
　このような構成により、絶縁トランスを直列に接続しても各絶縁トランスに印加する電圧を低く抑えることができ、小型化した絶縁通信部を構成することができる。ここで、コンデンサ９８，９９は、容量が小さいことが耐ノイズ性から望ましく、寄生容量９３，９５のアンバランスを調整できれば良いため、たとえば、プリント基板での配線の寄生Ｃなどを用いることも可能である。その結果、半導体駆動装置の小型化も可能である。 With this configuration, the voltage applied to each isolation transformer can be kept low even if the isolation transformers are connected in series, and a miniaturized isolation communication unit can be configured. Here, it is desirable that the capacitors 98 and 99 have a small capacitance from the viewpoint of noise resistance, and it is sufficient that the unbalance of the parasitic capacitances 93 and 95 can be adjusted. It is. As a result, the semiconductor drive device can be reduced in size.
≪第４の実施形態≫
　第４の実施形態では、図８に示した半導体駆動装置１０ａを複数用いた場合における電力変換装置の応用例について説明する。
　図１３は、半導体駆動装置１０９，１１４，１１９，１２０，１２１，１２２を用いた電力変換装置２００の構成例を示す図である。半導体駆動装置１０９，１１４，１１９，１２０，１２１，１２２のそれぞれが、半導体駆動装置１０ａに該当する。
　本応用例は、上位論理回路１０１からの指令を受ける半導体スイッチング素子Ｑ１１，Ｑ１２，Ｑ１３，Ｑ１４，Ｑ１５，Ｑ１６を駆動する半導体駆動装置１０９，１１４，１１９，１２０，１２１，１２２を備え、負荷であるモータ１２３を駆動する三相インバータ型の電力変換装置２００である。 << Fourth Embodiment >>
In the fourth embodiment, an application example of the power conversion device when a plurality of semiconductor drive devices 10a shown in FIG. 8 are used will be described.
FIG. 13 is a diagram illustrating a configuration example of the power conversion device 200 using the semiconductor drive devices 109, 114, 119, 120, 121, and 122. Each of the semiconductor drive devices 109, 114, 119, 120, 121, and 122 corresponds to the semiconductor drive device 10a.
This application example includes semiconductor drive devices 109, 114, 119, 120, 121, and 122 that drive semiconductor switching elements Q11, Q12, Q13, Q14, Q15, and Q16 that receive a command from the higher-order logic circuit 101. This is a three-phase inverter type power converter 200 that drives a certain motor 123.
　上位論理回路１０１は、例えば、マイクロコンピュータを用いて構成され、オン指令演算回路１０２と連続パルス生成部１０３，１０４とを備えている。オン指令演算回路１０２は、半導体スイッチング素子（Ｑ１１，Ｑ１２，Ｑ１３，Ｑ１４，Ｑ１５，Ｑ１６）のオン、オフの指令信号（ＩＮ）と、クロック信号（ＣＬＫ）とを連続パルス生成部１０３，１０４に供給する。なお、半導体スイッチング素子のゲートをオンとする指令信号（ＩＮ）のことを指令信号オン（ＩＮ）と表記する。 The higher-order logic circuit 101 is configured using, for example, a microcomputer, and includes an ON command calculation circuit 102 and continuous pulse generation units 103 and 104. The on command calculation circuit 102 sends the on / off command signal (IN) of the semiconductor switching elements (Q11, Q12, Q13, Q14, Q15, Q16) and the clock signal (CLK) to the continuous pulse generators 103, 104. Supply. Note that a command signal (IN) for turning on the gate of the semiconductor switching element is referred to as a command signal on (IN).
　連続パルス生成部１０３は、オン指令演算回路１０２から供給されるクロック信号（ＣＬＫ）と指令信号オン（ＩＮ）に基づいて連続パルスを生成し、該連続パルスを保護回路１０７を介して半導体駆動装置１０９に供給する。
　連続パルス生成部１０４は、オン指令演算回路１０２から供給されるクロック信号と（ＣＬＫ）と指令信号オン（ＩＮ）に基づいて連続パルスを生成し、該連続パルスを保護回路１０６を介して半導体駆動装置１１４に供給する。 The continuous pulse generator 103 generates a continuous pulse based on the clock signal (CLK) and the command signal ON (IN) supplied from the ON command calculation circuit 102, and the continuous pulse is supplied to the semiconductor drive device via the protection circuit 107. 109.
The continuous pulse generation unit 104 generates a continuous pulse based on the clock signal, (CLK), and command signal ON (IN) supplied from the ON command calculation circuit 102, and drives the continuous pulse through the protection circuit 106 by semiconductor driving. Supply to device 114.
　また、上位論理回路１０１は、半導体駆動装置１１９，１２０，１２１，１２２のそれぞれに対応する連続パルス生成部（図示しない）を備え、それぞれの連続パルス生成部（図示しない）が保護回路（図示しない）を介して各半導体駆動装置（１１９，１２０，１２１，１２２）に接続されている。 The higher-order logic circuit 101 includes a continuous pulse generator (not shown) corresponding to each of the semiconductor driving devices 119, 120, 121, and 122, and each continuous pulse generator (not shown) is a protection circuit (not shown). ) To the respective semiconductor drive devices (119, 120, 121, 122).
　前記したように、半導体駆動装置１０９，１１４，１１９，１２０，１２１，１２２へ供給される指令信号オン（ＩＮ）に基づく連続パルスは、すべて同一のクロック信号（ＣＬＫ）に同期して出力される。
　なお、図１３では、直列接続されて上下アームを構成する半導体スイッチング素子Ｑ１１，Ｑ１２を駆動する半導体駆動装置１０９，１１４の回路構成を示し、同様の回路構成を備える半導体駆動装置１１９，１２０と半導体駆動装置１２１，１２２について図示を省略している。 As described above, continuous pulses based on the command signal ON (IN) supplied to the semiconductor drive devices 109, 114, 119, 120, 121, and 122 are all output in synchronization with the same clock signal (CLK). .
FIG. 13 shows the circuit configuration of the semiconductor drive devices 109 and 114 that drive the semiconductor switching elements Q11 and Q12 that are connected in series to form the upper and lower arms, and the semiconductor drive devices 119 and 120 having the same circuit configuration and the semiconductors. The driving devices 121 and 122 are not shown.
　半導体駆動装置１０９は、駆動部１１０，絶縁通信部１１１，出力部１１２，状態出力部１１３，状態信号駆動部１３０を備える。半導体駆動装置１０９と図８に示す半導体駆動装置１０ａとを対比すると、駆動部１１０が駆動部７に相当し、絶縁通信部１１１が絶縁通信部２に相当し、出力部１１２が出力部３Ａに相当し、状態出力部１１３が状態出力部６６に相当し、状態信号駆動部１３０が状態信号駆動部６７に相当する。 The semiconductor drive device 109 includes a drive unit 110, an insulation communication unit 111, an output unit 112, a state output unit 113, and a state signal drive unit 130. When the semiconductor drive device 109 and the semiconductor drive device 10a shown in FIG. 8 are compared, the drive unit 110 corresponds to the drive unit 7, the insulated communication unit 111 corresponds to the insulated communication unit 2, and the output unit 112 corresponds to the output unit 3A. The state output unit 113 corresponds to the state output unit 66, and the state signal drive unit 130 corresponds to the state signal drive unit 67.
　駆動部１１０は、保護回路１０７を介して供給される連続パルスに応じて絶縁通信部１１１にパルス電圧を印加する。絶縁通信部１１１は、絶縁トランスで構成され、該絶縁トランスの送信側（入力側）端子間に駆動部１１０からのパルス電圧が印加され、該絶縁トランスの受信側（出力側）端子間でパルス電圧が出力部１１２に出力される。 The driving unit 110 applies a pulse voltage to the insulating communication unit 111 in accordance with a continuous pulse supplied via the protection circuit 107. The insulation communication unit 111 is configured by an insulation transformer, and a pulse voltage from the drive unit 110 is applied between the transmission side (input side) terminals of the insulation transformer, and a pulse is generated between the reception side (output side) terminals of the insulation transformer. The voltage is output to the output unit 112.
　出力部１１２は、入力されるパルス電圧に基づいて一定幅の駆動電圧を半導体スイッチング素子Ｑ１１のゲートに出力する。この駆動電圧は、半導体スイッチング素子Ｑ１１のゲートをオンにする。
　状態信号駆動部１３０は、半導体スイッチング素子Ｑ１１のオン状態を判定して状態信号を絶縁通信部１１１の受信側に送信する。
　状態出力部１１３は、絶縁通信部１１１の送信側で受信される状態信号を半導体駆動装置１１４の駆動部１１５に出力する。 The output unit 112 outputs a drive voltage having a certain width to the gate of the semiconductor switching element Q11 based on the input pulse voltage. This drive voltage turns on the gate of the semiconductor switching element Q11.
The state signal driving unit 130 determines the ON state of the semiconductor switching element Q11 and transmits a state signal to the reception side of the insulated communication unit 111.
The state output unit 113 outputs a state signal received on the transmission side of the insulated communication unit 111 to the drive unit 115 of the semiconductor drive device 114.
　半導体駆動装置１１４は、駆動部１１５に状態信号が入力されることにより、半導体スイッチング素子Ｑ１１のオン，オフ状態を検知することができる。
　一方、半導体駆動装置１１４は、駆動部１１５，絶縁通信部１１６，出力部１１７，状態出力部１１８，状態信号駆動部１３１を備える。半導体駆動装置１１４と図８に示す半導体駆動装置１０ａとを対比すると、駆動部１１５が駆動部７に相当し、絶縁通信部１１６が絶縁通信部２に相当し、出力部１１７が出力部３Ａに相当し、状態出力部１１８が状態出力部６６に相当し、状態信号駆動部１３１が状態信号駆動部６７に相当する。 The semiconductor drive device 114 can detect the on / off state of the semiconductor switching element Q11 when a state signal is input to the drive unit 115.
On the other hand, the semiconductor drive device 114 includes a drive unit 115, an insulation communication unit 116, an output unit 117, a state output unit 118, and a state signal drive unit 131. When comparing the semiconductor drive device 114 with the semiconductor drive device 10a shown in FIG. 8, the drive unit 115 corresponds to the drive unit 7, the insulated communication unit 116 corresponds to the insulated communication unit 2, and the output unit 117 serves as the output unit 3A. The state output unit 118 corresponds to the state output unit 66, and the state signal drive unit 131 corresponds to the state signal drive unit 67.
　駆動部１１５は、保護回路１０６を介して供給される連続パルスに応じて絶縁通信部１１６にパルス電圧を印加する。絶縁通信部１１６は、絶縁トランスで構成され、該絶縁トランスの送信側（入力側）端子間に駆動部１１５からのパルス電圧が印加され、該絶縁トランスの受信側（出力側）端子間でパルス電圧が出力部１１７に出力される。 The driving unit 115 applies a pulse voltage to the insulating communication unit 116 in accordance with a continuous pulse supplied via the protection circuit 106. The insulation communication unit 116 is configured by an insulation transformer, and a pulse voltage from the drive unit 115 is applied between the transmission side (input side) terminals of the insulation transformer, and a pulse is generated between the reception side (output side) terminals of the insulation transformer. The voltage is output to the output unit 117.
　出力部１１７は、入力されるパルス電圧に基づいて一定幅の駆動電圧を半導体スイッチング素子Ｑ１２のゲートに出力する。この駆動電圧は、半導体スイッチング素子Ｑ１２のゲートをオンにする。
　状態信号駆動部１３１は、半導体スイッチング素子Ｑ１２のオン状態を判定して状態信号を絶縁通信部１１６の受信側に送信する。
　状態出力部１１８は、絶縁通信部１１６の送信側で受信される状態信号を半導体駆動装置１０９の駆動部１１０に出力する。
　半導体駆動装置１０９は、駆動部１１０に状態信号が入力されることにより、半導体スイッチング素子Ｑ１２のオン，オフ状態を検知することができる。 The output unit 117 outputs a drive voltage having a certain width to the gate of the semiconductor switching element Q12 based on the input pulse voltage. This drive voltage turns on the gate of the semiconductor switching element Q12.
The state signal driver 131 determines the ON state of the semiconductor switching element Q12 and transmits a state signal to the reception side of the insulated communication unit 116.
The state output unit 118 outputs a state signal received on the transmission side of the insulating communication unit 116 to the drive unit 110 of the semiconductor drive device 109.
The semiconductor drive device 109 can detect the on / off state of the semiconductor switching element Q12 when a state signal is input to the drive unit 110.
　前記したように、半導体スイッチング素子Ｑ１１のオン、オフの状態が、半導体スイッチング素子Ｑ１１を駆動する半導体駆動装置１０９の状態信号駆動部１３０，絶縁通信部１１１，状態出力部１１３を経由して半導体スイッチング素子Ｑ１２の半導体駆動装置１１４の駆動部１１５に伝送される。
　同様に、半導体スイッチング素子Ｑ１２のオン、オフの状態が、半導体スイッチング素子Ｑ１２を駆動する半導体駆動装置１１４の状態信号駆動部１３１，絶縁通信部１１６，状態出力部１１８を経由して半導体スイッチング素子Ｑ１１の半導体駆動装置１０９の駆動部１１０に伝送される。 As described above, the semiconductor switching element Q11 is turned on and off via the state signal driving unit 130, the insulating communication unit 111, and the state output unit 113 of the semiconductor driving device 109 that drives the semiconductor switching element Q11. It is transmitted to the drive unit 115 of the semiconductor drive device 114 of the element Q12.
Similarly, the semiconductor switching element Q12 is turned on and off via the state signal driving unit 131, the insulating communication unit 116, and the state output unit 118 of the semiconductor driving device 114 that drives the semiconductor switching element Q12. Is transmitted to the drive unit 110 of the semiconductor drive device 109.
　このような構成により、インバータ（半導体駆動装置１０９，１１４）の対となる上下のアーム間で、双方向通信により受信した対アームの半導体スイッチング素子（Ｑ１１，Ｑ１２）のオン、オフの状態を共有し、対アームがオンの時には自アームをオンしないように制御される。
　そして、半導体駆動装置１１９，１２０と半導体駆動装置１２１，１２２とが、前記した半導体駆動装置１０９，１１４と同様に対アームとして制御される。 With such a configuration, the on / off states of the paired semiconductor switching elements (Q11, Q12) received by bidirectional communication are shared between the upper and lower arms that form a pair of the inverters (semiconductor driving devices 109, 114). When the pair arm is on, control is performed so that the own arm is not turned on.
Then, the semiconductor drive devices 119 and 120 and the semiconductor drive devices 121 and 122 are controlled as a pair of arms similarly to the semiconductor drive devices 109 and 114 described above.
　なお、本応用例では、上位論理回路１０１と各半導体駆動装置（１０９，１１４，１１９，１２０，１２１，１２２）との間に、保護回路１０６，１０７，及び図示しない保護回路を設けている。保護回路１０６，１０７，及び図示しない保護回路は、サージ吸収回路，ヒューズ等で構成され、各半導体駆動装置の絶縁通信部や他の部分で放電等が生じた場合を想定し、このときに発生する過電流や過電圧によって上位論理回路１０１に破壊が生じないようにしている。 In this application example, protection circuits 106 and 107 and a protection circuit (not shown) are provided between the upper logic circuit 101 and each semiconductor drive device (109, 114, 119, 120, 121, 122). The protection circuits 106 and 107 and the protection circuit (not shown) are composed of a surge absorption circuit, a fuse, and the like, and are assumed at the time when a discharge or the like occurs in the insulation communication part or other part of each semiconductor drive device. Therefore, the upper logic circuit 101 is prevented from being damaged by the overcurrent and the overvoltage.
　この第４の実施形態によれば、電力変換装置２００は、ノイズ等により誤まった指令が発生しても、対アームの半導体スイッチング素子の同時オンによる不具合を回避でき、信頼性の高い制御を可能とする。
　また、電力変換装置２００は、指令信号と連続パルス信号とが同期するので、半導体スイッチング素子のゲートのオン期間の時間精度が高く、より高精度な制御を可能とする。 According to the fourth embodiment, the power conversion device 200 can avoid a malfunction due to simultaneous turn-on of the semiconductor switching elements of the opposite arm even when an erroneous command is generated due to noise or the like, and performs highly reliable control. Make it possible.
In addition, since the command signal and the continuous pulse signal are synchronized with each other, the power conversion device 200 has a high time accuracy of the on period of the gate of the semiconductor switching element, and enables more accurate control.
　さらに、電力変換装置２００は、オン期間の時間精度を高めるために上位論理回路１０１からのクロック信号に各半導体駆動装置間の連続パルスを同期させるようにしても良く、各半導体駆動装置間のパルス出力を同期させるようにしても良い。
　また、保護回路を用いることにより、電力変換装置２００を、より高精度で信頼性の高い装置にすることができる。
　前記した半導体駆動装置、電力変換装置を用いることにより、例えば、高速鉄道などの交通手段、風力発電などの発電設備で、小型、高精度、さらに信頼性の高い機器を提供することができる。 Further, the power conversion device 200 may synchronize the continuous pulse between the semiconductor driving devices with the clock signal from the higher-order logic circuit 101 in order to increase the time accuracy of the ON period. The output may be synchronized.
Further, by using the protection circuit, the power conversion device 200 can be a highly accurate and reliable device.
By using the semiconductor drive device and the power conversion device described above, it is possible to provide a small, highly accurate, and highly reliable device using, for example, transportation means such as a high-speed railway and power generation facilities such as wind power generation.
　１，４１，６１　指令信号駆動部
　２，４２　絶縁通信部
　３，４３，６３　出力部
　４　　　負荷
　５　　　電源
　６　　　連続パルス生成部
　７　　　駆動部
　８　　　判定部
　９　　　出力パルス生成部
　１０，１０ａ，１０ｂ　半導体駆動装置
　１２，５３　絶縁トランス
　１９　　駆動回路
　２０　　駆動指令側ＧＮＤ
　２１　　オン指令出力側ＧＮＤ
　２４　　立上りエッジパルス発生回路（第１のパルス発生回路）
　２５　　立下りエッジパルス発生回路（第２のパルス発生回路）
　６６　　状態出力部
　６７　　状態信号駆動部
　１００，１００ａ，２００　電力変換装置
　Ｑ１，Ｑ１１，Ｑ１２，Ｑ１３，Ｑ１４，Ｑ１５，Ｑ１６　半導体スイッチング素子
　９２，９４　絶縁トランス（第１のトランス、第２のトランス）
　９３，９５　コンデンサ（第１のコンデンサ、第２のコンデンサ）
　２０１，２０３　電圧調整回路（第１、第２の基準電圧調整回路）
　２０２，２０４　電圧調整回路（第１、第２の判定電圧調整回路） DESCRIPTION OF SYMBOLS 1,41,61 Command signal drive part 2,42 Insulation communication part 3,43,63 Output part 4 Load 5 Power supply 6 Continuous pulse generation part 7 Drive part 8 Judgment part 9 Output pulse generation part 10, 10a, 10b Semiconductor drive device 12, 53 Insulation transformer 19 Drive circuit 20 Drive command side GND
21 ON command output side GND
24 Rising edge pulse generation circuit (first pulse generation circuit)
25 Falling edge pulse generation circuit (second pulse generation circuit)
66 State output unit 67 State signal drive unit 100, 100a, 200 Power conversion device Q1, Q11, Q12, Q13, Q14, Q15, Q16 Semiconductor switching element 92, 94 Insulating transformer (first transformer, second transformer)
93,95 capacitor (first capacitor, second capacitor)
201, 203 Voltage adjustment circuit (first and second reference voltage adjustment circuits)
202, 204 Voltage adjustment circuit (first and second determination voltage adjustment circuits)

Claims (17)

  1. 　半導体スイッチング素子のオン、オフを駆動制御する半導体駆動装置において、
    　前記半導体スイッチング素子のオン駆動を指令する期間中、該オン駆動を指令する連続パルスの電圧信号を生成する指令信号駆動部と、
    　前記指令信号駆動部を介して生成される連続パルスの電圧信号をトランスにより伝送する絶縁通信部と、
    　前記絶縁通信部で伝送される連続パルスの電圧信号に基づいて、前記連続パルスを構成するパルス間のすき間を埋めるように前記半導体スイッチング素子をオン駆動する駆動電圧を生成して出力する出力部と、
    　を備えることを特徴とする半導体駆動装置。     In a semiconductor drive device that drives and controls on / off of a semiconductor switching element,
    A command signal drive unit that generates a voltage signal of a continuous pulse that commands the on-drive during a period of commanding the on-drive of the semiconductor switching element;
    An insulating communication unit that transmits a voltage signal of a continuous pulse generated through the command signal driving unit by a transformer;
    An output unit for generating and outputting a drive voltage for driving the semiconductor switching element to fill a gap between pulses constituting the continuous pulse based on a voltage signal of the continuous pulse transmitted by the insulation communication unit; ,
    A semiconductor drive device comprising:
  2. 　前記指令信号駆動部は、前記連続パルスの立上りエッジに対応して所定幅のパルス電圧を出力する第１のパルス発生回路と、前記連続パルスの立下りエッジに対応して所定幅のパルス電圧を出力する第２のパルス発生回路と、を備え、
    　前記第１のパルス発生回路から出力されるパルス電圧が前記絶縁通信部のトランスの一方の入力端子に印加され、前記第２のパルス発生回路から出力されるパルス電圧が前記絶縁通信部のトランスの他方の入力端子に印加されることを特徴とする請求項１に記載の半導体駆動装置。     The command signal drive unit outputs a pulse voltage having a predetermined width corresponding to the rising edge of the continuous pulse, and a pulse voltage having a predetermined width corresponding to the falling edge of the continuous pulse. A second pulse generation circuit for outputting,
    A pulse voltage output from the first pulse generation circuit is applied to one input terminal of the transformer of the insulation communication unit, and a pulse voltage output from the second pulse generation circuit is applied to the transformer of the insulation communication unit. The semiconductor drive device according to claim 1, wherein the semiconductor drive device is applied to the other input terminal.
  3. 　前記出力部は、前記絶縁通信部のトランスの一方の出力端子と他方の出力端子との間に発生する端子間電圧を入力して連続パルス電圧を出力する判定部を備え、該出力される連続パルス電圧のエッジをトリガにして前記指令信号駆動部で生成される連続パルスの周期の１／２より長い所定幅のパルスに応じて駆動電圧を出力することを特徴とする請求項１に記載の半導体駆動装置。 The output unit includes a determination unit that inputs a voltage between terminals generated between one output terminal and the other output terminal of the transformer of the insulation communication unit and outputs a continuous pulse voltage, and outputs the continuous The drive voltage is output according to a pulse having a predetermined width longer than a half of a period of a continuous pulse generated by the command signal drive unit using an edge of a pulse voltage as a trigger. Semiconductor drive device.
  4. 　前記判定部は、
    　前記絶縁通信部のトランスの一方の出力端子に接続され、基準レベルの電圧を調整する第１の基準電圧調整回路と、判定レベルの電圧を調整する第１の判定電圧調整回路とを備えるとともに、
    　前記絶縁通信部のトランスの他方の出力端子に接続され、基準レベルの電圧を調整する第２の基準電圧調整回路と、判定レベルの電圧を調整する第２の判定電圧調整回路とを備えることを特徴とする請求項３に記載の半導体駆動装置。     The determination unit
    A first reference voltage adjustment circuit that is connected to one output terminal of the transformer of the insulation communication unit and adjusts a reference level voltage; and a first determination voltage adjustment circuit that adjusts a determination level voltage;
    A second reference voltage adjusting circuit for adjusting a reference level voltage, and a second determination voltage adjusting circuit for adjusting a determination level voltage, which is connected to the other output terminal of the transformer of the isolation communication unit; The semiconductor drive device according to claim 3, characterized in that:
  5. 　前記第１の基準電圧調整回路と前記第２の判定電圧調整回路とに同一電圧が入力された場合に、前記第１の基準電圧調整回路から出力される基準電圧よりも前記第２の判定電圧調整回路から出力される判定電圧が低くなるように電圧調整され、
    　前記第２の基準電圧調整回路と前記第１の判定電圧調整回路とに同一電圧が入力された場合に、前記第２の基準電圧調整回路から出力される基準電圧よりも前記第１の判定電圧調整回路から出力される判定電圧が低くなるように電圧調整されていることを特徴とする請求項４に記載の半導体駆動装置。     When the same voltage is input to the first reference voltage adjustment circuit and the second determination voltage adjustment circuit, the second determination voltage is higher than the reference voltage output from the first reference voltage adjustment circuit. The voltage is adjusted so that the judgment voltage output from the adjustment circuit is low,
    When the same voltage is input to the second reference voltage adjustment circuit and the first determination voltage adjustment circuit, the first determination voltage is higher than the reference voltage output from the second reference voltage adjustment circuit. The semiconductor drive device according to claim 4, wherein the voltage is adjusted so that the determination voltage output from the adjustment circuit is low.
  6. 　前記出力部は、前記絶縁通信部で伝送される連続パルスの電圧信号を全波整流する全波整流回路を備えることを特徴とする請求項１に記載の半導体駆動装置。 2. The semiconductor drive device according to claim 1, wherein the output unit includes a full-wave rectification circuit that full-wave rectifies a voltage signal of a continuous pulse transmitted by the insulating communication unit.
  7. 　前記絶縁通信部は、直列に接続される第１のトランスと第２のトランスとを備え、該第１のトランスと該第２のトランスの接続点に第１のコンデンサと第２のコンデンサが接続され、該第１のコンデンサの他端が前記指令信号駆動部側に接地され、該第２のコンデンサの他端が前記出力部側に接地されて構成されることを特徴とする請求項１に記載の半導体駆動装置。 The insulation communication unit includes a first transformer and a second transformer connected in series, and a first capacitor and a second capacitor are connected to a connection point of the first transformer and the second transformer. The other end of the first capacitor is grounded to the command signal driving unit side, and the other end of the second capacitor is grounded to the output unit side. The semiconductor drive device described.
  8. 　前記半導体駆動装置が、
    　前記半導体スイッチング素子のオン状態を検知して前記指令信号駆動部で生成される連続パルスとは異なる第２の連続パルスの電圧信号を生成し、該第２の連続パルスの電圧信号を前記絶縁通信部のトランスに印加する状態信号駆動部と、
    　前記絶縁通信部で伝送される前記第２の連続パルスの電圧信号に基づいて、前記第２の連続パルスを構成するパルス間のすき間を埋めるように前記半導体スイッチング素子のオン状態の検知信号を生成して出力する状態出力部と、
    　をさらに備えることを特徴とする請求項１に記載の半導体駆動装置。     The semiconductor drive device is
    A voltage signal of a second continuous pulse different from a continuous pulse generated by the command signal driving unit is detected by detecting an ON state of the semiconductor switching element, and the voltage signal of the second continuous pulse is generated by the insulation communication A state signal driving unit to be applied to the transformer of the unit;
    Based on the voltage signal of the second continuous pulse transmitted by the insulating communication unit, a detection signal for detecting the ON state of the semiconductor switching element is generated so as to fill a gap between pulses constituting the second continuous pulse. A status output unit that outputs
    The semiconductor drive device according to claim 1, further comprising:
  9. 　半導体スイッチング素子と、該半導体スイッチング素子のオン、オフを駆動制御する半導体駆動装置とを備えた電力変換装置であって、
    　前記半導体駆動装置が、
    　前記半導体スイッチング素子のオン駆動を指令する期間中、該オン駆動を指令する連続パルスの電圧信号を生成する指令信号駆動部と、
    　前記指令信号駆動部で生成される連続パルスの電圧信号をトランスにより伝送する絶縁通信部と、
    　前記絶縁通信部を介して伝送される連続パルスの電圧信号に基づいて、前記連続パルスを構成するパルス間のすき間を埋めるように前記半導体スイッチング素子をオン駆動する駆動電圧を生成して出力する出力部と、
    　を備えることを特徴とする電力変換装置。     A power conversion device comprising a semiconductor switching element and a semiconductor drive device that controls driving of the semiconductor switching element on and off,
    The semiconductor drive device is
    A command signal drive unit that generates a voltage signal of a continuous pulse that commands the on-drive during a period of commanding the on-drive of the semiconductor switching element;
    An insulating communication unit that transmits a voltage signal of a continuous pulse generated by the command signal driving unit by a transformer;
    An output for generating and outputting a drive voltage for driving the semiconductor switching element to fill a gap between pulses constituting the continuous pulse based on a voltage signal of the continuous pulse transmitted through the insulation communication unit And
    A power conversion device comprising:
  10. 　前記指令信号駆動部は、前記連続パルスの立上りエッジに対応して所定幅のパルス電圧を出力する第１のパルス発生回路と、前記連続パルスの立下りエッジに対応して所定幅のパルス電圧を出力する第２のパルス発生回路と、を備え、
    　前記第１のパルス発生回路から出力されるパルス電圧が前記絶縁通信部のトランスの一方の入力端子に印加され、前記第２のパルス発生回路から出力されるパルス電圧が前記絶縁通信部のトランスの他方の入力端子に印加されることを特徴とする請求項９に記載の電力変換装置。     The command signal drive unit outputs a pulse voltage having a predetermined width corresponding to the rising edge of the continuous pulse, and a pulse voltage having a predetermined width corresponding to the falling edge of the continuous pulse. A second pulse generation circuit for outputting,
    A pulse voltage output from the first pulse generation circuit is applied to one input terminal of the transformer of the insulation communication unit, and a pulse voltage output from the second pulse generation circuit is applied to the transformer of the insulation communication unit. The power converter according to claim 9, wherein the power converter is applied to the other input terminal.
  11. 　前記出力部は、前記絶縁通信部のトランスの一方の出力端子と他方の出力端子との間に発生する端子間電圧を入力して連続パルス電圧を出力する判定部を備え、該出力される連続パルス電圧のエッジをトリガにして前記指令信号駆動部で生成される連続パルスの周期の１／２より長い所定幅のパルスに応じて駆動電圧を出力することを特徴とする請求項９に記載の電力変換装置。 The output unit includes a determination unit that inputs a voltage between terminals generated between one output terminal and the other output terminal of the transformer of the insulation communication unit and outputs a continuous pulse voltage, and outputs the continuous The drive voltage is output according to a pulse having a predetermined width longer than a half of a period of a continuous pulse generated by the command signal drive unit using a pulse voltage edge as a trigger. Power conversion device.
  12. 　前記判定部は、
    　前記絶縁通信部のトランスの一方の出力端子に接続され、基準レベルの電圧を調整する第１の基準電圧調整回路と、判定レベルの電圧を調整する第１の判定電圧調整回路とを備えるとともに、
    　前記絶縁通信部のトランスの他方の出力端子に接続され、基準レベルの電圧を調整する第２の基準電圧調整回路と、判定レベルの電圧を調整する第２の判定電圧調整回路とを備えることを特徴とする請求項１１に記載の電力変換装置。     The determination unit
    A first reference voltage adjustment circuit that is connected to one output terminal of the transformer of the insulation communication unit and adjusts a reference level voltage; and a first determination voltage adjustment circuit that adjusts a determination level voltage;
    A second reference voltage adjusting circuit for adjusting a reference level voltage, and a second determination voltage adjusting circuit for adjusting a determination level voltage, which is connected to the other output terminal of the transformer of the isolation communication unit; The power converter according to claim 11, wherein
  13. 　前記第１の基準電圧調整回路と前記第２の判定電圧調整回路とに同一電圧が入力された場合に、前記第１の基準電圧調整回路から出力される基準電圧よりも前記第２の判定電圧調整回路から出力される判定電圧が低くなるように電圧調整され、
    　前記第２の基準電圧調整回路と前記第１の判定電圧調整回路とに同一電圧が入力された場合に、前記第２の基準電圧調整回路から出力される基準電圧よりも前記第１の判定電圧調整回路から出力される判定電圧が低くなるように電圧調整されていることを特徴とする請求項１２に記載の電力変換装置。     When the same voltage is input to the first reference voltage adjustment circuit and the second determination voltage adjustment circuit, the second determination voltage is higher than the reference voltage output from the first reference voltage adjustment circuit. The voltage is adjusted so that the judgment voltage output from the adjustment circuit is low,
    When the same voltage is input to the second reference voltage adjustment circuit and the first determination voltage adjustment circuit, the first determination voltage is higher than the reference voltage output from the second reference voltage adjustment circuit. The power conversion device according to claim 12, wherein the voltage is adjusted so that the determination voltage output from the adjustment circuit is low.
  14. 　前記出力部は、前記絶縁通信部で伝送される連続パルスの電圧信号を全波整流する全波整流回路を備えることを特徴とする請求項９に記載の電力変換装置。 The power conversion device according to claim 9, wherein the output unit includes a full-wave rectification circuit that full-wave rectifies a voltage signal of a continuous pulse transmitted by the insulation communication unit.
  15. 　前記絶縁通信部は、直列に接続される第１のトランスと第２のトランスとを備え、該第１のトランスと該第２のトランスの接続点に第１のコンデンサと第２のコンデンサが接続され、該第１のコンデンサの他端が前記指令信号駆動部側に接地され、該第２のコンデンサの他端が前記出力部側に接地されて構成されることを特徴とする請求項９に記載の電力変換装置。 The insulation communication unit includes a first transformer and a second transformer connected in series, and a first capacitor and a second capacitor are connected to a connection point of the first transformer and the second transformer. The other end of the first capacitor is grounded to the command signal drive unit side, and the other end of the second capacitor is grounded to the output unit side. The power converter described.
  16. 　前記半導体駆動装置が、
    　前記半導体スイッチング素子のオン状態を検知して前記指令信号駆動部で生成される連続パルスとは異なる第２の連続パルスの電圧信号を生成し、該第２の連続パルスの電圧信号を前記絶縁通信部のトランスに印加する状態信号駆動部と、
    　前記絶縁通信部で伝送される前記第２の連続パルスの電圧信号に基づいて、前記第２の連続パルスを構成するパルス間のすき間を埋めるように前記半導体スイッチング素子のオン状態の検知信号を生成して出力する状態出力部と、
    　をさらに備えることを特徴とする請求項９に記載の電力変換装置。     The semiconductor drive device is
    A voltage signal of a second continuous pulse different from a continuous pulse generated by the command signal driving unit is detected by detecting an ON state of the semiconductor switching element, and the voltage signal of the second continuous pulse is generated by the insulation communication A state signal driving unit to be applied to the transformer of the unit;
    Based on the voltage signal of the second continuous pulse transmitted by the insulating communication unit, a detection signal for detecting the ON state of the semiconductor switching element is generated so as to fill a gap between pulses constituting the second continuous pulse. A status output unit that outputs
    The power converter according to claim 9, further comprising:
  17. 　２個の半導体スイッチング素子が直列接続されて構成される上下アームを複数組備え、前記半導体スイッチング素子ごとにオン、オフを駆動制御する複数の半導体駆動装置を備えた電力変換装置であって、
    　前記半導体駆動装置が、
    　前記半導体スイッチング素子のオン駆動を指令する期間中、該オン駆動を指令する第１の連続パルスの電圧信号を生成する指令信号駆動部と、
    　前記指令信号駆動部で生成される第１の連続パルスの電圧信号をトランスにより伝送する絶縁通信部と、
    　前記絶縁通信部を介して伝送される第１の連続パルスの電圧信号に基づいて、前記連続パルスを構成するパルス間のすき間を埋めるように前記半導体スイッチング素子をオン駆動する駆動電圧を生成して出力する出力部と、
    　前記半導体スイッチング素子のオン状態を検知して第２の連続パルスの電圧信号を生成し、該第２の連続パルスの電圧信号を前記絶縁通信部のトランスに印加する状態信号駆動部と、
    　前記絶縁通信部で伝送される前記第２の連続パルスの電圧信号に基づいて、前記連続パルスを構成するパルス間のすき間を埋めるように前記半導体スイッチング素子のオン状態の検知信号を生成し、当該半導体駆動装置が駆動制御する半導体スイッチング素子の上下アームを構成する他方の半導体スイッチング素子を駆動制御する半導体駆動装置が備える指令信号駆動部に該検知信号を出力する状態出力部と、
    　を備えることを特徴とする電力変換装置。     A power conversion device comprising a plurality of upper and lower arms configured by connecting two semiconductor switching elements in series, and comprising a plurality of semiconductor drive devices for driving on and off for each of the semiconductor switching elements,
    The semiconductor drive device is
    A command signal drive unit that generates a voltage signal of a first continuous pulse that commands the on-drive during a period of commanding the on-drive of the semiconductor switching element;
    An insulated communication unit that transmits a voltage signal of a first continuous pulse generated by the command signal driving unit by a transformer;
    Based on the voltage signal of the first continuous pulse transmitted through the insulation communication unit, a drive voltage for driving the semiconductor switching element to be turned on so as to fill a gap between the pulses constituting the continuous pulse is generated. An output section to output,
    A state signal driving unit that detects an ON state of the semiconductor switching element to generate a voltage signal of the second continuous pulse, and applies the voltage signal of the second continuous pulse to the transformer of the insulating communication unit;
    Based on the voltage signal of the second continuous pulse transmitted by the insulation communication unit, the detection signal of the ON state of the semiconductor switching element is generated so as to fill a gap between pulses constituting the continuous pulse, A state output unit that outputs the detection signal to a command signal drive unit included in the semiconductor drive device that drives and controls the other semiconductor switching element that constitutes the upper and lower arms of the semiconductor switching element that is driven and controlled by the semiconductor drive device;
    A power conversion device comprising:
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013100005A1 (en) * 2011-12-28 2013-07-04 株式会社日立製作所 Communication system, semiconductor drive device, and power conversion device
JP2019062263A (en) * 2017-09-25 2019-04-18 三菱電機株式会社 Semiconductor integrated circuit
WO2024069449A1 (en) * 2022-09-28 2024-04-04 Delphi Technologies Ip Limited Systems and methods for non-overlap enforcement for inverter for electric vehicle
WO2024069400A1 (en) * 2022-09-28 2024-04-04 Delphi Technologies Ip Limited Systems and methods for non-overlap enforcement for inverter for electric vehicle

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012067282A1 (en) 2010-11-17 2012-05-24 (주)이지템 Mobile device and method for measuring temperature of thermal picture including body temperature
CN108065915B (en) * 2017-11-01 2021-06-08 杭州远舟医疗科技有限公司 Infrared-based constitution identification method, electronic equipment, storage medium and system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006074372A (en) * 2004-09-01 2006-03-16 Toshiba Corp Digital signal transmitter

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220204A (en) * 1991-05-24 1993-06-15 Rockwell International Corporation Voltage and temperature compensated emitter-follower driver
JP3417127B2 (en) * 1995-03-01 2003-06-16 松下電工株式会社 Drive circuit of power converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006074372A (en) * 2004-09-01 2006-03-16 Toshiba Corp Digital signal transmitter

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013100005A1 (en) * 2011-12-28 2013-07-04 株式会社日立製作所 Communication system, semiconductor drive device, and power conversion device
JP2013138389A (en) * 2011-12-28 2013-07-11 Hitachi Ltd Communication system, semiconductor drive device, and power conversion device
JP2019062263A (en) * 2017-09-25 2019-04-18 三菱電機株式会社 Semiconductor integrated circuit
JP7038511B2 (en) 2017-09-25 2022-03-18 三菱電機株式会社 Semiconductor integrated circuit
WO2024069449A1 (en) * 2022-09-28 2024-04-04 Delphi Technologies Ip Limited Systems and methods for non-overlap enforcement for inverter for electric vehicle
WO2024069400A1 (en) * 2022-09-28 2024-04-04 Delphi Technologies Ip Limited Systems and methods for non-overlap enforcement for inverter for electric vehicle

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