WO2011016641A2 - Substrate for ball grid array semiconductor package and fabrication method thereof - Google Patents

Substrate for ball grid array semiconductor package and fabrication method thereof Download PDF

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Publication number
WO2011016641A2
WO2011016641A2 PCT/KR2010/004909 KR2010004909W WO2011016641A2 WO 2011016641 A2 WO2011016641 A2 WO 2011016641A2 KR 2010004909 W KR2010004909 W KR 2010004909W WO 2011016641 A2 WO2011016641 A2 WO 2011016641A2
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Prior art keywords
substrate
grid array
ball grid
semiconductor package
array semiconductor
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PCT/KR2010/004909
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French (fr)
Korean (ko)
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WO2011016641A3 (en
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김운수
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주식회사 일렉켐
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Publication of WO2011016641A2 publication Critical patent/WO2011016641A2/en
Publication of WO2011016641A3 publication Critical patent/WO2011016641A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a substrate for a ball grid array semiconductor package and a method of manufacturing the same.
  • the present invention relates to a substrate for a ball grid array semiconductor package manufactured by plating a conductive metal without using an adhesive to bond the conductive metal to a bismarademide triazine film.
  • packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability.
  • the demand for miniaturization is accelerating the development of technologies for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting and mechanical and electrical reliability after mounting. I'm making it.
  • the ball grid array semiconductor package has an overall size of the semiconductor package that is about the same as or similar to that of a semiconductor chip.
  • the ball grid array semiconductor package includes solder balls as an electrical connection means to the outside, that is, a mounting means on a printed circuit board.
  • a substrate for a ball grid array semiconductor package used in the related art has a structure in which a copper thin film layer is laminated on a substrate substrate through an adhesive.
  • the copper thin film adhesive type substrate substrate as described above uses the copper thin film in mass production as it is, so that the thickness of the copper thin film laminated on the upper portion of the base substrate cannot be freely controlled to be less than the thickness of the applied copper thin film. Accordingly, there is a problem that fine patterning is difficult in an etching process for forming a circuit or a terminal on a base substrate.
  • An object of the present invention for solving the problems of the prior art described above is a ball grid that can control the thickness of the metal thin film provided in the substrate for the ball grid array semiconductor package freely, and can strengthen the adhesion between the substrate substrate and the metal thin film
  • the present invention provides a substrate for an array semiconductor package and a method of manufacturing the same.
  • a substrate for a ball grid array semiconductor package for achieving the above object, the substrate substrate formed of bismarimide triazine; A first electroless plating layer formed on the base substrate; And a first electroplating layer formed on the first electroless plating layer. It includes.
  • the surface of the substrate may be etched to form an imide group or a carboxyl group, and a coupling agent may be bonded to the imide group or the carboxyl group.
  • the first electroless plating layer is a metal selected from at least one member selected from the group consisting of gold, nickel and copper.
  • the first electroplating layer is a metal selected from one or more types from the group consisting of gold, nickel and copper.
  • a said 1st electroless plating layer is 0.2 micrometer or less.
  • the said 1st electroplating layer is 10-20 micrometers.
  • the method of manufacturing a substrate for a ball grid array semiconductor package of the present invention comprises the steps of: 1) etching cleavage of the surface of the substrate substrate formed of bismarademide triazine with an etching solution to generate an imide group or a carboxyl group on the surface; 2) introducing a coupling agent to the surface of the base substrate and coupling the imide group or carboxyl group; 3) forming a first electroless plating layer on the surface of the base substrate; And 4) forming a first electroplating layer on the first electroless plating layer; It includes.
  • the method of manufacturing a substrate for a ball grid array semiconductor package may further include: 5) forming at least one through hole having a size of 3 to 7 ⁇ m in a desired portion of the substrate; 6) forming a second electroless plating layer on the through hole and the surface of the substrate by an electroless plating method; 7) forming a second electroplating layer on the surface of the second electroless plating layer by an electroplating method; 8) providing a mask having a diameter exceeding a diameter of the through hole on the through hole; And 9) etching away portions other than the mask to leave only the substrate substrate. Do more.
  • the manufacturing method of the substrate for the ball grid array semiconductor package further comprises: 5) forming at least one through hole having a size of 3 ⁇ 7 ⁇ m in the desired portion of the substrate; 6) forming a second electroless plating layer on the surface of the through hole and the substrate by an electroless plating method; 7) providing a mask on the substrate to expose the diameter of the through hole to exceed; 8) forming a second electroplating layer on the second electroless plating layer by an electroplating method; And 9) removing the mask and etching the lower portion of the mask to leave only the substrate. Do more.
  • the etching solution is at least one selected from the group consisting of potassium hydroxide, sodium hydroxide, calcium hydroxide and magnesium hydroxide as hydroxides, and selected from the group consisting of ethylene glycol, propylene glycol, butanediol, neopentyl glycol and diethylene glycol as alcohols. It can be used the thing of the solution which mixed 1 or more types chosen from dimethylacetamide or dimethylformamide which is 1 or more types of nitrogen compounds.
  • the etching solution may be mixed with 1 to 3 parts by weight of alcohol to 14 parts by weight of hydroxide, and is preferably prepared by mixing 1 to 3 parts by weight of a nitrogen compound to 2 parts by weight of alcohol.
  • the etching may immerse the substrate substrate in the etching solution at 45 to 50 °C 5-7 minutes.
  • Bonding palladium or tin to the base substrate may be further performed between step 2) and step 3).
  • the first electroless plating layer and the second electroless plating layer may be formed of gold, nickel, or copper.
  • the first electrolytic plating layer and the second electrolytic plating layer may be formed of gold, nickel or copper.
  • the thickness of a said 1st electroless plating layer is 0.2 micrometer or less.
  • the formation thickness of the said 1st electroplating layer is about 10-20 micrometers.
  • the substrate for a ball grid array semiconductor package of the present invention is formed of bismarimide triazine and provided with a plurality of through holes; A first electroless plating layer formed on the base substrate; A first electroplating layer formed on the first electroless plating layer; A second electroless plating layer formed in and around the through hole; A second electroplating layer formed on the second electroless plating layer; It includes.
  • Conductive metal plated bismarimide triazine film manufacturing method is formed by forming a metal thin film on the substrate substrate by a plating method, unlike the conventional method does not adhere the metal thin film to the substrate substrate using an adhesive The thickness of the metal thin film can be freely adjusted.
  • the metal thin film is directly formed on the base substrate by the plating method, the formed metal thin film has excellent adhesion to the base substrate.
  • the bismarimide triazine film plated with the conductive metal of the present invention does not use an adhesive layer, it is excellent in heat resistance, chemical resistance and migration, and the overall thickness can be achieved thin.
  • the polymer film is chemically modified by depositing the polymer film in a chemical solution in an atmospheric pressure atmosphere, not in a special environment requiring high cost such as vacuum conditions, and directly conducting the surface of the modified polymer film.
  • a metal layer After forming a metal layer, it is a method of manufacturing a non-adhesive type metal laminated film by laminating a metal thin film using electrolytic plating method. Since the manufacturing method of the present invention does not require a special working environment during the manufacturing process, it is possible to secure excellent price competitiveness.
  • the film of the present invention and its manufacturing method are technologies capable of producing high functionality and producing core materials of competitively priced circuit boards, which is expected to grow rapidly in the future. It can be expected to have the effect of possessing high value-added parts and material production technology.
  • FIG. 1 shows a process of manufacturing a substrate for a ball grid array semiconductor package according to an embodiment of the present invention.
  • FIGS. 2 and 3 illustrate two methods for forming a terminal portion on a substrate for a ball grid array semiconductor package according to an embodiment of the present invention, respectively.
  • Figure 4 is an electron micrograph of the surface of the bismarimide triazine film used in the present invention.
  • the present applicant is studying a method for providing a metal thin film layer on a substrate for a ball grid array semiconductor package, using a bismarimide triazine substrate as a substrate substrate, and using a chemical to surface the bismarimide triazine substrate. After the etching, the coupling agent and the metal catalyst were introduced to the etched surface, and it was confirmed that the metal thin film could be directly formed on the substrate substrate by the plating method, thereby completing the present invention.
  • FIG. 1 shows a process of manufacturing a substrate for a ball grid array semiconductor package according to an embodiment of the present invention.
  • the etching surface 11 is formed using an etching solution.
  • a coupling 12 is provided using a coupling agent, and this is immersed in an electroless plating solution to form the first electroless plating layer 13. Let's do it.
  • the bismaleimide triazine substrate on which the first electroless plating layer is formed is immersed in an electrolytic plating solution, and a current is applied to form the first electrolytic plating layer 14.
  • the substrate for the ball grid array semiconductor package provided with the metal layer manufactured through the above process is excellent in heat resistance, chemical resistance, migration, and the like, and has weak heat resistance of the ball grid array semiconductor package substrate provided by the metal layer using an adhesive in the related art. , Chemical resistance and migration can be improved.
  • FIGS. 2 and 3 illustrate two methods for forming a terminal portion on a substrate for a ball grid array semiconductor package according to an embodiment of the present invention, respectively.
  • a through hole 16 having an appropriate size is formed in the substrate.
  • the second electroless plating layer 17 is formed using the electroless plating solution, and the second electroplating layer 18 is formed on the second electroplating layer 17 using the electrolytic plating solution.
  • the mask 19 is provided in excess of the through-hole 16, the portions except for the portion provided with the mask 19 are etched, and the mask is removed to provide a terminal portion on the substrate for a ball grid array semiconductor package according to the present invention. To form.
  • another method of forming a terminal portion on the substrate for the ball grid array semiconductor package includes a mask for exposing the substrate having the second electroless plating layer 17 to exceed the diameter of the through hole 16. 19) is formed, and the second electroplating layer 18 is formed using an electrolytic plating solution on the portion where the mask 19 is not formed. Subsequently, the mask 19 and the portion where the mask is formed are etched to form terminal portions on the substrate for the ball grid array semiconductor package according to the present invention.
  • the method for manufacturing a substrate for a ball grid array semiconductor package of the present invention may include at least some of an etching process, a neutralization process, a coupling process, a catalyst addition process, a reaction promotion process, an electroless plating process, and an electrolytic plating process.
  • the bismarademide triazine film is modified using an etching solution to modify the film surface.
  • Etching solutions that can be used in this process include potassium hydroxide, sodium hydroxide, calcium hydroxide or magnesium hydroxide, which are hydroxides, ethylene glycol, propylene glycol, butanediol, neopentylglycol or diethylene glycol, which are alcohols, and dimethylacetamide, which is a nitrogen compound. It is preferable that it is a solution which mixed dimethylformamide and the like.
  • the etching process is performed by immersing the bismarademide triazine film in the etching solution at about 20 to 40 ° C. for about 3 to 5 minutes.
  • the etching solution has a large effect on the etching effect and the coupling of the coupling agent according to the mixing ratio, thereby having a large influence on the electroless plating efficiency of the metal.
  • the alcohol or nitrogen compound in the etching solution plays an important role in opening the imide ring by opening the imide ring on the surface of the bismarimide triazine film.
  • the etching solution may be mixed with 1 to 3 parts by weight of alcohol to 14 parts by weight of hydroxide, and is preferably prepared by mixing 1 to 3 parts by weight of a nitrogen compound to 2 parts by weight of alcohol.
  • the nitrogen compound is less than 1 part by weight, it is difficult to ring-open the imide ring present on the surface of the triazine film.
  • the nitrogen compound exceeds 3 parts by weight, the expansion or partial dissolution of the surface of the bismarimide triazine film may occur. Too much occurs, a problem may occur that the adhesion strength of the metal plating layer formed later.
  • the bismaramide triazine film surface modified by the present etching process may enhance adhesion strength by maximizing adhesion between the plating layer and the bismaramide triazine film in the subsequent plating process.
  • This etching process results in the cleavage of the imide ring of bismarademide triazine, which is converted to an imide group or a carboxyl group to increase reactivity.
  • the process temperature of such an etching process is 20 ° C. or less, the activity of the etching solution is lowered, so that the desired etching effect cannot be achieved, and long-term reaction may cause partial damage on the bismarimide triazine film.
  • the process temperature of an etching process is 40 degreeC or more, the rapid progress of an etching makes it difficult to control the uniformity and continuity of the whole uniformity on the bismarademide triazine film surface.
  • the bismarimide triazine film whose surface obtained in the etching process was modified was neutralized with an acidic neutralization solution.
  • This process removes metal salts such as K + ions that are expected to remain on the bismarademide triazine film surface obtained in the etching process.
  • metal salts such as K + ions that are expected to remain on the bismarademide triazine film surface obtained in the etching process.
  • the metal salts compete with the coupling ions for imparting polarity to the bismarademide triazine film, thereby preventing the reaction between the coupling ions and the imide group.
  • the temperature of the neutralization step is 10 ° C. or lower, the activity of the reaction solution is low, so that the desired neutralization effect cannot be achieved, and damage to the partial bismarimide triazine film is remarkable. Moreover, when the temperature of a neutralization process is 30 degreeC or more, it becomes difficult to adjust overall uniformity and continuity by a rapid reaction.
  • the bismaramide triazine film modified in the neutralization process is subjected to a coupling reaction using a coupling agent solution.
  • the coupling ions are bonded to the sites where the chemical bonds on the surface of the bismarimide triazine film are cleaved by the etching process to impart polarity on the bismarimide triazine film. To improve the adhesion strength of the target product.
  • the coupling agent solution that can be used in the present process may be a silane coupling agent or an amine coupling agent.
  • silane coupling agent various commercial products such as Shinetsu, Japan Energy or Dow Corning coupling agent can be used.
  • amine coupling agent an alkali coupling agent prepared by mixing sodium hydroxide and monometal amine, or an acid coupling agent prepared by mixing ethylenediamine and hydrochloric acid may be used.
  • reaction conditions vary depending on the characteristics of the coupling agent used, in the case of the silane coupling agent, the reaction is performed by immersing for about 5 to 7 minutes at about 25 to 30 ° C.
  • the coupled bismaleimide triazine film obtained in the coupling process is immersed at room temperature using an acidic solution to remove the coupling ions which are not bound to the cleavage site on the surface of the bismaramide triazine film. If the present pickling process is long or the acidic solution used is an excessively strong acidic solution, the coupled coupling ions can be removed, so that the reaction conditions are appropriately adjusted.
  • the coupled bismarimide triazine film is immersed in the catalyst solution to adsorb palladium as a metal catalyst on the bismarimide triazine film surface.
  • the catalyst solution is prepared by diluting palladium chloride and stannous chloride in hydrochloric acid at a mass ratio of 1: 3 to 1: 5. If the reaction time of this process is too short, the adsorption rate of palladium and tin as catalysts on the surface of the bismarimide triazine film is low, so that the desired catalytic effect cannot be achieved. If the reaction time is too long, bismarray is formed by hydrochloric acid in the process solution. Adverse conditions of corrosive mid-triazine film surfaces can occur, so the reaction conditions are properly adjusted.
  • the bismaleimide triazine film to which the catalyst is added is immersed in an electroless plating solution to electroless plate the bismaleimide triazine film.
  • the electroless plating refers to plating a desired metal on a substrate without applying current.
  • nickel sulfate prepared by mixing an aqueous solution of EDTA, an aqueous solution of caustic soda, an aqueous solution of formalin, and an aqueous copper sulfate solution, or an aqueous nickel hypophosphite, sodium citrate, ammonia, and nickel hexahydrate solution.
  • Electroless plating solutions can be used.
  • the electroless plating solution may also include a small amount of a brightener component, a stabilizer component, etc. in order to maximize metal properties. Such brighteners and stabilizers enable recycling and long term storage of the electroless plating solution.
  • the electroless plating process is performed by immersing the catalyst-added bismarademide triazine film at a temperature of about 65 to 75 ° C. for about 5 to 10 minutes without applying a current.
  • the thickness of the electroless plating layer obtained in an electroless plating process can be adjusted suitably according to plating time. If the reaction temperature of the electroless plating process is less than 65 ° C., the plating solution activity is low, so unplating and partial plating proceed to form an electroless plating layer, and the temperature of the electroless plating process is 75 ° C. When exceeded, the overall uniformity and adhesion on the electroless plated film are insufficient due to the rapid progress of plating.
  • the electroless plating process is performed by immersing the catalyst-added bismaleimide triazine film at a temperature of about 35 to 40 ° C for about 2 minutes.
  • This process is a process for the electroplating process after, but may be carried out with a plating thickness of about 0.2 ⁇ m or less, it is preferable to perform for a time to the extent that the unplated portion is lost.
  • the electroless plated bismarimide triazine film is immersed in the plating solution, and a plating process is performed by applying an electric current.
  • the electroless plated bismarimide triazine film is immersed in the plating solution, and the plating is performed by applying a current of 5 A / dm ⁇ 2 or less at about 20 to 30 ° C. for about 30 minutes to provide a substrate for a ball grid array semiconductor package. Manufacture.
  • the plating solution is stirred smoothly to minimize the non-uniformity of the plating solution concentration.
  • Such plating conditions can be appropriately adjusted according to the thickness of the copper plating film to be obtained.
  • plating solution that can be used in this embodiment, commercially available plating solutions (Enthone OMI, diluent metal, sunrays, etc.) can be used. However, the plating process is performed slowly over a long period of time under conditions milder than those of commercial plating solutions. Prolonged plating time can minimize the generation of stress inside the plating film to lower the hardness and obtain a plating film excellent in strength and ductility.
  • a plating solution prepared by diluting a copper sulfate aqueous solution, a sulfuric acid and hydrochloric acid mixed solution with purified water may be used.
  • Such plating solutions may include minor amounts of brighteners and additives.
  • the degree of plating of the substrate was evaluated by visually observing the continuity of the substrate for the ball grid array semiconductor package obtained according to the embodiment of the present invention.
  • (Circle) is a case where the whole sample surface is uniformly and beautifully plated
  • (circle) is a case where the sample surface is uniformly plated
  • delta) is a case where the part which is partially unplated exists
  • x is a case where there are many unplated parts. Point.
  • the adhesion strength is evaluated according to the JIS-6471 standard.
  • the bismarademide triazine film used in the embodiment of the present invention is prepared with a bismarademide triazine film (Mitsubishi Chemical) having a width of 100 mm, a length of 200 mm and a thickness of 100 ⁇ m, and dried at 150 ° C. for about 5 minutes as a pretreatment. To remove the water contained in the bismarimide triazine film.
  • a bismarademide triazine film Mitsubishi Chemical
  • the following examples are suitable processes for the bismarimide triazine film, which process may be appropriately modified by those skilled in the art according to the bismarademide triazine film and conditions.
  • the bismarimide triazine film was mixed in a 1 L etching solution (20 g of ethylene glycol and 10 g of dimethylacetamide in 1 L of distilled water, and 280 g of potassium hydroxide was added thereto to prepare a mixed solution) at 35 ° C for 4 minutes. It was immersed and etched. The etched bismarimide triazine film was immersed in 100 ml / l solution of hydrochloric acid for about 6 minutes to neutralize the surface. Thereafter, the silane coupling agent containing aminopropyl triethoxy silane was diluted to 1.2% / l, and soaked for 5 minutes at a temperature of about 26 ° C.
  • copper sulfate bottom plating prepared by mixing an aqueous copper sulfate solution (15.8 g / l) with an aqueous solution consisting of an aqueous EDTA solution (4.2 g / l), an aqueous solution of caustic soda (13.7 g / l), and an aqueous formalin solution (9.5 g / l).
  • the bismaleimide triazine film catalyzed by the solution was immersed for about 10 minutes at a temperature of about 70 ° C. without applying an electric current to perform electroless plating to form a first electroless plating layer.
  • the bismaleimide triazine film having the first electroless plating layer formed thereon was dried at about 110 ° C. for 10 minutes, and the first electroless plating layer was coated in a plating solution prepared by diluting an aqueous copper sulfate solution, sulfuric acid, and hydrochloric acid with ion-exchanged water.
  • the formed bismarimide triazine film was immersed at a temperature of about 30 ° C. for 30 minutes, and a current of 3 A / dm ⁇ 2 was applied to prepare a ball grid array semiconductor package substrate having a first electroplating layer.
  • Example 1 except that 20 g of ethylene glycol and 20 g of dimethylacetamide were mixed in 1 L of distilled water as an etching solution, and an etching solution prepared by adding 280 g of potassium hydroxide was used. In the same manner as in Example 1, a substrate for a ball grid array semiconductor package was manufactured.
  • a through hole having a size of 4 ⁇ m was formed in the substrate prepared in Example 1, the surface of the substrate was etched to roughen the surface, and immersed in an electroless plating solution to form a second electroless plating layer.
  • the substrate on which the second electroless plating layer was formed was immersed in an electrolytic plating solution and a current was applied to form the second electroplating layer.
  • a mask having a diameter exceeding the through hole is formed on the through hole, and a portion except for the portion provided with the mask is etched away so that only the substrate substrate remains, thereby forming a terminal portion on the substrate for the ball grid array semiconductor package. I was.
  • a through hole having a size of 4 ⁇ m was formed in the substrate prepared in Example 1, the surface of the substrate was etched to roughen the surface, and immersed in an electroless plating solution to form a second electroless plating layer.
  • the through hole is provided, and a mask is provided on the substrate to expose the substrate having the second electroless plating layer to exceed the diameter of the through hole.
  • a mask and a lower portion of the mask were etched to retain only the substrate substrate, thereby forming a terminal portion on the substrate for a ball grid array semiconductor package.
  • Comparative Example 1 Fabrication of a substrate for a ball grid array semiconductor package 1
  • Example 1 20 g of ethylene glycol was mixed with 1 L of distilled water as an etching solution, and the same procedure as in Example 1 was performed except that only an etching solution prepared by adding 280 g of potassium hydroxide was used. Thus, a substrate for a ball grid array semiconductor package was manufactured.
  • Example 1 20 g of ethylene glycol and 100 g of dimethylacetamide were mixed in 1 L of distilled water as the etching solution, and only the etching solution prepared by adding 280 g of potassium hydroxide was used. In the same manner as in Example 1, a substrate for a ball grid array semiconductor package was manufactured.
  • Example 1 a substrate for a ball grid array semiconductor package was prepared in the same manner as in Example 1, except that 280 g of potassium hydroxide was dissolved in 1 L of distilled water as an etching solution.
  • Example 1 a substrate for a ball grid array semiconductor package was manufactured in the same manner as in Example 1, except that 1 L solution in which 20 g of ethylene glycol was mixed in distilled water was used as an etching solution.
  • Example 1 a substrate for a ball grid array semiconductor package was prepared by the same process as Example 1, except that a solution dissolved in 1 L of 200 g of sodium hydroxide in distilled water was used as an etching solution. .
  • Example 1 Plating accuracy Copper thin film / film thickness ( ⁇ m) Average adhesion strength (kg / cm)
  • Example 1 ⁇ 12/100 0.85 Example 2 ⁇ 12/100 0.80 Comparative Example 1 ⁇ 12/100 0.65 Comparative Example 2 ⁇ 12/100 0.55 Comparative Example 3 ⁇ 12/100 0.50 Comparative Example 4 ⁇ 12/100 0.60 Comparative Example 5 ⁇ 12/100 0.30
  • the substrate for a ball grid array semiconductor package of the present invention is suitable for use in printed circuit boards, and can be widely used in semiconductor fields, sensor fields, and the like.

Abstract

The present invention relates to a substrate for a ball grid array semiconductor package and a fabrication method thereof. The substrate for a ball grid array semiconductor package of the present invention comprises: a base substrate formed of Bismaleimide-Triazine; a first electroless plated layer formed over the base substrate; and a first electroplated layer formed over the first electroless plated layer. The present invention makes it possible to fabricate a substrate for a ball grid array semiconductor package, which does not require any use of an adhesive, is capable of adjusting the thickness of an electro-conductive metal plated layer and exhibits excellent adhesion strength. Moreover, without the use of an adhesive layer, the present invention substrate for a ball grid array semiconductor package provides superior heat resistance, chemical resistance and migration properties.

Description

볼 그리드 어레이 반도체 패키지용 기판 및 이의 제조방법Substrate for ball grid array semiconductor package and manufacturing method thereof
본 발명은 볼 그리드 어레이 반도체 패키지용 기판 및 이의 제조방법에 관한 것이다. 본 발명은 비스마레이미드 트리아진 필름에 전도성 금속을 결합시키기 위하여 접착제를 사용하지 않고, 전도성 금속을 도금하여 제조되는 볼 그리드 어레이 반도체 패키지용 기판에 관한 것이다.The present invention relates to a substrate for a ball grid array semiconductor package and a method of manufacturing the same. The present invention relates to a substrate for a ball grid array semiconductor package manufactured by plating a conductive metal without using an adhesive to bond the conductive metal to a bismarademide triazine film.
반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전되고 있다. 예컨대, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장 후의 기계적, 전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다.In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technologies for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting and mechanical and electrical reliability after mounting. I'm making it.
상기 패키지의 소형화를 이룬 한 예로서, 볼 그리드 어레이(Ball Grid Array) 반도체 패키지를 들 수 있다. 상기 볼 그리드 어레이 반도체 패키지는 전체적인 반도체 패키지의 크기가 반도체 칩의 크기와 동일하거나 거의 유사하며, 특히, 외부와의 전기적 접속 수단, 즉, 인쇄회로기판(Printed Circuit Board)에의 실장 수단으로서, 솔더 볼이 구비됨에 따라 실장 면적이 감소되고 있는 추세에 매우 유리하게 적용할 수 있다는 이점이 있다.One example of miniaturization of the package is a ball grid array semiconductor package. The ball grid array semiconductor package has an overall size of the semiconductor package that is about the same as or similar to that of a semiconductor chip. In particular, the ball grid array semiconductor package includes solder balls as an electrical connection means to the outside, that is, a mounting means on a printed circuit board. With this, there is an advantage that it can be very advantageously applied to the trend that the mounting area is decreasing.
종래에 사용되는 볼 그리드 어레이 반도체 패키지용 기판은 기재 기판에 구리 박막층을 접착제를 통하여 적층한 구조이다.A substrate for a ball grid array semiconductor package used in the related art has a structure in which a copper thin film layer is laminated on a substrate substrate through an adhesive.
그러나 상기와 같은 구리 박막 접착형 기재 기판은 양산되고 있는 구리박막을 그대로 사용하기 때문에, 기재 기판의 상부에 적층되는 구리박막의 두께를 적용되는 구리 박막의 두께 이하로 얇게 자유롭게 제어할 수 없다. 그에 따라, 기재 기판상의 회로 또는 단자 형성을 위한 에칭 공정에서 미세 패터닝이 어렵다는 문제점이 있다.However, the copper thin film adhesive type substrate substrate as described above uses the copper thin film in mass production as it is, so that the thickness of the copper thin film laminated on the upper portion of the base substrate cannot be freely controlled to be less than the thickness of the applied copper thin film. Accordingly, there is a problem that fine patterning is difficult in an etching process for forming a circuit or a terminal on a base substrate.
상술한 종래 기술의 문제점을 해결하기 위한 본 발명의 목적은 볼 그리드 어레이 반도체 패키지용 기판에 구비되는 금속 박막의 두께를 자유롭게 제어할 수 있으면서도, 기재 기판과 금속 박막의 밀착을 강하게 할 수 있는 볼 그리드 어레이 반도체 패키지용 기판 및 이를 제조하는 방법을 제공하는 것이다.An object of the present invention for solving the problems of the prior art described above is a ball grid that can control the thickness of the metal thin film provided in the substrate for the ball grid array semiconductor package freely, and can strengthen the adhesion between the substrate substrate and the metal thin film The present invention provides a substrate for an array semiconductor package and a method of manufacturing the same.
위와 같은 과제를 달성하기 위한 본 발명의 한 특징에 따른 볼 그리드 어레이 반도체 패키지용 기판은, 비스마레이미드 트리아진으로 형성된 기재 기판; 상기 기재 기판 상부에 형성된 제 1 무전해 도금층; 및 상기 제 1 무전해 도금층 상에 형성된 제 1 전해 도금층; 을 포함한다.A substrate for a ball grid array semiconductor package according to an aspect of the present invention for achieving the above object, the substrate substrate formed of bismarimide triazine; A first electroless plating layer formed on the base substrate; And a first electroplating layer formed on the first electroless plating layer. It includes.
상기 기재 기판의 표면이 에칭 개열되어 이미드기 또는 카르복실기가 형성되고, 상기 이미드기 또는 카르복실기에 커플링제가 결합될 수 있다.The surface of the substrate may be etched to form an imide group or a carboxyl group, and a coupling agent may be bonded to the imide group or the carboxyl group.
상기 제 1 무전해 도금층은 금, 니켈 및 구리로 이루어지는 군으로부터 1종 이상 선택되는 금속이다.The first electroless plating layer is a metal selected from at least one member selected from the group consisting of gold, nickel and copper.
상기 제 1 전해 도금층은 금, 니켈 및 구리로 이루어지는 군으로부터 1종 이상 선택되는 금속이다.The first electroplating layer is a metal selected from one or more types from the group consisting of gold, nickel and copper.
상기 제 1 무전해 도금층은 0.2 ㎛ 이하인 것이 바람직하다.It is preferable that a said 1st electroless plating layer is 0.2 micrometer or less.
상기 제 1 전해 도금층은 10 내지 20 ㎛인 것이 바람직하다.It is preferable that the said 1st electroplating layer is 10-20 micrometers.
또한, 본 발명의 볼 그리드 어레이 반도체 패키지용 기판의 제조방법은, 1) 비스마레이미드 트리아진으로 형성된 기재 기판의 표면을 에칭 용액으로 에칭 개열하여, 상기 표면에 이미드기 또는 카르복실기를 생성하는 단계; 2) 상기 기재 기판 표면에 커플링제를 도입하여 상기 이미드기 또는 카르복실기에 커플링하는 단계; 3) 상기 기재 기판의 상기 표면에 제 1 무전해 도금층을 형성하는 단계; 및 4) 상기 제 1 무전해 도금층에 제 1 전해 도금층을 형성하는 단계; 을 포함한다.In addition, the method of manufacturing a substrate for a ball grid array semiconductor package of the present invention comprises the steps of: 1) etching cleavage of the surface of the substrate substrate formed of bismarademide triazine with an etching solution to generate an imide group or a carboxyl group on the surface; 2) introducing a coupling agent to the surface of the base substrate and coupling the imide group or carboxyl group; 3) forming a first electroless plating layer on the surface of the base substrate; And 4) forming a first electroplating layer on the first electroless plating layer; It includes.
상기 볼 그리드 어레이 반도체 패키지용 기판의 제조방법은 추가적으로, 5) 상기 기판의 목적하는 부위에 3~7 ㎛ 크기의 관통홀을 1종 이상 형성시키는 단계; 6) 상기 관통홀 및 상기 기판 표면에 무전해 도금 방법으로 제 2 무전해 도금층을 형성하는 단계; 7) 상기 제 2 무전해 도금층의 표면에 전해 도금 방법으로 제 2 전해 도금층을 형성하는 단계; 8) 상기 관통홀의 직경을 초과하는 직경을 가지는 마스크를 상기 관통홀 상부에 구비시키는 단계; 및 9) 상기 마스크를 제외한 부분을 식각 제거시켜 상기 기재 기판만 잔존시키는 단계; 을 더 수행한다.The method of manufacturing a substrate for a ball grid array semiconductor package may further include: 5) forming at least one through hole having a size of 3 to 7 μm in a desired portion of the substrate; 6) forming a second electroless plating layer on the through hole and the surface of the substrate by an electroless plating method; 7) forming a second electroplating layer on the surface of the second electroless plating layer by an electroplating method; 8) providing a mask having a diameter exceeding a diameter of the through hole on the through hole; And 9) etching away portions other than the mask to leave only the substrate substrate. Do more.
또한, 상기 볼 그리드 어레이 반도체 패키지용 기판의 제조방법은 추가적으로, 5) 상기 기판의 목적하는 부위에 3~7 ㎛ 크기의 관통홀을 1종 이상 형성시키는 단계; 6) 상기 관통홀 및 상기 기판의 표면에 무전해 도금 방법으로 제 2 무전해 도금층을 형성하는 단계; 7) 상기 관통홀의 직경을 초과하도록 노출시키는 마스크를 기판의 상부에 구비시키는 단계; 8) 상기 제 2 무전해 도금층에 전해 도금 방법으로 제 2 전해 도금층을 형성하는 단계; 및 9) 상기 마스크를 제거하고, 상기 마스크 하부를 식각 제거시켜 상기 기재기판만 잔존시키는 단계; 을 더 수행한다.In addition, the manufacturing method of the substrate for the ball grid array semiconductor package further comprises: 5) forming at least one through hole having a size of 3 ~ 7 ㎛ in the desired portion of the substrate; 6) forming a second electroless plating layer on the surface of the through hole and the substrate by an electroless plating method; 7) providing a mask on the substrate to expose the diameter of the through hole to exceed; 8) forming a second electroplating layer on the second electroless plating layer by an electroplating method; And 9) removing the mask and etching the lower portion of the mask to leave only the substrate. Do more.
상기 에칭 용액은 수산화물인 수산화칼륨, 수산화나트륨, 수산화칼슘 및 수산화마그네늄으로 이루어지는 군으로부터 선택되는 1종 이상, 알코올인 에틸렌글리콜, 프로필렌글리콜, 부탄디올, 네오펜틸글리콜 및 디에틸렌글리콜으로 이루어지는 군으로부터 선택되는 1종 이상, 질소화합물인 디메틸아세트아미드 또는 디메틸포름아미드에서 선택되는 1종 이상을 혼합한 용액인 것을 사용할 수 있다.The etching solution is at least one selected from the group consisting of potassium hydroxide, sodium hydroxide, calcium hydroxide and magnesium hydroxide as hydroxides, and selected from the group consisting of ethylene glycol, propylene glycol, butanediol, neopentyl glycol and diethylene glycol as alcohols. It can be used the thing of the solution which mixed 1 or more types chosen from dimethylacetamide or dimethylformamide which is 1 or more types of nitrogen compounds.
상기 에칭 용액은 수산화물 14 중량부에 알코올이 1~3 중량부 혼합될 수 있으며, 알코올 2 중량부에 질소화합물은 1~3 중량부 혼합하여 제조되는 것이 바람직하다.The etching solution may be mixed with 1 to 3 parts by weight of alcohol to 14 parts by weight of hydroxide, and is preferably prepared by mixing 1 to 3 parts by weight of a nitrogen compound to 2 parts by weight of alcohol.
상기 단계 1)에서, 상기 에칭은 기재 기판을 에칭용액에 45 내지 50 ℃에서 5~7분간 침지할 수 있다.In the step 1), the etching may immerse the substrate substrate in the etching solution at 45 to 50 ℃ 5-7 minutes.
상기 단계 2)와 단계 3) 사이에 상기 기재 기판에 팔라듐 또는 주석을 결합시키는 단계를 더 수행할 수 있다.Bonding palladium or tin to the base substrate may be further performed between step 2) and step 3).
상기 제 1 무전해 도금층 및 제 2 무전해 도금층은 금, 니켈 또는 구리로 형성될 수 있다.The first electroless plating layer and the second electroless plating layer may be formed of gold, nickel, or copper.
상기 제 1 전해 도금층 및 제 2 전해 도금층은 금, 니켈 또는 구리로 형성될 수 있다.The first electrolytic plating layer and the second electrolytic plating layer may be formed of gold, nickel or copper.
상기 제 1 무전해 도금층의 두께는 0.2 ㎛ 이하인 것이 바람직하다.It is preferable that the thickness of a said 1st electroless plating layer is 0.2 micrometer or less.
상기 제 1 전해 도금층의 형성 두께가 약 10 내지 20 ㎛인 것이 바람직하다.It is preferable that the formation thickness of the said 1st electroplating layer is about 10-20 micrometers.
또한, 본 발명의 볼 그리드 어레이 반도체 패키지용 기판은, 비스마레이미드 트리아진으로 형성되며 복수개의 관통홀이 구비되어 있는 기재 기판; 상기 기재 기판 상부에 형성된 제 1 무전해 도금층; 상기 제 1 무전해 도금층 상부에 형성된 제 1 전해 도금층; 상기 관통홀 내부 및 주변에 형성되는 제 2 무전해 도금층; 상기 제 2 무전해 도금층 상에 형성된 제 2 전해 도금층; 을 포함한다.In addition, the substrate for a ball grid array semiconductor package of the present invention, the substrate substrate is formed of bismarimide triazine and provided with a plurality of through holes; A first electroless plating layer formed on the base substrate; A first electroplating layer formed on the first electroless plating layer; A second electroless plating layer formed in and around the through hole; A second electroplating layer formed on the second electroless plating layer; It includes.
본 발명에 따른 전도성 금속이 도금된 비스마레이미드 트리아진 필름의 제조방법은 종래의 방법과 달리 접착제를 이용하여 금속 박막을 기재 기판에 부착하지 않고, 도금 방법으로 기재 기판 상의 금속 박막을 형성하므로 형성되는 금속 박막의 두께를 자유롭게 조절할 수 있다. 또한, 도금 방법으로 기재 기판상에 직접 금속 박막을 형성하므로 형성된 금속 박막은 기재 기판에 대한 밀착력이 우수하게 된다.Conductive metal plated bismarimide triazine film manufacturing method according to the present invention is formed by forming a metal thin film on the substrate substrate by a plating method, unlike the conventional method does not adhere the metal thin film to the substrate substrate using an adhesive The thickness of the metal thin film can be freely adjusted. In addition, since the metal thin film is directly formed on the base substrate by the plating method, the formed metal thin film has excellent adhesion to the base substrate.
또한, 본 발명의 전도성 금속이 도금된 비스마레이미드 트리아진 필름은 접착층을 사용하지 않기 때문에, 내열성, 내약품성, 마이그레이션이 우수하고, 전체 두께가 얇게 달성될 수 있다.In addition, since the bismarimide triazine film plated with the conductive metal of the present invention does not use an adhesive layer, it is excellent in heat resistance, chemical resistance and migration, and the overall thickness can be achieved thin.
본 발명의 전도성 금속 도금방법은 진공조건과 같은 고비용이 소요되는 특수환경이 아니라, 대기압 분위기에서 단지 고분자필름을 화학약품용액 중에 침적시켜 그 표면을 화학적으로 개질시키고, 개질된 고분자필름 표면에 직접 전도성 금속층을 형성시킨 후, 전해 도금 방법으로 이용하여 금속 박막을 적층시켜 무접착제 타입의 금속 적층필름을 제조하는 방법이다. 본 발명의 제조방법은 제조과정 중, 별도로 특수한 분위기의 작업환경이 필요 없기 때문에 뛰어난 가격경쟁력을 확보할 수 있다. In the conductive metal plating method of the present invention, the polymer film is chemically modified by depositing the polymer film in a chemical solution in an atmospheric pressure atmosphere, not in a special environment requiring high cost such as vacuum conditions, and directly conducting the surface of the modified polymer film. After forming a metal layer, it is a method of manufacturing a non-adhesive type metal laminated film by laminating a metal thin film using electrolytic plating method. Since the manufacturing method of the present invention does not require a special working environment during the manufacturing process, it is possible to secure excellent price competitiveness.
또한 기존 제조방법과 달리 상품화된 금속 박막을 접착하는 것이 아니라 전기도금법에 의해서 금속 박막을 적층시키는 것이기 때문에 초극박 금속두께 구현이 가능한 파인 패터닝(fine patterning) 전용소재 제조기술로 대단히 적합한 미래기술이다. In addition, unlike conventional manufacturing methods, it is a future technology that is very suitable as a fine patterning material manufacturing technology capable of realizing ultra-thin metal thickness because the metal thin film is laminated by an electroplating method rather than bonding a commercialized metal thin film.
한편, 볼 그리드 어레이 반도체 패키지용 기재 기판으로 비스마레이미드 트리아진 소재가 사용되는 경우, 아직 무접착제 구조의 금속 적층기술이 확립되어 있지 않은 상태이다. 그렇기 때문에, 본 발명의 필름 및 이의 제조방법은 고기능성을 구현할 수 있으면서 가격경쟁력이 있는 회로기판의 핵심소재를 생산할 수 있는 기술로서, 향후 급속하게 성장하리라고 예상되는 회로부품 소재분야에서 우리나라가 국제적인 경쟁력을 갖춘 고부가가치의 부품소재생산기술을 보유하는 효과를 기대할 수 있다.On the other hand, when bismarimide triazine material is used as a base substrate for ball grid array semiconductor packages, the metal lamination | stacking technology of an adhesive agentless structure is not yet established. Therefore, the film of the present invention and its manufacturing method are technologies capable of producing high functionality and producing core materials of competitively priced circuit boards, which is expected to grow rapidly in the future. It can be expected to have the effect of possessing high value-added parts and material production technology.
도 1은 본 발명의 일 실시예에 따른 볼 그리드 어레이 반도체 패키지용 기판을 제조하는 공정을 나타낸 것이다.1 shows a process of manufacturing a substrate for a ball grid array semiconductor package according to an embodiment of the present invention.
도 2 및 3은 본 발명의 일 실시예에 따른 볼 그리드 어레이 반도체 패키지용 기판에 단자부를 형성하는 두 가지 방법을 각각 나타낸 것이다. 2 and 3 illustrate two methods for forming a terminal portion on a substrate for a ball grid array semiconductor package according to an embodiment of the present invention, respectively.
도 4는 본 발명에 사용되는 비스마레이미드 트리아진 필름의 표면을 관찰한 전자현미경 사진이다.Figure 4 is an electron micrograph of the surface of the bismarimide triazine film used in the present invention.
본 출원인은 볼 그리드 어레이 반도체 패키지용 기재 기판에 금속 박막층을 구비시키는 방법을 연구하던 중, 기재 기판으로 비스마레이미드 트리아진 기판을 이용하고, 비스마레이미드 트리아진 기재 기판을 화학약품을 이용하여 표면을 에칭하고, 에칭된 표면에 커플링제 및 금속 촉매를 도입시켜 기재 기판상에 금속 박막을 도금방법으로 직접 형성할 수 있음을 확인하고, 본 발명을 완성하였다.The present applicant is studying a method for providing a metal thin film layer on a substrate for a ball grid array semiconductor package, using a bismarimide triazine substrate as a substrate substrate, and using a chemical to surface the bismarimide triazine substrate. After the etching, the coupling agent and the metal catalyst were introduced to the etched surface, and it was confirmed that the metal thin film could be directly formed on the substrate substrate by the plating method, thereby completing the present invention.
이하, 본 발명에 첨부된 도면을 참조하여 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다.Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail to be easily carried out by those of ordinary skill in the art.
도 1은 본 발명의 일 실시예에 따른 볼 그리드 어레이 반도체 패키지용 기판을 제조하는 공정을 나타낸 것이다.1 shows a process of manufacturing a substrate for a ball grid array semiconductor package according to an embodiment of the present invention.
적절한 크기의 비스마레이미드 트리아진 기판(10)에 접착제를 사용하지 않고, 금속 도금층을 형성하기 위해서는 기판 표면에 표면적을 넓게하기 위하여, 기판 표면을 에칭용액을 이용하여 에칭면(11)을 형성시킨다. 상기 에칭면(11)에 금속이 더욱 용이하게 결합할 수 있도록, 커플링제를 이용하여 커플링(12)을 구비시키고, 이를 무전해 도금 용액에 침지하여, 제 1 무전해 도금층(13)을 형성시킨다. 상기 제 1 무전해 도금층이 형성된 비스마레이미드 트리아진 기판을 전해 도금 용액에 침지하고, 전류를 인가하여, 제 1 전해 도금층(14)을 형성시킨다. 상기와 같은 과정을 거쳐 제조된 금속층이 구비된 볼 그리드 어레이 반도체 패키지용 기판은 내열성, 내약품성, 마이그레이션 등이 우수하여, 종래에 접착제를 사용하여 금속층이 구비시키는 볼 그리드 어레이 반도체 패키지 기판의 약한 내열성, 내약품성, 마이그레이션 등을 개선시킬 수 있다.In order to form a metal plating layer without using an adhesive on an appropriate size bismarademide triazine substrate 10, in order to increase the surface area on the substrate surface, the etching surface 11 is formed using an etching solution. . In order to bond the metal to the etching surface 11 more easily, a coupling 12 is provided using a coupling agent, and this is immersed in an electroless plating solution to form the first electroless plating layer 13. Let's do it. The bismaleimide triazine substrate on which the first electroless plating layer is formed is immersed in an electrolytic plating solution, and a current is applied to form the first electrolytic plating layer 14. The substrate for the ball grid array semiconductor package provided with the metal layer manufactured through the above process is excellent in heat resistance, chemical resistance, migration, and the like, and has weak heat resistance of the ball grid array semiconductor package substrate provided by the metal layer using an adhesive in the related art. , Chemical resistance and migration can be improved.
도 2 및 3은 본 발명의 일 실시예에 따른 볼 그리드 어레이 반도체 패키지용 기판에 단자부를 형성하는 두 가지 방법을 각각 나타낸 것이다.2 and 3 illustrate two methods for forming a terminal portion on a substrate for a ball grid array semiconductor package according to an embodiment of the present invention, respectively.
도 2를 참조하여 설명하면, 상기 제 1 무전해 도금층 및 제 1 전해 도금층이 형성된 볼 그리드 어레이 반도체 패키지용 기판에 단자부를 형성하기 위해서, 상기 기판에 적절한 크기의 관통홀(16)을 형성시키고, 무전해 도금용액을 사용하여 제 2 무전해 도금층(17)을 형성시키고, 전해 도금용액을 사용하여 제 2 전해 도금층(17) 상부에 제 2 전해 도금층(18)을 형성시킨다. 이후, 마스크(19)를 관통홀(16)을 초과하여 구비시키고, 마스크(19)가 구비된 부분을 제외한 부분을 식각하고, 마스크를 제거하여 본 발명에 따른 볼 그리드 어레이 반도체 패키지용 기판에 단자부를 형성시킨다.Referring to FIG. 2, in order to form a terminal portion on a substrate for a ball grid array semiconductor package in which the first electroless plating layer and the first electrolytic plating layer are formed, a through hole 16 having an appropriate size is formed in the substrate. The second electroless plating layer 17 is formed using the electroless plating solution, and the second electroplating layer 18 is formed on the second electroplating layer 17 using the electrolytic plating solution. Subsequently, the mask 19 is provided in excess of the through-hole 16, the portions except for the portion provided with the mask 19 are etched, and the mask is removed to provide a terminal portion on the substrate for a ball grid array semiconductor package according to the present invention. To form.
도 3을 참조하여 설명하면, 상기 볼 그리드 어레이 반도체 패키지용 기판에 단자부를 형성시키는 다른 방법은 제 2 무전해 도금층(17)이 형성된 기판에 관통홀(16)의 직경을 초과하도록 노출시키는 마스크(19)를 형성시키고, 마스크(19)가 형성되지 않은 부분에 전해 도금 용액을 사용하여 제 2 전해 도금층(18)을 형성시킨다. 이후, 마스크(19), 및 마스크가 형성된 부분을 식각하여 본 발명에 따른 볼 그리드 어레이 반도체 패키지용 기판에 단자부를 형성시킨다.Referring to FIG. 3, another method of forming a terminal portion on the substrate for the ball grid array semiconductor package includes a mask for exposing the substrate having the second electroless plating layer 17 to exceed the diameter of the through hole 16. 19) is formed, and the second electroplating layer 18 is formed using an electrolytic plating solution on the portion where the mask 19 is not formed. Subsequently, the mask 19 and the portion where the mask is formed are etched to form terminal portions on the substrate for the ball grid array semiconductor package according to the present invention.
이하에서는 본 발명의 볼 그리드 어레이 반도체 패키지용 기판의 제조방법을 설명하기로 한다. Hereinafter, a method of manufacturing a substrate for a ball grid array semiconductor package according to the present invention will be described.
본 발명의 제조방법에서는 설명의 편의를 위해서, 구리 박막이 도금된 비스마레이미드 트리아진 필름에 대해서 설명한다.In the manufacturing method of this invention, the bismarimide triazine film by which the copper thin film was plated is demonstrated for convenience of description.
본 발명의 볼 그리드 어레이 반도체 패키지용 기판 제조방법은 에칭 공정, 중화 공정, 커플링 공정, 촉매 부가 공정, 반응 촉진 공정, 무전해 도금 공정, 전해 도금 공정 중 일부 이상의 공정을 포함할 수 있다. The method for manufacturing a substrate for a ball grid array semiconductor package of the present invention may include at least some of an etching process, a neutralization process, a coupling process, a catalyst addition process, a reaction promotion process, an electroless plating process, and an electrolytic plating process.
이하, 각 공정들을 통해 본 발명의 볼 그리드 어레이 반도체 패키지용 기판 제조 방법을 구체적으로 설명한다. 또한, 하기의 각 공정에서는 플라즈마 또는 초음파를 가하여, 연속적인 공정을 유발할 수 있다.Hereinafter, a method of manufacturing a substrate for a ball grid array semiconductor package according to the present invention will be described in detail through the processes. In addition, in each of the following processes, plasma or ultrasonic waves may be added to cause a continuous process.
1. 에칭 공정1. Etching process
비스마레이미드 트리아진 필름을 에칭 용액을 이용하여 필름 표면을 개질 처리한다. The bismarademide triazine film is modified using an etching solution to modify the film surface.
본 공정에서 사용될 수 있는 에칭 용액은 수산화물인 수산화칼륨, 수산화나트륨, 수산화칼슘 또는 수산화마그네늄 등과, 알코올인 에틸렌글리콜, 프로필렌글리콜, 부탄디올, 네오펜틸글리콜 또는 디에틸렌글리콜 등과, 질소화합물인 디메틸아세트아미드 또는 디메틸포름아미드 등을 혼합한 용액인 것이 바람직하다. 에칭 공정은 약 20 내지 40 ℃에서 약 3 ~ 5 분간 비스마레이미드 트리아진 필름을 에칭 용액에 침지하여 수행된다. 이때, 상기 에칭용액은 혼합되는 비율에 따라, 그 에칭효과와 이후 커플링제와의 결합에 큰 영향을 미치게 되고, 이로 인해서 금속의 무전해 도금 효율에 큰 영향을 끼칠 수 있다. 특히 상기 에칭용액에서 알코올 또는 질소화합물은 비스마레이미드 트리아진 필름 표면에 존재하는 이미드 링을 개환시켜 이미드기가 생성되는데 중요한 역할을 한다.Etching solutions that can be used in this process include potassium hydroxide, sodium hydroxide, calcium hydroxide or magnesium hydroxide, which are hydroxides, ethylene glycol, propylene glycol, butanediol, neopentylglycol or diethylene glycol, which are alcohols, and dimethylacetamide, which is a nitrogen compound. It is preferable that it is a solution which mixed dimethylformamide and the like. The etching process is performed by immersing the bismarademide triazine film in the etching solution at about 20 to 40 ° C. for about 3 to 5 minutes. At this time, the etching solution has a large effect on the etching effect and the coupling of the coupling agent according to the mixing ratio, thereby having a large influence on the electroless plating efficiency of the metal. In particular, the alcohol or nitrogen compound in the etching solution plays an important role in opening the imide ring by opening the imide ring on the surface of the bismarimide triazine film.
상기 에칭 용액은 수산화물 14 중량부에 알코올이 1~3 중량부 혼합될 수 있으며, 알코올 2 중량부에 질소화합물은 1~3 중량부 혼합하여 제조되는 것이 바람직하다. 이때, 상기 질소화합물은 1 중량부 미만일 경우, 트리아진 필름 표면에 존재하는 이미드 링을 개환시키기 힘들어지고, 3 중량부를 초과할 경우, 비스마레이미드 트리아진 필름의 표면의 팽창 또는 부분적인 녹임이 너무 과하게 발생하여, 추후 형성된 금속 도금층의 밀착강도가 떨어지는 문제점이 발생할 수 있다.The etching solution may be mixed with 1 to 3 parts by weight of alcohol to 14 parts by weight of hydroxide, and is preferably prepared by mixing 1 to 3 parts by weight of a nitrogen compound to 2 parts by weight of alcohol. At this time, when the nitrogen compound is less than 1 part by weight, it is difficult to ring-open the imide ring present on the surface of the triazine film. When the nitrogen compound exceeds 3 parts by weight, the expansion or partial dissolution of the surface of the bismarimide triazine film may occur. Too much occurs, a problem may occur that the adhesion strength of the metal plating layer formed later.
본 에칭 공정으로 개질된 비스마레이미드 트리아진 필름 표면은 차후 도금 공정시 도금 층과 비스마레이미드 트리아진 필름과의 밀착을 극대화하여 밀착강도를 증진시킬 수 있다. 이러한 에칭 공정으로 인해 비스마레이미드 트리아진의 이미드 링이 개열되면서 이미드기 또는 카르복실기로 전환되어 반응성이 증가된다.The bismaramide triazine film surface modified by the present etching process may enhance adhesion strength by maximizing adhesion between the plating layer and the bismaramide triazine film in the subsequent plating process. This etching process results in the cleavage of the imide ring of bismarademide triazine, which is converted to an imide group or a carboxyl group to increase reactivity.
이러한 에칭 공정의 공정 온도가 20 ℃ 이하의 경우는 에칭 용액의 활성이 낮아져서, 목적하는 에칭 효과를 달성할 수 없고, 장기간의 반응으로 인해 비스마레이미드 트리아진 필름 상에 부분적인 손상이 발생할 수 있으며, 에칭 공정의 공정 온도가 40 ℃ 이상인 경우, 급격한 에칭의 진행으로 인해 비스마레이미드 트리아진 필름 표면상 전체적인 균일성 및 연속성의 조절이 어려워진다. When the process temperature of such an etching process is 20 ° C. or less, the activity of the etching solution is lowered, so that the desired etching effect cannot be achieved, and long-term reaction may cause partial damage on the bismarimide triazine film. When the process temperature of an etching process is 40 degreeC or more, the rapid progress of an etching makes it difficult to control the uniformity and continuity of the whole uniformity on the bismarademide triazine film surface.
2. 중화 공정2. Neutralization Process
에칭 공정에서 수득된 표면이 개질된 비스마레이미드 트리아진 필름을 산성 중화 용액을 이용하여 비스마레이미드 트리아진 필름 표면을 중화 처리한다. The bismarimide triazine film whose surface obtained in the etching process was modified was neutralized with an acidic neutralization solution.
본 공정은 상기 에칭 공정에서 얻어진 비스마레이미드 트리아진 필름 표면에 잔존하리라 예상되는 K+ 이온과 같은 금속염을 제거한다. 이러한 금속염이 잔존하는 경우, 후공정인 커플링 공정에서, 금속염들이 비스마레이미드 트리아진 필름에 극성을 부여하기 위한 커플링 이온과 경쟁하게 되어, 커플링 이온과 이미드기의 반응을 방해하게 된다.This process removes metal salts such as K + ions that are expected to remain on the bismarademide triazine film surface obtained in the etching process. When such a metal salt remains, in a coupling process which is a post process, the metal salts compete with the coupling ions for imparting polarity to the bismarademide triazine film, thereby preventing the reaction between the coupling ions and the imide group.
중화 공정의 온도가 10 ℃ 이하인 경우는 반응액의 활성이 낮아서 목적하는 중화 효과를 달성할 수 없고, 또한 부분적인 비스마레이미드 트리아진 필름의 손상이 현저히 나타난다. 또한, 중화 공정의 온도가 30 ℃ 이상인 경우, 급격한 반응에 의해 전체적인 균일성 및 연속성의 조절이 어려워진다.When the temperature of the neutralization step is 10 ° C. or lower, the activity of the reaction solution is low, so that the desired neutralization effect cannot be achieved, and damage to the partial bismarimide triazine film is remarkable. Moreover, when the temperature of a neutralization process is 30 degreeC or more, it becomes difficult to adjust overall uniformity and continuity by a rapid reaction.
3. 커플링 공정3. Coupling Process
중화 공정에서 개질된 비스마레이미드 트리아진 필름을 커플링제 용액을 이용하여 커플링 반응시킨다.The bismaramide triazine film modified in the neutralization process is subjected to a coupling reaction using a coupling agent solution.
커플링 반응은 에칭 공정에 의해 비스마레이미드 트리아진 필름 표면의 화학결합이 개열된 곳에 커플링 이온을 결합시켜 비스마레이미드 트리아진 필름 상에 극성을 부여함으로써, 이후 무전해 및 전해 도금 공정의 진행을 원활하게 하고, 목적 제품의 밀착강도를 향상시킨다.In the coupling reaction, the coupling ions are bonded to the sites where the chemical bonds on the surface of the bismarimide triazine film are cleaved by the etching process to impart polarity on the bismarimide triazine film. To improve the adhesion strength of the target product.
본 공정에서 사용될 수 있는 커플링제 용액은 실란계 커플링제 또는 아민계 커플링제일 수 있다. 실란계 커플링제로서, Shinetsu, Japan Energy 또는 다우코닝의 커플링제 등 여러 가지 시판 제품을 이용할 수 있다. 아민계 커플링제로는 수산화나트륨 및 모노메탈아민을 혼합시켜 제조되는 알칼리계 커플링제, 또는 에틸렌디아민 및 염산을 혼합시켜 제조되는 산계 커플링제를 사용할 수 있다. The coupling agent solution that can be used in the present process may be a silane coupling agent or an amine coupling agent. As the silane coupling agent, various commercial products such as Shinetsu, Japan Energy or Dow Corning coupling agent can be used. As the amine coupling agent, an alkali coupling agent prepared by mixing sodium hydroxide and monometal amine, or an acid coupling agent prepared by mixing ethylenediamine and hydrochloric acid may be used.
본 커플링 공정은 사용되는 커플링제의 특성에 따라 그 반응 조건이 달라지나, 실란계 커플링제의 경우는 약 25 내지 30 ℃ 에서 약 5 내지 7분간 침지시켜 반응을 수행한다. Although the reaction conditions vary depending on the characteristics of the coupling agent used, in the case of the silane coupling agent, the reaction is performed by immersing for about 5 to 7 minutes at about 25 to 30 ° C.
4. 산세 공정4. Pickling process
상기 커플링 공정에서 수득된 커플링된 비스마레이미드 트리아진 필름을 산성 용액을 이용하여 상온에서 침지시켜 비스마레이미드 트리아진 필름 표면의 개열 부위에 결합되지 않은 커플링 이온들을 제거한다. 본 산세 공정이 길거나, 사용되는 산성 용액이 지나치게 강한 산성 용액인 경우, 결합된 커플링 이온을 제거할 수 있으므로, 반응 조건을 적절하게 조절한다.The coupled bismaleimide triazine film obtained in the coupling process is immersed at room temperature using an acidic solution to remove the coupling ions which are not bound to the cleavage site on the surface of the bismaramide triazine film. If the present pickling process is long or the acidic solution used is an excessively strong acidic solution, the coupled coupling ions can be removed, so that the reaction conditions are appropriately adjusted.
5. 촉매 부가 공정5. Catalyst addition process
상기 커플링된 비스마레이미드 트리아진 필름을 촉매 용액에 침지시켜 비스마레이미드 트리아진 필름 표면에 금속촉매로서 팔라듐을 흡착시킨다. The coupled bismarimide triazine film is immersed in the catalyst solution to adsorb palladium as a metal catalyst on the bismarimide triazine film surface.
촉매 용액은 염화팔라듐 및 염화제일주석을 염산에 1:3~1:5 질량비로 희석하여 제조한다. 본 공정의 반응 시간이 지나치게 짧으면 비스마레이미드 트리아진 필름 표면에 촉매인 팔라듐 및 주석의 흡착률이 낮아 목적하는 촉매 효과를 달성할 수 없고, 반응 시간이 지나치게 길면 본 공정액 중 염산에 의해서 비스마레이미드 트리아진 필름 표면이 부식하는 역효과가 발생할 수 있으므로, 반응 조건을 적절하게 조절한다. The catalyst solution is prepared by diluting palladium chloride and stannous chloride in hydrochloric acid at a mass ratio of 1: 3 to 1: 5. If the reaction time of this process is too short, the adsorption rate of palladium and tin as catalysts on the surface of the bismarimide triazine film is low, so that the desired catalytic effect cannot be achieved. If the reaction time is too long, bismarray is formed by hydrochloric acid in the process solution. Adverse conditions of corrosive mid-triazine film surfaces can occur, so the reaction conditions are properly adjusted.
6. 무전해 도금 공정6. Electroless Plating Process
상기 촉매가 부가된 비스마레이미드 트리아진 필름을 무전해 도금 용액에 침지시켜 비스마레이미드 트리아진 필름을 무전해 도금한다. 상기 무전해 도금이란, 전류 인가 없이 원하는 금속을 기재 위에 도금하는 것을 말한다. The bismaleimide triazine film to which the catalyst is added is immersed in an electroless plating solution to electroless plate the bismaleimide triazine film. The electroless plating refers to plating a desired metal on a substrate without applying current.
무전해 도금 용액으로서, EDTA 수용액, 가성소다 수용액, 포르말린 수용액 및 황산동 수용액을 혼합하여 제조된 황산동 하부 도금 용액, 또는 차아인산나트륨, 구연산나트륨, 암모니아 및 6수 황산니켈 수용액을 혼합하여 제조된 황산니켈 무전해 도금 용액을 사용할 수 있다. 여기서, 무전해 도금 용액은 또한 금속 물성을 극대화시키기 위하여 광택제 성분 및 안정제 성분 등을 소량 포함할 수 있다. 이러한 광택제 및 안정제는 무전해 도금 용액의 재활용 및 장기간의 보존을 가능하게 한다. 황산동 무전해 도금 용액을 사용하는 경우, 무전해 도금 공정은 촉매가 부가된 비스마레이미드 트리아진 필름을 전류를 인가함 없이 약 65 내지 75 ℃ 의 온도에서 약 5 내지 10분간 침지시켜 수행된다. 이때, 무전해 도금 공정에서 얻어지는 무전해 도금층의 두께는 도금 시간에 따라서 적절히 조절할 수 있다. 만약 무전해 도금 공정의 반응 온도가 65 ℃ 미만인 경우, 도금 용액의 활성이 낮아서 미도금의 발생 및 부분적인 도금이 진행되어 무전해 도금층을 형성할 수 없고, 무전해 도금 공정의 온도가 75 ℃를 초과할 경우에는 급격한 도금의 진행으로 인해 무전해 도금막 상에 전체적인 균일성 및 밀착성이 부족하게 된다. As an electroless plating solution, nickel sulfate prepared by mixing an aqueous solution of EDTA, an aqueous solution of caustic soda, an aqueous solution of formalin, and an aqueous copper sulfate solution, or an aqueous nickel hypophosphite, sodium citrate, ammonia, and nickel hexahydrate solution. Electroless plating solutions can be used. Here, the electroless plating solution may also include a small amount of a brightener component, a stabilizer component, etc. in order to maximize metal properties. Such brighteners and stabilizers enable recycling and long term storage of the electroless plating solution. When using a copper sulfate electroless plating solution, the electroless plating process is performed by immersing the catalyst-added bismarademide triazine film at a temperature of about 65 to 75 ° C. for about 5 to 10 minutes without applying a current. At this time, the thickness of the electroless plating layer obtained in an electroless plating process can be adjusted suitably according to plating time. If the reaction temperature of the electroless plating process is less than 65 ° C., the plating solution activity is low, so unplating and partial plating proceed to form an electroless plating layer, and the temperature of the electroless plating process is 75 ° C. When exceeded, the overall uniformity and adhesion on the electroless plated film are insufficient due to the rapid progress of plating.
황산니켈 무전해 도금 용액을 사용하는 경우, 무전해 도금 공정은 촉매가 부가된 비스마레이미드 트리아진 필름을 약 35 내지 40 ℃의 온도에서 약 2 분간 침지시켜 수행된다. 본 공정은 이후 전해 도금 공정을 위한 공정으로, 약 0.2 ㎛ 이하의 도금 두께로 수행될 수 있으나, 미도금 부분이 없어질 정도의 시간 동안 수행하는 것이 바람직하다. In the case of using a nickel sulfate electroless plating solution, the electroless plating process is performed by immersing the catalyst-added bismaleimide triazine film at a temperature of about 35 to 40 ° C for about 2 minutes. This process is a process for the electroplating process after, but may be carried out with a plating thickness of about 0.2 ㎛ or less, it is preferable to perform for a time to the extent that the unplated portion is lost.
7. 전해 도금 공정7. Electrolytic Plating Process
무전해 도금된 비스마레이미드 트리아진 필름을 도금 용액에 침지시키고, 전류를 가하여 도금 공정을 수행한다.The electroless plated bismarimide triazine film is immersed in the plating solution, and a plating process is performed by applying an electric current.
구체적으로, 무전해 도금된 비스마레이미드 트리아진 필름을 도금 용액에 침지시키고, 20 내지 30 ℃에서 약 30분간 5A/dm^2 이하의 전류를 가해 도금을 수행하여 볼 그리드 어레이 반도체 패키지용 기판을 제조한다. 도금 반응 과정에서, 도금 용액을 원활히 교반시켜, 도금 용액 농도의 불균일을 최소화한다. 이러한 도금 조건은 수득하고자 하는 구리 도금 막의 두께에 따라 적절히 조절될 수 있다.Specifically, the electroless plated bismarimide triazine film is immersed in the plating solution, and the plating is performed by applying a current of 5 A / dm ^ 2 or less at about 20 to 30 ° C. for about 30 minutes to provide a substrate for a ball grid array semiconductor package. Manufacture. In the plating reaction, the plating solution is stirred smoothly to minimize the non-uniformity of the plating solution concentration. Such plating conditions can be appropriately adjusted according to the thickness of the copper plating film to be obtained.
본 실시예에서 사용될 수 있는 도금 용액으로서, 시판되는 도금 용액(Enthone OMI, 희성금속, 일광상사 등)을 사용할 수 있다. 그러나 시판의 도금 용액의 사용조건 보다 온건한 조건에서 장시간에 걸쳐서 천천히 막을 도금 공정을 수행한다. 장기간의 도금 수행 시간은 도금막 내부의 응력 발생을 최소한으로 억제하여 경도를 낮추고, 강도 및 연성이 우수한 도금막을 얻을 수 있게 한다.As the plating solution that can be used in this embodiment, commercially available plating solutions (Enthone OMI, diluent metal, sunrays, etc.) can be used. However, the plating process is performed slowly over a long period of time under conditions milder than those of commercial plating solutions. Prolonged plating time can minimize the generation of stress inside the plating film to lower the hardness and obtain a plating film excellent in strength and ductility.
시판되는 도금 용액 이외에 황산구리 수용액, 황산 및 염산 혼합용액을 정제수로 희석하여 조제된 도금 용액을 사용할 수 있다. 이러한 도금 용액은 광택제 및 첨가제를 소량 포함할 수 있다. In addition to the commercially available plating solution, a plating solution prepared by diluting a copper sulfate aqueous solution, a sulfuric acid and hydrochloric acid mixed solution with purified water may be used. Such plating solutions may include minor amounts of brighteners and additives.
8. 구리 도금막이 형성된 볼 그리드 어레이 반도체 패키지용 기판의 물성 검사8. Physical property inspection of substrate for ball grid array semiconductor package with copper plating film
본 발명의 실시예에 따라 수득된 볼 그리드 어레이 반도체 패키지용 기판의 연속성을 육안으로 관찰하여 상기 기판의 도금 정도를 평가한다. ◎는 샘플 표면 전체가 균일하고, 미려하게 도금된 경우이며, ○는 샘플 표면이 균일하게 도금된 경우, △는 부분적으로 미도금된 부분이 존재하는 경우, × 는 미도금된 부분이 많은 경우를 가리킨다. The degree of plating of the substrate was evaluated by visually observing the continuity of the substrate for the ball grid array semiconductor package obtained according to the embodiment of the present invention. (Circle) is a case where the whole sample surface is uniformly and beautifully plated, (circle) is a case where the sample surface is uniformly plated, (triangle | delta) is a case where the part which is partially unplated exists, and x is a case where there are many unplated parts. Point.
JIS-6471 규격에 따라 밀착 강도를 평가한다.The adhesion strength is evaluated according to the JIS-6471 standard.
이하, 본 발명을 실시예를 통하여 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다.Hereinafter, the present invention will be described in detail with reference to examples so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
본 발명의 실시예에 사용되는 비스마레이미드 트리아진 필름은 폭 100 ㎜, 길이 200 ㎜ 및 두께 100 ㎛의 비스마레이미드 트리아진 필름(미쯔비시 화학)을 준비하고, 전처리로서 150 ℃ 에서 약 5분간 건조하여 비스마레이미드 트리아진 필름에 포함된 수분을 제거하였다. 하기 실시예는 상기 비스마레이미드 트리아진 필름에 적합한 공정으로서 상기 공정은 비스마레이미드 트리아진 필름 및 조건에 따라 당업자에 의한 적절한 변이가 가능하다.The bismarademide triazine film used in the embodiment of the present invention is prepared with a bismarademide triazine film (Mitsubishi Chemical) having a width of 100 mm, a length of 200 mm and a thickness of 100 μm, and dried at 150 ° C. for about 5 minutes as a pretreatment. To remove the water contained in the bismarimide triazine film. The following examples are suitable processes for the bismarimide triazine film, which process may be appropriately modified by those skilled in the art according to the bismarademide triazine film and conditions.
실시예 1: 볼 그리드 어레이 반도체 패키지용 기판의 제조 1Example 1 Fabrication of Substrates for Ball Grid Array Semiconductor Packages 1
비스마레이미드 트리아진 필름을 35 ℃의 1 ℓ 에칭 용액(에틸렌글리콜 20 g 및 디메틸아세트아미드 10 g을 증류수 1 ℓ에 혼합하고, 여기에 280 g의 수산화칼륨을 투입하여 혼합용액 제조)에 4 분간 침지하여 에칭하였다. 상기 에칭된 비스마레이미드 트리아진 필름을 염산 100 ㎖/l 용액에 약 6 분간 침지하여 표면을 중화 처리하였다. 이후, 아미노프로필 트리에톡시 실란을 함유하는 실란계 커플링제를 1.2 %/ℓ로 희석하여, 약 26 ℃의 온도에서 5 분간 침지하였다. 이를 염산 수용액으로 세척하고, 염화 팔라듐(0.5 g/ℓ) 및 염화 제일 주석(2 g/ℓ)로 이루어진 용액을 염산에 1:1의 부피비로 희석하여 만든 촉매 용액에 커플링 처리된 비스마레이미드 트리아진 필름을 실온에서 약 5 분간 침지하였다. The bismarimide triazine film was mixed in a 1 L etching solution (20 g of ethylene glycol and 10 g of dimethylacetamide in 1 L of distilled water, and 280 g of potassium hydroxide was added thereto to prepare a mixed solution) at 35 ° C for 4 minutes. It was immersed and etched. The etched bismarimide triazine film was immersed in 100 ml / l solution of hydrochloric acid for about 6 minutes to neutralize the surface. Thereafter, the silane coupling agent containing aminopropyl triethoxy silane was diluted to 1.2% / l, and soaked for 5 minutes at a temperature of about 26 ° C. This was washed with an aqueous hydrochloric acid solution, and a bismaradeimide coupled to a catalyst solution prepared by diluting a solution consisting of palladium chloride (0.5 g / l) and chlorinated tin tin (2 g / l) in hydrochloric acid at a volume ratio of 1: 1. The triazine film was immersed for about 5 minutes at room temperature.
다음으로, EDTA 수용액(4.2 g/ℓ), 가성 소다 수용액(13.7 g/ℓ), 포르말린 수용액(9.5 g/ℓ)로 구성된 수용액에 황산동 수용액(15.8 g/ℓ)을 혼합하여 제조된 황산동 하부 도금 용액에 촉매 처리된 비스마레이미드 트리아진 필름을 전류의 인가 없이 약 70 ℃의 온도에서 약 10 분간 침지하여 무전해 도금을 수행하여 제 1 무전해 도금층을 형성시켰다.Next, copper sulfate bottom plating prepared by mixing an aqueous copper sulfate solution (15.8 g / l) with an aqueous solution consisting of an aqueous EDTA solution (4.2 g / l), an aqueous solution of caustic soda (13.7 g / l), and an aqueous formalin solution (9.5 g / l). The bismaleimide triazine film catalyzed by the solution was immersed for about 10 minutes at a temperature of about 70 ° C. without applying an electric current to perform electroless plating to form a first electroless plating layer.
다음으로, 제 1 무전해 도금층이 형성된 비스마레이미드 트리아진 필름을 약 110 ℃에서 10 분간 건조하고, 황산구리 수용액, 황산, 염산을 이온교환수로 희석하여 제조된 도금 용액에 상기 제 1 무전해 도금층이 형성된 비스마레이미드 트리아진 필름을 약 30 ℃의 온도에서 30 분간 침지하고, 3 A/dm^2의 전류를 인가하여, 제 1 전해 도금층이 형성된 볼 그리드 어레이 반도체 패키지용 기판을 제조하였다.Next, the bismaleimide triazine film having the first electroless plating layer formed thereon was dried at about 110 ° C. for 10 minutes, and the first electroless plating layer was coated in a plating solution prepared by diluting an aqueous copper sulfate solution, sulfuric acid, and hydrochloric acid with ion-exchanged water. The formed bismarimide triazine film was immersed at a temperature of about 30 ° C. for 30 minutes, and a current of 3 A / dm ^ 2 was applied to prepare a ball grid array semiconductor package substrate having a first electroplating layer.
실시예 2: 볼 그리드 어레이 반도체 패키지용 기판의 제조 2Example 2 Fabrication of Substrate for Ball Grid Array Semiconductor Package 2
상기 실시예 1에서, 에칭 용액으로서 에틸렌글리콜 20 g 및 디메틸아세트아미드 20 g을 증류수 1 ℓ에 혼합하고, 여기에 280 g의 수산화칼륨을 투입하여 제조된 에칭 용액을 사용하는 것을 제외하고, 상기 실시예 1 과 동일하게 수행하여, 볼 그리드 어레이 반도체 패키지용 기판을 제조하였다. In Example 1, except that 20 g of ethylene glycol and 20 g of dimethylacetamide were mixed in 1 L of distilled water as an etching solution, and an etching solution prepared by adding 280 g of potassium hydroxide was used. In the same manner as in Example 1, a substrate for a ball grid array semiconductor package was manufactured.
실시예 3: 볼 그리드 어레이 반도체 패키지용 기판 단자부의 제조 3Example 3 Fabrication of Substrate Terminal Part for Ball Grid Array Semiconductor Package 3
상기 실시예 1에 의해 제조된 기판에 4 ㎛ 크기의 관통홀을 생성시키고, 이 기판의 표면을 에칭하여 표면을 거칠게 하고, 무전해 도금액에 침지하여 제 2 무전해 도금층을 형성하였다. 제 2 무전해 도금층이 형성된 기판을 전해 도금액에 침지하고 전류를 가하여 제 2 전해 도금층을 형성하였다. 여기에 관통홀을 초과하는 직경을 가지는 마스크를 상기 관통홀 상부에 형성시키고, 마스크가 구비된 부분을 제외한 부분을 식각 제거시켜 상기 기재 기판만 잔존시켜, 볼 그리드 어레이 반도체 패키지용 기판에 단자부를 형성시켰다.A through hole having a size of 4 μm was formed in the substrate prepared in Example 1, the surface of the substrate was etched to roughen the surface, and immersed in an electroless plating solution to form a second electroless plating layer. The substrate on which the second electroless plating layer was formed was immersed in an electrolytic plating solution and a current was applied to form the second electroplating layer. A mask having a diameter exceeding the through hole is formed on the through hole, and a portion except for the portion provided with the mask is etched away so that only the substrate substrate remains, thereby forming a terminal portion on the substrate for the ball grid array semiconductor package. I was.
실시예 4: 볼 그리드 어레이 반도체 패키지용 기판 단자부의 제조 4Example 4 Fabrication of Substrate Terminal Parts for Ball Grid Array Semiconductor Package 4
상기 실시예 1에 의해 제조된 기판에 4 ㎛ 크기의 관통홀을 생성시키고, 이 기판의 표면을 에칭하여 표면을 거칠게 하고, 무전해 도금액에 침지하여 제 2 무전해 도금층을 형성하였다. 상기 관통홀이 구비되어 있으며, 제 2 무전해 도금층이 형성된 기판에 관통홀의 직경을 초과하도록 노출시키는 마스크를 기판의 상부에 구비시켰다. 상기 기판을 전해 도금액에 침지하여 제 2 전해 도금층을 형성시킨 후, 마스크와 마스크 하부를 식각하여 상기 기재 기판만 잔존시켜 볼 그리드 어레이 반도체 패키지용 기판에 단자부를 형성시켰다. A through hole having a size of 4 μm was formed in the substrate prepared in Example 1, the surface of the substrate was etched to roughen the surface, and immersed in an electroless plating solution to form a second electroless plating layer. The through hole is provided, and a mask is provided on the substrate to expose the substrate having the second electroless plating layer to exceed the diameter of the through hole. After the substrate was immersed in an electrolytic plating solution to form a second electroplating layer, a mask and a lower portion of the mask were etched to retain only the substrate substrate, thereby forming a terminal portion on the substrate for a ball grid array semiconductor package.
비교예 1: 볼 그리드 어레이 반도체 패키지용 기판의 제조 1Comparative Example 1: Fabrication of a substrate for a ball grid array semiconductor package 1
상기 실시예 1에서, 에칭 용액으로서 에틸렌글리콜 20 g을 증류수 1 ℓ에 혼합하고, 여기에 280 g의 수산화칼륨을 투입하여 제조된 에칭 용액만을 사용하는 것을 제외하고, 상기 실시예 1 과 동일하게 수행하여, 볼 그리드 어레이 반도체 패키지용 기판을 제조하였다.In Example 1, 20 g of ethylene glycol was mixed with 1 L of distilled water as an etching solution, and the same procedure as in Example 1 was performed except that only an etching solution prepared by adding 280 g of potassium hydroxide was used. Thus, a substrate for a ball grid array semiconductor package was manufactured.
비교예 2: 볼 그리드 어레이 반도체 패키지용 기판의 제조 2Comparative Example 2: Fabrication of Substrate for Ball Grid Array Semiconductor Package 2
상기 실시예 1에서, 에칭 용액으로서 에틸렌글리콜 20 g 및 디메틸아세트아미드 100 g을 증류수 1 ℓ에 혼합하고, 여기에 280 g의 수산화칼륨을 투입하여 제조된 에칭 용액만을 사용하는 것을 제외하고, 상기 실시예 1 과 동일하게 수행하여, 볼 그리드 어레이 반도체 패키지용 기판을 제조하였다.In Example 1, 20 g of ethylene glycol and 100 g of dimethylacetamide were mixed in 1 L of distilled water as the etching solution, and only the etching solution prepared by adding 280 g of potassium hydroxide was used. In the same manner as in Example 1, a substrate for a ball grid array semiconductor package was manufactured.
비교예 3: 볼 그리드 어레이 반도체 패키지용 기판의 제조 3Comparative Example 3: Fabrication of Substrate for Ball Grid Array Semiconductor Package 3
상기 실시예 1에서, 에칭 용액으로서 280 g의 수산화칼륨을 증류수 1ℓ에 녹인 용액을 사용하는 것을 제외하고, 상기 실시예 1과 동일한 공정을 수행하여 볼 그리드 어레이 반도체 패키지용 기판을 제조하였다. In Example 1, a substrate for a ball grid array semiconductor package was prepared in the same manner as in Example 1, except that 280 g of potassium hydroxide was dissolved in 1 L of distilled water as an etching solution.
비교예 4: 볼 그리드 어레이 반도체 패키지용 기판의 제조 4Comparative Example 4 Fabrication of Substrate for Ball Grid Array Semiconductor Package 4
상기 실시예 1에서, 에칭 용액으로서 증류수에 에틸렌 글리콜 20 g이 혼합된 1 ℓ 용액을 사용하는 것을 제외하고, 상기 실시예 1과 동일한 공정을 수행하여 볼 그리드 어레이 반도체 패키지용 기판을 제조하였다.In Example 1, a substrate for a ball grid array semiconductor package was manufactured in the same manner as in Example 1, except that 1 L solution in which 20 g of ethylene glycol was mixed in distilled water was used as an etching solution.
비교예 5: 볼 그리드 어레이 반도체 패키지용 기판의 제조 5Comparative Example 5: Fabrication of Substrate for Ball Grid Array Semiconductor Package 5
상기 실시예 1에서, 에칭 용액으로서 증류수에 200 g의 수산화나트륨이 혼합된 1ℓ에 녹인 용액을 사용하는 것을 제외하고, 상기 실시예 1과 동일한 공정을 수행하여 볼 그리드 어레이 반도체 패키지용 기판을 제조하였다.In Example 1, a substrate for a ball grid array semiconductor package was prepared by the same process as Example 1, except that a solution dissolved in 1 L of 200 g of sodium hydroxide in distilled water was used as an etching solution. .
상기 실시예 1 및 2와 비교예 1~5에 따라 제조된 볼 그리드 어레이 반도체 패키지용 기판에 대한 물성을 테스트하여 하기 표 1에 나타내었다.The physical properties of the substrates for the ball grid array semiconductor packages manufactured according to Examples 1 and 2 and Comparative Examples 1 to 5 were tested and shown in Table 1 below.
표 1
도금정도 구리박막/필름두께(㎛) 평균 밀착강도(㎏/㎝)
실시예 1 ◎ 12/100 0.85
실시예 2 ◎ 12/100 0.80
비교예 1 ◎ 12/100 0.65
비교예 2 ◎ 12/100 0.55
비교예 3 ○ 12/100 0.50
비교예 4 ○ 12/100 0.60
비교예 5 △ 12/100 0.30
Table 1
Plating accuracy Copper thin film / film thickness (㎛) Average adhesion strength (㎏ / ㎝)
Example 1 ◎ 12/100 0.85
Example 2 ◎ 12/100 0.80
Comparative Example 1 ◎ 12/100 0.65
Comparative Example 2 ◎ 12/100 0.55
Comparative Example 3 ○ 12/100 0.50
Comparative Example 4 ○ 12/100 0.60
Comparative Example 5 △ 12/100 0.30
상기 표 1에서 볼 수 있는 바와 같이, 비교예 1 및 2는 도금 정도는 좋았으나, 평균 밀착강도는 각각 0.65 및 0.55로 낮게 나타났다. 그러나, 실시예 1 및 2의 기판은 비교예 1 및 2에 비하여 도금특성과 밀착강도가 모두 우수하게 나타났다. As can be seen in Table 1, Comparative Examples 1 and 2, but the degree of plating was good, the average adhesion strength was low as 0.65 and 0.55, respectively. However, the substrates of Examples 1 and 2 showed better plating properties and adhesion strengths than Comparative Examples 1 and 2.
이유는 상기 에틸렌글리콜 및 디메틸아세트아미드가 비스마레이미드 트리아진 필름의 표면 팽창 또는 부분적인 녹임과 같은 반응을 유도하여, 비스마레이미드 트리아진 필름의 표면개질을 촉진시켰기 때문이다. 그러나, 디메틸아세트아미드가 과다하게 첨가될 경우, 표면 팽창 또는 부분적인 녹임이 너무 과하게 발생하여, 이후 과정에서 무전해 및 전해 도금하여 형성된 구리박막의 평균 밀착강도는 떨어지는 특성을 나타내었다.The reason is that the ethylene glycol and dimethylacetamide induced reactions such as surface expansion or partial dissolution of the bismaleimide triazine film, thereby promoting the surface modification of the bismaleimide triazine film. However, when too much dimethylacetamide is added, the surface expansion or partial melting occurs too much, so that the average adhesion strength of the copper thin film formed by electroless and electrolytic plating in the subsequent process is inferior.
상기에서는 본 발명의 바람직한 실시예에 대하여 설명하였지만, 본 발명은 이에 한정되는 것이 아니고 특허청구범위와 발명의 상세한 설명 및 첨부한 도면의 범위 안에서 여러 가지로 변형하여 실시하는 것이 가능하고 이 또한 본 발명의 범위에 속하는 것은 당연하다.Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it belongs to the range of.
본 발명의 볼 그리드 어레이 반도체 패키지용 기판은 인쇄회로기판에 사용하기에 적합하며, 반도체 분야, 센서 분야 등에 폭 넓게 이용할 수 있다.The substrate for a ball grid array semiconductor package of the present invention is suitable for use in printed circuit boards, and can be widely used in semiconductor fields, sensor fields, and the like.

Claims (20)

  1. 볼 그리드 어레이 반도체 패키지용 기판에 있어서,A substrate for a ball grid array semiconductor package,
    비스마레이미드 트리아진으로 형성된 기재 기판;A base substrate formed of bismarimide triazine;
    상기 기재 기판 상부에 형성된 제 1 무전해 도금층; 및A first electroless plating layer formed on the base substrate; And
    상기 제 1 무전해 도금층 상에 형성된 제 1 전해 도금층; A first electroplating layer formed on the first electroless plating layer;
    을 포함하는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판.A substrate for a ball grid array semiconductor package comprising a.
  2. 제1항에 있어서,The method of claim 1,
    상기 기재 기판의 표면이 에칭 개열되어 이미드기 또는 카르복실기가 형성되고, 상기 이미드기 또는 카르복실기에 커플링제가 결합되어 있는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키징용 기판.The surface of the said base substrate is etched and cleaved, the imide group or the carboxyl group is formed, and the coupling agent is couple | bonded with the said imide group or the carboxyl group, The board | substrate for ball grid array semiconductor packaging characterized by the above-mentioned.
  3. 제1항에 있어서,The method of claim 1,
    상기 제 1 무전해 도금층은 금, 니켈 및 구리로 이루어지는 군으로부터 1종 이상 선택되는 금속인 것을 특징을 하는 볼 그리드 어레이 반도체 패키지용 기판.The first electroless plating layer is a ball grid array semiconductor package substrate, characterized in that at least one metal selected from the group consisting of gold, nickel and copper.
  4. 제1항에 있어서,The method of claim 1,
    상기 제 1 전해 도금층은 금, 니켈 및 구리로 이루어지는 군으로부터 1종 이상 선택되는 금속인 것을 특징을 하는 볼 그리드 어레이 반도체 패키지용 기판.The first electroplating layer is a ball grid array semiconductor package substrate, characterized in that at least one metal selected from the group consisting of gold, nickel and copper.
  5. 제1항에 있어서,The method of claim 1,
    상기 제 1 무전해 도금층은 0.2 ㎛ 이하인 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판.The first electroless plating layer is 0.2 ㎛ or less substrate for a ball grid array semiconductor package.
  6. 제1항에 있어서,The method of claim 1,
    상기 제 1 전해 도금층은 10 내지 20 ㎛인 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판.The first electroplating layer is a ball grid array semiconductor package substrate, characterized in that 10 to 20 ㎛.
  7. 볼 그리드 어레이 반도체 패키지용 기판에 있어서,A substrate for a ball grid array semiconductor package,
    비스마레이미드 트리아진으로 형성되며 복수개의 관통홀이 구비되어 있는 기재 기판;A base substrate formed of bismarimide triazine and having a plurality of through holes;
    상기 기재 기판 상부에 형성된 제 1 무전해 도금층;A first electroless plating layer formed on the base substrate;
    상기 제 1 무전해 도금층 상부에 형성된 제 1 전해 도금층;A first electroplating layer formed on the first electroless plating layer;
    상기 관통홀 내부 및 주변에 형성되는 제 2 무전해 도금층;A second electroless plating layer formed in and around the through hole;
    상기 제 2 무전해 도금층 상에 형성된 제 2 전해 도금층;A second electroplating layer formed on the second electroless plating layer;
    을 포함하는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판.A substrate for a ball grid array semiconductor package comprising a.
  8. 볼 그리드 어레이 반도체 패키지용 기판의 제조방법에 있어서,In the method of manufacturing a substrate for a ball grid array semiconductor package,
    1) 비스마레이미드 트리아진으로 형성된 기재 기판의 표면을 에칭 용액으로 에칭 개열하여, 상기 표면에 이미드기 또는 카르복실기를 생성하는 단계;1) etching and cleaving the surface of the substrate substrate formed of bismarademide triazine with an etching solution to generate an imide group or a carboxyl group on the surface;
    2) 상기 기재 기판 표면에 커플링제를 도입하여 상기 이미드기 또는 카르복실기에 커플링하는 단계;2) introducing a coupling agent to the surface of the base substrate and coupling the imide group or carboxyl group;
    3) 상기 기재 기판의 상기 표면에 제 1 무전해 도금층을 형성하는 단계; 및3) forming a first electroless plating layer on the surface of the base substrate; And
    4) 상기 제 1 무전해 도금층에 제 1 전해 도금층을 형성하는 단계;4) forming a first electroplating layer on the first electroless plating layer;
    을 포함하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.Method of manufacturing a substrate for a ball grid array semiconductor package comprising a.
  9. 제8항에 있어서,The method of claim 8,
    상기 에칭 용액은 수산화물인 수산화칼륨, 수산화나트륨, 수산화칼슘 및 수산화마그네늄으로 이루어지는 군으로부터 선택되는 1종 이상, 알코올인 에틸렌글리콜, 프로필렌글리콜, 부탄디올, 네오펜틸글리콜 및 디에틸렌글리콜으로 이루어지는 군으로부터 선택되는 1종 이상, 질소화합물인 디메틸아세트아미드 또는 디메틸포름아미드에서 선택되는 1종 이상을 혼합한 용액인 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.The etching solution is at least one selected from the group consisting of potassium hydroxide, sodium hydroxide, calcium hydroxide and magnesium hydroxide as hydroxides, and selected from the group consisting of ethylene glycol, propylene glycol, butanediol, neopentyl glycol and diethylene glycol as alcohols. A method for producing a substrate for a ball grid array semiconductor package, characterized in that the solution is a mixture of one or more selected from dimethylacetamide or dimethylformamide, which is a nitrogen compound.
  10. 제9항에 있어서,The method of claim 9,
    상기 에칭 용액은 수산화물 14 중량부에 알코올이 1~3 중량부 혼합되고, 알코올 2 중량부에 질소화합물은 1~3 중량부 혼합하여 제조되는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.The etching solution is prepared by mixing 1 to 3 parts by weight of alcohol in 14 parts by weight of hydroxide, and 1 to 3 parts by weight of nitrogen compound in 2 parts by weight of alcohol. Method of manufacturing a substrate for a ball grid array semiconductor package, characterized in that.
  11. 제8항에 있어서,The method of claim 8,
    상기 단계 1)에서, In step 1) above,
    상기 에칭은 기재 기판을 에칭용액에 45 내지 50 ℃에서 5~7분간 침지하는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.The etching is a method of manufacturing a substrate for a ball grid array semiconductor package, characterized in that the substrate is immersed in the etching solution at 45 to 50 ℃ for 5 to 7 minutes.
  12. 제8항에 있어서,The method of claim 8,
    상기 단계 2)와 단계 3) 사이에 상기 기재 기판에 팔라듐 또는 주석을 결합시키는 단계를 더 수행하는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.And bonding palladium or tin to the base substrate between the step 2) and the step 3).
  13. 제8항에 있어서, The method of claim 8,
    상기 제 1 무전해 도금층은 금, 니켈 또는 구리로 형성되는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.The first electroless plating layer is a method of manufacturing a substrate for a ball grid array semiconductor package, characterized in that formed of gold, nickel or copper.
  14. 제8항에 있어서,The method of claim 8,
    상기 제 1 전해 도금층은 금, 니켈 또는 구리로 형성되는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.The first electroplating layer is a method of manufacturing a substrate for a ball grid array semiconductor package, characterized in that formed of gold, nickel or copper.
  15. 제8항에 있어서,The method of claim 8,
    상기 제 1 무전해 도금층의 두께는 0.2 ㎛ 이하인 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.The thickness of the first electroless plating layer is 0.2 ㎛ or less method for manufacturing a substrate for a ball grid array semiconductor package.
  16. 제8항에 있어서,The method of claim 8,
    상기 제 1 전해 도금층의 형성 두께가 약 10 내지 20 ㎛인 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.Forming thickness of the first electroplating layer is about 10 to 20 ㎛ method of manufacturing a substrate for a ball grid array semiconductor package.
  17. 제8항에 있어서,The method of claim 8,
    5) 상기 기판의 목적하는 부위에 3~7 ㎛ 크기의 관통홀을 1종 이상 형성시키는 단계;5) forming at least one through hole having a size of 3 ~ 7 ㎛ in the desired portion of the substrate;
    6) 상기 관통홀 및 상기 기판 표면에 무전해 도금 방법으로 제 2 무전해 도금층을 형성하는 단계;6) forming a second electroless plating layer on the through hole and the surface of the substrate by an electroless plating method;
    7) 상기 제 2 무전해 도금층의 표면에 전해 도금 방법으로 제 2 전해 도금층을 형성하는 단계;7) forming a second electroplating layer on the surface of the second electroless plating layer by an electroplating method;
    8) 상기 관통홀의 직경을 초과하는 직경을 가지는 마스크를 상기 관통홀 상부에 구비시키는 단계; 및8) providing a mask having a diameter exceeding a diameter of the through hole on the through hole; And
    9) 상기 마스크를 제외한 부분을 식각 제거시켜 상기 기재 기판만 잔존시키는 단계;9) etching away portions other than the mask to leave only the substrate substrate;
    을 더 수행하는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.Method of manufacturing a substrate for a ball grid array semiconductor package, characterized in that further performing.
  18. 제8항에 있어서,The method of claim 8,
    5) 상기 기판의 목적하는 부위에 3~7 ㎛ 크기의 관통홀을 1종 이상 형성시키는 단계;5) forming at least one through hole having a size of 3 ~ 7 ㎛ in the desired portion of the substrate;
    6) 상기 관통홀 및 상기 기판의 표면에 무전해 도금 방법으로 제 2 무전해 도금층을 형성하는 단계;6) forming a second electroless plating layer on the surface of the through hole and the substrate by an electroless plating method;
    7) 상기 관통홀의 직경을 초과하도록 노출시키는 마스크를 기판의 상부에 구비시키는 단계;7) providing a mask on the substrate to expose the diameter of the through hole to exceed;
    8) 상기 제 2 무전해 도금층에 전해 도금 방법으로 제 2 전해 도금층을 형성하는 단계; 및8) forming a second electroplating layer on the second electroless plating layer by an electroplating method; And
    9) 상기 마스크를 제거하고, 상기 마스크 하부를 식각 제거시켜 상기 기재기판만 잔존시키는 단계;9) removing the mask and etching the lower portion of the mask to leave only the base substrate;
    을 더 수행하는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.Method of manufacturing a substrate for a ball grid array semiconductor package, characterized in that further performing.
  19. 제17항 또는 제18항에 있어서, The method of claim 17 or 18,
    상기 제 2 무전해 도금층은 금, 니켈 또는 구리로 형성되는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.The second electroless plating layer is a method of manufacturing a substrate for a ball grid array semiconductor package, characterized in that formed of gold, nickel or copper.
  20. 제17항 또는 제18항에 있어서,The method of claim 17 or 18,
    상기 제 2 전해 도금층은 금, 니켈 또는 구리로 형성되는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지용 기판의 제조방법.The second electroplating layer is a method of manufacturing a substrate for a ball grid array semiconductor package, characterized in that formed of gold, nickel or copper.
PCT/KR2010/004909 2009-08-03 2010-07-27 Substrate for ball grid array semiconductor package and fabrication method thereof WO2011016641A2 (en)

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