JP2005197442A - Wire bonding terminal and its manufacturing method, and semiconductor mounting substrate having the wire bonding terminal - Google Patents
Wire bonding terminal and its manufacturing method, and semiconductor mounting substrate having the wire bonding terminal Download PDFInfo
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- JP2005197442A JP2005197442A JP2004001921A JP2004001921A JP2005197442A JP 2005197442 A JP2005197442 A JP 2005197442A JP 2004001921 A JP2004001921 A JP 2004001921A JP 2004001921 A JP2004001921 A JP 2004001921A JP 2005197442 A JP2005197442 A JP 2005197442A
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- wire bonding
- plating film
- palladium
- bonding terminal
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 114
- 238000007747 plating Methods 0.000 claims abstract description 95
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 65
- 229910052737 gold Inorganic materials 0.000 claims abstract description 39
- 239000010931 gold Substances 0.000 claims abstract description 39
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 150000002940 palladium Chemical class 0.000 claims abstract description 16
- 229910052802 copper Inorganic materials 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims abstract description 12
- 238000006073 displacement reaction Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 abstract description 10
- 150000002343 gold Chemical class 0.000 abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 229910052759 nickel Inorganic materials 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 238000007654 immersion Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 239000010953 base metal Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/01004—Beryllium [Be]
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- H01L2924/01019—Potassium [K]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
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- H01L2924/01046—Palladium [Pd]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、ワイヤボンディング用端子とその製造方法及びそのワイヤボンディング用端子を有する半導体搭載用基板に関する。 The present invention relates to a wire bonding terminal, a manufacturing method thereof, and a semiconductor mounting substrate having the wire bonding terminal.
プリント配線板は、近年、高密度化が進んでおり、配線板に直接半導体チップを搭載する半導体搭載用パッケージであるチップオンボード（以下、ＣＯＢという。）やマルチチップモジュール（以下ＭＣＭという。）等の需要が伸びている。これらのパッケージと半導体チップとの電気的接続は、通常、ワイヤボンディングが用いられる。このパッケージにおけるワイヤボンディング用端子としては、例えば社団法人プリント回路学会誌「サーキットテクノロジー」（１９９３年Ｖｏｌ．８Ｎｏ．５ ３６８〜３７２頁）に記載されているように、端子部分の銅箔表面に、ニッケルめっき皮膜／置換金めっき皮膜／無電解金めっき皮膜を形成することが知られている。また、特開平５−５５７２７号公報には、端子部分の回路銅の表面に、ニッケルめっき皮膜／パラジウム皮膜を形成することが記載されている。 In recent years, the density of printed wiring boards has been increasing, and a chip-on-board (hereinafter referred to as COB) or a multi-chip module (hereinafter referred to as MCM) which is a package for mounting a semiconductor chip directly on the wiring board. Demand is growing. For the electrical connection between these packages and the semiconductor chip, wire bonding is usually used. As a terminal for wire bonding in this package, for example, as described in the Journal of the Printed Circuit Society of Japan “Circuit Technology” (1993 Vol. 8 No. 5 pages 368-372), on the copper foil surface of the terminal portion, It is known to form a nickel plating film / displacement gold plating film / electroless gold plating film. Japanese Patent Application Laid-Open No. 5-55727 discloses that a nickel plating film / palladium film is formed on the surface of the circuit copper of the terminal portion.
また、配線板の端部にコネクタへ挿入する端子部として、金めっきを行うことは、古くから知られており、例えば、特開平１−１８０９８５号公報には、銅箔の表面に、ニッケルめっき皮膜／パラジウムのめっき核の形成／無電解金めっき皮膜を形成することが記載され、特開平５−３２７１８７号公報には、銅箔の表面に、パラジウムめっき皮膜／金めっき皮膜あるいはパラジウムめっき皮膜を形成することが記載され、特開平６−２２８７６２号公報には、銅箔の表面に、ニッケルめっき皮膜／パラジウムストライクめっき皮膜／置換金めっき皮膜を形成することが記載されている。
ところで、上記した従来の構造や方法においては、めっきを行なった後の加熱処理によって、ワイヤボンディングの確実な接続（成功率）が著しく低下して、接続不良になるという課題がある。このような加熱処理とは、例えば、めっきを行なった後に、水分を除去するために乾燥するときに加わる熱であり、１５０〜１８０℃で数時間行われる。これにより、下地金属である銅、又はニッケルが、パラジウムめっき表面又は金めっき表面に拡散し、ワイヤボンディングの成功率が著しく低下する。 By the way, in the above-described conventional structure and method, there is a problem that a reliable connection (success rate) of wire bonding is remarkably lowered by the heat treatment after plating, resulting in poor connection. Such heat treatment is, for example, heat applied when drying is performed in order to remove moisture after plating, and is performed at 150 to 180 ° C. for several hours. Thereby, copper or nickel which is a base metal diffuses on the palladium plating surface or the gold plating surface, and the success rate of wire bonding is significantly reduced.
本発明は、加熱処理を行なってもワイヤボンディング性が良好なワイヤボンディング用端子とその製造方法及びそのワイヤボンディング用端子を有する半導体搭載用基板を提供することを目的とする。 An object of the present invention is to provide a wire bonding terminal having good wire bonding property even after heat treatment, a manufacturing method thereof, and a semiconductor mounting substrate having the wire bonding terminal.
本発明は、以下に記載の各事項に関する。
（１）ワイヤボンディング用端子の銅の表面に、パラジウム純度が９９．５重量％以上の置換パラジウムめっき皮膜またはパラジウム純度が９９．５重量％以上の無電解パラジウムめっき皮膜、置換金めっき皮膜、無電解金めっき皮膜を、この順序に形成したワイヤボンディング用端子。
（２）置換パラジウムめっき皮膜または無電解パラジウムめっき皮膜の厚さが、０．０１μｍ以上である（１）に記載のワイヤボンディング用端子。
（３）置換金めっき皮膜と無電解金めっき皮膜の厚さの和が、０．０３μｍ以上である（１）又は（２）に記載のワイヤボンディング用端子。
（４）ワイヤボンディング用端子の銅の表面に、パラジウム純度が９９．５重量％以上の置換パラジウムめっき皮膜またはパラジウム純度が９９．５重量％以上の無電解パラジウムめっき皮膜を形成する工程、その表面に置換金めっき皮膜を形成する工程、その表面に無電解金めっき皮膜を形成する工程を含むワイヤボンディング用端子の製造方法。
（５）半導体搭載部と、ワイヤボンディング用端子と、外部接続用端子と、前記ワイヤボンディング用端子と外部接続用端子とを電気的に接続する導体回路と、これらを支持する絶縁部からなる半導体搭載用基板において、前記ワイヤボンディング用端子が、（１）〜（３）のいずれかに記載されたワイヤボンディング用端子、または（４）に記載のワイヤボンディング用端子の製造方法で製造されたワイヤボンディング用端子を有する半導体搭載用基板。
The present invention relates to each item described below.
(1) On the copper surface of the wire bonding terminal, a substituted palladium plating film having a palladium purity of 99.5% by weight or more, an electroless palladium plating film having a palladium purity of 99.5% by weight or more, a substituted gold plating film, Wire bonding terminal in which electrolytic gold plating film is formed in this order.
(2) The wire bonding terminal according to (1), wherein the thickness of the substituted palladium plating film or the electroless palladium plating film is 0.01 μm or more.
(3) The wire bonding terminal according to (1) or (2), wherein the sum of the thicknesses of the displacement gold plating film and the electroless gold plating film is 0.03 μm or more.
(4) A step of forming a substituted palladium plating film having a palladium purity of 99.5% by weight or more or an electroless palladium plating film having a palladium purity of 99.5% by weight or more on the copper surface of the wire bonding terminal, its surface The manufacturing method of the terminal for wire bonding including the process of forming a substituted gold plating film, and the process of forming an electroless gold plating film on the surface.
(5) A semiconductor comprising a semiconductor mounting portion, a wire bonding terminal, an external connection terminal, a conductor circuit that electrically connects the wire bonding terminal and the external connection terminal, and an insulating portion that supports them. In the mounting substrate, the wire bonding terminal is a wire bonding terminal described in any one of (1) to (3) or a wire manufactured by the method for manufacturing a wire bonding terminal described in (4). A semiconductor mounting substrate having bonding terminals.
本発明によって、加熱処理によってもワイヤボンディング性が良好なワイヤボンディング用端子とその製造方法及びそのワイヤボンディング端子を有する半導体搭載用基板を提供することができる。 According to the present invention, it is possible to provide a wire bonding terminal having good wire bonding property even by heat treatment, a manufacturing method thereof, and a semiconductor mounting substrate having the wire bonding terminal.
本発明のワイヤボンディング用端子は、端子の銅の表面に、パラジウム純度が９９．５重量％以上の置換パラジウムめっき皮膜またはパラジウム純度が９９．５重量％以上の無電解パラジウムめっき皮膜、置換金めっき皮膜、無電解金めっき皮膜を、この順序に形成したことを特徴とする。銅の表面に高純度のパラジウムめっき層を形成することにより、加熱による銅の拡散を防止し、また下地金属としてニッケルめっきを用いていないため、加熱によりニッケルが拡散することもない。なお、置換パラジウムめっきと無電解パラジウムめっきは、単独で行っても良い。また両方行っても良く、その場合は、置換パラジウムめっき、無電解パラジウムめっきの順序が好ましい。 The terminal for wire bonding of the present invention is a substituted palladium plating film having a palladium purity of 99.5% by weight or more, an electroless palladium plating film having a palladium purity of 99.5% by weight or more, and a displacement gold plating on the copper surface of the terminal. A film and an electroless gold plating film are formed in this order. By forming a high-purity palladium plating layer on the surface of copper, diffusion of copper due to heating is prevented, and since nickel plating is not used as the base metal, nickel is not diffused by heating. In addition, you may perform substitution palladium plating and electroless palladium plating independently. Moreover, you may perform both, In that case, the order of substituted palladium plating and electroless palladium plating is preferable.
置換パラジウムめっき皮膜または無電解パラジウムめっき皮膜の厚さは、０．０１μｍ以上であることが好ましい。０．０１μｍ未満であると、加熱処理後のワイヤボンディングの成功率が低下する。また、上限は、ほとんど経済的な理由によってのみ制限され、通常は、２μｍまでとするのが好ましい。 The thickness of the substituted palladium plating film or electroless palladium plating film is preferably 0.01 μm or more. If it is less than 0.01 μm, the success rate of wire bonding after the heat treatment is lowered. Also, the upper limit is limited almost exclusively for economic reasons, and is usually preferably up to 2 μm.
置換金めっき皮膜と無電解金めっき皮膜の厚さの和は、０．０３μｍ以上であることが好ましく、０．０３μｍ未満であると、加熱処理後のワイヤボンディングの成功率が低下するまた、上限は、ほとんど経済的な理由によってのみ制限され、通常は、２μｍまでとするのが好ましい。このようなワイヤボンディング用端子を製造するには、端子の銅の表面に、パラジウム純度が９９．５重量％以上の置換パラジウムめっき皮膜またはパラジウム純度が９９．５重量％以上の無電解パラジウムめっき皮膜を形成し、その表面に置換金めっき皮膜を形成し、その表面に無電解金めっき皮膜を形成することによって、得られる。 The sum of the thickness of the displacement gold plating film and the electroless gold plating film is preferably 0.03 μm or more, and if it is less than 0.03 μm, the success rate of wire bonding after heat treatment is reduced. Is limited only for most economic reasons and is usually preferably up to 2 μm. In order to manufacture such a wire bonding terminal, a substituted palladium plating film having a palladium purity of 99.5% by weight or more or an electroless palladium plating film having a palladium purity of 99.5% by weight or more is formed on the copper surface of the terminal. , A replacement gold plating film is formed on the surface, and an electroless gold plating film is formed on the surface.
パラジウム純度が９９．５重量％以上の置換パラジウムめっき皮膜を形成できる市販の置換パラジウムめっき液としては、ＭＣＡ（株式会社ワールドメタル製、商品名）などが挙げられ、またパラジウム純度が９９．５重量％以上の無電解パラジウムめっき皮膜を形成できる市販の無電解パラジウムめっき液としては、プレシアＰＤＳ（奥野製薬工業株式会社製、商品名）などが挙げられる。また、本発明に使用できる置換金めっき液及び無電解金めっき液としては、配線板製造に用いられる市販品であれば、特に限定されない。 Examples of commercially available substituted palladium plating solutions capable of forming a substituted palladium plating film having a palladium purity of 99.5% by weight or more include MCA (trade name, manufactured by World Metal Co., Ltd.), and the palladium purity is 99.5% by weight. Examples of a commercially available electroless palladium plating solution capable of forming an electroless palladium plating film of at least% include Presia PDS (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.). Moreover, if it is a commercial item used for wiring board manufacture, it will not specifically limit as substitution gold plating solution and electroless gold plating solution which can be used for this invention.
半導体搭載部と、ワイヤボンディング用端子と、外部接続用端子と、前記ワイヤボンディング用端子と外部接続用端子とを電気的に接続する導体回路と、これらを支持する絶縁部からなる半導体搭載用基板としては、ＣＯＢ，ＭＣＭの他、ピングリッドアレイ（以下、ＰＧＡという。）、ボールグリッドアレイ（以下、ＢＧＡという。）等、が挙げられ、前記半導体搭載用基板は、本発明のワイヤボンディング用端子を有している。また、半導体搭載用基板の絶縁基材としては、セラミクス等無機質基板や、フェノール樹脂、エポキシ樹脂、ポリイミド樹脂等の有機質基板、エポキシ樹脂、ポリイミド樹脂等のフレキシブル基板等、どのような材料でも用いることができる。 A semiconductor mounting substrate comprising a semiconductor mounting portion, a wire bonding terminal, an external connection terminal, a conductor circuit that electrically connects the wire bonding terminal and the external connection terminal, and an insulating portion that supports them In addition to COB and MCM, a pin grid array (hereinafter referred to as PGA), a ball grid array (hereinafter referred to as BGA), and the like can be mentioned. The semiconductor mounting substrate is a wire bonding terminal according to the present invention. have. In addition, as an insulating base material for a semiconductor mounting substrate, any material such as an inorganic substrate such as ceramics, an organic substrate such as phenol resin, epoxy resin or polyimide resin, or a flexible substrate such as epoxy resin or polyimide resin should be used. Can do.
（実施例１）
銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株式会社製、商品名）に孔をあけ、スルーホールめっきを行ない、エッチングレジストを形成し、不要な銅をエッチング除去し、不要な箇所にめっきを析出させないように、ソルダーレジストを兼ねためっきレジストを形成した後、以下の工程によりワイヤボンディング端子を形成した。
工程１：（前処理）
上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。
工程２：（活性化）
続いて、めっき活性化処理液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗した。
工程３：（無電解パラジウムめっき）
続いて、無電解パラジウムめっき液であるプレシアＰＤＳ（奥野製薬工業株式会社製、商品名）に、５０℃で２０分間、浸漬処理した。そして、パラジウム純度が９９．９重量％の無電解パラジウムめっき皮膜を０．０５μｍ形成した。
工程４：（置換金めっき）
続いて、置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社製、商品名）に、８５℃で１０分間、浸漬処理した。
工程５：（無電解金めっき）
続いて、無電解金めっき液であるＨＧＳ−２０００（日立化成工業株式会社製、商品名）に、６５℃で４０分間、浸漬処理し、トータル厚み０．１μｍの金めっき皮膜を形成した。以上、ワイヤボンディング端子を有する配線板を製造した。
(Example 1)
MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a copper-clad laminate, is drilled, through-hole plating is performed, an etching resist is formed, and unnecessary copper is removed by etching. After forming a plating resist that also serves as a solder resist so as not to deposit plating on the wire, wire bonding terminals were formed by the following steps.
Step 1: (Pretreatment)
The substrate is immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then immersed in a 100 g / l ammonium persulfate solution for 1 minute. It was washed with water for 1 minute, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes.
Step 2: (Activation)
Subsequently, immersion treatment was performed at 25 ° C. for 5 minutes in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a plating activation treatment solution, and washed with water for 2 minutes.
Process 3: (electroless palladium plating)
Subsequently, it was immersed in Precia PDS (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.), which is an electroless palladium plating solution, at 50 ° C. for 20 minutes. Then, 0.05 μm of an electroless palladium plating film having a palladium purity of 99.9% by weight was formed.
Process 4: (Substitution gold plating)
Subsequently, immersion treatment was performed at 85 ° C. for 10 minutes in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a displacement gold plating solution.
Process 5: (electroless gold plating)
Subsequently, immersion treatment was performed at 65 ° C. for 40 minutes in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless gold plating solution, to form a gold plating film having a total thickness of 0.1 μm. As described above, a wiring board having wire bonding terminals was manufactured.
（実施例２）
工程３の無電解パラジウムめっきを置換パラジウムめっきに変更し、置換パラジウムめっき液であるＭＣＡ（株式会社ワールドメタル製、商品名）に、６５℃で５分間、浸漬処理し、パラジウム純度が９９．９重量％の置換パラジウムめっき皮膜を０．０５μｍ形成した以外は、実施例１と同様にし、ワイヤボンディング端子を有する配線板を製造した。
(Example 2)
The electroless palladium plating in step 3 was changed to substituted palladium plating, and immersed in MCA (trade name, manufactured by World Metal Co., Ltd.) which is a substituted palladium plating solution for 5 minutes at 65 ° C., the palladium purity was 99.9. A wiring board having wire bonding terminals was produced in the same manner as in Example 1 except that 0.05% by weight of the substituted palladium plating film of wt% was formed.
（比較例１）
工程３のパラジウムめっきを省略した以外は、実施例１と同様にし、ワイヤボンディング端子を有する配線板を製造した。
(Comparative Example 1)
A wiring board having wire bonding terminals was manufactured in the same manner as in Example 1 except that the palladium plating in Step 3 was omitted.
（比較例２）
工程４の置換金めっき及び工程５の無電解金めっきを省略した以外は、実施例１と同様にし、ワイヤボンディング端子を有する配線板を製造した。
(Comparative Example 2)
A wiring board having wire bonding terminals was manufactured in the same manner as in Example 1 except that the replacement gold plating in step 4 and the electroless gold plating in step 5 were omitted.
（比較例３）
置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社製、商品名）に、８５℃で１０分間、浸漬処理し、厚み０．０１μｍの置換金めっき皮膜を形成し、工程５の無電解金めっきを省略した以外は、実施例１と同様にし、ワイヤボンディング端子を有する配線板を製造した。
(Comparative Example 3)
An immersion gold plating solution of HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a displacement gold plating solution, is immersed at 85 ° C. for 10 minutes to form a displacement gold plating film having a thickness of 0.01 μm. A wiring board having wire bonding terminals was manufactured in the same manner as in Example 1 except that gold plating was omitted.
（比較例４）
工程３の無電解パラジウムめっきの無電解パラジウムめっき液をＡＰＰ（石原薬品株式会社製、商品名）に変更し、５０℃で２０分間、浸漬処理し、パラジウム純度が９６重量％の無電解パラジウムめっき皮膜を０．０５μｍ形成した以外は、実施例１と同様にし、ワイヤボンディング端子を有する配線板を製造した。
(Comparative Example 4)
The electroless palladium plating solution for the electroless palladium plating in step 3 is changed to APP (trade name, manufactured by Ishihara Pharmaceutical Co., Ltd.) and immersed for 20 minutes at 50 ° C., and the electroless palladium plating has a palladium purity of 96% by weight. A wiring board having wire bonding terminals was manufactured in the same manner as in Example 1 except that the film was formed to have a thickness of 0.05 μm.
以上のようにして作製したワイヤボンディング端子を有する配線板を、１８０℃で２時間熱処理、ワイヤボンディング試験を行なった。このときに、１つの配線板に行なうワイヤボンディングの数を１００本とし、ワイヤボンディングに成功したものの数を付着率とした。熱処理を行なったものは、実施例１、２では付着率１００％であり、ワイヤの密着強度も８〜１２ｇであったが、比較例ではいずれも、付着率は、２０〜６０％であり、付着しないものが多く、ワイヤの密着強度も０〜１０ｇとばらついた。
The wiring board having the wire bonding terminals produced as described above was heat-treated at 180 ° C. for 2 hours and subjected to a wire bonding test. At this time, the number of wire bondings performed on one wiring board was 100, and the number of successful wire bondings was defined as the adhesion rate. Those subjected to the heat treatment had an adhesion rate of 100% in Examples 1 and 2 and the adhesion strength of the wire was 8 to 12 g. There were many things that did not adhere, and the adhesion strength of the wires varied from 0 to 10 g.
Claims (5)
A semiconductor mounting substrate comprising a semiconductor mounting portion, a wire bonding terminal, an external connection terminal, a conductor circuit that electrically connects the wire bonding terminal and the external connection terminal, and an insulating portion that supports them The wire bonding terminal is a wire bonding terminal according to any one of claims 1 to 3, or a wire bonding terminal manufactured by the method for manufacturing a wire bonding terminal according to claim 4. A substrate for mounting a semiconductor, comprising:
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| JP2004001921A JP4449459B2 (en) | 2004-01-07 | 2004-01-07 | A wire mounting terminal, a manufacturing method thereof, and a semiconductor mounting substrate having the wire bonding terminal. |
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| JP2004001921A JP4449459B2 (en) | 2004-01-07 | 2004-01-07 | A wire mounting terminal, a manufacturing method thereof, and a semiconductor mounting substrate having the wire bonding terminal. |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8426742B2 (en) | 2007-04-27 | 2013-04-23 | Hitachi Chemical Company, Ltd. | Connecting terminal, semiconductor package using connecting terminal and method for manufacturing semiconductor package |
| JP2013089630A (en) * | 2011-10-13 | 2013-05-13 | Hitachi Chemical Co Ltd | Semiconductor package and manufacturing method of the same |
| EP3722459A1 (en) | 2019-04-10 | 2020-10-14 | C. Uyemura & Co., Ltd. | Gold plating method and plating film |
-
2004
- 2004-01-07 JP JP2004001921A patent/JP4449459B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8426742B2 (en) | 2007-04-27 | 2013-04-23 | Hitachi Chemical Company, Ltd. | Connecting terminal, semiconductor package using connecting terminal and method for manufacturing semiconductor package |
| JP2013089630A (en) * | 2011-10-13 | 2013-05-13 | Hitachi Chemical Co Ltd | Semiconductor package and manufacturing method of the same |
| EP3722459A1 (en) | 2019-04-10 | 2020-10-14 | C. Uyemura & Co., Ltd. | Gold plating method and plating film |
| KR20200119740A (en) | 2019-04-10 | 2020-10-20 | 우에무라 고교 가부시키가이샤 | Gold plating method and plating film |
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