WO2011013949A2 - Système et procédé d'arrêt prématuré pour un turbo-décodeur à faible consommation de courant - Google Patents

Système et procédé d'arrêt prématuré pour un turbo-décodeur à faible consommation de courant Download PDF

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Publication number
WO2011013949A2
WO2011013949A2 PCT/KR2010/004841 KR2010004841W WO2011013949A2 WO 2011013949 A2 WO2011013949 A2 WO 2011013949A2 KR 2010004841 W KR2010004841 W KR 2010004841W WO 2011013949 A2 WO2011013949 A2 WO 2011013949A2
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component decoder
decoder
decoding
post
information
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PCT/KR2010/004841
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English (en)
Korean (ko)
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WO2011013949A3 (fr
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송봉섭
김재범
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(주)네스랩
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2975—Judging correct decoding, e.g. iteration stopping criteria

Definitions

  • the present invention relates to an early stop system and method of a low-power turbo decoder, and more particularly, to compare the hard decision output value of the information bits output from the constituent decoders of the turbo decoder, and to determine whether the iterative decoding of the turbo decoder is completed.
  • the present invention relates to an early stop system and method for a low-power turbo decoder that enables early stop of a turbo decoder in a component decoder unit with low computation and low memory requirements.
  • the turbo code is in the spotlight as the channel code of the next generation mobile communication systems such as HSDPA (High Speed Downlink Packet Access), WiBro (Wireless Broadband Internet) and IMT-2000. It is decoded by the decoder.
  • HSDPA High Speed Downlink Packet Access
  • WiBro Wireless Broadband Internet
  • IMT-2000 IMT-2000
  • the conventional turbo decoder consists of two first and second component decoders 10 and 20, an interleaver 15, a reverse interleaver 25 and a hard decision output device 30, respectively.
  • the first and second constituent decoders 10 and 20 are decoded by a maximum a posteriori (MAP) decoding algorithm.
  • MAP maximum a posteriori
  • an external output LLR Log Likelihood Ratio
  • the interleaver 15 is interleaved and input to the second component decoder 20, which is an external output LLR of the second component decoder 20.
  • the reverse interleaver is reversed through the reverse interleaver 25 and fed back to the first component decoder 10 to perform one iterative decoding.
  • the conventional turbo decoder has excellent performance, the decoding delay is long due to the repeated decoding, and there are many problems in power consumption.
  • Algorithms include Cross Entropy (CE), Sign Change Ration (SCR), and Hard Decision Aided (HDA).
  • the CE early stop method stops the decoding repetition when it calculates the cross entropy (CE) as the Log Likelihood Ratio (LLR) value of the internal decoders constituting the entire turbo decoder for each iteration. do.
  • CE cross entropy
  • LLR Log Likelihood Ratio
  • the SCR early stop method accumulates the number of changed codes between the immediately preceding external information and the current external information for each repeated decoding and stops the decoding repetition when it is smaller than the threshold value.
  • the SCR early stop method is an external output (LLR) of the second component decoder 20 in the i-th and (i-1) -th decoding processes.
  • LLR external output
  • C (i) ⁇ (0.005 ⁇ 0.03) N is satisfied and the code change amount of C (i) is satisfied, iterative decoding is stopped and the decoding bit is hard-determined. It requires an integer operation and an integer memory of (N + 2).
  • the HDA early stop method compares the hard decision code of the previous iterative decoding output with the hard decision code of the current output and stops the decoding repetition when the codes for the entire frames match.
  • the HDA early stop method is a Posteriori of the second component decoder 20 in the i-th and (i-1) -th decoding processes.
  • the turbo decoder stops iterative decoding and hard-determines the decoding bits.
  • N bit operations and N size bit memories are required.
  • CE interchange entropy
  • SCR signal change rate
  • the HDA (hard board information) early stop method can obtain the stop criteria with much lower complexity and less memory requirements than the CE (cross-entropy) and SCR (sign change rate) early stop methods, but performance degradation occurs. There is a problem.
  • the present invention has been made to solve the above problems, and an object thereof is to compare the hard decision output values of the information bits output from the component decoders of the turbo decoder, and to determine whether to repeat the decoding of the turbo decoder, and then to decode the information bits.
  • the present invention provides an early stop system and method for a low power turbo decoder that can reduce the decoding delay and power consumption of a turbo decoder by prematurely stopping the iterative decoding process when it is determined that no more iterative decoding is necessary.
  • the early stop system of the low-power turbo decoder for achieving the above object, the first component decoder 110 to perform decoding of the information bits (u) and the first coded bits received through the channel );
  • An interleaver for interleaving interleaving the output signal of the first component decoder (110);
  • a second component decoder (120) for performing decoding of the second coded bit received through the interleaved signal and the channel through the interleaver (115);
  • Post information of the first component decoder 110 1 storage unit 123 for storing the code from the; Post information of the second component decoder 120 ( A second storage unit 125 for storing a code from N s; Post-output of the first component decoder 110 stored in the first storage unit 123 ( ) And post-output of the second component decoder 120 stored in the second storage unit 125.
  • a code comparator 130 for comparing the amount of code change (SDR) between the two sides; And a post output of the first component decoder 110 ( ) And post-output of the second component decoder 120 ( Code change between If 0) is 0, repeated decoding is stopped, and the post-output (1) of the first component decoder 110 through the hard decision output unit 150 ( ) And a control unit 140 to decode the information bits.
  • the external information (from the output signal of the second component decoder 120) ) Further includes a reverse interleaver 121 for extracting the reverse interleaved and feeding back the deinterleaved signal to the first component decoder 110.
  • control unit 140 is a post-output of the first component decoder 110 ( ) And post-output of the second component decoder 120 ( Code change between If 0) is 0, repeated decoding is stopped, and the post-output (2) of the second component decoder 120 through the hard decision output unit 150 ) Hardly decodes the information bits.
  • the early stop method of the low-power turbo decoder (A) the first component decoder 110 of the turbo decoder information bits received through the channel and the first encoding Performing bit decoding (S210); (B) post information of the first component decoder 110 ( Storing the code from the first storage unit 123 (S220); (C) After the code comparator 130 of the first component decoder 110 stored in the first storage unit 123 ( And post information (2) of the second component decoder 120 stored in the second storage unit 125 through iterative decoding.
  • the control unit 140 changes the code change amount ( Calculating (S230); And (D) the controller 140 displays post-mortem information of the first component decoder 110 ( ) And post information of the second component decoder 120 ( Code change between ) Determines whether the code change amount ( If 0) is 0, the process ends the decoding (S240).
  • the controller 140 controls the external information (1) of the first component decoder 110.
  • the second component decoder 120 performing decoding of the interleaved signal input through the step (E) and the second coded bit received through the channel (S260);
  • G) Post information of the second component decoder 120 Storing the code from the second storage unit 125 (S270);
  • the code comparator 130 stores the second component decoder 120 stored in the second storage unit 125, And post information (1) of the first component decoder 110 stored in the first storage unit 123 through iterative decoding.
  • the control unit 140 changes the code change amount ( Calculating (S280); And (G) the controller 140 controls the post-information of the second component decoder 120 ( ) And post information of the first component decoder 110 ( Code change between ) Is determined to be 0, and the code change amount ( If 0) is 0, the process ends the decoding (S290).
  • the control unit 140 determines whether or not the predetermined maximum number of repeated decoding has been reached (S300); And (I) ending the decoding if the preset maximum number of repeated decoding is reached, and if the maximum number of repeated decoding has not been reached, external information of the second component decoder 120 ( (S310) to perform the step (A) after deinterleaving a) and feeding back the deinterleaved signal to the first component decoder 110.
  • the decoding of the information bits Is terminated and the repetitive decoding process is stopped early when it is determined that no more repeated decoding is necessary, thereby reducing the power consumption and reducing the bit error rate (BER: Bit) by reducing the average number of repeated decoding and the decoding delay of the turbo decoder. Error Rate) can be improved.
  • BER bit error rate
  • 1 is a view showing the configuration of a conventional turbo decoder.
  • Figure 2 is a block diagram showing an early stop system of a low power turbo decoder according to an aspect of the present invention.
  • Figure 3 is a flow chart showing a method for early stopping of the low power turbo decoder according to another aspect of the present invention.
  • BER bit error rate
  • BER bit error rate
  • N 5114.
  • FIG. 2 is a block diagram showing an early stop system of a low power turbo decoder according to an embodiment of the present invention.
  • an early stop system of a low power turbo decoder includes a first component decoder 110, an interleaver 115, a second component decoder 120, and an inverse interleaver 121. ), A first storage unit 123, a second storage unit 125, a code comparator 130, a control unit 140, and a hard decision outputter 150.
  • the first component decoder 110 decodes the information bit u received through the channel and the first coded bit received through the channel, and outputs the decoded result.
  • the interleaver 115 performs an interleaving process to make a burst error existing in the output signal of the first component decoder 110 into a random error and outputs the interleaved signal.
  • the second component decoder 120 decodes the signal interleaved through the interleaver 115 and the second coded bit received through the channel and outputs the decoded result.
  • the signal fed back through the second component decoder 120 and the inverse interleaver 121 is transmitted to the post information (the first component decoder 110). This iterative decoding continues until the user achieves the desired performance.
  • the first storage unit 123 is the post information of the first component decoder 110 ( Stores the sign from
  • the second storage unit 125 is the post-information of the second component decoder 120 ( The sign from) is stored.
  • the code comparator 130 is a post-output (1) of the first component decoder 110 stored in the first storage unit 123 ( ) And post-output of the second component decoder 120 stored in the second storage unit 125. Sign difference ratio (SDR) is compared.
  • Equation 2 the early stop criterion of the code change amount SDR is expressed by Equation 2 below.
  • FIG. 3 is a flowchart illustrating an early stop method of a low power turbo decoder through an early stop system of a low power turbo decoder according to the present invention.
  • the first component decoder 110 of the turbo decoder decodes the information bits and the first coded bits received through the channel (S210).
  • the code comparator 130 is the post-information of the first component decoder 110 stored in the first storage unit 123 ( And post information (2) of the second component decoder 120 stored in the second storage unit 125 through iterative decoding. ), And the controller 140 is a code change amount SDR. To calculate (S230).
  • SDR Sign change
  • SDR code change amount
  • step S240 the code change amount (SDR) ( ) Is not 0, the controller 140 controls the external information (1) of the first component decoder 110. ) And the interleaved signal is input to the second component decoder 120 (S250).
  • the second component decoder 120 decodes the interleaved signal input through the step S250 and the second coded bit received through the channel (S260).
  • the post information of the second component decoder 120 ( The code from) is stored in the second storage unit 125 (S270).
  • the code comparator 130 may store post-information information of the second component decoder 120 stored in the second storage unit 125. And post information (1) of the first component decoder 110 stored in the first storage unit 123 through iterative decoding. ), The controller 140 controls the code change amount SDR ( ) Is calculated (S280).
  • the controller 140 controls the post-information of the second component decoder 120 ( ) And post information of the first component decoder 110 ( It is determined whether or not the code change amount SDR () between 0 is 0, and the code change amount SDR ( If 0) is 0, the decoding ends (S290).
  • step S290 the code change amount (SDR) ( If) is not 0, the controller 140 determines whether or not the predetermined maximum number of repeated decodings has been reached (S300).
  • the decoding is terminated. If the maximum number of repeated decoding has not been reached, the external information of the second component decoder 120 ( ) And after interleaving the feedback signal to the first component decoder 110, the step S210 is performed (S310).
  • the early stop is performed in each of the first component decoder and the second component decoder unit, thereby preventing the decoding process of the second component decoder from being performed unnecessarily. . That is, while reducing the average number of times of repeated decoding of the turbo decoder, the power consumption of the turbo decoder is reduced.
  • the early stop method of the low power turbo decoder according to the present invention was applied to a WCDMA turbo decoder, and the low power efficiency was evaluated by analyzing bit error rate (BER) performance and average iteration decoding.
  • BER bit error rate
  • the simulation environment of the experiment computer uses BPSK (Binary Phase Shift Key) modulation method on AWGN (Additive White Gaussion Noise) channel, and the maximum number of iteration decoding of turbo decoder is set to 8, and CE (The cross entropy stop criterion was set to T (i) ⁇ 10 -2 T (1), and the SCR (signal change rate) stop criterion was set to C (i) ⁇ 0.03N.
  • BPSK Binary Phase Shift Key
  • AWGN Additional White Gaussion Noise
  • the conventional CE, SCR, and HDA early stop methods have about 0.9 times more average repeat decoding times than the GENIE mode, whereas the early stop method according to the present invention has a GENIE mode. It can be seen that the average number of times of repeated decoding is about 0.2 times as compared to.
  • the early stop method according to the present invention has the lowest average repetition decoding times without deterioration of performance as compared to the conventional CE, SCR, and HDA early stop methods, and thus has the highest low power efficiency without deterioration of performance.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

La présente invention concerne un système et un procédé d'arrêt prématuré pour un turbo-décodeur à faible consommation de courant. Le système compare des valeurs de sortie à décision douce de bits d'information produits par des décodeurs de composantes du turbo-décodeur pour déterminer si un processus de décodage itératif du turbo-décodeur est terminé, et il arrête prématurément le processus de décodage itératif s'il est établi que ce processus de décodage itératif n'est plus nécessaire puisque le décodage des bits d'information est terminé, ce qui permet de réduire un nombre moyen de processus de décodage itératif du turbo-décodeur et, par conséquent, de réduire la consommation de courant et d'améliorer le taux d'erreurs sur les bits (BER).
PCT/KR2010/004841 2009-07-28 2010-07-23 Système et procédé d'arrêt prématuré pour un turbo-décodeur à faible consommation de courant WO2011013949A2 (fr)

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Cited By (2)

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CN105187073A (zh) * 2015-10-13 2015-12-23 东南大学 一种极化码的bp译码方法及装置
CN115579013A (zh) * 2022-12-09 2023-01-06 深圳市锦锐科技股份有限公司 一种新型低功耗音频解码器

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KR20070079923A (ko) * 2006-02-03 2007-08-08 한국전자통신연구원 가변 이득계수를 이용한 저복잡도 및 저전력 터보 복호기

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US20030066018A1 (en) * 2000-12-23 2003-04-03 Samsung Electronics Co., Ltd. Apparatus and method for stopping iterative decoding in a CDMA mobile communication system
US20030023920A1 (en) * 2001-07-26 2003-01-30 Gibong Jeong Method and apparatus for reducing the average number of iterations in iterative decoding
US20040225941A1 (en) * 2003-02-03 2004-11-11 Nortel Networks Limited. Method of controlling the number of iterations of an iterative decoding process and device for the implementation of the method
EP1499025A1 (fr) * 2003-07-17 2005-01-19 Evolium S.A.S. Critère d'arrêt pour une méthode de traitement de données iterative
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105187073A (zh) * 2015-10-13 2015-12-23 东南大学 一种极化码的bp译码方法及装置
CN105187073B (zh) * 2015-10-13 2018-07-27 东南大学 一种极化码的bp译码方法及装置
CN115579013A (zh) * 2022-12-09 2023-01-06 深圳市锦锐科技股份有限公司 一种新型低功耗音频解码器
CN115579013B (zh) * 2022-12-09 2023-03-10 深圳市锦锐科技股份有限公司 一种低功耗音频解码器

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KR20110011223A (ko) 2011-02-08

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