WO2011004535A1

WO2011004535A1 - Field-effect transistor

Info

Publication number: WO2011004535A1
Application number: PCT/JP2010/003337
Authority: WO
Inventors: 安藤裕二; 中山達峰; 岡本康宏; 大田一樹; 井上隆
Original assignee: 日本電気株式会社
Priority date: 2009-07-07
Filing date: 2010-05-18
Publication date: 2011-01-13
Also published as: JPWO2011004535A1; JP5462261B2

Abstract

A field-effect transistor is provided with a multilayer body formed by stacking a first nitride semiconductor layer (13) comprised of a first nitride semiconductor, and a second nitride semiconductor layer (15) comprised of a second nitride semiconductor having a band gap larger than the first nitride semiconductor; a gate insulating film (16); a gate electrode (18); a drain electrode (172); and a source electrode (171); such that on a sandwiched region between the gate electrode (18) and the drain electrode (172) of the second nitride semiconductor layer (15), a striped pattern is formed by alternately arranging an n-type impurity doped region (151) into which an n-type impurity has been doped and a p-type impurity doped region (152) into which a p-type impurity has been doped along a direction in which the gate electrode (18) extends.

Description

Field effect transistor

The present invention relates to a field effect transistor.

An example of a field effect transistor (Field Effect Transistor: FET) containing a group III nitride semiconductor as a main material is shown in FIG. FIG. 12 is a schematic diagram showing a cross-sectional structure of a field effect transistor. A field effect transistor having such a structure is reported in Non-Patent Document 1, for example.

The field effect transistor shown in FIG. 12 has a buffer layer 101, a channel layer 103 made of undoped GaN (gallium nitride), and an electron supply made of n-type AlGaN (aluminum gallium nitride) on a SiC (silicon carbide) substrate 100. The layer 105 is laminated. The crystal growth direction with respect to the substrate surface is parallel to [0001]. An n-type conduction region 104 made of a two-dimensional electron gas (hereinafter referred to as “2DEG”) is formed in the channel layer 103 near the interface with the electron supply layer 105.

In addition, a source electrode 1071 and a drain electrode 1072 are formed on the electron supply layer 105 and are in ohmic contact with the n-type conduction region 104. Further, a gate electrode 108 is formed on the electron supply layer 105 via an insulating film 106 made of Si ₃ N ₄ (silicon nitride).

In addition, Patent Documents 1 and 2 disclose GaN field effect transistors employing a RESURF structure.

JP 2007-134608 A JP 2008-159631 A

FIG. 14 is a schematic diagram of the charge density, electric field strength, and potential distribution when the channel is pinched off and the breakdown voltage (V _d = BV) is applied to the drain in the field effect transistor shown in FIG. 14A shows the charge density distribution, FIG. 14B shows the electric field intensity distribution, and FIG. 14C shows the potential distribution.

Here, when the channel is pinched off and a breakdown voltage (V _d = BV) is applied to the drain in the field effect transistor shown in FIG. 12, the electron supply layer (AlGaN layer) 105 has a depletion layer 200 as shown in FIG. (Shaded area) occurs. A fixed charge due to ionization of the n-type impurity is generated between the gate electrode 108 end (x = 0) and the depletion layer end (x = L). When the gate width is W _g , the doping concentration to the electron supply layer (AlGaN layer) 105 is N _d , and the thickness (depth) of the doping region is t, this fixed charge density is q × N _d × W _g × t. (Q = 1.6 × 10 ⁻¹⁹ C: elementary charge) (FIG. 14A).

The electric field strength in the depletion layer increases almost linearly from the depletion layer end (x = L) to the gate end (x = 0), and takes a maximum value at the gate end (x = 0) (FIG. 14B). ). In the case of the field effect transistor shown in FIG. 12, electric field concentration occurs in the vicinity of the gate end (x = 0) in this way. According to Gauss's law, the maximum electric field strength is (qN _d L) / ε (ε: dielectric constant of AlGaN). Therefore, the breakdown electric field strength F _c is expressed as the following formula (1).

Since the electric field integrated by the distance becomes the electric potential, the off breakdown voltage BV is expressed by the following equation (2), and the electric potential distribution is as shown in FIG.

Assuming that the ratio of the drain depletion layer resistance to the entire on resistance is sufficiently large, the product of the on resistance R _on and the cross-sectional area A of the depletion layer is expressed by the following equation (3).

Note that μ _n is the electron mobility. Next, when L and _Nd are eliminated from the equations (1), (2), and (3), the following equation (4) is obtained.

Here, FIG. 15 shows an off breakdown voltage BV when ε / ε ₀ = 10 (ε ₀ : vacuum dielectric constant), μ _n = 2000 cm ² / Vs, and F _c = 3 MV / cm in Equation (4). It shows the calculation results of the relationship between the on-resistance R _on. FIG. 15 shows that the on-resistance R _on increases in proportion to the square of the off breakdown voltage BV.

Field effect transistor has a high off-state breakdown voltage BV, the on-resistance R _on low characteristics are required. However, when the field effect transistor shown in FIG. 12, increasing the off-state breakdown voltage BV, in proportion to the square will increases the on-resistance R _on, both off-state breakdown voltage BV and the on-resistance R _on the required characteristics Is difficult to satisfy simultaneously.

Further, in the case of the RESURF structure as disclosed in Patent Documents 1 and 2, the electric field concentration can be reduced by stacking the n-type RESURF layer on the p-type channel layer. However, in the case of the RESURF structure disclosed in Patent Documents 1 and 2, since the influence of depletion of the n-type RESURF layer due to the influence of the surface potential is unavoidable, the impurity concentration of the RESURF layer and the film are considered in consideration of this effect. The thickness must be designed. Further, since the surface potential depends on the formation conditions of the protective film, there has been a problem that the electric field concentration relaxation effect varies depending on the process factor.

Also, a so-called super junction structure is known for reducing electric field concentration. The super junction structure is a structure widely used in Si (silicon) -based vertical power devices, in which n-type pillar layers and p-type pillar layers are alternately formed in the horizontal direction. In order to form an n-type pillar layer and a p-type pillar layer having a depth of at least several μm, impurity ions are doped with acceleration energy of several MeV. However, when this process is applied to a nitride semiconductor material, since the nitride semiconductor has a very high melting point and it is difficult to recover lattice defects, an annealing process at about 2000 ° C. exceeding the crystal growth temperature is required. That is, it is not practical to apply the vertical super junction structure as described above to a nitride semiconductor device.

An object of the present invention is to provide a field effect transistor made of a nitride semiconductor that solves the above-described problems and improves the trade-off between on-resistance and off-breakdown voltage.

According to the present invention, a first nitride semiconductor layer made of a first nitride semiconductor, and a second nitride semiconductor layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor, A stacked body in which the first nitride semiconductor layer is electrically connected to the stacked body, and the gate insulating film and the gate electrode formed on the stacked body are opposed to the gate electrode. A drain electrode provided on the stacked body, and a source electrode electrically connected to the first nitride semiconductor layer and provided on the opposite side of the drain electrode across the gate electrode. The region of the second nitride semiconductor layer sandwiched between the gate electrode and the drain electrode is doped with an n-type impurity doped with an n-type impurity and doped with a p-type impurity. FET stripes arranged alternately along the band, a direction extending said gate electrode is formed is provided.

The field effect transistor realized by the present invention includes an n-type impurity doped region and a p-type impurity doped region formed in the second nitride semiconductor layer, and / or the first nitride semiconductor layer and the second nitride semiconductor layer. In the vicinity of the interface between the first nitride semiconductor layer and the second nitride semiconductor layer, an n-type conduction region containing 2DEG and a two-dimensional hole gas ( Hereinafter, a p-type conductive region including “2DHG”) is formed. Specifically, an n-type conductive region is formed near the interface with the n-type impurity doped region of the second nitride semiconductor layer, and a p-type conductive region is formed near the interface with the p-type impurity doped region. .

In the OFF state in which the gate electrode is set to 0 (zero) potential and a high voltage is applied to the drain electrode, the entire n-type conduction region and p-type conduction region are depleted, resulting from ionization of the n-type impurity and the p-type impurity. In the case of this embodiment, the n-type conduction region and the p-type conduction region are formed in a striped pattern in the region sandwiched between the gate electrode and the drain electrode, so that the space charge cancels out. It will meet. For this reason, in the region sandwiched between the gate electrode and the drain electrode, the electric field strength is substantially constant, and the electric field concentration is alleviated.

According to the present invention, a field effect transistor made of a nitride semiconductor having a high off breakdown voltage and a low on resistance can be obtained, and a high breakdown voltage and low loss of a nitrogen-based power semiconductor can be realized.

1 is a structural diagram of a field effect transistor according to Embodiment 1. FIG. 1 is a structural diagram of a field effect transistor according to Embodiment 1. FIG. It is an energy band figure of a field effect transistor. FIG. 6 is a correlation diagram between on-resistance and off-breakdown voltage. It is a distribution map of charge density, electric field strength, and potential. 6 is a structural diagram of a field effect transistor according to Embodiment 2. FIG. It is an energy band figure of a field effect transistor. 6 is a structural diagram of a field effect transistor according to Embodiment 3. FIG. 6 is a structural diagram of a field effect transistor according to Embodiment 4. FIG. 6 is a structural diagram of a field effect transistor according to Embodiment 5. FIG. 6 is a structural diagram of a field effect transistor according to Embodiment 5. FIG. It is a structural diagram of a field effect transistor. It is a structural diagram of a field effect transistor. It is a distribution map of charge density, electric field strength, and potential. FIG. 6 is a correlation diagram between on-resistance and off-breakdown voltage.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
<< Embodiment 1 >>
<Configuration of Field Effect Transistor of Embodiment 1>

FIG. 1 shows the configuration of the field effect transistor of this embodiment. 1A is a schematic plan view, FIG. 1B is a schematic cross-sectional view taken along the plane (X1-Y1) of FIG. 1A, and FIG. 1C is a schematic view of (X2-Y2) of FIG. It is the cross-sectional schematic in a surface.

As shown in FIGS. 1B and 1C, the field effect transistor of the present embodiment includes a first nitride semiconductor layer 13 made of a first nitride semiconductor and a first nitride semiconductor layer 13 on the substrate 10.

Laminated bodies

13 and 15 each including a second nitride semiconductor layer 15 made of a second nitride semiconductor having a band gap larger than that of the nitride semiconductor are provided.

In the present embodiment, the vertical relationship between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15 is not particularly limited, but for example, on the first nitride semiconductor layer 13 as shown in the figure. A second nitride semiconductor layer 15 may be provided. The

stacked bodies

13 and 15 may be epitaxial layers, and the crystal growth may be parallel to the [0001] direction. Furthermore, a buffer layer 11 of (0001) plane growth that lattice-matches with the first nitride semiconductor may be provided on the outermost surface between the

stacked bodies

13 and 15 and the substrate 10.

As the substrate 10, a silicon (Si) substrate, a SiC substrate, an Al ₂ O ₃ (sapphire) substrate, a GaN substrate, or the like can be used. As the first nitride semiconductor, one of GaN, InGaN (indium gallium nitride), AlGaN, InAlN (indium aluminum nitride), InAlGaN (indium aluminum gallium nitride), InN (indium nitride), and the like is selected. be able to. As the second nitride semiconductor, a nitride having a larger band gap than the nitride semiconductor selected as the first nitride semiconductor from AlGaN, InGaN, InAlN, InAlGaN, GaN, AlN (aluminum nitride), etc. A semiconductor can be selected. For example, GaN can be selected as the first nitride semiconductor, and AlGaN can be selected as the second nitride semiconductor.

In addition, as shown in FIGS. 1B and 1C, the field effect transistor of the present embodiment has a gate insulating film 16 and a gate electrode 18 and a first nitride semiconductor layer 13 on the

stacked bodies

13 and 15. A drain electrode 172 electrically connected to the gate electrode 18 and a source electrode 171 electrically connected to the first nitride semiconductor layer 13 and provided on the opposite side of the drain electrode 172 across the gate electrode 18; Is provided. The electrical coupling between the first nitride semiconductor layer 13 and the drain electrode 172 and the electrical coupling between the first nitride semiconductor layer 13 and the source electrode 173 are preferably in ohmic contact.

The gate electrode 18 can be formed using a material such as Ti (titanium) / Pt (platinum) / Au (gold), Ni (nickel) / Au, or Pd (palladium) / Au. The drain electrode 172 and the source electrode 171 are made of a material such as Ti / Al (aluminum) / Ni / Au, Ti / Al / Mo (molybdenum) / Au, or Ti / Al / Nb (niobium) / Au. Can be formed. The gate insulating film 16 can be formed using a material such as Al ₂ O ₃ , Si ₃ N ₄ , or SiO ₂ (silicon oxide).

The gate electrode 18 is preferably formed on the recess. When formed in this way, a normally-off operation is possible. However, a planar structure that does not form a recess is also possible. In order to enable a normally-off operation in the planar structure, the concentration of the activated impurity in the first nitride semiconductor layer 13 may be a p-type of 1 × 10 ¹⁷ cm ⁻³ . Alternatively, the portion of the second nitride semiconductor layer 15 that contacts the gate electrode 18 may be the p-type impurity doped region 152.

In the field effect transistor of this embodiment, as shown in FIG. 1A, the region sandwiched between the gate electrode 18 and the drain electrode 172 of the second nitride semiconductor layer 15 is doped with an n-type impurity. Striped patterns are formed in which n-type impurity doped regions 151 and p-type impurity doped regions 152 doped with p-type impurities are alternately arranged along the direction in which the gate electrode 18 extends.

In the second nitride semiconductor layer 15, an n-type impurity doped region 151 and / or a p-type impurity doped region 152 extending from immediately below the source electrode 171 to immediately below the drain electrode 172 are formed. FIG. 1 shows, as an example, an n-type impurity doped region 151 that extends from directly below the source electrode 171 to immediately below the drain electrode 172 (see FIG. 1B).

As the n-type impurity, for example, Si can be selected. As the p-type impurity, for example, Mg (magnesium), Be (beryllium), H (hydrogen), or the like can be selected.

Here, in the case of the field effect transistor of the present embodiment configured as described above, in the vicinity of the interface between the first nitride semiconductor layer 13 and the n-type impurity doped region 151 of the second nitride semiconductor layer 15, An n-type conductive region 141 containing 2DEG is formed in a column shape. On the other hand, in the vicinity of the interface between the first nitride semiconductor layer 13 and the p-type impurity doped region 152 of the second nitride semiconductor layer 15, a p-type conductive region 142 containing 2DHG is formed in a column shape. Hereinafter, this principle will be described with reference to FIG.

3, the field-effect transistor of the present embodiment, when the drain electrode 172 and source electrode 171 was set to equal voltage (V _{ds = 0),} the gate - shows the channel near the drain potential profile. FIG. 3A shows the profile of the (X1-Y1) plane, and FIG. 3B shows the profile of the (X2-Y2) plane.

When a second nitride semiconductor layer (eg, AlGaN layer) 15 is grown on the (0001) plane first nitride semiconductor layer (eg, GaN layer) 13, tensile strain is applied to the second nitride semiconductor layer 15. Works and piezo polarization occurs. Furthermore, since spontaneous polarization also occurs, a positive charge having a surface density (σ _p ) is generated at the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15. Here, σ _p is a function of the Al composition x of the second nitride semiconductor layer 15 and can be approximated by the following equation (5).

N-type impurity concentration N _d , activation rate η _d , n-type impurity doped region thickness (depth) t _d , p-type impurity concentration N _a , activation rate η _{a of} second nitride semiconductor layer 15 when satisfying the thickness of the p-type impurity doped region (depth) t _a, but the following expression (6), the sum of the fixed charge of the second nitride semiconductor layer 15 is positive.

The surface density N _n of the positive fixed charge at this time is expressed by the following formula (7).

In the case of the present embodiment, the n-type impurity doped region 151 of the second nitride semiconductor layer 15 is formed as an electron supply layer because the configuration is such that the formula (6) is satisfied between the gate and drain on the (X1-Y1) plane. In the vicinity of the interface between the first nitride semiconductor layer 13 and the n-type impurity doped region 151 of the second nitride semiconductor layer 15, an n-type conductive region 141 containing 2DEG is formed (see FIG. 3 (a)).

On the other hand, concentration N _d , activation rate η _d , thickness (depth) t _{d of} n-type impurity doped region, p-type impurity concentration N _a , activation rate η _a , thickness of p-type impurity doped region ( depth) t a _case, but satisfying the formula (8), the sum of the fixed charge of the second nitride semiconductor layer 15 is negative.

Surface density N _p of the negative fixed charge at this time is represented by the following formula (9).

In the present embodiment, since the gate-drain of the (X2-Y2) plane is configured to satisfy the formula (8), the p-type impurity doped region 152 of the second nitride semiconductor layer 15 supplies holes. A p-type conductive region 142 containing 2DHG is formed in the vicinity of the interface between the first nitride semiconductor layer 13 and the p-type impurity doped region 152 of the second nitride semiconductor layer 15. FIG. 3 (b)).

Based on the principle described above, an n-type conductive region 141 containing 2DEG is formed in a column shape in the vicinity of the interface between the first nitride semiconductor layer 13 and the n-type impurity doped region 151 of the second nitride semiconductor layer 15. In the vicinity of the interface between the first nitride semiconductor layer 13 and the p-type impurity doped region 152 of the second nitride semiconductor layer 15, a p-type conductive region 142 containing 2DHG is formed in a column shape.

In the case of the configuration shown in FIG. 1, the electron transit layer formed by the n-type conduction region 141 is spatially isolated from the n-type impurity doped region 151 of the second nitride semiconductor layer 15. Impurity scattering is suppressed and the mobility of 2DEG is improved. Further, when the heterointerface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15 is configured to be flat at the atomic level, interface scattering is suppressed, and the mobility of 2DEG is further improved. In such a case, an electron mobility of about 1500 to 2000 cm ² / Vs can be realized.

Next, as shown in FIG. 1A, an n-type impurity doped region 151 and a p-type impurity doped region are formed in a region sandwiched between the gate electrode 18 and the drain electrode 172 except just below the gate electrode 18 and the drain electrode 172. The effect of forming the stripe pattern in which the regions 152 are alternately arranged will be described with reference to FIG.

FIG. 5 shows the center line of the n-type conductive region 141 when a breakdown voltage (V _d = BV) is applied to the drain electrode 172 by pinching off the channel in the field effect transistor of this embodiment (X1-Y1 in FIG. 1). It is a schematic diagram of a charge density, electric field strength, and potential distribution along (direction). 5A shows the charge density distribution, FIG. 5B shows the electric field distribution, and FIG. 5C shows the potential distribution.

When the channel is pinched off and a breakdown voltage (V _d = BV) is applied to the drain electrode 172 in the field effect transistor of this embodiment, the depletion layer 20 (oblique line) is formed in the second nitride semiconductor layer 15 as shown in FIG. Area) occurs. Then, a fixed charge is generated due to ionization of the n-type impurity and the p-type impurity.

Here, if the width of the n-type impurity doped region 151 of the second nitride semiconductor layer 15 is W _n and the surface density of the fixed charge is qN _n , the unit in the n-type impurity doped region 151 of the second nitride semiconductor layer 15 is The fixed charge density per length is represented by q × N _n × W _n (FIG. 5A).

Further, when the width of the p-type impurity doped region 152 of the second nitride semiconductor layer 15 is W _p and the surface density of the fixed charge is −qN _p , the unit in the p-type impurity doped region 152 of the second nitride semiconductor layer 15 is The fixed charge density per length is represented by −q × N _p × W _p (FIG. 5A).

The field effect transistor of the present embodiment sets the _{_{_{N n, N p, W n}}} , W p so as to satisfy the following equation (10).

That is, the surface density n _d1 of the n-type activation impurity in the n-type impurity doped region 151, the surface density n _a1 of the p-type activation impurity in the n-type impurity doped region 151, and the width W _{n of the n-type} impurity doped region 151. The surface density n _a2 of the p-type activation impurity in the p-type impurity doped region 152, the surface density n _d2 of the n-type activation impurity in the p-type impurity doped region 152, and the width W _{p of the p-type} impurity doped region 152. The surface density σ _{p of the} polarization charge formed at the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15, and the elementary charge q (= 1.6 × 10 ⁻¹⁹ C). Is set so as to satisfy the relational expression of | n _d1 −n _a1 + σ _p / q | × W _n = | −n _d2 + n _a2 −σ _p / q | × W _p .

In such a configuration, since the average charge in the second nitride semiconductor layer 15 is 0 (zero), as shown in FIG. 5B, at the gate electrode side end (x = 0) of the depletion layer. The electric field concentration between the gate electrode side end (x = 0) and the depletion layer end (x = L) of the depletion layer becomes substantially constant (F = F _c ). As a result, the off breakdown voltage is improved.

It should be noted that the field effect transistor of the present embodiment desirably satisfies Equation (10), but can be configured within the range satisfying Equation (11) below.

That is, the surface density n _d1 of the n-type activation impurity in the n-type impurity doped region 151, the surface density n _a1 of the p-type activation impurity in the n-type impurity doped region 151, and the width W _{n of the n-type} impurity doped region 151. The surface density n _a2 of the p-type activation impurity in the p-type impurity doped region 152, the surface density n _d2 of the n-type activation impurity in the p-type impurity doped region 152, and the width W _{p of the p-type} impurity doped region 152. The surface density σ _{p of the} polarization charge formed at the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15, and the elementary charge q (= 1.6 × 10 ⁻¹⁹ C). Is set so as to satisfy the relational expression 0.1 <(| n _d1 −n _a1 + σ _p / q | × W _n ) / (| −n _d2 + n _a2 −σ _p / q | × W _p ) <10 It is also possible to do.

Also in the case where it is configured within the range satisfying the expression (11), the same effect as the above-described effect obtained when the structure is satisfied so as to satisfy the expression (10) can be obtained.

Here, in actuality, a surface depletion layer is formed due to the influence of the surface potential, but the fixed charge in the surface depletion layer portion is compensated by the charge of the surface trap. it is necessary to subtract the surface depletion from _{n n} and _{n p} in).

However, in the present embodiment, as shown in FIG. 1A, the n-type impurity doped regions 151 and the p-type impurity doped regions 152 are alternately arranged along the direction in which the gate electrode 18 extends. The influence of the depletion layer acts equally on both the n-type impurity doped region 151 and the p-type impurity doped region 152. For this reason, it is not necessary to consider the influence of the surface depletion layer in the equation (10), and there is an advantage that the epi-design is facilitated. This is a feature that does not exist in the RESURF structure in which the p-type layer and the n-type layer are stacked in the vertical direction.

Next, a description will be given of the relationship on-resistance of the field-effect transistor R _on and off-state breakdown voltage BV of the present embodiment.

First, since the the integral of the electric field in the distance is the potential, when electric field strength F = F _c as shown in FIG. 5 (b), off-breakdown voltage BV is expressed by the following equation (12) (FIG. 5 (c)).

Assuming that the ratio of the depletion layer resistance to the entire on-resistance is sufficiently large, the product of the on-resistance R _on and the cross-sectional area A of the depletion layer is expressed by the following equation (13). Here, t is the channel thickness and μ _n is the electron mobility.

Then, the following equation (14) is obtained from the equations (12) and (13).

Here, FIG. 4 shows the calculated on-relationship of the resistance R _on and off-state breakdown voltage BV using equation (14) by a solid line. It was assumed that W _n = W _p , μ _n = 2000 cm ² / Vs, F _c = 3 MV / cm, N _n / t = 5 × 10 ¹⁷ cm ⁻³ . FIG. 4 also shows the calculation result (dotted line in the figure) of the horizontal field effect transistor as shown in FIG. This is the same as the relationship between the resistance R _on and off-state breakdown voltage BV shown in FIG. 15.

In the case of the lateral field effect transistor as shown in FIG. 12, the on-resistance R _on is proportional to the square of the off breakdown voltage BV, whereas in the case of the field effect transistor of this embodiment, the on resistance R _on is the off breakdown voltage. Proportional to BV. That is, in the field effect transistor of this embodiment, the on-resistance Ron has a gentle dependence _on the off-breakdown voltage BV. As a result, the field effect transistor of this embodiment can reduce the increase in the on-resistance R _on even when the off-breakdown voltage BV is increased, as compared with the lateral field-effect transistor as shown in FIG. Can do. In other words, towards the field effect transistor of the present embodiment, as compared with the lateral field effect transistor as shown in FIG. 12, also reduces the on-resistance R _on, to reduce the off-state breakdown voltage BV is to reduce be able to. In addition, as shown in FIG. 4, when the off breakdown voltage BV is set higher, the field effect transistor of this embodiment has a lower on-resistance R _on than the lateral field effect transistor as shown in FIG. Can do. For example, if you set the off-state breakdown voltage BV and 1.0 × 10 ⁴ V, the on-resistance _{R on} of the field effect transistor of this embodiment, the on-resistance _{R on} of the lateral field effect transistor as shown in FIG. 12, It becomes about 1/200 times.

FIG. 4 also shows a calculation result (broken line in the figure) when a vertical device structure having a super junction is applied to a GaN-based semiconductor material. This was assumed to be W _n = W _p , μ _n = 200 cm ² / Vs, F _c = 3 MV / cm, N _n / t = 5 × 10 ¹⁷ cm ⁻³ . Here, in the vertical device structure having a super junction, the electron mobility μ _n is lower than that in the field effect transistor of this embodiment. In the vertical device structure having a super junction, electrons are bulky. This is because the semiconductor travels due to the influence of ionized impurity scattering. From FIG. 4, in the case of the same off-breakdown voltage BV, the on-resistance R _on of the field effect transistor of the present embodiment is about 1/10 smaller than the on-resistance R _on of the vertical device structure having a super junction. I understand.

Here, as shown in FIGS. 1B and 1C, the field effect transistor of the present embodiment is on the

stacked bodies

13 and 15 on the opposite side of the gate electrode 18 with the source electrode 171 interposed therebetween. A fourth electrode 19 can be provided. A third nitride semiconductor made of a third nitride semiconductor doped with a p-type or n-type impurity at a position below the

stacked bodies

13 and 15 and in contact with the

stacked bodies

13 and 15. A layer 12 can be provided.

Then, the p-type or n-type 1-type impurity doped region constituting the stripe region of the second nitride semiconductor layer 15 does not extend to just below the source electrode 171, but directly below the fourth electrode 19. A 1-type impurity doped region doped with a 1-type impurity that is a n-type or an n-type may be formed. For example, as shown in FIGS. 1B and 1C, the p-type impurity doped region 152 constituting the stripe region of the second nitride semiconductor layer 15 does not extend to directly below the source electrode 171, and the fourth electrode A p-type impurity doped region 152 doped with a p-type impurity may be formed immediately below 19.

When configured as shown in FIGS. 1B and 1C, when the fourth electrode 19 is electrically grounded, for example, via the source electrode 171, holes generated by impact ionization are removed from the third nitride semiconductor. The layer 12 and the fourth electrode 19 can be extracted outside the device. As a result, the avalanche resistance of the device can be improved. The fourth electrode 19 is formed using a material such as Ti (titanium) / Pt (platinum) / Au (gold), Ni (nickel) / Au, or Pd (palladium) / Au. be able to.

As described above, when the channel is turned on by applying a positive voltage to the gate electrode 18 from the state shown in FIG. 1B, the field effect transistor of the present embodiment has the drain electrode 172 and the n-type conduction region 141. A 2DEG channel connecting the source electrodes 171 is formed, and electrons travel. On the other hand, in the OFF state in which the gate electrode 18 is set to 0 (zero) potential and a high voltage is applied to the drain electrode 172, the entire n-type conduction region 141 and p-type conduction region 142 are depleted and the space charges cancel each other. For this reason, in the region sandwiched between the gate electrode 18 and the drain electrode 172, the electric field strength is substantially constant, and the electric field concentration is reduced. In addition, by grounding the fourth electrode 19 to the same potential as the source electrode 171, for example, holes generated by impact ionization can be extracted outside the device, and the avalanche resistance of the element can be improved.

In addition, the field effect transistor of this embodiment can also be made into the structure which reversed the n-type and p-type in the above-mentioned description.

In the above description, the second nitride semiconductor layer 15 is doped with impurities to form a stripe pattern. However, the field effect transistor according to the present embodiment includes the first nitride semiconductor layer 13 in the first nitride semiconductor layer 13. It is also possible to form a stripe pattern by doping impurities. In such a case, the carriers travel not in the heterointerface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15 but in the first nitride semiconductor layer 13, but the same effect as described above. Can be obtained.

These assumptions are the same for all of the following embodiments.
<Example of Field Effect Transistor of Embodiment 1>

Next, one implementation example of the field effect transistor of the present embodiment will be described.

First, the manufacturing method will be described. The following manufacturing method is an example of a manufacturing method for manufacturing an example of the field effect transistor of the present embodiment. That is, the field effect transistor of this embodiment is not limited to the one manufactured by the method described below. This assumption is the same in all the following embodiments.

First, the following layers (1) to (5) are sequentially formed on the Si substrate 10 in the following order, for example, by metal organic chemical vapor deposition (hereinafter referred to as “MOCVD”). Grow.

(1) Undoped AlN layer (buffer layer 11) ... 200 nm
(2) Undoped GaN layer (buffer layer 11) 1 μm
(3) p-type GaN layer “Mg doping: concentration 1 × 10 ¹⁹ cm ⁻³ ” (third nitride semiconductor layer 12) 100 nm
(4) Undoped GaN layer (first nitride semiconductor layer 13) ... 100 nm
(5) p-type Al _0.05 Ga _0.95 N layer “Mg doping: concentration 1 × 10 ¹⁹
cm ⁻³ ”(second nitride semiconductor layer 15) ... 60 nm

Here, the p-type Al _0.05 Ga _0.95 N layer “Mg doping: concentration 1 × 10 ¹⁹ cm ⁻³ ” (second nitride semiconductor layer 15) is thinner than the critical film thickness of dislocation generation, and is strained lattice It is a layer. From the viewpoint of obtaining good crystal quality, the Al composition is generally preferably 0 <x <0.4. In this example, x = 0.05, and the thickness of the p-type Al _0.05 Ga _0.95 N layer “Mg doping: concentration 1 × 10 ¹⁹ cm ⁻³ ” (second nitride semiconductor layer 15) is 200 nm. By making it below, it is within the critical film thickness of dislocation generation.

Next, a surface protective film (not shown) such as SiN is formed on the second nitride semiconductor layer 15 by using, for example, a plasma-enhanced chemical vapor deposition (hereinafter referred to as “PECVD”) method. And a surface protective film for preventing surface damage due to ion implantation is formed.

Next, ion implantation is performed on the dinitride semiconductor layer 15. For example, Si (n-type impurity) is doped in a state where a region other than a region to be doped with n-type impurity is covered with a resist film. The doping conditions are, for example, an acceleration energy of 60 kev, a dose of 6 × 10 ¹³ cm ⁻² , an average atomic concentration of 1 × 10 ¹⁹ cm ⁻³ , and a depth-wise expansion (t _d ) of 60 nm. A region (n-type impurity doped region 151) can be selectively formed in the second nitride semiconductor layer 15. Note that the width W _n of the region doped with n-type impurities and the width W _p of the region not doped with n-type impurities were set to W _n = W _p = 100 nm (arbitrary design matters). After ion implantation, activation annealing is performed at 1000 to 1200 ° C. in an N ₂ atmosphere, so that an Si activation rate of about 10% can be obtained. In the case of this example, since the depth of ion implantation is as shallow as about 100 nm or less, the activation annealing temperature can be lowered to 1200 ° C. or less, and the compatibility with the conventional GaN process is good.

Next, after removing the surface protective film, the source electrode 171 and the drain electrode 172 are formed on the second nitride semiconductor layer 15 by evaporating and alloying a metal such as Ti / Al / Ni / Au, for example. The ohmic contact between 2DEG formed at the interface between the second nitride semiconductor layer 15 and the first nitride semiconductor layer 13 is formed. Further, an insulating film (not shown) such as SiN is deposited on the second nitride semiconductor layer 15 by using, for example, PECVD, for example, by 50 nm. Then, element isolation is performed by performing ion implantation of N (nitrogen) or the like through the insulating film.

Further, an opening is formed in a region sandwiched between the source electrode 171 and the drain electrode 172 using a reactive gas such as SF ₆ (sulfur fluoride), and then a reaction such as BCl ₃ (boron chloride) is performed. A recess is formed by etching away a part of the second nitride semiconductor layer 15 using a gas. Thereafter, an insulating film 16 such as Al ₂ O _{3 is} deposited to a thickness of about 50 nm using, for example, low-pressure chemical vapor deposition (hereinafter referred to as “LPCVD”) so as to fill the recess. Then, a gate electrode 18 and a fourth electrode 19 are formed on the insulating film 16 by evaporating and lifting off a metal such as Ti / Pt / Au.

In the case of the field effect transistor of this example manufactured by the manufacturing method described above, the Al composition of the p-type Al _0.05 Ga _0.95 N layer (second nitride semiconductor layer 15) is x = 0.05. From Equation (5), σ _p / q = + 3 × 10 ¹² cm ⁻² is obtained.

In the region 152 of the p-type Al _0.05 Ga _0.95 N layer (second nitride semiconductor layer 15) that is not doped with the n-type impurity, the concentration of the n-type impurity is N _d = 0 cm ⁻³ , and the p-type Since the impurity concentration is N _a = 1 × 10 ¹⁹ cm ⁻³ , the activation rate η _a = 0.1, and the thickness (depth) of the p-type impurity doped region t _a = 60 nm, the relational expression (8) Thus, a negative fixed charge having a surface density N _p = 3 × 10 ¹² cm ⁻² is formed in the second nitride semiconductor layer 15. For this reason, the p-type conduction region 142 is formed.

In the region 151 doped with the n-type impurity of the p-type Al _0.05 Ga _0.95 N layer (second nitride semiconductor layer 15), the concentration of the n-type impurity is N _d = 1 × 10 ¹⁹ cm ^{−. 3,} the concentration of the p-type impurity _{^{^{n a = 1 × 10 19 cm}}} -3, activation ratio η _a = η _d = 0.1, the thickness of the p-type impurity doped region _(depth) t a = 60nm, n Since the thickness (depth) of the impurity doped region t _d = 60 nm, the relational expression (6) is established, and the surface density N _n = 3 × 10 ¹² cm ⁻² in the second nitride semiconductor layer 15 is positive. Are formed. For this reason, an n-type conductive region 141 is formed.

Thus, in the case of the field effect transistor of this example manufactured by the above-described manufacturing method, Expression (10) is established. For this reason, based on the above principle of operation, the electric field strength in the region sandwiched between the gate electrode 18 and the drain electrode 172 becomes substantially constant, and the electric field concentration is alleviated. Further, when the fourth electrode 19 is coupled with the source electrode 171, the avalanche resistance can be improved.

In the manufacturing method described above, in the crystal growth stage, the Al _0.05 Ga _0.95 N layer (second nitride semiconductor layer 15) is made p-type (Mg doping), and in the subsequent steps, n Although the n-type impurity doped region 151 is formed by doping the n-type impurity, the process of forming the n-type and the p-type can be reversed. That is, in the crystal growth stage, the Al _0.05 Ga _0.95 N layer (second nitride semiconductor layer 15) is made n-type (n-type impurity doping), and in the subsequent process, p-type impurities are doped. Thus, the p-type impurity doped region 152 may be formed.

Further, (4) the GaN layer (first nitride semiconductor layer 13) is undoped, but it may be p-type or n-type having an activation impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ or less.

These assumptions are the same in the implementation examples of all the following embodiments.
<< Embodiment 2 >>
<Configuration of Field Effect Transistor of Second Embodiment>

FIG. 6 shows the configuration of the field effect transistor of this embodiment. 6A is a schematic plan view, FIG. 6B is a schematic cross-sectional view of the (X1-Y1) plane of FIG. 6A, and FIG. 6C is (X2-Y2) of FIG. 6A. It is the cross-sectional schematic in a surface. In FIG. 6A, the second nitride semiconductor layer 15 located below the first nitride semiconductor layer 13 is indicated by a dotted line. That is, the n-type impurity doped region 151 and the p-type impurity doped region 152 shown in FIG. 6A are formed in the second nitride semiconductor layer 15.

In the field effect transistor of the present embodiment, the first nitride semiconductor layer 13 is provided on the upper side of the second nitride semiconductor layer 15 as shown in FIGS. Even if comprised in this way, the effect similar to the field effect transistor of Embodiment 1 is realizable. Further, with such a configuration, a semiconductor layer having a large band gap between the n-type conductive region 141 and the drain electrode 172 serving as an electron channel and between the n-type conductive region 141 and the source electrode 171. No longer exists. As a result, the contact resistance is reduced, it is possible to further improve the on-resistance R _on.

The

stacked bodies

13 and 15 are epitaxial layers, and the crystal growth may be parallel to the [0001] direction. Further, a buffer layer 11 of (0001) plane growth that lattice matches with the second nitride semiconductor on the outermost surface may be provided between the

stacked bodies

13 and 15 and the substrate 10.

Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted here.
<Example of Field Effect Transistor of Embodiment 2>

Next, one implementation example of the field effect transistor of the present embodiment will be described. The field effect transistor of this example is manufactured by the following manufacturing method, for example.

First, on the Si substrate 10, the layers shown in the following (1) to (5) are sequentially grown in the order shown below, for example, by MOCVD.

(1) Undoped AlN layer (buffer layer 11) ... 200 nm
(2) Undoped Al _0.06 Ga _0.94 N layer (buffer layer 11) 1 μm
(3) p-type Al _0.06 Ga _0.94 N layer “Mg doping: concentration 1 × 10 ¹⁹
cm ⁻³ ”(third nitride semiconductor layer 12) ... 100 nm
(4) Undoped Al _0.06 Ga _0.94 N layer (second nitride semiconductor layer 15) 40 nm
(5) n-type Al _0.06 Ga _0.94 N layer “Si doping: concentration 1 × 10 ¹⁸
cm ⁻³ ”(second nitride semiconductor layer 15) ... 60 nm
(6) Undoped GaN layer (first nitride semiconductor layer 13) 100 nm

Here, the first nitride semiconductor layer 13 is thinner than the thickness of dislocation generation and is a strained lattice layer. From the viewpoint of obtaining good crystal quality, the Al composition is generally preferably 0 <x <0.4. In the case of this example, x = 0.06, and the thickness of the first nitride semiconductor layer 13 is set to 200 nm or less, so that it is within the critical film thickness for occurrence of transition.

In the case of the field effect transistor of this example, for example, the density of impurity ions is maximized in the second nitride semiconductor layer 15 after forming a surface protective film (not shown) such as SiN using PECVD. Ion implantation is performed.

In the ion implantation, for example, H (p-type impurity) is doped in a state where a region other than a region to be doped with a p-type impurity is covered with a resist film. As doping conditions, for example, an acceleration energy of 150 kev, a dose of 6 × 10 ¹³ cm ⁻² , an average atomic concentration of 1 × 10 ¹⁹ cm ⁻³ , and an extension in the depth direction (t _a ) of 60 nm are H-doped. A region (p-type impurity doped region 152) can be selectively formed in the second nitride semiconductor layer 15. Note that the width W _{n of the} region not doped with the p-type impurity and the width W _p of the region doped with the p-type impurity were set to W _n = W _p = 100 nm (arbitrary design matters). After ion implantation, activation annealing is performed at 400 to 500 ° C. in an N ₂ atmosphere, so that an activation rate of H of about 10% can be obtained. Thus, the activation annealing temperature can be lowered to 600 ° C. or lower, and the compatibility with the conventional GaN process is good.

Thereafter, in accordance with the manufacturing method described in the first embodiment, the gate electrode is formed on the first nitride semiconductor layer 13 via the source electrode 171, the drain electrode 172, the fourth electrode 19, and the insulating film 16. 18 is formed.

Here, FIG. 7 shows a potential profile in the vicinity of the channel between the gate and the drain when the drain electrode 172 and the source electrode 171 have the same voltage (V _ds = 0) in the field effect transistor according to the present embodiment. . 7A shows the profile of the (X1-Y1) plane, and FIG. 7B shows the profile of the (X2-Y2) plane.

When the first nitride semiconductor layer (eg, GaN layer) 13 is crystal-grown on the (0001) plane second nitride semiconductor layer (eg, AlGaN layer) 15, the first nitride semiconductor layer 13 has a compressive strain. Works and piezo polarization occurs. Furthermore, since spontaneous polarization is also generated, a negative charge having a surface density (σ _p ) is generated at the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15. Here, σ _p is a function of the Al composition x of the second nitride semiconductor layer 15 and can be approximated by the following equation (15).

Here, the value of the coefficient is smaller than the formula (5) when the second nitride semiconductor layer 15 is formed on the first nitride semiconductor layer 13 (Embodiment 1: FIG. 1). In contrast, when the first nitride semiconductor layer 13 is formed on the second nitride semiconductor layer 15 (Embodiment 2: FIG. 6), the spontaneous polarization and piezoelectricity are the same. This is because the directions of polarization are reversed and cancel each other.

In this example, since the Al composition of the n-type Al _0.06 Ga _0.94 N layer (second nitride semiconductor layer 15) is x = 0.06, σ _p / q = −3 from Equation (15). × 10 ¹² cm ^-2

In the region 151 of the n-type Al _0.06 Ga _0.94 N layer (second nitride semiconductor layer 15) which is not doped with the p-type impurity, the concentration of the n-type impurity is N _d = 1 × 10 ¹⁸ cm ^{−. 3. Since} the activation rate η _d = 1.0, the thickness (depth) of the n-type impurity doped region t _d = 60 nm, and the concentration of the p-type impurity is N _a = 0 cm ⁻³ , the relational expression (6 ) Is formed, and a positive fixed charge having an areal density N _n = 3 × 10 ¹² cm ⁻² is formed in the second nitride semiconductor layer 15. For this reason, an n-type conductive region 141 is formed.

In the n-type Al _0.06 Ga _0.94 N layer (second nitride semiconductor layer 15) doped with the p-type impurity, the n-type impurity concentration is N _d = 1 × 10 ¹⁸ cm ^{−. 3.} Activation rate η _d = 1.0, n-type impurity doped region thickness (depth) t _d = 60 nm, p-type impurity concentration is N _p = 1 × 10 ¹⁹ cm ⁻³ , activation rate η _{Since a} = 1.0 and the thickness (depth) of the p-type impurity doped region t _a = 60 nm, the relational expression (8) is established, and the surface density N _p = 3 in the second nitride semiconductor layer 15. A negative fixed charge of × 10 ¹² cm ^-2 is formed. For this reason, the p-type conduction region 142 is formed.

Thus, in the case of the field effect transistor of this example, Expression (10) is established. For this reason, based on the operation principle described in the first embodiment, the electric field strength in the region sandwiched between the gate electrode 18 and the drain electrode 172 becomes substantially constant, and the electric field concentration is alleviated. Further, when the fourth electrode 19 is coupled with the source electrode 171, the avalanche resistance can be improved.

In the manufacturing method described above, in the crystal growth stage, the Al _0.06 Ga _0.94 N layer (second nitride semiconductor layer 15) is made n-type (Si doping), and in the subsequent steps, p Although the p-type impurity doped region 152 is formed by doping the n-type impurity, the process of forming the n-type and the p-type can be reversed. That is, in the crystal growth stage, the Al _0.06 Ga _0.94 N layer (second nitride semiconductor layer 15) is made p-type (p-type impurity doping), and after that, n-type impurities are doped. Thus, the n-type impurity doped region 151 may be formed.

Also, (5) GaN layer (first nitride semiconductor layer 13) was undoped, it may be about 1 × ¹⁰ 17 ^{cm -3} or less of p-type or n-type, which was activated impurity concentration.

These assumptions are the same in the implementation examples of all the following embodiments.
<< Embodiment 3 >>
<Configuration of Field Effect Transistor of Embodiment 3>

FIG. 8 shows the configuration of the field effect transistor of this embodiment. 8 (a) is a schematic plan view, FIG. 8 (b) is a schematic cross-sectional view in the (X1-Y1) plane of FIG. 8 (a), and FIG. 8 (c) is (X2-Y2) in FIG. 8 (a). It is the cross-sectional schematic in a surface.

The field effect transistor according to the present embodiment is based on the field effect transistor according to the first embodiment, and a region sandwiched between the gate electrode 18 and the drain electrode 172 of the second nitride semiconductor layer 15 as shown in FIG. Is different in that a striped pattern in which p-type impurity doped regions 152 doped with p-type impurities and undoped regions 151 are alternately arranged is formed. However, in the first embodiment, electrons are generated by the n-type impurity doping and the polarization effect, whereas in this embodiment, electrons are generated only by the polarization effect. Therefore, the Al composition of the second nitride semiconductor layer 15 and the p-type impurity The density setting has been changed. For example, when the first nitride semiconductor constituting the first nitride semiconductor layer 13 is GaN, the buffer layer 11 can have a laminated structure including an AlN layer and a GaN layer formed thereon.

The field effect transistor according to the present embodiment can have the same configuration as that of the field effect transistor according to the first embodiment except for the differences. The

stacked bodies

13 and 15 are (0001) plane growth in which the second nitride semiconductor layer 15 is stacked on the first nitride semiconductor layer 13.

In the field effect transistor according to this embodiment, the second nitride semiconductor constituting the second nitride semiconductor layer 15 has a shorter a-axis length than the material constituting the buffer layer 11, and thus the second nitride. A tensile strain is inherent in the semiconductor layer 15. Since positive fixed charges are generated at the interface between the second nitride semiconductor layer 15 and the first nitride semiconductor layer 13 based on the piezoelectric polarization effect and the spontaneous polarization effect, the undoped region 151 functions as an electron supply region. To do. As a result, in the vicinity of the interface between the first nitride semiconductor layer 13 and the undoped region 151 of the second nitride semiconductor layer 15, an n-type conductive region 141 containing 2DEG is formed in a column shape.

On the other hand, in the vicinity of the interface between the first nitride semiconductor layer 13 and the p-type impurity doped region 152 of the second nitride semiconductor layer 15, a p-type conductive region 142 containing 2DHG is formed in a column shape.

As a result, the same effect as the field effect transistor described in the first embodiment can be realized.

The field effect transistor of this embodiment supplies electrons in the n-type conduction region 141 by using the polarization effect of the second nitride semiconductor layer 15 formed on the (0001) plane first nitride semiconductor layer 13. It is configured as follows. In the case of the configuration in which the electrons of the n-type conduction region 141 are supplied using doping as in the first embodiment, the activation rate of the impurity atoms depends on the process conditions and the like, but in the present embodiment, the second nitridation is performed. The charge concentration is automatically determined by the Al composition of the physical semiconductor layer 15 (eg, AlGaN layer). For this reason, it is easy to adjust the epi structure so as to satisfy the relational expression (11), and the reproducibility of the device characteristics is improved.
<Example of Field Effect Transistor of Embodiment 3>

(1) Undoped AlN layer (buffer layer 11) ... 200 nm
(2) Undoped GaN layer (buffer layer 11) 1 μm
(3) p-type GaN layer “Mg doping: concentration 1 × 10 ¹⁹ cm ⁻³ ” (third nitride semiconductor layer 12) 100 nm
(4) Undoped GaN layer (first nitride semiconductor layer 13) ... 100 nm
(5) Undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) ... 40 nm

Here, the second nitride semiconductor layer 15 is thinner than the film thickness of dislocation generation and is a strained lattice layer. From the viewpoint of obtaining good crystal quality, the Al composition is generally preferably 0 <x <0.4. In the case of this example, x = 0.2, and the thickness of the second nitride semiconductor layer 15 is set to 60 nm or less, so that it is within the critical film thickness for occurrence of transition.

Thereafter, in accordance with the manufacturing method described in Embodiment 1, ion implantation into the undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) and undoped Al _0.2 Ga _{0.8 are performed.} A gate electrode 18 is formed on the N layer (second nitride semiconductor layer 15) via the source electrode 171, the drain electrode 172, the fourth electrode 19, and the insulating film 16.

As the doping conditions for ion implantation, for example, H is used as the p-type impurity, the acceleration energy is 40 kev, and the dose amount is 2.4 × 10 ¹⁴ cm ⁻² , so that the average atomic concentration is 6 × 10 ¹⁹ cm ^{−. 3} , an H-doped region (p-type impurity doped region 152) having _a depthwise extension (t _a ) of 40 nm can be selectively formed in the second nitride semiconductor layer 15. Note that the width W _n of the region doped with n-type impurities and the width W _p of the region not doped with n-type impurities were set to W _n = W _p = 100 nm (arbitrary design matters). After ion implantation, activation annealing is performed at 400 to 500 ° C. in an N ₂ atmosphere, so that an activation rate of H of about 10% can be obtained. Thus, the activation annealing temperature can be lowered to 600 ° C. or lower, and the compatibility with the conventional GaN process is good.

The field effect transistor of this example has a HEMT structure in which the buffer layer 11 is GaN, the first nitride semiconductor layer 13 is GaN, and the second nitride semiconductor layer 15 is Al _0.2 Ga _0.8 N in this order. The impurity doped region 152 is doped with H (proton). The fact that the buffer layer 11 is GaN is lattice-relaxed during the growth process of the thick GaN layer 11, and no strain is generated even if GaN is grown to a certain thickness. For this reason, no distortion occurs in the first nitride semiconductor layer 13. However, tensile strain is generated in the second nitride semiconductor layer 15 grown on the first nitride semiconductor layer 13, and the second nitride semiconductor layer 15 and the first nitride are caused by spontaneous polarization and piezoelectric polarization. A positive polarization charge σ _p is generated at the interface with the physical semiconductor layer 13.

In this example, since the Al composition of the undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) is x = 0.2, σ _p / q = + 1 from Equation (5). 2 × 10 ¹³ cm ⁻² .

In the region 151 of the undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) that is not doped with the p-type impurity, the concentration of the n-type impurity is N _d = 0 cm ⁻³ , and the p-type impurity is Since the concentration of N _a = 0 cm ⁻³ , the relational expression (6) is established, and a positive fixed charge having a surface density N _n = 1.2 × 10 ¹³ cm ⁻² in the second nitride semiconductor layer 15 is satisfied. Is formed. For this reason, an n-type conductive region 141 is formed.

Further, in the region 152 of the undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) doped with the p-type impurity, the concentration of the n-type impurity is N _d = 0 cm ⁻³ , and the p-type impurity is Since N _a = 6 × 10 ¹⁹ cm ⁻³ , activation rate η _a = 0.1, and p-type impurity doped region thickness (depth) t _a = 40 nm, the relational expression (8) Thus, a negative fixed charge having a surface density N _p = 1.2 × 10 ¹³ cm ⁻² is formed in the second nitride semiconductor layer 15. For this reason, the p-type conduction region 142 is formed.

Thus, in the case of the field effect transistor of this example, Expression (10) is established. For this reason, based on the operation principle described in the first embodiment, the electric field strength in the region sandwiched between the gate electrode 18 and the drain electrode 172 becomes substantially constant, and the electric field concentration is alleviated. Further, when the fourth electrode 19 is coupled with the source electrode 171, the avalanche resistance can be improved.
<< Embodiment 4 >>
<Configuration of Field Effect Transistor of Embodiment 4>

FIG. 9 shows the configuration of the field effect transistor of this embodiment. 9A is a schematic plan view, FIG. 9B is a schematic cross-sectional view of the (X1-Y1) plane of FIG. 9A, and FIG. 9C is (X2-Y2) of FIG. 9A. It is the cross-sectional schematic in a surface. In FIG. 9A, the second nitride semiconductor layer 15 located below the first nitride semiconductor layer 13 is indicated by a dotted line. That is, the n-type impurity doped region 151 and the undoped region 152 shown in FIG. 9A are formed in the second nitride semiconductor layer 15.

The field effect transistor according to the present embodiment is based on the field effect transistor according to the second embodiment, and a region sandwiched between the gate electrode 18 and the drain electrode 172 of the second nitride semiconductor layer 15 as shown in FIG. 9A. Is different in that a striped pattern in which n-type impurity doped regions 151 doped with n-type impurities and undoped regions 152 are alternately arranged is formed. However, in the second embodiment, holes are generated by the p-type impurity doping and the polarization effect, whereas in this embodiment, holes are generated only by the polarization effect, so that the Al composition of the second nitride semiconductor layer, the n-type The impurity concentration setting has been changed. For example, when the second nitride semiconductor constituting the second nitride semiconductor layer 15 is Al _0.2 Ga _0.8 N, the buffer layer 11 includes an AlN layer and Al _0.2 Ga ₀ formed thereon. _{.8 A} multilayer structure composed of N layers can be formed.

The field effect transistor according to the present embodiment can have the same configuration as that of the field effect transistor according to the second embodiment except for the differences. The

stacked bodies

13 and 15 are (0001) plane growth in which the first nitride semiconductor layer 13 is stacked on the second nitride semiconductor layer 15.

In the case of the field effect transistor of this embodiment, the first nitride semiconductor constituting the first nitride semiconductor layer 13 has a longer a-axis length than the material constituting the buffer layer 11, and thus the first nitride A compressive strain is inherent in the semiconductor layer 13. Based on the piezoelectric polarization effect and the spontaneous polarization effect, negative fixed charges are generated at the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15, so that the undoped region 152 serves as a hole supply region. Function. As a result, in the vicinity of the interface between the first nitride semiconductor layer 13 and the undoped region 152 of the second nitride semiconductor layer 15, a p-type conductive region 142 containing 2DHG is formed in a column shape.

On the other hand, in the vicinity of the interface between the first nitride semiconductor layer 13 and the n-type impurity doped region 151 of the second nitride semiconductor layer 15, an n-type conductive region 141 containing 2DEG is formed in a column shape.

As a result, the same effect as the field effect transistor described in the second embodiment can be realized.

In addition, the field effect transistor of this embodiment uses the polarization effect on the first nitride semiconductor layer 13 formed on the (0001) plane second nitride semiconductor layer 15 to cause holes in the p-type conduction region 142 to flow. It is configured to supply. In the case of the configuration in which the holes of the p-type conduction region 142 are supplied using doping as in the second embodiment, the activation rate of the impurity atoms depends on the process conditions and the like. The charge concentration is automatically determined by the Al composition of the nitride semiconductor layer 15 (eg, AlGaN layer). For this reason, it is easy to adjust the epi structure so as to satisfy the relational expression (11), and the reproducibility of the device characteristics is improved.
<Example of Field Effect Transistor of Embodiment 4>

(1) Undoped AlN layer (buffer layer 11) ... 200 nm
(2) the undoped _Al 0.2 _{Ga 0.8} N layer (buffer layer 11) · · · 1 [mu] m
(3) p-type Al _0.2 Ga _0.8 N layer “Mg doping: concentration 1 × 10 ¹⁹ cm ⁻³ ” (third nitride semiconductor layer 12)... 100 nm
(4) Undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) ... 100 nm
(5) Undoped GaN layer (first nitride semiconductor layer 13) ... 40 nm

Here, the first nitride semiconductor layer 13 is thinner than the thickness of dislocation generation and is a strained lattice layer. From the viewpoint of obtaining good crystal quality, the Al composition is generally preferably 0 <x <0.4. In the case of this example, x = 0.2, and the thickness of the first nitride semiconductor layer 13 is set to 60 nm or less, so that it is within the critical film thickness for occurrence of transition.

Thereafter, in accordance with the manufacturing method described in the second embodiment, ion implantation into the undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) and the undoped GaN layer (first nitride semiconductor) A gate electrode 18 is formed on the layer 13) via a source electrode 171, a drain electrode 172, a fourth electrode 19, and an insulating film 16.

In addition, as doping conditions for ion implantation, for example, Si is used as an n-type impurity, acceleration energy is 200 kev, and a dose is 2.0 × 10 ^14.
By setting cm ⁻² , the Si-doped region (n-type impurity doped region 151) having an average atomic concentration of 5 × 10 ¹⁹ cm ⁻³ and a spread in the depth direction (t _d ) of 40 nm in the second nitride semiconductor layer 15 Can be selectively formed. Note that the width W _n of the region doped with n-type impurities and the width W _p of the region not doped with n-type impurities were set to W _n = W _p = 100 nm (arbitrary design matters). After ion implantation, activation annealing is performed at 1000 to 1200 ° C. in an N ₂ atmosphere, so that an Si activation rate of about 10% can be obtained. Thus, the activation annealing temperature can be lowered to 1200 ° C. or lower, and the compatibility with the conventional GaN process is good.

In the field effect transistor of the present example, the buffer layer 11 is made of Al _0.2 Ga _0.8 N, the second nitride semiconductor layer 15 is made of Al _0.2 Ga _0.8 N, and the first nitride semiconductor layer 13 is made of GaN. The structure is an inverse HEMT structure, in which the n-type impurity doped region 151 is doped with Si. That the buffer layer 11 is that _Al 0.2 _{Ga 0.8} N is lattice relaxation during the growth of a thick _Al 0.2 _{Ga 0.8} N layer 11, _Al 0.2 _{Ga 0.8} thereon No strain is generated no matter how thick N grows. For this reason, no distortion occurs in the second nitride semiconductor layer 15. However, compressive strain is generated in the first nitride semiconductor layer 13 grown on the second nitride semiconductor layer 15, and the first nitride semiconductor layer 13 and the second nitride are caused by spontaneous polarization and piezoelectric polarization. Negative polarization charge σ _p is generated at the interface of the physical semiconductor layer 15.

In this example, since the Al composition of the undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) is x = 0.2, σ _p / q = − from Equation (15). 1.0 × 10 ¹³ cm ⁻² .

In the region 152 of the undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) not doped with the n-type impurity, the concentration of the n-type impurity is N _d = 0 cm ⁻³ , and the p-type impurity is Since the concentration of N _a = 0 cm ⁻³ , the relational expression (8) is satisfied, and the negative fixed charge having the surface density N _p = 1.0 × 10 ¹³ cm ⁻² in the second nitride semiconductor layer 15 is satisfied. Is formed. For this reason, the p-type conduction region 142 is formed.

In the undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) in which the n-type impurity is doped, the concentration of the n-type impurity is N _d = 5 × 10 ¹⁹ cm ^−3. Since the activation rate η _d = 0.1, the thickness (depth) of the n-type impurity doped region t _d = 40 nm, and the concentration of the p-type impurity is N _a = 0 cm ⁻³ , the relational expression (6) is As a result, a positive fixed charge having a surface density N _n = 1.0 × 10 ¹³ cm ⁻² is formed in the second nitride semiconductor layer 15. For this reason, an n-type conductive region 141 is formed.

Thus, in the case of the field effect transistor of this example, Expression (10) is established. For this reason, based on the operation principle described in the first embodiment, the electric field strength in the region sandwiched between the gate electrode 18 and the drain electrode 172 becomes substantially constant, and the electric field concentration is alleviated. Further, when the fourth electrode 19 is coupled with the source electrode 171, the avalanche resistance can be improved.
<< Embodiment 5 >>
<Configuration of Field Effect Transistor of Embodiment 5>

FIG. 10 shows the configuration of the field effect transistor of this embodiment. 10 (a) is a schematic plan view, FIG. 10 (b) is a schematic cross-sectional view in the (X1-Y1) plane of FIG. 10 (a), and FIG. 10 (c) is (X2-Y2) in FIG. 10 (a). It is the cross-sectional schematic in a surface.

The field effect transistor according to the present embodiment is based on the configuration of the field effect transistor according to any one of the first to fourth embodiments, and is provided with the fourth electrode 19, and the stripe pattern of the second nitride semiconductor layer 15 is essential. The p-type or n-type impurity doped region that constitutes n-type extends to a position immediately below the source electrode 171 and is the n-type or p-type that constitutes the stripe pattern of the second nitride semiconductor layer 15, which is The second-type impurity-doped regions having different shapes extend to just below the fourth electrode 19.

For example, as shown in FIGS. 10B and 10C, the n-type impurity doped region 151 constituting the stripe pattern of the second nitride semiconductor layer 15 extends to a position immediately below the source electrode 171, and the second nitride semiconductor The p-type impurity doped region 152 constituting the stripe pattern of the layer 15 extends to a position immediately below the fourth electrode 19.

Such a field effect transistor according to this embodiment can achieve the same effect as the field effect transistors described in the first to fourth embodiments.

In the field effect transistor of this embodiment, the p-type impurity doped region 152 constituting the stripe region of the second nitride semiconductor layer 15 extends to the fourth electrode 19 and is electrically connected to the fourth electrode 19. By doing so, holes generated in the channel can be extracted through the fourth electrode 19. With such a configuration, the p-type channel layer 12 (see FIG. 1 and the like) is not formed below the

stacked bodies

13 and 15 including the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15. Can do. As a result, there is an advantage that the epi structure can be simplified and the increase in parasitic capacitance is relatively small.

As shown in FIG. 11, the field effect transistor of the present embodiment may be configured such that the upper and lower positions of the first nitride semiconductor layer 13 and the second nitride semiconductor layer 15 are reversed.
<Example of Field Effect Transistor of Embodiment 5>

Next, one implementation example of the field effect transistor of the present embodiment will be described.
<< Example 1 >>

The field effect transistor of this example is manufactured by the following manufacturing method, for example.

First, on the Si substrate 10, the layers shown in the following (1) to (4) are sequentially grown in the following order, for example, by MOCVD.

(1) Undoped AlN layer (buffer layer 11) ... 200 nm
(2) Undoped GaN layer (buffer layer 11) 1 μm
(3) Undoped GaN layer (first nitride semiconductor layer 13) ... 100 nm
(4) Undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) ... 40 nm

In the present embodiment, since the second nitride semiconductor layer (example: AlGaN layer) 15 is crystal-grown on the (0001) plane first nitride semiconductor layer (example: GaN layer) 13, according to the equation (5) A positive polarization charge σ _p is generated at the heterointerface.

Thus, in the case of the field effect transistor of this example, Expression (10) is established. For this reason, based on the operation principle described in the first embodiment, the electric field strength in the region sandwiched between the gate electrode 18 and the drain electrode 172 becomes substantially constant, and the electric field concentration is alleviated. Further, when the fourth electrode 19 is coupled with the source electrode 171, the avalanche resistance can be improved.
<< Example 2 >>

First, on the Si substrate 10, the layers shown in the following (1) to (4) are sequentially grown in the order shown below, for example, by MOCVD.

(1) Undoped AlN layer (buffer layer 11) ... 200 nm
(2) Undoped Al _0.2 Ga _0.8 N layer (buffer layer 11) 1 μm
(3) Undoped Al _0.2 Ga _0.8 N layer (second nitride semiconductor layer 15) ... 100 nm
(4) Undoped GaN layer (first nitride semiconductor layer 13) ... 40 nm

In the present embodiment, since the first nitride semiconductor layer (example: GaN layer) 13 is crystal-grown on the (0001) plane second nitride semiconductor layer (example: AlGaN layer) 15, according to the equation (15) Negative polarization charge σ _p is generated at the heterointerface.

Thus, in the case of the field effect transistor of this example, Expression (10) is established. For this reason, based on the operation principle described in the first embodiment, the electric field strength in the region sandwiched between the gate electrode 18 and the drain electrode 172 becomes substantially constant, and the electric field concentration is alleviated. In addition, if the fourth electrode 19 is electrically connected to the source electrode 171, the avalanche resistance can be improved.

This application claims priority based on Japanese Patent Application No. 2009-160698 filed on July 7, 2009, the entire disclosure of which is incorporated herein.

Claims

A laminated body in which a first nitride semiconductor layer made of a first nitride semiconductor and a second nitride semiconductor layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor are laminated; ,
A gate insulating film and a gate electrode formed on the laminate;
A drain electrode electrically connected to the first nitride semiconductor layer on the stacked body and provided to face the gate electrode;
On the stacked body, electrically connected to the first nitride semiconductor layer, a source electrode provided on the opposite side of the drain electrode across the gate electrode,
With
In the region sandwiched between the gate electrode and the drain electrode of the second nitride semiconductor layer,
An electric field in which an n-type impurity doped region doped with an n-type impurity and a p-type impurity doped region doped with a p-type impurity are alternately arranged along the direction in which the gate electrode extends. Effect transistor.
N-type activation impurity surface density n d1 of the n-type impurity doped region;
A surface density na1 of the p-type activation impurity in the n-type impurity doped region;
A width W n of the n-type impurity doped region;
The surface density na2 of the p-type activation impurity in the p-type impurity doped region;
The surface density n d2 of the n-type activation impurity in the p-type impurity doped region;
A width W p of the p-type impurity doped region;
The surface density σ p of the polarization charge formed at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer;
Elementary charge q (= 1.6 × 10 −19 C) and 0.1 <(| n d1 −n a1 + σ p / q | × W n ) / (| −n d2 + n a2 −σ p / q | × W p ) <10
The field effect transistor according to claim 1, wherein:
N-type activation impurity surface density n d1 of the n-type impurity doped region;
A surface density na1 of the p-type activation impurity in the n-type impurity doped region;
A width W n of the n-type impurity doped region;
The surface density na2 of the p-type activation impurity in the p-type impurity doped region;
The surface density n d2 of the n-type activation impurity in the p-type impurity doped region;
A width W p of the p-type impurity doped region;
The surface density σ p of the polarization charge formed at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer;
Relational expression of elementary charge q (= 1.6 × 10 −19 C) and | n d1 −n a1 + σ p / q | × W n = | −n d2 + n a2 −σ p / q | × W p The field effect transistor according to claim 2, wherein:
4. The field effect transistor according to claim 1, wherein the first nitride semiconductor layer is provided on an upper side or a lower side of the second nitride semiconductor layer.
On the first nitride semiconductor layer made of the first nitride semiconductor, a second nitride semiconductor layer made of the second nitride semiconductor having a larger band gap than the first nitride semiconductor was laminated (0001) A surface-growing laminate,
A gate insulating film and a gate electrode formed on the laminate;
A drain electrode electrically connected to the first nitride semiconductor layer on the stacked body and provided to face the gate electrode;
On the stacked body, electrically connected to the first nitride semiconductor layer, a source electrode provided on the opposite side of the drain electrode across the gate electrode,
On the substrate,
In the region sandwiched between the gate electrode and the drain electrode of the second nitride semiconductor layer,
A striped pattern in which p-type impurity doped regions doped with p-type impurities and undoped regions are alternately arranged is formed,
A field effect transistor further comprising a buffer layer having a (0001) plane growth lattice-matched with the first nitride semiconductor at an interface with the first nitride semiconductor layer between the stacked body and the substrate.
A second nitride semiconductor layer made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor was laminated under the first nitride semiconductor layer made of the first nitride semiconductor (0001) A surface-growing laminate,
A gate insulating film and a gate electrode formed on the laminate;
A drain electrode electrically connected to the first nitride semiconductor layer on the stacked body and provided to face the gate electrode;
On the stacked body, electrically connected to the first nitride semiconductor layer, a source electrode provided on the opposite side of the drain electrode across the gate electrode,
On the substrate,
In the region sandwiched between the gate electrode and the drain electrode of the second nitride semiconductor layer,
A striped pattern in which n-type impurity doped regions doped with n-type impurities and undoped regions are alternately arranged is formed,
A field effect transistor further comprising a (0001) plane grown buffer layer lattice-matched with the second nitride semiconductor at the interface with the second nitride semiconductor layer between the stacked body and the substrate.
The charge effect transistor according to any one of claims 1 to 6, wherein the stacked body is an epitaxial layer.
A fourth electrode is provided on the stacked body, on the opposite side of the gate electrode across the source electrode, and
A third nitride semiconductor layer made of a third nitride semiconductor doped with a p-type or n-type impurity at a position below the multilayer body and in contact with the multilayer body;
The p-type or n-type 1-type impurity doped region constituting the striped pattern of the second nitride semiconductor layer does not extend to just below the source electrode,
The field effect transistor according to any one of claims 1 to 7, wherein the first-type impurity doped region doped with the first-type impurity is formed immediately below the fourth electrode.
A fourth electrode is provided on the stacked body, on the opposite side of the gate electrode across the source electrode,
A p-type or n-type impurity doped region constituting the striped pattern of the second nitride semiconductor layer extends to a position immediately below the source electrode;
2. The n-type or p-type, which is the n-type or p-type that forms the stripe pattern of the second nitride semiconductor layer, and has a shape different from the type 1, extends to a position immediately below the fourth electrode. 8. The field effect transistor according to any one of 1 to 7.
The field effect transistor according to claim 8 or 9, wherein the fourth electrode is electrically grounded via the source electrode.