CN113066864B - Semiconductor device with a plurality of transistors - Google Patents

Semiconductor device with a plurality of transistors Download PDF

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CN113066864B
CN113066864B CN202110316798.0A CN202110316798A CN113066864B CN 113066864 B CN113066864 B CN 113066864B CN 202110316798 A CN202110316798 A CN 202110316798A CN 113066864 B CN113066864 B CN 113066864B
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nitride semiconductor
type doped
doped nitride
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island
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CN113066864A (en
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郝荣晖
黄敬源
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Innoscience Suzhou Semiconductor Co Ltd
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Innoscience Suzhou Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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Abstract

The semiconductor device includes a nitride semiconductor layer, source and drain electrodes, a gate electrode, first and second p-type doped nitride semiconductor layers, and a drain field plate. The source electrode, the drain electrode and the gate electrode are disposed on the nitride semiconductor layer. And the gate is located between the source and the drain. The first p-type doped nitride semiconductor layer is disposed on the nitride semiconductor layer and between the gate and the drain. The first p-type doped nitride semiconductor layer includes first, second and third p-type doped nitride semiconductor islands that are separated. The second p-type doped nitride semiconductor island is located between the first and third p-type doped nitride semiconductor islands. Portions of the drain are filled in the spaces of the first, second and third p-type doped nitride semiconductor islands. The second p-type doped nitride semiconductor layer is located between the nitride semiconductor layer and the gate electrode. The drain field plate is located directly above the first, second and third p-type doped nitride semiconductor islands.

Description

Semiconductor device with a plurality of transistors
This application is a divisional application of chinese patent application 202080002210.8 entitled "semiconductor device and method of manufacturing a semiconductor device" filed on 30/04/2020.
Technical Field
The present invention generally relates to semiconductor devices. More particularly, the present invention relates to a High Electron Mobility Transistor (HEMT) semiconductor device having a p-type doped group III-V compound/nitride semiconductor layer to achieve a reduction in hot carrier effects.
Background
In recent years, research into High Electron Mobility Transistors (HEMTs) has been widely used in semiconductor devices, such as high power switching devices and high frequency application devices. HEMTs utilize the junction between two materials with different band gaps as a channel. For example, an aluminum gallium nitride/gallium nitride (AlGaN/GaN) HEMT is a heterojunction device that can operate at higher frequencies than conventional transistors. In a HEMT heterojunction structure, a quantum well structure is formed due to the band gap discontinuity between two materials, which can accommodate a two-dimensional electron gas (2 DEG), thereby causing the carrier concentration at the heterojunction interface to increase to meet the requirements of high power/high frequency devices. For a device having a heterojunction structure, examples thereof include: heterojunction Bipolar Transistors (HBTs), Heterojunction Field Effect Transistors (HFETs), High Electron Mobility Transistors (HEMTs) or modulation-doped field effect transistors (MODFETs).
Currently, the needs faced include how to improve device performance and overcome existing deficiencies. For example, hot carrier effects may occur during device operation. That is, hot carriers will likely pass through the thin layer body and appear as leakage current due to having sufficient energy. Electrons in the form of such hot carriers will likely transition from the channel region or drain to the gate or substrate. That is, electrons in the form of hot carriers do not contribute to the current flow through the channel in the intended form, but instead flow as a leakage current. The presence of such carriers in the device triggers many physical damage phenomena that can greatly alter the characteristics of the device and ultimately cause the failure of the circuit in which the device is incorporated. Therefore, there is a need in the art for a novel HEMT structure to prevent hot carrier effects, thereby improving device performance and reliability thereof.
Disclosure of Invention
According to one aspect of the present disclosure, a semiconductor device is provided that includes a first nitride semiconductor layer, a second nitride semiconductor layer, source and drain electrodes, a gate electrode, a first p-type doped nitride semiconductor layer, a second p-type doped nitride semiconductor layer, and a drain field plate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap greater than that of the first nitride semiconductor layer. The source electrode and the drain electrode are disposed on the second nitride semiconductor layer. The gate electrode is disposed on the second nitride semiconductor layer and between the source electrode and the drain electrode. The first p-type doped nitride semiconductor layer is disposed on the second nitride semiconductor layer and between the gate and the drain, wherein the first p-type doped nitride semiconductor layer includes a first p-type doped nitride semiconductor island, a second p-type doped nitride semiconductor island, and a third p-type doped nitride semiconductor island that are separated from each other. The second p-type doped nitride semiconductor island is located between the first p-type doped nitride semiconductor island and the third p-type doped nitride semiconductor island, wherein a portion of the drain is filled in a space between the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island. The second p-type doped nitride semiconductor layer is disposed on the second nitride semiconductor layer and between the second nitride semiconductor layer and the gate electrode. The drain field plate is disposed over the first p-type doped nitride semiconductor layer so as to be directly over the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island.
By applying the above configuration, the reliability problem caused by the hot carrier effect to the semiconductor device can be advantageously improved by the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island which are located between the gate and the drain. In this regard, since the electric field strength at the drain edge increases with the increase of the drain voltage, the high electric field in this region generates electron-hole pairs (electron-hole pairs) by impact ionization (impact ionization), which provides enough energy for electrons in the form of hot carriers to accidentally penetrate certain layers in the semiconductor device and cause permanent degradation of the semiconductor device. In short, these p-type doped nitride semiconductor islands can suppress the electric field at the edge of the drain, and therefore, since the electric field at the edge of the drain is lowered, electrons in the form of hot carriers are also reduced, so that the reliability problem of the semiconductor device can be improved.
Drawings
Aspects of the present disclosure can be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
Embodiments of the invention are described in more detail below with reference to the accompanying drawings, in which:
fig. 1A and 1B are cross-sectional and top views depicting a semiconductor device, in accordance with some embodiments of the present disclosure;
FIG. 1C shows a cross-sectional view along line 1C-1C in FIG. 1B;
fig. 2 illustrates a top view of a semiconductor device, in accordance with some embodiments of the present disclosure;
fig. 3 illustrates a top view of a semiconductor device, in accordance with some embodiments of the present disclosure;
fig. 4A and 4B are cross-sectional and top views depicting a semiconductor device, in accordance with some embodiments of the present disclosure;
fig. 5A and 5B are cross-sectional and top views depicting a semiconductor device, in accordance with some embodiments of the present disclosure; and
fig. 6A-6C are various stage diagrams illustrating a method of fabricating a semiconductor device, according to some embodiments of the present disclosure.
Detailed Description
The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.
In the description, terms such as "upper," "lower," "above," "left," "right," "below," "top," "bottom," "longitudinal," "lateral," "side," "upper," "lower," "upper," "over," "under," and the like are defined with respect to a device or a plane of a group of devices, as oriented in the corresponding figure. It should be understood that the spatial description used herein is for illustrative purposes only and that the structures described herein may be physically embodied in any orientation or manner within a space provided that the advantages of the embodiments of the present disclosure are not necessarily offset by this arrangement.
In the following description, a semiconductor device, a manufacturing method thereof, and the like are listed as preferred examples. Those skilled in the art will appreciate that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the present invention. Specific details may be omitted in order to avoid obscuring the invention; this disclosure, however, is intended to enable one skilled in the art to practice the teachings herein without undue experimentation.
Fig. 1A and 1B are cross-sectional and top views depicting a semiconductor device 100A, in accordance with some embodiments of the present invention. The semiconductor device 100A includes a substrate 110, a buffer layer 120, a semiconductor layer 130, a semiconductor layer 132, a gate structure 140, a source 146, a drain 148, and a p-type doped III-V compound/nitride semiconductor layer 150. For simplicity, some elements in FIG. 1A are omitted from the depiction of FIG. 1B.
Exemplary materials for substrate 110 may include, but are not limited to, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), p-doped silicon (p-doped Si), n-doped silicon (n-doped Si), sapphire (sapphire), semiconductor-on-insulator layers, such as silicon-on-insulator (SOI), or other suitable semiconductor materials including group iii elements, group iv elements, group v elements, or combinations thereof, for example. In some other embodiments, the substrate 110 may also include one or more other features, such as doped regions, buried layers, epitaxial (epitaxiy) layers, or combinations thereof.
The buffer layer 120 is disposed on the substrate 110. Exemplary materials of the buffer layer 120 may include, but are not limited to, for example, nitrides or III-V compounds, such as gallium nitride (GaN), gallium arsenide (GaAs), indium nitride (InN), aluminum nitride (AlN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), or combinations thereof. The buffer layer 120 may serve to reduce lattice mismatch and thermal mismatch between the substrate 110 and a layer to be formed on the buffer layer 120 (e.g., epitaxially formed thereon), thereby repairing defects caused by the mismatch. That is, the occurrence of dislocations and defects may be reduced by the buffer layer 120. The buffer layer may be a single layer or a multilayer of the same or different composition and may also be deposited using the same material under different conditions.
The semiconductor layer 130 is disposed on the buffer layer 120. Exemplary materials of the semiconductor layer 130 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium aluminum gallium nitride (In) x Al y Ga (1–x–y) N, wherein x + y is less than or equal to 1), aluminum gallium nitride (Al) y Ga (1–y) N, wherein y is less than or equal to 1). The semiconductor layer 132 is disposed on the semiconductor layer 130. Exemplary materials of semiconductor layer 132 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium aluminum gallium nitride (In) x Al y Ga (1–x–y) N, wherein x + y is less than or equal to 1), aluminum gallium nitride (Al) y Ga (1–y) N, wherein y is less than or equal to 1).
Exemplary materials for the semiconductor layers 130 and 132 may be selectively chosen such that the band gap (bandgap), or forbidden band width (forbidden band width), of the semiconductor layer 132 is greater than the band gap of the semiconductor layer 130, which will result in different electron affinities from each other. For example, when the semiconductor layer 130 is an undoped GaN layer and it has a band gap of about 3.4ev, the semiconductor layer 132 may be an AlGaN layer and it has a band gap of about 4.0 ev. Accordingly, the semiconductor layers 130 and 132 may function as a channel layer and a barrier layer, respectively. A triangular potential well is generated at the bonding interface between the channel layer and the barrier layer such that electrons are accumulated in the triangular potential well, thereby generating a two-dimensional electron gas (2 DEG) region 134 at the same interface. Therefore, the semiconductor device 100A can be used as a High Electron Mobility Transistor (HEMT).
The gate structure 140 is disposed on the semiconductor layer 132. In this embodiment, the gate structure 140 includes a p-type doped group III-V compound/nitride semiconductor layer 142 that forms an interface with the semiconductor layer 132, and also includes a conductive gate 144 stacked on the p-type doped group III-V compound/nitride semiconductor layer 142. In other embodiments, the gate structure 140 may further comprise a dielectric structure (not shown) disposed between the p-type doped III-V compound/nitride semiconductor layer 142 and the conductive gate 144, and wherein the dielectric structure may be formed of one or more layers of dielectric material.
In the present disclosure, the semiconductor device 100A is an enhancement mode (enhancement mode) device that is normally off when the conductive gate 144 is at substantially zero bias. Specifically, the p-type doped III-V compound/nitride semiconductor layer 142 and the semiconductor layer 132 form a p-n junction to deplete the 2DEG region 134 such that the region under the 2DEG region 134 corresponding to the gate structure 140 has different characteristics (e.g., different electron concentration) than the rest of the 2DEG region 134, and is thus blocked.
By this mechanism, the semiconductor device 100A can have a normally-off characteristic. In other words, when no voltage is applied to the conductive gate 144, or the voltage applied to the conductive gate 144 is less than the threshold voltage (i.e., the minimum voltage required to form the inversion layer under the gate structure 140), the region of the 2DEG region 134 under the gate structure 140 remains blocked, and thus no current will flow through this region. Further, by providing the p-type doped group III-V compound/nitride semiconductor layer 142, gate leakage current can be reduced, and the effect of increasing the threshold voltage during the off state can be achieved.
Exemplary materials for the p-type doped III-V compound/nitride layer 142 may include, for example, but are not limited to, p-type doped III-V nitride semiconductor materials such as p-type gallium nitride (GaN), p-type aluminum gallium nitride (AlGaN), p-type indium nitride (InN), p-type aluminum indium nitride (AlInN), p-type indium gallium nitride (InGaN), p-type aluminum indium gallium nitride (AlInGaN), or combinations thereof. In some embodiments, p-type doping materials can Be achieved by using p-type impurities, such as beryllium (Be), magnesium (Mg), zinc (Zn), cadmium (Cd). In one embodiment, the semiconductor layer 130 includes no dopingThe hetero-GaN, semiconductor layer 132 comprises AlGaN and the p-doped III-V compound/nitride layer 142 is a p-type GaN layer that can bend the band structure of the underlying layers upward and deplete the corresponding regions of the 2DEG region 134 to bring the semiconductor device 100A into an off-state condition. Exemplary materials for the conductive gate 144 may be metals or metal compounds including, but not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), other metal compounds, nitrides, oxides, silicides, doped semiconductors, metal alloys, or combinations thereof. Alternative dielectric structures may include, for example, but are not limited to, one or more layers of oxide, silicon oxide (SiO) x ) Layer, silicon nitride (SiN) x ) Layer, high dielectric constant (high-k) material, like hafnium oxide (HfO) 2 ) Alumina (Al) 2 O 3 ) Titanium dioxide (TiO) 2 ) Hafnium zirconium oxide (HfZrO), tantalum oxide (Ta) 2 O 3 ) Hafnium silicate (HfSiO) 4 ) Zirconium dioxide (ZrO) 2 ) Zirconium silicate (ZrSiO) 2 ) And the like or combinations thereof.
Source 146 and drain 148 are disposed on semiconductor layer 132 and on opposite sides of gate structure 140 (i.e., gate structure 140 is between source 146 and drain 148). In the exemplary depiction of fig. 1A, source 146 and drain 148 are asymmetric to gate structure 140, and source 146 is closer to gate structure 140 than drain 148. However, the disclosure is not limited thereto, i.e., the arrangement relationship of the source 146 and the drain 148 is adjustable. Exemplary materials for source 146 and drain 148 may include, for example, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), other conductor materials, or combinations thereof.
A p-type doped III-V compound/nitride semiconductor layer 150 is disposed on the semiconductor layer 132 and also between the gate structure 140 and the drain 148, wherein the drain 148 is closer to the p-type doped III-V compound/nitride semiconductor layer 150 than the gate structure 140.
In the exemplary depictions of fig. 1A and 1B, the p-type doped III-V compound/nitride semiconductor layer 150 is in contact with the drain 148 and thus electrically coupled with the drain 148, and at least one surface of the p-type doped III-V compound/nitride semiconductor layer 150 may form at least one interface with the drain 148. Specifically, p-type doped III-V compound/nitride semiconductor layer 150 has side surface SS1 and it faces away from gate structure 140, and also has top surface ST and it faces away from semiconductor layer 132. Side surface SS1 and top surface ST form interfaces with drain 148, respectively, and these interfaces extend in different directions (e.g., in the longitudinal and lateral directions). Further, p-type doped III-V compound/nitride semiconductor layer 150 has side surface SS2 and faces gate structure 140 and is closer to gate structure 140 than drain 148 so that drain 148 and p-type doped III-V compound/nitride semiconductor layer 150 may collectively form a stepped profile on semiconductor layer 132.
The p-type doped III-V compound/nitride semiconductor layer 150 improves reliability problems caused by hot carrier effects in the semiconductor device 100A. In general, since the potential at the edge of the drain changes dramatically, the electric field strength at the edge of the drain increases with the increase of the drain voltage. Therefore, in a semiconductor device, a high electric field in this region generates electron-hole pairs (electron-hole pairs) by bombardment ionization (ionization). Due to this mechanism, the generated electrons have sufficient energy and may accidentally penetrate the layer in certain areas of the semiconductor device, resulting in permanent degradation of the semiconductor device. In other words, if the semiconductor device is allowed to operate in an environment outside these safe operating conditions, a serious reliability degradation problem may result.
To address these defects, the p-type doped III-V compound/nitride semiconductor layer 150 in contact with the drain 148 and the semiconductor layer 132 may form a p-n junction such that the p-type doped III-V compound/nitride semiconductor layer 150 is able to provide minority charge carriers (e.g., holes) into the semiconductor layer 130, thereby suppressing the electric field at the drain edge (e.g., the edge of the drain 148). As a result, the electric field at the edge of the drain is reduced, thereby reducing electrons in the form of hot carriers and improving the reliability of the semiconductor device 100A. For example, with such an improvement, the semiconductor device 100A will allow a higher critical current Id (i.e., drain current) to flow therein, and also allow a higher drain-to-source voltage Vds (drain-to-source voltage) as the on-resistance (Ron) begins to decrease. With such a contribution, the voltage application range in the semiconductor device 100A can be higher than that in the previous device. Accordingly, the semiconductor device 100A having such a p-type doped III-V group compound/nitride semiconductor layer is also referred to as a reduced surface field (RESURF) device performed at a high or ultra-high voltage. In addition to the above mechanism, since the electric field at the drain edge is suppressed, the electric field strength can be effectively discharged, which can enhance the breakdown voltage of the semiconductor device 100A. In some embodiments, the semiconductor device 100A is allowed to operate under high voltage conditions in the range of about 20V to about 1200V. In various embodiments, the reliability of the semiconductor device 100A may allow the semiconductor device 100A to operate at a breakdown voltage of at least about 20V.
In addition, a p-type doped III-V compound/nitride semiconductor layer 150 is disposed at a position between the gate structure 140 and the drain electrode 148, since the resistance from the 2DEG region 134 to the drain electrode 148 is considered.
Referring to fig. 1B, a p-type doped III-V compound/nitride semiconductor layer 150 has a plurality of p-type doped III-V compound/nitride semiconductor islands 152. In some embodiments, each p-type doped III-V compound group/nitride semiconductor island 152 is rectangular and has a length between about 0.1 microns (μm) to about 3 microns and a width between about 0.1 microns to about 3 microns. Here, the rectangular p-type doped III-V group compound/nitride semiconductor islands 152 are defined as viewed in a direction perpendicular to the second semiconductor layer 132. However, the present disclosure is not so limited and in other embodiments, each p-type doped III-V compound/nitride semiconductor island 152 may be other types of polygons. The width of the drain 148 may be greater than the width of the overlap between the drain 148 and any one of the p-type doped III-V compound/nitride semiconductor islands 152.
The p-type doped group III-V compound/nitride semiconductor islands 152 may be separated from each other by at least the drain electrodes 148 and may be aligned in a direction (e.g., a longitudinal direction of fig. 1B) by the same pitch SP. In some embodiments, the pitch SP of the p-type doped III-V compound/nitride semiconductor islands 152 is in the range of about 0.1 microns to about 10 microns. Further, the drain 148 may fill in the spaces between the p-type doped III-V compound/nitride semiconductor islands 152 such that each p-type doped III-V compound/nitride semiconductor island 152 has two opposing side surfaces SS3 and SS4 that are at least partially covered by the drain 148.
On the other hand, as shown in fig. 1C, which shows a cross-sectional view along line 1C-1C in fig. 1B, since the p-type doped III-V compound/nitride semiconductor islands 152 form some of the bumps 154 that protrude from the top surface of the semiconductor layer 132, the drain 148 covering the p-type doped III-V compound/nitride semiconductor islands 152 and the semiconductor layer 132 may conform to the contour of the islands 152. Specifically, the drain 148 has a top surface ST1 and is located above the space between the bumps 154, and also has a top surface ST2 and is located above the bumps 154, and the top surface ST1 of the drain 148 is located lower than the top surface ST2 of the drain 148. This conformal profile can be used as evidence that the formed drain 148 is covered with bump-like p-type doped III-V compound/nitride semiconductor islands 152 arranged at the same pitch SP.
Exemplary materials of the P-type doped III-V compound/nitride semiconductor layer 150 may include, but are not limited to, P-type doped nitride semiconductor materials such as P-type gallium nitride (GaN), P-type aluminum gallium nitride (AlGaN), P-type indium nitride (InN), P-type aluminum indium nitride (AlInN), P-type indium gallium nitride (InGaN), P-type aluminum indium gallium nitride (AlInGaN), or combinations thereof, for example. In some embodiments, p-type doping materials can Be achieved by using p-type impurities, such as beryllium (Be), magnesium (Mg), zinc (Zn), cadmium (Cd). In one embodiment, the p-type doped group III-V compound/nitride semiconductor layers 142 and 150 have the same thickness of p-type doped group III-V/nitride semiconductor material, and thus the p-type doped group III-V compound/nitride semiconductor layers 142 and 150 may be selectively formed in the same process, which is advantageous in simplifying the manufacturing process of the semiconductor device 100A. At one isIn an embodiment, semiconductor layer 130 comprises undoped GaN, semiconductor layer 132 comprises AlGaN, and both p-type doped III-V compound layers 142 and 150 comprise p-type GaN. Since the size of the p-type doped III-V compound/nitride semiconductor layer/island 150/152 is related to the degree of reduction of the electric field at the drain edge, dimensions that fall outside the design range (i.e., the size range described above) may have less of an impact. Further, the doping concentration of the p-type doped group III-V compound/nitride semiconductor layer 150 may be at 1 × 10 17 cm -3 To 1X 10 20 cm -3 In the presence of a surfactant. Likewise, doping concentrations outside this design range may result in a reduced electric field.
Referring back to fig. 1A and 1B, the semiconductor device 100A further includes one or more dielectric layers 160 disposed on the semiconductor layer 132 and covering the gate structure 140. In addition, the dielectric layer 160 also at least partially covers the p-type doped group III-V compound/nitride semiconductor layer 150. For example, the side surface SS2 of the p-type doped III-V compound/nitride semiconductor layer 150 is covered by the dielectric layer 160, and the top surface ST and the two opposing side surfaces SS3 and SS4 thereof are also at least partially covered by the dielectric layer 160 and form an interface therebetween. That is, all side surfaces SS1-SS4 of the p-type doped group III-V compound/nitride semiconductor layer 150 are collectively covered by the dielectric layer 160 and the drain electrode 148, so that the p-type doped group III-V compound/nitride semiconductor layer 150 is completely covered by the combination of the semiconductor layer 132, the dielectric layer 160 and the drain electrode 148. In some embodiments, the dielectric layer 160 may serve as a passivation layer to protect underlying components or layers. In various embodiments, the dielectric layer 160 has an uppermost surface that is planar, which can serve as a planar substrate to carry the layer formed after the dielectric layer 160 is formed. Exemplary materials for the dielectric layer 160 may include, for example, but are not limited to, silicon nitride (SiN) x ) Silicon oxide (SiO) x ) Silicon oxynitride (SiON), silicon carbide (SiC), silicon boron nitrogen (SiBN), silicon carbo-nitride-boron (SiCBN), oxides, nitrides or combinations thereof. In some embodiments, the dielectric layer 160 is a multilayer structure, such as alumina/silicon nitride (Al) 2 O 3 /SiN), alumina/silica (Al) 2 O 3 /SiO 2 ) Aluminum nitride/silicon nitride (AlN/SiN), aluminum nitride/silicon oxide (AlN/SiO) 2 ) Or a combination thereof.
Optionally, the semiconductor device 100A further comprises a source field plate 162 disposed over the source electrode 146, a first via (via)164 between the source field plate 162 and the source electrode 146, a drain field plate 166 disposed over the drain electrode 148, and a second via 168 between the drain field plate 166 and the drain electrode 148, wherein the height of the source field plate 162 and the drain field plate 166 may be greater than the height of the gate structure 140 relative to the semiconductor layer 132.
Source field plate 162 may extend from a position above source 146 to a position above gate structure 140. In some embodiments, source field plate 162 has an extension length that is greater than the distance from source 146 to gate structure 140. That is, the vertical projection of the gate structure 140 onto the semiconductor layer 132 falls within the vertical projection of the source field plate 162 onto the semiconductor layer 132. A first via 164 connects the source electrode 146 and the source field plate 162 such that the source electrode 146 and the source field plate 162 are electrically coupled to each other.
A drain field plate 166 extends from a location above the drain 148 toward a location above the gate structure 140. In some embodiments, the extended length of the drain field plate 166 is less than the distance from the drain 148 to the gate structure 140. That is, the vertical projection of the gate structure 140 onto the semiconductor layer 132 exceeds the vertical projection of the drain field plate 166 onto the semiconductor layer 132. In some embodiments, the extended length of the drain field plate 166 is greater than the width or length of the p-type doped III-V compound/nitride semiconductor layer 150 such that a vertical projection of the drain field plate 166 onto the semiconductor layer 132 at least partially overlaps a vertical projection of the p-type doped III-V compound/nitride semiconductor layer 150 onto the semiconductor layer 132. In the exemplary illustration of fig. 1A, the vertical projection of the p-type doped III-V compound/nitride semiconductor layer 150 falls within the vertical projection of the drain field plate 166 on the semiconductor layer 132. A second via 168 connects the drain electrode 148 and the drain field plate 166 such that the drain electrode 148 and the drain field plate 166 are electrically coupled to each other.
The source field plate 162 and the drain field plate 166 can change the electric field distribution of the source region and the drain region and thereby affect the breakdown voltage of the semiconductor device 100A. In other words, the source field plate 162 and the drain field plate 166 can desirably suppress the electric field distribution of the target region and reduce the peak thereof. Exemplary materials for source field plate 162 and drain field plate 166 can include, for example, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), other suitable conductor materials, or combinations thereof.
Referring to fig. 2, which illustrates a top view of a semiconductor device 100B according to some embodiments of the present disclosure, at least one difference between the present embodiment and the previous embodiments is that each p-type doped III-V compound/nitride semiconductor island 152 has an approximately circular configuration as viewed along a direction perpendicular to the semiconductor layer (see semiconductor layer 132 in fig. 1A or 1C). With this arrangement, the interface of the drain 148 and the p-type doped III-V compound/nitride semiconductor island 152 also includes a curvilinear boundary, which may correspond to the circular arrangement of the p-type doped III-V compound/nitride semiconductor island 152. In the exemplary illustration of fig. 2, for each p-type doped III-V compound/nitride semiconductor island 152, approximately half of it is covered by the drain 148 and the other half is not covered by the drain 148 (i.e., it is covered by the dielectric layer). Thus, for a single p-type doped III-V compound/nitride semiconductor island 152, the two portions thereof that are covered by the drain 148 and not covered by the drain 148, respectively, are semicircular symmetrical to each other. However, the present disclosure is not so limited and in other embodiments, the ratio between the covered portion and the uncovered portion of a single p-type doped group III-V compound/nitride semiconductor island 152 may be adjusted.
Referring to fig. 3, which illustrates a top view of a semiconductor device 100C according to some embodiments of the present disclosure, at least one difference between the present embodiment and the previous embodiments is that each p-type doped III-V compound/nitride semiconductor island 152 exhibits a tapered profile as viewed along a direction perpendicular to the semiconductor layer (see semiconductor layer 132 in fig. 1A or 1C). In the exemplary illustration of fig. 3, for a single tapered p-type doped III-V compound/nitride semiconductor island 152, the shorter side of the taper profile is covered by drain 148 while the longer side is not covered by drain 148 (i.e., it is covered by a dielectric layer). Likewise, the ratio between the covered and uncovered portions of a single p-type doped III-V compound/nitride semiconductor island 152 is adjustable.
In the present disclosure, the shape of the p-type doped III-V group compound/nitride semiconductor islands 152 is not limited to the above-described embodiments, but may be other two-dimensional shapes such as polygons, ellipses, or combinations thereof (even combinations of the previously described shapes) when the line of sight is along a direction perpendicular to the semiconductor layer.
Referring to fig. 4A and 4B, which illustrate a cross-sectional view and a top view of a semiconductor device 100D according to some embodiments of the present disclosure, at least one difference between this embodiment and the previous embodiments is that the upper surface ST of the p-type doped III-V compound/nitride semiconductor layer 150 is not covered by the drain 148. Specifically, in the exemplary illustrations of fig. 4A and 4B, side surface SS1 of p-type doped III-V/nitride semiconductor island 152 interfaces with drain 148, while the remaining side surfaces SS2-SS4 of p-type doped III-V/nitride semiconductor island 152 interface with dielectric layer 160. Thus, the vertical projections of the p-type doped group III-V compound/nitride semiconductor layer 150 and the drain electrode 148 on the semiconductor layer 132 may have edges that coincide with each other, as shown in fig. 4B.
The semiconductor device 100D further includes a conductive layer 170 disposed on the p-type doped III-V compound/nitride semiconductor layer 150 and also includes a third via 172 that is located between the conductive layer 170 and the drain field plate 166. The conductive layer 170 contacts the upper surface ST of the p-type doped group III-V compound/nitride semiconductor layer 150, and the third via 172 connects the drain field plate 166 and the conductive layer 170 so that the drain field plate 166 and the p-type doped group III-V compound/nitride semiconductor layer 150 are electrically coupled to each other. In some embodiments, the conductive layer 170 is a metal layer and may be formed by the same process as the conductive gate 144, and thus the conductive layer 170 and the conductive gate 144 may have the same thickness and composition.
In the present disclosure, the relationship between the p-type doped III-V compound/nitride semiconductor layer 150 and the drain electrode 148 is not limited to the relationship illustrated in the drawings. In other embodiments, the p-type doped III-V compound/nitride semiconductor layer 150 may be formed further away from the drain 148 such that the p-type doped III-V compound/nitride semiconductor layer 150 can be separated from the drain 148 by the dielectric layer 160 and all side surfaces SS1-SS4 of the p-type doped III-V compound/nitride semiconductor island 152 are covered by the dielectric layer 160. The relationship between the P-type doped III-V compound/nitride semiconductor layer 150 and the drain electrode 148 is adjustable, and the effect of reducing the drain-side electric field provided by the P-type doped III-V compound/nitride semiconductor layer 150 remains unchanged. Therefore, it is flexible to the process of manufacturing the semiconductor device 100D. The location of formation of the p-type doped III-V compound/nitride semiconductor layer 150 is selectable depending on the final application of the semiconductor device and depending on the desired shape of the drain electric field profile.
Referring to fig. 5A and 5B, which illustrate a cross-sectional view and a top view of a semiconductor device 100E according to some embodiments of the present disclosure, at least one difference between the present embodiment and the previous embodiments is that the upper surface ST of the p-type doped III-V compound/nitride semiconductor layer 150 is completely covered by the drain electrode 148. Specifically, in the exemplary illustration of fig. 5A and 5B, p-type doped III-V compound/nitride semiconductor layer 150 is embedded in drain 148 such that side surfaces SS2 of p-type doped III-V compound/nitride semiconductor islands 152 are in a coplanar relationship with side surfaces of drain 148, wherein the side surfaces of drain 148 are above semiconductor layer 132 and face gate structure 140. Therefore, the vertical projection of the p-type doped group III-V compound/nitride semiconductor layer 150 on the semiconductor layer 132 falls within the vertical projection of the drain electrode 148 on the semiconductor layer 132, and the edge thereof coincides with the edge of the vertical projection of the drain electrode 148. In such a structural configuration, the p-type doped group III-V compound/nitride semiconductor layer 150 can still reduce the electric field on the drain side, which is advantageous in making the process of the semiconductor device 100E flexible.
In the present disclosure, a method of manufacturing a semiconductor device having a p-type doped III-V compound/nitride semiconductor layer capable of reducing a drain fringe electric field is also provided. As shown in fig. 6A-6C, different stages in a method for manufacturing the semiconductor device 100A are illustrated, wherein the stages may also be applied to other semiconductor devices of the different embodiments described above.
Referring to fig. 6A, a substrate 110 is prepared, and one or more buffer layers 120, a semiconductor layer 130 and a semiconductor layer 132 are sequentially formed on the substrate 110. In some embodiments, the buffer layer 120, the semiconductor layer 130, and the semiconductor 132 may be formed by using Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), epitaxial growth (epitaxial growth), or other suitable processes.
Referring to fig. 6B, a p-type doped III-V compound/nitride semiconductor cladding layer 136 is formed on the semiconductor layer 132. In some embodiments, the p-type doped group III-V compound/nitride semiconductor cap layer 136 may be formed by using an epitaxial growth process. In various embodiments, the p-type doped group III-V compound/nitride semiconductor cap layer 136 may be formed by using a combination of deposition and ion implantation (ion implantation). For example, ALD, PVD, CVD, or MOCVD may be used to form the III-V compound/nitride semiconductor cap layer, followed by ion implantation such that the III-V compound/nitride semiconductor cap layer is doped with impurities to become the p-type doped III-V compound/nitride semiconductor cap layer 136.
Referring to fig. 6C, a patterning process may be performed on the p-type doped group III-V compound/nitride semiconductor cladding layer 136 to form a p-type doped group III-V compound/nitride semiconductor layer 150 and a p-type doped group III-V compound/nitride semiconductor layer 142 separated from each other, wherein the p-type doped group III-V compound/nitride semiconductor layer 150 is further patterned into a plurality of p-type doped group III-V compound/nitride semiconductor islands as described above.
Through the patterning process, the shape and location of the p-type doped group III-V compound/nitride semiconductor islands (i.e., their locations on the second semiconductor layer 132) can be determined. For example, the mask used in the patterning process may have openings and it is used to define the shape of the p-type doped group III-V compound/nitride semiconductor islands. In some embodiments, the patterning process may be performed by photolithography, exposure and development, etching, other suitable processes, or a combination thereof.
After the stage of fig. 6C, metal gates, source electrodes, drain electrodes, vias and field plates may be formed on semiconductor layer 132. In some embodiments, the metal gate, source, drain, via, and field plate may be formed using a deposition process. The resulting structure is shown in FIGS. 1A-1C.
In some embodiments, the interfacial area between the drain and the p-type doped group III-V compound/nitride semiconductor layer increases (i.e., gradually increases) as the deposition process proceeds during the formation of the drain by the deposition process. In addition, at least one dielectric layer 160 may be formed on the semiconductor layer 132 during the processes used to form these structures. Also, the formed dielectric materials may be combined with each other at different stages, thereby forming a dielectric layer structure on the semiconductor layer 132.
The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. It is intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will be apparent to practitioners skilled in the art.
The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
Terms as used herein, and not otherwise defined, such as "substantially," "approximately," and "about," are used for descriptive and explanatory purposes as small variations. When used with an event or condition, the term can include instances where the event or condition occurs precisely as well as instances where the event or condition occurs approximately. For example, when used with numerical values, the term can encompass a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. By the term "substantially coplanar", it may refer to two surfaces lying in the micrometer range along the same plane, for example within 40 micrometers (μm), within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane.
As used herein, the singular terms "a", "an" and "the" may include the plural reference unless the context clearly dictates otherwise. In the description of some embodiments, a component that is provided "above" or "on top of" another component may include situations where the former component is directly on (e.g., in physical contact with) the latter component, and situations where one or more intervening components are located between the former and the latter component.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not to be construed in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents substituted for elements thereof without departing from the true spirit and scope of the disclosure as defined in the following claims. The drawings are not necessarily to scale. Due to manufacturing process and tolerance factors, there may be a distinction between the processes presented in this disclosure and the actual devices. Other embodiments of the disclosure may not be specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein are described by performing particular operations in a particular order with reference to that order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of such operations is not limiting.

Claims (18)

1. A semiconductor device, comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer;
a source electrode and a drain electrode disposed on the second nitride semiconductor layer;
a gate electrode disposed on the second nitride semiconductor layer and between the source electrode and the drain electrode;
a first p-type doped nitride semiconductor layer disposed on the second nitride semiconductor layer and between the gate and the drain, wherein the first p-type doped nitride semiconductor layer includes a first p-type doped nitride semiconductor island, a second p-type doped nitride semiconductor island, and a third p-type doped nitride semiconductor island that are separated from each other, and the second p-type doped nitride semiconductor island is located between the first p-type doped nitride semiconductor island and the third p-type doped nitride semiconductor island, wherein a portion of the drain is filled in a space between the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island, as viewed in a direction perpendicular to the second nitride semiconductor layer, toward the first p-type doped nitride semiconductor island, The second p-type doped nitride semiconductor island and the third p-type doped nitride semiconductor island each having a tapered shape, in the tapered profile of each of the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island, the shorter side thereof is covered by the drain and the longer side thereof is not covered by the drain;
a second p-type doped nitride semiconductor layer disposed on the second nitride semiconductor layer and between the second nitride semiconductor layer and the gate electrode; and
a drain field plate disposed above the first p-type doped nitride semiconductor layer so as to be directly above the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island.
2. The semiconductor device according to claim 1, wherein the portion of the drain is formed higher than the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island.
3. The semiconductor device according to claim 1, further comprising:
and a dielectric layer at least covering the second nitride semiconductor layer, the gate electrode and the first p-type doped nitride semiconductor layer.
4. The semiconductor device according to claim 3, wherein a part of the dielectric layer is further filled in a space between the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island.
5. The semiconductor device of claim 4, wherein the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island each have a side surface, and the dielectric layer covers the side surface.
6. The semiconductor device according to claim 4, wherein the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island each have a top surface, and the dielectric layer covers the top surface, and in a tapered profile of each of the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island, a shorter side thereof is covered by the drain and a longer side thereof is not covered by the drain.
7. The semiconductor device according to claim 1, wherein the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island are arranged along a direction by the same pitch.
8. The semiconductor device of claim 7, said pitch being in the range of 0.1 microns to 10 microns.
9. The semiconductor device of claim 1, wherein the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island and second p-type doped nitride semiconductor layer of the first p-type doped nitride semiconductor layer have the same thickness and have the same p-type doped group III-V/nitride semiconductor material.
10. The semiconductor device of claim 9, wherein the first nitride semiconductor layer comprises undoped gallium nitride (GaN), the second nitride semiconductor layer comprises aluminum gallium nitride (AlGaN), the first, second, and third p-type doped nitride semiconductor islands of the first p-type doped nitride semiconductor layer each comprise p-type gallium nitride (p-GaN), and the second p-type doped nitride semiconductor layer comprises p-type gallium nitride (p-GaN).
11. The semiconductor device according to claim 1, wherein the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island each contact the drain, thereby forming an interface.
12. The semiconductor device of claim 11, wherein the interface is curvilinear.
13. The semiconductor device of claim 11, wherein an edge of the drain is closer to the gate than the interface.
14. The semiconductor device of claim 13, wherein the edge of the drain is located above the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island.
15. The semiconductor device of claim 1, wherein the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island each have a length between 0.1 micrometers and 3 micrometers and a width between 0.1 micrometers and 3 micrometers.
16. The semiconductor device of claim 1, further comprising a via connecting said drain electrode with said drain field plate and extending upwardly from said drain electrode to said drain field plate.
17. The semiconductor device according to claim 16, wherein a contact position of the drain with the via is higher than the first p-type doped nitride semiconductor island, the second p-type doped nitride semiconductor island, and the third p-type doped nitride semiconductor island.
18. The semiconductor device of claim 1, wherein the first, second, and third p-type doped nitride semiconductor islands each comprise p-type gallium nitride (GaN), p-type aluminum gallium nitride (AlGaN), p-type indium nitride (InN), p-type aluminum indium nitride (AlInN), p-type indium gallium nitride (InGaN), p-type aluminum indium gallium nitride (AlInGaN), or a combination thereof.
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