WO2010143881A3 - 반도체 검증용 ｆｐｇａ 보드의 뱅크구조 - Google Patents

반도체 검증용 ｆｐｇａ 보드의 뱅크구조 Download PDF

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Publication number
WO2010143881A3
WO2010143881A3 PCT/KR2010/003692 KR2010003692W WO2010143881A3 WO 2010143881 A3 WO2010143881 A3 WO 2010143881A3 KR 2010003692 W KR2010003692 W KR 2010003692W WO 2010143881 A3 WO2010143881 A3 WO 2010143881A3
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WO
WIPO (PCT)
Prior art keywords
fpga
allocated
locations
connectors
board
Prior art date
Application number
PCT/KR2010/003692
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English (en)
French (fr)
Other versions
WO2010143881A2 (ko
Inventor
국일호
박종진
한창석
강성태
Original Assignee
(주)브이알인사이트
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by (주)브이알인사이트 filed Critical (주)브이알인사이트
Publication of WO2010143881A2 publication Critical patent/WO2010143881A2/ko
Publication of WO2010143881A3 publication Critical patent/WO2010143881A3/ko

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G01R31/318519—Test of field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31915—In-circuit Testers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

본 발명은 반도체 검증용 FPGA 보드의 뱅크구조에 관한 것으로, 반도체 설계물 검증을 위한 프로그래머블 로직 디바이스(PLD) 보드에 있어서, 반도체 검증을 위한 논리회로가 내장된 FPGA 소자와 여기에 신호를 입/출력하기 위한 다수의 커넥터가 구비된 적어도 하나 이상의 FPGA 보드 및 상기 FPGA 소자에 구성되는 다수의 입/출력핀을 임의의 개수로 나누어 다수의 영역으로 각각 할당하고, 각 할당된 영역에 대응하게 상기 FPGA보드에 구비된 커넥터에도 다수의 영역으로 할당하며, 상기 FPGA 소자의 입/출력핀 할당영역과 커넥터에 할당된 영역을 대응하게 집적화시켜 구성되는 것을 특징으로 한다. 이와 같이 구성되는 본 발명은 FPGA 보드를 구성하는데 있어 FPGA 소자와 커넥터간의 연결을 최적화시킬 수 있는 이점이 있다.
PCT/KR2010/003692 2009-06-12 2010-06-09 반도체 검증용 ｆｐｇａ 보드의 뱅크구조 WO2010143881A2 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2009-0052439 2009-06-12
KR20090052439A KR101090303B1 (ko) 2009-06-12 2009-06-12 반도체 검증용 ｆｐｇａ 보드의 뱅크구조

Publications (2)

Publication Number Publication Date
WO2010143881A2 WO2010143881A2 (ko) 2010-12-16
WO2010143881A3 true WO2010143881A3 (ko) 2011-03-31

Family

ID=43309362

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/003692 WO2010143881A2 (ko) 2009-06-12 2010-06-09 반도체 검증용 ｆｐｇａ 보드의 뱅크구조

Country Status (2)

Country Link
KR (1) KR101090303B1 (ko)
WO (1) WO2010143881A2 (ko)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000013186U (ko) * 1998-12-23 2000-07-15 서평원 보드 계측용 테스트 보드
KR20020095620A (ko) * 2001-06-15 2002-12-28 주식회사 마이다스엔지니어링 라이터 일체형 씨피엘디 에프피지에이 보드
KR20040023699A (ko) * 2001-07-30 2004-03-18 액시스 시스템즈, 인크. 동작 프로세서 시스템 및 방법
KR100581237B1 (ko) * 1998-04-01 2006-05-22 몰렉스 인코포레이티드 테스트용 소켓의 격자 배열

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993012638A1 (en) 1991-12-18 1993-06-24 Crosspoint Solutions, Inc. Extended architecture for field programmable gate array
JP2001318124A (ja) 2000-05-09 2001-11-16 Hitachi Ltd 論理モジュール
JP2006079447A (ja) 2004-09-10 2006-03-23 Fujitsu Ltd 集積回路設計支援装置、集積回路設計支援方法及び集積回路設計支援プログラム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100581237B1 (ko) * 1998-04-01 2006-05-22 몰렉스 인코포레이티드 테스트용 소켓의 격자 배열
KR20000013186U (ko) * 1998-12-23 2000-07-15 서평원 보드 계측용 테스트 보드
KR20020095620A (ko) * 2001-06-15 2002-12-28 주식회사 마이다스엔지니어링 라이터 일체형 씨피엘디 에프피지에이 보드
KR20040023699A (ko) * 2001-07-30 2004-03-18 액시스 시스템즈, 인크. 동작 프로세서 시스템 및 방법

Also Published As

Publication number Publication date
KR101090303B1 (ko) 2011-12-07
KR20100133741A (ko) 2010-12-22
WO2010143881A2 (ko) 2010-12-16

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