WO2010139216A1 - 实现在扩展处理器和交换芯片之间传输报文的方法和系统 - Google Patents
实现在扩展处理器和交换芯片之间传输报文的方法和系统 Download PDFInfo
- Publication number
- WO2010139216A1 WO2010139216A1 PCT/CN2010/072207 CN2010072207W WO2010139216A1 WO 2010139216 A1 WO2010139216 A1 WO 2010139216A1 CN 2010072207 W CN2010072207 W CN 2010072207W WO 2010139216 A1 WO2010139216 A1 WO 2010139216A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- packet
- switch chip
- destination mac
- message
- chip
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3009—Header conversion, routing tables or routing tags
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/50—Routing or path finding of packets in data switching networks using label swapping, e.g. multi-protocol label switch [MPLS]
Definitions
- the present invention relates to the field of communications technologies, and in particular, to a method and system for implementing transmission of messages between an extension processor and a switching chip. Background technique
- the physical port connected to the CPU on the switch chip is usually a special port of the switch chip.
- the packet carries the source physical port information.
- the destination port of the switch chip can be specified, so that the CPU can be configured. Normally send and receive packets.
- the switch chip cannot transmit the source physical port information when the extended processor receives the packet; the switch chip cannot specify the physics of the message when the extended processor sends the packet. port. This results in the inability to transfer messages between the extended processor and the switch chip. Summary of the invention
- the technical problem to be solved by the present invention is to provide a method and system for transmitting messages between an extension processor and a switch chip, so as to implement transmission of messages between the extension processor and the switch chip.
- the technical solution of the present invention is implemented as follows: A method for transmitting a message between an extension processor and a switch chip, the method comprising:
- the switching chip sends the first packet to the extension processor, and the first destination message is sent to the extension processor, where the first destination MAC address is sent to the extension processor.
- the switching chip corresponding to the MAC is configured to receive a service physical port of the first packet;
- the extension processor parses the first destination MAC, and learns that the first packet is from the physical port of the service.
- the method further includes:
- the extension processor adds related information to a second packet for sending to the switch chip, and sends the second packet to the switch chip; the related information includes a second destination MAC and a multi-protocol Label Switching (MPLS) tunnel label.
- MPLS multi-protocol Label Switching
- the method further includes:
- the switching chip determines an egress port of the second packet according to the second destination MAC and the MPLS tunnel label.
- Determining, by the switch chip, the egress port of the second packet according to the second destination MAC and the MPLS tunnel label includes:
- the switching chip determines, according to the second destination MAC, that the second packet needs to perform MPLS processing
- the switching chip performs tunnel termination on the second packet according to the label value of the MPLS tunnel label, and learns an egress port corresponding to the label value.
- the method for tunnel termination of the second packet by the switch chip is:
- the switch chip removes the related information of the second packet.
- a system for transmitting messages between an extended processor and a switch chip including a switch core a slice and an extension processor, the switch chip comprising a service physical port for receiving a first message processed by the extension processor, where:
- the switching chip is configured to: after modifying the destination MAC address of the first packet to be the first destination MAC address of the service physical port, send the modified first packet to the extension processor; And configured to parse the first destination MAC, and learn that the first packet is from the service physical port.
- the extension processor is further configured to add related information to a second packet for sending to the switch chip, and send the second packet to the switch chip; the related information includes a second purpose MAC and multi-protocol label switching MPLS tunnel labels.
- the switch chip is further configured to determine an egress port of the second packet according to the second destination MAC and the MPLS tunnel label.
- the number of the switch chip and the extension processor is one, respectively.
- the system is set up in the switch device.
- the switch chip of the present invention can modify the destination MAC of the packet to be sent to the extended processor to be the destination MAC of the port corresponding to the switch chip receiving the packet, so that the extended processor can know the source of the packet. .
- the invention enables the transmission of messages between the extension processor and the switch chip.
- FIG. 1 is a block diagram of a system connection for implementing an extended processor transceiver packet according to a preferred embodiment of the present invention
- FIG. 2 is a specific flowchart of a method for implementing an extended processor transceiver packet according to a preferred embodiment of the present invention. detailed description
- a system for transmitting messages between chips comprising at least one switch chip and at least one extended processor, the switch chip comprising a physical port 32 and a service physical port 1-20 for connecting the extended processor.
- the switching chip is configured to send the message to the extension processor after receiving the destination MAC of the packet, and receive the packet from the extension processor according to the received packet.
- the destination MAC and MPLS tunnel labels determine the outgoing port of the packet.
- the extension processor is configured to parse the destination MAC address of the packet from the switch chip to learn the physical port of the service from which the packet is sent, and send the packet to the switch chip after adding the related information to the packet for sending to the switch chip, where relevant
- the information includes the destination MAC and MPLS tunnel label of the message.
- the switch chip receives the packet sent from the physical port 3 of the service for sending to the extended processor, and then the destination MAC of the modified message is 00.00.00.00.00.03 and then sent to the extended processor through the physical port 32.
- the destination MAC address is 00.00.00.00.00.03 corresponding to the physical port 3 of the service.
- the packet used for sending to the extension processor is a packet of Ethernet type 0xfe47.
- the extended processor parses the destination MAC address of the packet to be 00.00.00.00.00.03, so that the packet is sent from the physical port 3 of the switch chip, and is sent in the packet to be sent.
- the related information is added to the switch, and the related information includes the destination MAC (01.02.03.04.05.06) and the MPLS label (the label value is set to 1048558). Then, the packet with the added information is sent to the switch chip through the physical port 32.
- the switch chip After receiving the packet that is received from the physical port 32, the switch chip performs MPLS processing on the packet according to the destination MAC address of the packet (01.02.03.04.05.06), and according to the label value of the MPLS label of the packet, 1048558.
- the packet is terminated by the tunnel (the tunnel termination refers to the extension processor removing the added information and restoring the original packet), and the label value of the MPLS label according to the packet is 1048558.
- the packet is sent from the physical port 3 of the service.
- the tunnel is terminated.
- the egress port corresponding to the MPLS label value is the physical port 1 to 20, for example, the label value is 1048556.
- the outgoing port of the packet is the physical port 1 of the service; if the label value is 1048557, the outgoing port of the packet is the physical port 2 of the service.
- the switching chip of the present invention modifies the destination MAC of the packet to be sent to the extension processor to the destination MAC of the port corresponding to the switch chip receiving the packet, so that the extension processor can know the source of the packet.
- the method and system of the present invention enable the transmission of messages between the extension processor and the switching chip.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Small-Scale Networks (AREA)
- Computer And Data Communications (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP10782920.2A EP2439889B1 (en) | 2009-06-05 | 2010-04-26 | Method and system for realizing transmission of messages between an extended processor and a switch chip |
AU2010256230A AU2010256230B2 (en) | 2009-06-05 | 2010-04-26 | Method and system for realizing transmission of message between an extended processor and a switch chip |
RU2011149882/08A RU2510142C2 (ru) | 2009-06-05 | 2010-04-26 | Способ и система для передачи сообщения между дополнительным процессором и переключающей схемой |
US13/375,266 US8576849B2 (en) | 2009-06-05 | 2010-04-26 | Method and system for realizing transmission of message between an extended processor and switch chip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2009101076789A CN101610217B (zh) | 2009-06-05 | 2009-06-05 | 实现在扩展处理器和交换芯片之间传输报文的方法和系统 |
CN200910107678.9 | 2009-06-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010139216A1 true WO2010139216A1 (zh) | 2010-12-09 |
Family
ID=41483808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2010/072207 WO2010139216A1 (zh) | 2009-06-05 | 2010-04-26 | 实现在扩展处理器和交换芯片之间传输报文的方法和系统 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8576849B2 (zh) |
EP (1) | EP2439889B1 (zh) |
CN (1) | CN101610217B (zh) |
AU (1) | AU2010256230B2 (zh) |
RU (1) | RU2510142C2 (zh) |
WO (1) | WO2010139216A1 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101610217B (zh) * | 2009-06-05 | 2011-08-24 | 中兴通讯股份有限公司 | 实现在扩展处理器和交换芯片之间传输报文的方法和系统 |
CN103209141A (zh) * | 2012-01-17 | 2013-07-17 | 中兴通讯股份有限公司 | 一种交换芯片处理数据报文的方法及交换芯片 |
CN107517105A (zh) * | 2017-09-18 | 2017-12-26 | 北京百卓网络技术有限公司 | 线卡和通信设备 |
CN112437028A (zh) * | 2020-12-10 | 2021-03-02 | 福州创实讯联信息技术有限公司 | 一种嵌入式系统扩展多个网口的方法及系统 |
CN115801710B (zh) * | 2023-01-10 | 2023-04-21 | 北京六方云信息技术有限公司 | Cpu接口的扩展方法、装置、设备及存储介质 |
Citations (4)
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CN1608250A (zh) * | 2001-12-28 | 2005-04-20 | 英特尔公司 | 一种用于扩展处理器的局部存储器地址空间的方法 |
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CN101610217A (zh) * | 2009-06-05 | 2009-12-23 | 中兴通讯股份有限公司 | 实现在扩展处理器和交换芯片之间传输报文的方法和系统 |
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US5434850A (en) * | 1993-06-17 | 1995-07-18 | Skydata Corporation | Frame relay protocol-based multiplex switching scheme for satellite |
US6795448B1 (en) * | 2000-03-02 | 2004-09-21 | Intel Corporation | IP packet ready PBX expansion circuit for a conventional personal computer with expandable, distributed DSP architecture |
US6868086B1 (en) * | 2000-03-29 | 2005-03-15 | Intel Corporation | Data packet routing |
US7120683B2 (en) * | 2000-04-03 | 2006-10-10 | Zarlink Semiconductor V.N. Inc. | Single switch image for a stack of switches |
US7424012B2 (en) * | 2000-11-14 | 2008-09-09 | Broadcom Corporation | Linked network switch configuration |
US7068654B1 (en) * | 2001-04-18 | 2006-06-27 | 3Com Corporation | System and method for providing masquerading using a multiprotocol label switching |
JP4703657B2 (ja) * | 2004-11-05 | 2011-06-15 | 株式会社東芝 | ネットワーク探索方法 |
CN100446501C (zh) * | 2006-07-17 | 2008-12-24 | 华为技术有限公司 | 一种辅助cpu转发报文的方法及系统 |
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JP4823331B2 (ja) * | 2009-04-13 | 2011-11-24 | 富士通株式会社 | ネットワーク接続装置及びスイッチング回路装置、並びにアドレス学習処理方法 |
-
2009
- 2009-06-05 CN CN2009101076789A patent/CN101610217B/zh not_active Expired - Fee Related
-
2010
- 2010-04-26 RU RU2011149882/08A patent/RU2510142C2/ru not_active IP Right Cessation
- 2010-04-26 EP EP10782920.2A patent/EP2439889B1/en active Active
- 2010-04-26 WO PCT/CN2010/072207 patent/WO2010139216A1/zh active Application Filing
- 2010-04-26 US US13/375,266 patent/US8576849B2/en not_active Expired - Fee Related
- 2010-04-26 AU AU2010256230A patent/AU2010256230B2/en not_active Ceased
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1608250A (zh) * | 2001-12-28 | 2005-04-20 | 英特尔公司 | 一种用于扩展处理器的局部存储器地址空间的方法 |
US20080037544A1 (en) * | 2006-08-11 | 2008-02-14 | Hiroki Yano | Device and Method for Relaying Packets |
CN101106532A (zh) * | 2007-07-10 | 2008-01-16 | 中兴通讯股份有限公司 | 实现交换芯片与网络处理器混合转发的方法 |
CN101610217A (zh) * | 2009-06-05 | 2009-12-23 | 中兴通讯股份有限公司 | 实现在扩展处理器和交换芯片之间传输报文的方法和系统 |
Also Published As
Publication number | Publication date |
---|---|
EP2439889A1 (en) | 2012-04-11 |
AU2010256230A1 (en) | 2012-01-12 |
CN101610217B (zh) | 2011-08-24 |
US8576849B2 (en) | 2013-11-05 |
EP2439889A4 (en) | 2018-03-21 |
EP2439889B1 (en) | 2020-10-14 |
AU2010256230B2 (en) | 2013-08-22 |
US20120076147A1 (en) | 2012-03-29 |
RU2510142C2 (ru) | 2014-03-20 |
RU2011149882A (ru) | 2013-08-27 |
CN101610217A (zh) | 2009-12-23 |
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