WO2010137262A1 - マルチプロセッサシステム、マルチプロセッサ制御方法、及びマルチプロセッサ集積回路 - Google Patents
マルチプロセッサシステム、マルチプロセッサ制御方法、及びマルチプロセッサ集積回路 Download PDFInfo
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- WO2010137262A1 WO2010137262A1 PCT/JP2010/003388 JP2010003388W WO2010137262A1 WO 2010137262 A1 WO2010137262 A1 WO 2010137262A1 JP 2010003388 W JP2010003388 W JP 2010003388W WO 2010137262 A1 WO2010137262 A1 WO 2010137262A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5083—Techniques for rebalancing the load in a distributed system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to a multiprocessor system including a plurality of processors.
- Such a multi-processor system has a feature that a task processing amount per unit time is larger than a processor system composed of a single processor because a plurality of processors can process tasks in parallel.
- home appliances such as digital TVs and mobile phones are required to have high functionality and low power consumption.
- Patent Document 1 As a technique for realizing low power consumption of an LSI (Large Scale Integration) mounted on a home appliance or the like, for example, a technique (Patent Document 1) that performs power supply control for each power island is known.
- each processor needs to communicate with the processor when, for example, the task processing result of another processor is used to process a task assigned to the own processor.
- processors that communicate with each other are not directly connected, they communicate via the processors on the connection path of these processors.
- a processor on the path of the communicating processor in addition to processing of tasks originally assigned to the own processor, routing processing related to communication between other processors that communicate with each other Must also be done.
- the above-described routing processing is efficiently performed, thereby reducing the power consumption related to the routing processing. It is required to do.
- the present invention has been made in view of such a problem, and an object thereof is to provide a multiprocessor system capable of assigning tasks to each processor so that routing processing can be performed efficiently.
- a processor system is a multiprocessor system that includes three or more processors with which each processor communicates with each other and performs processing of a task group, and that reflects a connection relationship between the processors Storage means for storing information, and task management means for assigning a task to be processed by each processor with reference to connection information stored in the storage means, the task management means in the task assignment, For the first processor and the second processor to which the number of processors assigned to tasks among the directly connected processors is smaller than that of the first processor, the amount of tasks assigned to the first processor Is greater than the amount of tasks allocated to the second processor. And performing allocation of click.
- a processor that is assigned a larger amount of tasks communicates with a processor that is assigned other tasks than a processor that is assigned a smaller amount of tasks. The amount tends to increase.
- the first processor connected to the processor to which the task is assigned is assigned more than the second processor than the second processor. Since tasks can be assigned to each processor so that the amount of tasks to be increased, it is possible to assign tasks to each processor so that routing processing can be performed efficiently.
- operating frequency determining means for determining the operating frequency of each processor, and operating each processor at the operating frequency determined by the operating frequency determining means
- the operation frequency determining means determines the operation frequency when the operation frequency of the first processor is the second processor.
- the operating frequency may be determined so as to be equal to or higher than the operating frequency of the processor.
- the operating frequency of the second processor to which the amount of tasks equal to or less than the amount of tasks allocated to the first processor is set to be equal to or lower than the operating frequency of the first processor. Therefore, it is possible to improve the power consumption efficiency with respect to the performance of the multiprocessor system by efficiently determining the operating frequency of each processor.
- a processor operating at the first operating frequency and a second operating frequency that is an operating frequency lower than the first operating frequency When there is an operating processor, the operating voltage of each processor is determined so that the operating voltage of the processor operating at the first operating frequency is equal to or higher than the operating voltage of the processor operating at the second operating frequency.
- Operating voltage determining means for performing the operation, and voltage supply means for supplying the operating voltage determined by the operating voltage determining means to each processor may be provided.
- the operating voltage of the processor operating at the second operating frequency that is an operating frequency lower than the first operating frequency is set to be equal to or lower than the operating voltage of the processor operating at the first operating frequency. Therefore, it is possible to improve the power consumption efficiency with respect to the performance of the multiprocessor system by efficiently determining the operating voltage of each processor.
- the task management means may perform the task assignment so that at least one of the processors connected to each processor to which the task is assigned is a processor to which the task is assigned. .
- This configuration has an effect that communication between processors to which tasks are assigned can be realized without causing a processor to which tasks are not assigned to perform routing processing.
- the operating frequency determining means determines the operating frequency to be determined so that the operating frequency of the processor becomes 0 hertz when there is a processor to which no task is assigned. Also good.
- the amount of the task may be the number of tasks.
- a processor that is assigned a larger number of tasks communicates with a processor that is assigned another task than a processor that is assigned a smaller number of tasks. The amount tends to increase.
- the task management means includes a timer for measuring the passage of time, and assigns the task with the largest amount of tasks allocated immediately before by the processor with the largest number of tasks to be assigned for each predetermined time. It may be characterized in that it is performed so as to be other than a processor.
- the amount of generated heat per unit time of a processor having the largest number of assigned tasks tends to be the largest among all the processors.
- the processor may be in a state where it does not operate correctly (thermal runaway state) when the temperature exceeds a predetermined temperature.
- thermal runaway state When processing is performed by a processor having a high temperature, compared to when executing by a processor having a low temperature, Power consumption increases.
- the processor with the largest number of assigned tasks changes every predetermined time, so compared with the case where the processor with the largest number of tasks is not intentionally changed.
- the processor with the largest number of tasks is not intentionally changed.
- processors included in the multiprocessor system are arranged in a matrix in one semiconductor integrated circuit, and each processor is a rectangle having the same shape as each other, and is directly connected to another adjacent processor. It may be a feature.
- the figure which shows the connection relation of the processor in multiprocessor LSI100 A block diagram showing a configuration of a power supply block in the multiprocessor LSI 100 Block diagram of clock controller 202
- Block diagram showing modules operating on the multiprocessor LSI 100
- Data structure diagram of OS task correspondence information Data structure diagram of voltage frequency information
- startup process flowchart A diagram representing the operation pattern information in the case of seven OSs to which tasks are assigned.
- the figure which shows the operating frequency and power supply voltage of each processor in a specific example A block diagram showing a configuration of a power supply selection circuit 1300 Block diagram showing modules operating on the modified multiprocessor LSI Deformation voltage frequency information Data structure diagram of connection information Startup process flowchart Flow chart of system load management processing Flow chart of processor selection processing Block diagram showing modules operating on the modified multiprocessor LSI Flow chart of modified system load management process Flow chart of modified processor selection process
- the figure which shows OS and the number of tasks allocated to each processor in a specific example The figure which shows the example by which 18 processors are arrange
- Each of the processors constituting the multiprocessor LSI can operate at an operating frequency and an operating voltage independent of each other.
- a hypervisor On the multiprocessor LSI, a hypervisor, a plurality of OSs operating on the hypervisor, and tasks assigned to the OS operate.
- the hypervisor assigns each OS to one processor and operates the OS on the assigned processor.
- FIG. 1 is a diagram showing a connection relationship of 25 processors A111 to Y135 arranged in the multiprocessor LSI 100. As shown in FIG. 1
- the processors A111 to Y135 are arranged in a 5 ⁇ 5 matrix. These 25 processors are processors of the same shape having the same functions, and operate in parallel with each other while communicating with other processors.
- the dedicated communication line group 141 to the dedicated communication line group 180 are communication line groups that connect adjacent processors.
- Each processor is connected to another adjacent processor via a dedicated communication line group.
- Communication between processors adjacent to each other is performed directly using a dedicated communication line group, and communication between processors not adjacent to each other is performed via processors on a connection path of these processors.
- a processor on the path of the communicating processor in addition to processing of tasks originally assigned to the own processor, routing processing related to communication between other processors that communicate with each other I do.
- processor A111 and the processor D114 communicate via the processor B112 and the processor C113.
- FIG. 2 is a block diagram showing the configuration of the power supply block in the multiprocessor LSI 100.
- the power supply block is a block composed of a plurality of circuits having a common power supply voltage, and each power supply block operates with a power supply voltage independent from each other.
- the multiprocessor LSI 100 has a fixed potential power supply block 201 and 26 power supply blocks including a power supply block A 211 to a power supply block Y 235.
- the fixed potential power supply block 201 is a power supply block whose power supply voltage is fixed to 1.2 V, and includes a clock control unit 202 and a voltage control unit 203.
- the clock control unit 202 is controlled by a hypervisor operating on the multiprocessor LSI 100, and has a function of supplying ClockA271 to ClockY295, which are clock signals, to the power supply block A211 to the power supply block Y235, respectively.
- each of ClockA271 to ClockY295 is set to any one frequency of 800 MHz, 600 MHz, 300 MHz, 100 MHz, and 0 Hz, independently of each other.
- FIG. 3 is a block diagram of the clock control unit 202.
- the clock control unit 202 includes a 2400 MHz PLL (Phase Locked Loop) 301, a 1/3 divider circuit 302, a 1/4 divider circuit 303, a 1/8 divider circuit 304, a 1/24 divider circuit 305, and a 5-1 selector. It consists of 311 to 5-1 selector 335 and the like, and outputs 25 clock signals of ClockA271 to ClockY295.
- PLL Phase Locked Loop
- Each of ClockA271 to ClockY295 has any one frequency of 800 MHz, 600 MHz, 300 MHz, 100 MHz, and 0 Hz.
- the 2400 MHz PLL 301 is a PLL that outputs a clock signal having a frequency of 2.4 GHz.
- the 1/3 frequency divider 302 divides the 2.4 GHz output signal of the 2400 MHz PLL 301 by 3 and outputs an 800 MHz signal.
- the 1/4 frequency divider 303 divides the 2.4 GHz output signal of the 2400 MHz PLL 301 by 4 and outputs a 600 MHz signal.
- the 1/8 frequency divider 304 divides the 2.4 GHz output signal of the 2400 MHz PLL 301 by 8 and outputs a 300 MHz signal.
- the 1/24 frequency dividing circuit 305 divides the 2.4 GHz output signal of the 2400 MHz PLL 301 by 24 and outputs a 100 MHz signal.
- the 5-1 selector 311 to the 5-1 selector 335 are an 800 MHz output signal from the 1/3 frequency divider 302, a 600 MHz output signal from the 1/4 frequency divider 303, and a 300 MHz output from the 1/8 frequency divider 304.
- This is a 5-input selector that selects any one of the signal, the 100 MHz output signal of the 1/24 frequency divider 305, and the ground 306 of the VSS potential and outputs it as a clock signal.
- Each of the 5-1 selector 311 to the 5-1 selector 335 is controlled independently of each other by the hypervisor operating on the multiprocessor LSI 100.
- the clock control unit 202 outputs ClockA271 to ClockY295 that are clock signals of any one frequency of 800 MHz, 600 MHz, 300 MHz, 100 MHz, and 0 Hz.
- the clock control unit 202 is set to output an 800 MHz clock signal to the clock signal ClockM283 to the processor M, which is the central processor, when the multiprocessor LSI 100 is activated.
- the voltage control unit 203 is controlled by a hypervisor operating on the multiprocessor LSI 100, and outputs voltage signals A241 to Y265, which are signals indicating the power supply voltages of the power supply blocks, to the power supply blocks A211 to Y235, respectively. It has a function.
- Each of the voltage signal A241 to the voltage signal Y265 is a signal indicating any one voltage among 1.2V, 1.1V, 1.0V, 0.8V, and 0V.
- the voltage control unit 203 is set to output a signal indicating a voltage of 1.2 V as the voltage signal M253 when the multiprocessor LSI 100 is activated. This setting is set to operate the processor M123 at the power supply voltage of 1.2 V at the time of startup.
- the power supply of the multiprocessor LSI 100 includes a 1.2V power supply wiring that is a mesh structure wiring having a voltage of 1.2V, a 1.1V power supply wiring that is a mesh structure wiring having a voltage of 1.1V, 1.0V power supply wiring that is 1.0V mesh structure wiring, 0.8V power supply wiring that is mesh voltage having a voltage of 0.8V, and ground wiring that is mesh structure wiring having a voltage of 0V. .
- the power supply block A 211 to power supply block Y 235 operate using the input Clock A 271 to Clock Y 295 as clock signals, respectively, operate at the power supply voltage indicated by the input voltage signal A 241 to voltage signal Y 265, respectively, and each of the processors A 111 to It has a processor Y135.
- FIG. 4 is a block diagram showing a configuration of the power supply block M223.
- the configuration of the power supply block is described using the power supply block M223, but the other power supply blocks have the same configuration as the power supply block M223.
- the power supply block M223 includes a processor M123, a clock supply circuit M401, a power supply selection circuit M402, a local memory M403, a cache M404, and the like.
- the clock supply circuit M401 has a function of receiving the clock signal ClockM283 output from the clock control unit 202 and supplying the received clock signal to the processor M123, the power supply selection circuit M402, the local memory M403, and the cache M404.
- the power supply selection circuit M402 receives the voltage signal M253 output from the voltage control unit 203, and supplies the power supply voltage indicated by the received voltage signal M253 to the processor M123, the clock supply circuit M401, the local memory M403, and the cache M404. It has the function to do.
- the power supply selection circuit M402 is supplied to the 1.2V power supply wiring, 1.1V power supply wiring, 1.0V power supply wiring, 0.8V power supply wiring, and ground wiring, which are mesh structure wiring, according to the received voltage signal M253.
- One power source is selected from among the power sources, and the voltage of the selected power source is supplied to the power supply wiring in the power supply block, thereby supplying power to the clock supply circuit M401, the local memory M403, and the cache M404.
- FIG. 5 is a block diagram showing the configuration of the power supply selection circuit.
- the power source selection circuit 500 includes a changeover switch 510.
- the changeover switch 510 includes a 1.2V power supply line 531, a 1.1V power supply line 532, a 1.0V power supply line 533, a 0.8V power supply line 534, and a ground line 535 according to the voltage signal 521. Is a switch that selects one power supply wiring from the power supply and electrically connects the selected power supply wiring to the power supply wiring 537 in the power supply block.
- the capacitor 540 is inserted in the power supply selection circuit 500 in order to remove voltage noise when switching the switch.
- the power supply selection circuit 500 supplies one power supply voltage of 1.2V, 1.1V, 1.0V, 0.8V, and 0V to the clock supply circuit M401, the local memory M403, and the cache M404, respectively. To supply.
- the local memory M403 is a memory that is connected to the processor M123 and used by the processor M123 as a memory area, and temporarily stores programs and data used by the processor M123.
- the cache M404 is a cache memory connected to the processor M123 and the memory bus 430, and is used as a cache memory when the processor M123 accesses the external memory 440 connected via the memory bus 430.
- the processor M123 includes a processor H118 in the power supply block H218, a processor L122 in the power supply block L222, a processor N124 in the power supply block N224, a processor R128 in the power supply block R228, a local memory M403 in the same power supply block, and the same power supply block.
- the local memory M403, the cache M404 etc. Realize various functions jointly.
- the processor M123 has a function of performing the above-described routing processing.
- FIG. 6 is a block diagram showing program modules (hereinafter simply referred to as “modules”) operating on the multiprocessor LSI 100.
- Modules that operate on the multiprocessor LSI 100 include a hypervisor 631, a first OS 601 to KOS 604 that operate on the hypervisor 631, a first task 651 to an N task 655 that operate on each OS, and the like.
- These modules operate when a program stored in the external memory 440 is executed by one or more of the processors A111 to Y135.
- Each of the first task 651 to the Nth task 655 is assigned to any one of the first OS 601 to the KOS 604.
- Each of the first OS 601 to the KOS 604 is a different type of OS and is assigned to any one of the processors A 111 to Y 135 by the hypervisor 631 and operates on the assigned processor.
- the maximum number of OSs operating on the multiprocessor LSI 100 is 25.
- the hypervisor 631 includes an OS task correspondence information holding module 632, a processor selection module 633, a voltage frequency information holding module 634, and an operation pattern information holding module 635.
- the first OS 601 to the KOS 604 are respectively connected to the processor A 111 to the processor Y 135.
- a power supply voltage and an operating frequency of the assigned processor are determined, and the processor is operated with the determined power supply voltage and operating frequency.
- the OS task correspondence information holding module 632 communicates with the processor selection module 633, and has a function of reading and holding OS task correspondence information stored in a predetermined storage area of the external memory 440.
- the OS task correspondence information is information indicating the number of tasks assigned to each OS and the task IDs of the assigned tasks.
- FIG. 7 is a data configuration diagram of the OS task correspondence information held by the OS task correspondence information holding module 632.
- the OS task correspondence information includes an OS identifier 701 for specifying the OS, a task number 702 that is the number of tasks assigned to the OS specified by the OS identifier 701, and an OS identifier.
- a task ID 703 for specifying a task assigned to the OS specified in 701 is associated.
- the OS executed by the multiprocessor LSI 100 is a total of seven OSs, the first OS to the seventh OS, 70 tasks are assigned to the first OS, and 50 are assigned to the second OS. 30 tasks are assigned to the third OS, 20 tasks are assigned to the fourth OS, 15 tasks are assigned to the fifth OS, and 9 tasks are assigned to the sixth OS. It can be seen that eight tasks are assigned to the seventh OS.
- the voltage frequency information holding module 634 communicates with the processor selection module 633, and has a function of reading and holding voltage frequency information stored in a predetermined storage area of the external memory 440.
- the voltage frequency information is information for setting the power supply voltage and operating frequency of a processor according to the number of tasks assigned to the processor.
- FIG. 8 is a data configuration diagram of voltage frequency information held by the voltage frequency information holding module 634.
- the voltage frequency information includes the number of tasks 801 indicating the number of tasks assigned to the OS, the power supply voltage 802 indicating the power supply voltage of the power supply block, and the operating frequency indicating the operating frequency of the processor. 803 is associated.
- a power supply block to which a processor to which an OS assigned with 61 or more tasks is assigned is supplied with a power supply voltage of 1.2 V, and the processor has an operating frequency of 800 MHz. Shows that it works.
- the operation pattern information holding module 635 communicates with the processor selection module 633, and has a function of reading and holding operation pattern information stored in a predetermined storage area of the external memory 440.
- the operation pattern information indicates to which processor the OS is assigned in order from the OS with the largest number of assigned tasks for each case where the number of assigned OSs is 1 to 25. It is information to show.
- the operation pattern information is assigned to the tasks among the first processor and the processors directly connected.
- the number of tasks assigned to the first processor is greater than or equal to the amount of tasks assigned to the second processor when there is a second processor with fewer processors than the first processor.
- the OS and the processor are associated with each other.
- FIG. 9 is a diagram representing the motion pattern information held by the motion pattern information holding module 635 in a drawing.
- FIG. 9 shows to which processor the OS is assigned in order from the OS with the largest number of assigned tasks.
- FIG. 9A shows the case where there is one task assigned to the OS.
- FIG. 9c shows a case where there are three OSs to which tasks are assigned
- FIG. 9d shows a case where there are four OSs to which tasks are assigned
- FIG. 9 f is a diagram when the number of tasks assigned is 25.
- the processor selection module 633 communicates with the OS task correspondence information holding module 632, the voltage frequency information holding module 634, and the operation pattern information holding module 635, and has the following four functions.
- Function 1 A function for determining which processor to allocate each OS from the OS task correspondence information held by the OS task correspondence information holding module 632 and the operation pattern information held by the operation pattern information holding module 635.
- Function 2 With reference to the voltage frequency information held by the voltage frequency information holding module 634, for each determined processor, the operating frequency and power supply of the processor are determined from the number of tasks assigned to the OS assigned to the processor. Function to determine the voltage.
- Function 3 Stores a set of assigned OS, processor, operating frequency, and power supply voltage, controls the clock control unit 202 to achieve the determined operating frequency, and controls the voltage control unit to achieve the determined power supply voltage Function for controlling 203.
- Function 4 A function for starting a processor by sending a start signal to the processor.
- the activation signal is a reset cancellation signal, and each processor is activated by releasing the reset in a state where power is supplied.
- the multiprocessor LSI 100 realizes various functions such as MPEG (Moving Picture Experts Group) encoding processing, video processing processing, and the like according to software executed on the multiprocessor LSI 100.
- MPEG Motion Picture Experts Group
- the multiprocessor LSI 100 is activated by an external controller, and is configured to read and execute a program stored in a predetermined memory area of the external memory 440 at the time of activation. Before starting the processor LSI 100, a program to be executed is loaded into the predetermined memory area.
- FIG. 10 is a flowchart of the above-described startup process performed by the multiprocessor system according to the present embodiment.
- a power supply voltage of 1.2 V and a clock signal of 800 MHz are supplied to the processor M123, and the processor M123 is activated.
- the processor M123 activates the hypervisor 631 on its own processor (step S1000).
- the OS task correspondence information holding module 632 reads and holds the OS task correspondence information stored in a predetermined storage area of the external memory 440, and the voltage frequency information holding module 634 The voltage frequency information stored in the predetermined storage area of the memory 440 is read and held, and the operation pattern information holding module 635 reads and holds the operation pattern information stored in the predetermined storage area of the external memory 440.
- the processor selection module 633 starts from an OS with a large number of assigned tasks from the OS task correspondence information held by the OS task correspondence information holding module 632 and the operation pattern information held by the operation pattern information holding module 635. In order, in accordance with the operation pattern information, which processor is assigned to each OS is determined (step S1010).
- the processor selection module 633 refers to the voltage frequency information held by the voltage frequency information holding module 634 and is assigned to the OS assigned to the processor for each determined processor.
- the operating frequency and power supply voltage of the processor are determined from the number of tasks that are present (step S1020).
- the processor selection module 633 controls the clock control unit 202 to achieve the determined operating frequency, and controls the voltage control unit 203 to achieve the determined power supply voltage.
- An activation signal is transmitted to the processor to activate the processor (step S1030).
- each of the processors receiving the activation signal When each of the processors receiving the activation signal is activated, it activates the hypervisor on its own processor, and further activates the assigned OS on the hypervisor.
- Each of the activated processors starts processing the task assigned to the assigned OS (step S1040).
- This specific example is an example in which the OS task correspondence information held by the OS task correspondence information holding module 632 is as shown in FIG.
- step S1010 the processor selection module 633 recognizes that the number of OSs to which tasks are assigned is seven from the OS task correspondence information held by the OS task correspondence information holding module 632. Of the operation pattern information held in 635, the operation pattern information in the case where there are seven OSs to which tasks are assigned is read.
- FIG. 11 is a diagram representing the operation pattern information in the case where the number of OSs to which tasks are assigned among the operation pattern information held by the operation pattern information holding module 635 is seven.
- the operation pattern information when there are seven OSs to which tasks are assigned is processor 1101, processor 1102, processor 1103, processor 1104, processor 1105, OS in descending order of the number of assigned tasks. It is shown that the processor 1106 and the processor 1107 are assigned.
- the processor selection module 633 sends the first OS to the processor M123, the second OS to the processor H118, the third OS to the processor L122, the fourth OS to the processor G117, the fifth OS to the processor I119, and the sixth OS to the processor N124. It is determined that the seventh OS is assigned to the processor R128 (step S1010).
- the processor selection module 633 refers to the voltage frequency information held by the voltage frequency information holding module 634, and the processor M123 to which the first OS with 70 tasks is assigned has an operating frequency of 800 MHz and a power supply voltage of 1.2V.
- the processor H118 to which the second OS with 50 tasks is assigned is determined to have the operating frequency of 600 MHz and the power supply voltage is 1.1 V, and the processor L122 to which the third OS with 30 tasks is assigned is The processor G117, which is determined to have a power supply voltage of 1.0 V at an operating frequency of 300 MHz and is assigned a fourth OS with a task number of 20, is determined to have a power supply voltage of 1.0 V at an operating frequency of 300 MHz, and has a 15th task number.
- the processor I119 to which 5OS is assigned has an operating frequency of 3
- the processor N124 which is determined to have a power supply voltage of 1.0 V at 0 MHz and is assigned with a sixth OS with a task number of 9, determines that the power supply voltage is 0.8 V with an operating frequency of 100 MHz, and the seventh OS with a task number of 8 is
- the assigned processor R128 determines that the operating frequency is 100 MHz and the power supply voltage is 0.8 V (step S1020).
- the processor to which the OS to which the task is assigned is not assigned is determined to have the operating frequency of 0 Hz and the power supply voltage of 0V.
- FIG. 12 is a diagram showing the operating frequency and power supply voltage of each processor determined by the above specific example.
- processor A111 to processor F116, processor J120, processor K121, processor O125 to processor Q127, processor S129 to processor Y135 have an operating frequency of 0 Hz and a power supply voltage of 0 V
- processor M123 has an operating frequency of 800 MHz.
- the power supply voltage is 1.2V
- the processor H118 has an operation frequency of 600 MHz and the power supply voltage is 1.1V
- the processor L122, the processor G117, and the processor I119 have an operation frequency of 300 MHz and the power supply voltage is 1.0V.
- any one of the processors to which the task is assigned is assigned to the first processor.
- the second processor there are a first processor and a second processor to which a number of processors to which tasks are assigned among the directly connected processors is smaller than that of the first processor.
- the tasks are assigned to each processor so that the amount of tasks assigned to the first processor is equal to or greater than the amount of tasks assigned to the second processor.
- Processors assigned more tasks tend to have more traffic with processors assigned to other tasks than processors assigned fewer tasks, and are connected to each other It is not necessary to communicate with other processors via other processors.
- this multiprocessor system can assign tasks to each processor so that routing processing can be performed efficiently.
- the operating frequency of the second processor to which an amount of tasks equal to or less than the amount of tasks allocated to the first processor is less than or equal to the operating frequency of the first processor. Therefore, by efficiently determining the operating frequency of each processor, the efficiency of power consumption with respect to the performance of the multiprocessor system can be improved.
- the operation of the processor to which no task is assigned can be stopped, so that the operating power of the processor to which no task is assigned can be reduced to zero. Become.
- the operating voltage of the processor operating at the second operating frequency which is an operating frequency lower than the first operating frequency, may be less than or equal to the operating voltage of the processor operating at the first operating frequency. Therefore, by efficiently determining the operating voltage of each processor, the power consumption efficiency with respect to the performance of the multiprocessor system can be improved.
- Embodiment 2 a modified multiprocessor system according to Embodiment 2 in which a part of the multiprocessor system according to Embodiment 1 is modified will be described as an embodiment of the multiprocessor system according to the present invention.
- the modified multiprocessor system attempts to detect a change in the number of tasks to be processed at regular intervals (for example, 5 minutes), and when a change is detected, reassigns the task to the processor.
- the modified multiprocessor system is realized by using a modified multiprocessor LSI in which 25 processors are arranged in a 5 ⁇ 5 matrix like the multiprocessor system.
- the multiprocessor system according to the first embodiment is an example in which each of the K OSs to which tasks are assigned is assigned to one processor, whereas the modified multiprocessor system according to the second embodiment is Assume that there are three OSs operating on the processor, and each OS is assigned to one or more processors.
- each processor when a power supply voltage of 0.7 V and a clock signal of 0 Hz are supplied, each processor does not operate as a processor but continues to hold data stored in a register or the like.
- the hardware difference between the modified multiprocessor LSI according to the second embodiment and the multiprocessor LSI 100 according to the first embodiment is that (1) the mesh power supply wiring is a mesh structure wiring having a voltage of 0.7V. .7V power supply wiring is added, (2) the voltage control unit 203 is transformed into a modified voltage control unit, and (3) the power supply selection circuit 500 of each power supply block is connected to the power supply selection circuit 1300. (4) The clock control unit 202 is transformed into a modified clock control unit.
- the difference between the module operating on the modified multiprocessor LSI and the module operating on the multiprocessor LSI 100 is that (1) the hypervisor 631 is transformed into the hypervisor 1431 and (2) the multiprocessor LSI 100.
- the OS operating on the above is the first OS 601 to the KOS 604, whereas the OS operating on the modified multiprocessor LSI is changed to the first OS 1401 to the third OS 1403.
- the modified voltage control unit is controlled by the hypervisor 1431 operating on the modified multiprocessor LSI, and the voltage signal a to voltage signal y, which is a signal indicating the power supply voltage of the power supply block, is supplied to each of the power supply block A 211 to the power supply block Y 235. Has a function to output.
- Each of the voltage signal A241 to voltage signal Y265 output from the voltage control unit 203 is any one of signals indicating five types of voltages of 1.2V, 1.1V, 1.0V, 0.8V, and 0V.
- each of the voltage signal a to voltage signal y output from the deformation voltage control unit is 1.2V, 1.1V, 1.0V, 0.8V, 0.7V, and 0V. It is a signal indicating any one of the six kinds of voltages.
- the modified voltage control unit is set to output a signal indicating a voltage of 1.2 V as the voltage signal h, the voltage signal l, and the voltage signal m when the modified multiprocessor LSI is activated.
- This setting is set so that the processor H118, the processor L122, and the processor M123 are operated at a power supply voltage of 1.2 V at the time of startup.
- the power supply selection circuit 1300 receives the voltage signal output from the deformed voltage control unit, and supplies the power supply voltage indicated by the received voltage signal to the processor, clock supply circuit, local memory, and cache in the same power supply block. It has a function.
- the power supply selection circuit M402 selects one of the five types of power supplied to the 1.2V power supply wiring, 1.1V power supply wiring, 1.0V power supply wiring, 0.8V power supply wiring, and ground wiring.
- the power supply selection circuit 1300 is supplied to the power supply wiring in the block, whereas the power supply selection circuit 1300 has a 1.2V power supply wiring, a 1.1V power supply wiring, a 1.0V power supply wiring, a 0.8V power supply wiring, and a 0.7V power supply.
- One of the six types of power supplied to the wiring and the ground wiring is selected and supplied to the power supply wiring in the block.
- FIG. 13 is a block diagram showing the configuration of the power supply selection circuit 1300.
- the power supply selection circuit 1300 includes a changeover switch 1310.
- the changeover switch 1310 includes a 1.2V power wiring 1331, a 1.1V power wiring 1332, a 1.0V power wiring 1333, a 0.8V power wiring 1334, and a 0.7V power wiring 1335 according to the voltage signal 1321. And a ground line 1336, a power supply line is selected from the ground line 1336, and the selected power supply line and the power supply block internal power line 1337 are electrically connected.
- the capacitor 1340 is inserted in the power supply selection circuit 1300 in order to remove voltage noise when switching the switch.
- the modified clock control unit is set in the clock control unit 202 to output an 800 MHz clock signal to the ClockM 283 when the multiprocessor LSI 100 is started up.
- the modified clock control unit is set to 800 MHz to the ClockH 278, ClockL282, and ClockM283 when the modified multiprocessor LSI is started up. This is a modification to the setting of outputting the clock signal. This setting is set to operate the processor H118, the processor L122, and the processor M123 at the operating frequency of 800 MHz at the time of activation.
- FIG. 14 is a block diagram showing modules operating on the modified multiprocessor LSI.
- Modules that operate on the modified multiprocessor LSI include a hypervisor 1431, a first OS 1401 to third OS 1403 that operate on the hypervisor 1431, a first task 1451 to an Nth task 1455 that operate in the form of each OS, and the like.
- These modules operate when a program stored in the external memory 440 is executed by one or more of the processors A111 to Y135.
- Each of the first task 1451 to the Nth task 1455 is assigned to any one of the first OS 1401 to the third OS 1403.
- Each of the first OS 1401 to the third OS 1403 is a different type of OS, and includes a first scheduler 1411 to a third scheduler 1413 having a function for scheduling tasks, and one of the processors A111 to Y135 is selected by the hypervisor 1431. Assigned to more than one processor and runs on all assigned processors.
- Each of the first scheduler 1411 to the third scheduler 1413 has a function for scheduling a task assigned to a processor in which the own scheduler is activated, and a task load index indicating the number of tasks to be scheduled by the own scheduler. And a function of storing
- the scheduler When there is an increase or decrease in the tasks assigned to the processor, the scheduler reschedules the task group after the increase / decrease, and changes the task load index to be stored to indicate the number of task groups after the increase / decrease. Update.
- the processing of the assigned task may be terminated and the task may be excluded from the assignment target task.
- tasks increase, a task being processed may generate a new task.
- the hypervisor 1431 deletes the OS task correspondence information holding module 632 and the operation pattern information holding module 635 from the hypervisor 631, transforms the processor selection module 633 into the processor selection module 1433, and sets the voltage frequency information holding module 634 to the voltage.
- the frequency information holding module 1434 is modified and a task assignment flag holding module 1436 and a connection information holding module 1435 are newly added.
- the task assignment flag holding module 1436 communicates with the processor selection module 1433 and has a function of holding the task assignment flags of the processors A111 to Y135.
- the task assignment flag is a 1-bit flag indicating whether or not a task has been assigned to the corresponding processor during the period from when the modified multiprocessor LSI is started up to the present time. It is “0” when a task has never been assigned, and “1” when a task has been assigned.
- the voltage frequency information holding module 1434 communicates with the processor selection module 1433, and has a function of reading and holding deformed voltage frequency information stored in a predetermined storage area of the external memory 440.
- the deformed voltage frequency information is information for setting the power supply voltage and operating frequency of the processor according to the number of tasks assigned to the processor and the task assignment flag corresponding to the processor.
- FIG. 15 is a data configuration diagram of the deformed voltage frequency information held by the voltage frequency information holding module 1434.
- the deformed voltage frequency information includes the number of tasks 1501 indicating the number of tasks allocated to the processor, the task allocation flag 1502 indicating the value of the task allocation flag, and the power supply voltage of the power supply block.
- the power supply voltage 1503 shown is associated with the operating frequency 1504 showing the operating frequency of the processor.
- this deformed voltage frequency information for example, 0 tasks are allocated, and the corresponding task allocation flag is supplied with a power supply voltage of 0.7 V to the power supply block to which the processor belongs, and the processor operates at 0 Hz.
- 1 to 10 tasks are assigned and the corresponding task assignment flag value is 0 or 1 and the power supply block to which the processor belongs is 0.8V.
- the processor is operating at 100 MHz.
- a power supply voltage of 0.7 V is supplied to the power supply block, but the state in which the processor belonging to the power supply block is not operating means that the local memory, cache memory, and register in the processor belong to the power supply block. In this state, data is held because the power supply voltage is supplied, but no data is written or read because the processor is not operating.
- the processor Since the processor is not operating but the data continues to be retained, when the processor operates again, the processor can use the data without reloading.
- the system load management module 1432 communicates with the first scheduler 1411, the second scheduler 1412, the third scheduler 1413, and the processor selection module 1433, and has the following four functions.
- Function 1 A timer function that measures the passage of a predetermined time T1 (for example, 1 minute) and a predetermined time T2 (for example, 5 minutes).
- Function 2 A function for acquiring a task load index stored in each running scheduler every predetermined time T2 (for example, 5 minutes).
- Function 3 Function to store the acquired task load index.
- Function 4 The task load index to be stored is compared with the newly acquired task load index, and the total number of tasks indicated by the stored task load index and the total number of tasks indicated by the newly acquired task load index are calculated.
- connection information holding module 1435 communicates with the processor selection module 1433, and has a function of reading and holding connection information stored in a predetermined storage area of the external memory 440.
- Connection information is information indicating a connection relationship between processors.
- FIG. 16 is a data configuration diagram of connection information held by the connection information holding module 1435.
- connection information is obtained by associating a processor ID 1601 for specifying a processor with a connection processor ID for specifying a processor to be directly connected.
- the processor A indicates that it is connected to the processor B and the processor F.
- the processor selection module 1433 communicates with the system load management module 1432, the task assignment flag holding module 1436, the voltage frequency information holding module 1434, and the connection information holding module 1435, and has the following six functions.
- Function 1 A function to calculate the number of tasks assigned to each calculated processor by calculating the number of processors to which tasks are assigned for each OS type upon receiving a task load index from the system load management module.
- the processor selection module 1433 assigns 80 tasks to the processors of the number of quotients obtained by dividing the total number of tasks indicated by the task load index for each OS type by 80 in the function 1, and assigns one processor to each processor.
- the number of processors assigned and the number of tasks assigned to the processors are calculated so that a surplus number of tasks are assigned.
- Function 2 From the number of processors to which tasks are assigned, the number of tasks to be assigned to these processors, and the connection information held by the connection information holding module 1435, a candidate processor group to which a task is assigned (hereinafter referred to as an assigned processor group candidate). .) Function to calculate.
- the processor selection module 1433 calculates all combinations of processors to which tasks are assigned based on the connection information, and selects one of the processors to which tasks are assigned among all the combinations. Assuming that the first processor and the second processor are present, there are a first processor and a second processor in which the number of processors to which tasks are assigned among the directly connected processors is smaller than that of the first processor. In this case, a combination in which the amount of tasks assigned to the first processor is equal to or greater than the amount of tasks assigned to the second processor is selected, and the processor group indicated by the combination is calculated as an assigned processor group candidate.
- Function 3 Selects an allocation processor group from which the difference between the combination of the processor and the OS assigned to the processor and the combination of the processor group to which the task is currently assigned is the smallest from among the allocation processor group candidates.
- a function in which the assigned processor group is a processor group to which a task is assigned.
- Function 4 For each of the processors constituting the processor group to which the task is assigned, the processor uses the modified voltage frequency information held by the voltage frequency information holding module 1434 and the task assignment flag held by the task assignment flag holding module 1436. A function that calculates the operating frequency and power supply voltage of the processor from the number of tasks assigned to the.
- Function 5 A processor group that controls the modified clock control unit and the modified voltage control unit so that each of the processors constituting the processor group to which the task is assigned operates at the calculated operating frequency and the power supply voltage, and assigns the task.
- Function 6 A function for updating the task assignment flag held by the task assignment flag holding module 1436.
- the task assignment flag holding module 1436 holds the task assignment flag of the corresponding processor. Change the value from “0” to “1”.
- FIG. 17 is a flowchart of the startup process performed by the modified multiprocessor system according to the second embodiment.
- a 1.2 V power supply voltage and an 800 MHz clock signal are supplied to the processor H118, the processor L122, and the processor M123, and the processor H118, the processor L122, and the processor M123 are activated.
- the hypervisor 1431 is activated on the processor (step S1700).
- the processor M123 activates the first OS 1401 on the hypervisor 1431
- the processor H118 activates the second OS 1402 on the hypervisor 1431
- the processor L122 activates the third OS 1403 on the hypervisor 1431 (step S1710).
- the respective schedulers start scheduling tasks assigned to the processor in which the own scheduler is activated.
- the task load index indicating the number is stored (step S1720).
- the time required from when the hypervisor 1431 is activated until each scheduler stores the task load index is, for example, less than one minute.
- FIG. 18 is a flowchart of system load management processing performed by the modified multiprocessor system according to the second embodiment.
- the system load management module 1432 activates a timer and measures a predetermined time T1 (for example, 1 minute) in order to wait until each scheduler stores a task load index in the activation process. Is started (step S1800).
- the system load management module 1432 acquires a task load index from the scheduler of each OS, restarts the timer, and measures the predetermined time T2 (for example, 5 minutes). Is started (step S1810).
- the system load management module 1432 transmits the acquired task load index of each OS to the processor selection module 1433 (step S1820), and stores the acquired task load index of each OS (step S1830). ).
- step S1830 the system load management module 1432 waits until a predetermined time T2 (for example, 5 minutes) elapses after starting the timer (step S1840), and when a predetermined time T2 (for example, 5 minutes) elapses after the timer starts,
- the task load index is acquired from the scheduler of each OS, the timer is restarted, and measurement of a predetermined time T2 (for example, 5 minutes) is started again (step S1850).
- the system load management module 1432 compares the stored task load index with the acquired task load index (step S1860).
- step S1870: Yes when the amount of change in the total number of tasks indicated by the task load index is equal to or greater than a predetermined amount (for example, 5%) (step S1870: Yes), the modified multiprocessor system again performs the processing after step S1820. If the amount of change in the total number of tasks indicated by the task load index is less than a predetermined amount (for example, 5%) (step S1870: No), the modified multiprocessor system performs the processing from step S1840 onwards.
- a predetermined amount for example, 5%
- FIG. 19 is a flowchart of processor selection processing performed by the modified multiprocessor system according to the second embodiment.
- the task allocation flag holding module 1436 initializes the task allocation flag of each processor to be held with the initial value “0” (step S1905).
- step S1905 the processor selection module 1433 waits until a task load index is transmitted from the system load management module 1432 (step S1910: No to step S1910 loop).
- step S1910 when the processor selection module 1433 receives the task load index from the system load management module 1432 (step S1910: Yes), the processor selection module 1433 calculates the number of processors to which tasks are assigned for each OS type. The number of tasks assigned to each processor is calculated (step S1915).
- step S1915 for each OS type, the processor selection module 1433 assigns 80 tasks to the quotient number of processors obtained by dividing the total number of tasks indicated by the task load index by 80, and the number of remainders.
- the number of processors to be assigned and the number of tasks to be assigned to the processors are calculated so that the tasks are assigned to one processor.
- the processor selection module 1433 determines the assigned processor group candidate from the number of processors to which tasks are assigned, the number of tasks to be assigned to these processors, and the connection information held by the connection information holding module 1435. Is calculated (step S1920).
- the processor selection module 1433 calculates all combinations of processors to which tasks are assigned based on the connection information, and selects one of the processors to which tasks are assigned among all the combinations. Assuming that the first processor and the second processor are present, there are a first processor and a second processor in which the number of processors to which tasks are assigned among the directly connected processors is smaller than that of the first processor. In this case, a combination in which the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor is selected, and the processor group indicated by the combination is calculated as an assigned processor group candidate.
- the processor selection module 1433 determines the combination of the processor and the OS assigned to the processor from the calculated assignment processor group candidates and the combination in the processor group to which the current task is assigned.
- the assigned processor group with the smallest difference is selected, and the selected assigned processor group is set as the processor group to which the task is assigned (step S1925).
- the processor selection module 1433 holds the modified voltage frequency information held by the voltage frequency information holding module 1434 and the task assignment flag holding module 1436 for each of the processors constituting the processor group to which the task is assigned.
- the operation frequency and power supply voltage of the processor are calculated from the number of tasks assigned to the processor using the task assignment flag to be executed (step S1930).
- the processor selection module 1433 checks whether or not a processor to which a task is newly assigned exists in the processor group to which the task is assigned (step S1935).
- the newly assigned processor is a processor whose task assignment flag value held by the task assignment flag holding module 1436 is “0” among processors to which tasks are assigned.
- step S1935 when there is a processor to which a task is newly assigned (step S1935: Yes), the processor selection module 1433 displays the value of the task assignment flag of the corresponding processor held by the task assignment flag holding module 1436. “0” is changed to “1” (step S1940).
- the processor selection module 1433 is a processor that constitutes a processor group to which a task is assigned. Are controlled by the modified clock control unit and the modified voltage control unit so that each of them operates at the calculated operating frequency and power supply voltage, and an OS and a task are assigned to each of the processors constituting the processor group to which the task is assigned. Reassign (step S1945).
- step S1945 the modified multiprocessor system returns to the process of step S1910 again, and repeats the processes after step S1910.
- the OS and tasks can be reassigned to the processors.
- the second modified multiprocessor system assigns tasks to the processors so that the processor to which the most tasks are currently assigned does not become the processor to which the most tasks are newly assigned every fixed period (for example, 5 minutes). It is something to fix.
- FIG. 20 is a block diagram showing modules operating on the modified multiprocessor LSI in the second modified multiprocessor system.
- the module that operates in the second modified multiprocessor system is obtained by changing the hypervisor 1431 to the hypervisor 2031 among the modules that operate in the modified multiprocessor system.
- the hypervisor 2031 is obtained by changing the system load management module 1432 from the hypervisor 1431 to the system load management module 2032 and changing the processor selection module 1433 to the processor selection module 2033.
- the system load management module 2032 communicates with the first scheduler 1411, the second scheduler 1412, the third scheduler 1413, and the processor selection module 2033, and in addition to the function 1 and the function 2 of the system load management module 1432, the following functions Have
- Function 3a a function for transmitting the acquired task load index to the processor selection module 2033.
- the processor selection module 2033 communicates with the system load management module 2032, the task allocation flag holding module 1436, the voltage frequency information holding module 1434, and the connection information holding module 1435, and functions 1, 2, and 4 that the processor selection module 1433 has. In addition to function 5 and function 6, the following functions are provided.
- Function 3a In the processor group to which the current task is assigned with respect to the combination of the processor and the OS assigned to the processor that is assigned the most task to a processor different from the processor to which the most current task is assigned. A function of selecting an assigned processor group having the smallest difference from the combination, and setting the selected assigned processor group as a processor group to which a task is assigned.
- This modified system load management process is a modification of part of the system load management process in the second embodiment.
- the process of step S1830 is performed.
- the process from step S1840 is performed without performing step S1840, and when the process from step S1850 is completed, the process from step S1860 and the process from step S1870 are performed again, and the process from step S1820 is performed again.
- FIG. 21 is a flowchart of a modified system load management process performed by the second modified multiprocessor system according to the third embodiment.
- steps S2100 to S2120 and steps S2140 to S2150 correspond to the processes of steps S1800 to S1820 and steps S1840 to S1850 (see FIG. 18) of the system load management process in the second embodiment, respectively.
- the visor 1431 is replaced with a hypervisor 2031
- the system load management module 1432 is replaced with a system load management module 2032
- the processor selection module 1433 is replaced with a processor selection module 2033.
- step S2120 When the process of step S2120 is completed, the second modified multiprocessor system performs the process of step S2140. When the process of step S2150 is completed, the second modified multiprocessor system performs the processes after step S2120 again. .
- This modified processor selection process is a modification of a part of the processor selection process in the second embodiment, and the process in step S1925 of the processor selection process in the second embodiment is replaced with the process in step S2225 described later. It is a thing.
- FIG. 22 is a flowchart of modified processor selection processing performed by the modified multiprocessor system according to the third embodiment.
- steps S2200 to S2220 and steps S2230 to S2245 correspond to the processes in steps S1900 to S1920 and steps S1930 to S1945 (see FIG. 19) of the processor selection process in the second embodiment, respectively.
- 1431 is replaced with the hypervisor 2031
- the system load management module 1432 is replaced with the system load management module 2032
- the processor selection module 1433 is replaced with the processor selection module 2033.
- the processor selection module 2033 assigns the most tasks to a processor different from the processor to which the most tasks are currently assigned, and the combination of the processor and the OS assigned to the processor. Then, an assigned processor group having the smallest difference from the combination in the processor group to which the task is currently assigned is selected, and the selected assigned processor group is set as a processor group to which the task is assigned (step S2225).
- step S2225 When the process of step S2225 is completed, the second modified multiprocessor system performs the processes after step S2230.
- FIG. 23 shows the OS assigned to the processor at the time immediately before the task is reassigned to the processor by the hypervisor 2031 (hereinafter referred to as time t1) and the time immediately after (hereinafter referred to as time t2). It is a figure which shows an example with the number of tasks.
- the upper diagram in the figure shows the OS and the number of tasks assigned to the processor at time t1
- the lower diagram shows the OS and the number of tasks assigned to the processor at time t2. is there.
- the processor to which the most tasks are assigned is the processor M123 to which the first OS and the task number 80 are assigned, and the processor H118 to which the second OS and the task number 80 are assigned.
- the processor to which the most tasks are assigned is the processor L122 to which the first OS and the task number 80 are assigned, and the processor G117 to which the second OS and the task number 80 are assigned.
- the hypervisor 2031 reassigns a task to a processor, the processor to which the task is most assigned is changed, so that the most tasks are not continuously assigned to the same processor.
- a task when a task is reassigned to a processor, a task is assigned to a processor so that the processor to which the largest number of tasks are currently assigned does not become the processor to which the most new tasks are assigned. You can fix it.
- the present invention is not limited to the authentication system as shown in the above-described embodiment.
- the multiprocessor LSI 100 is configured by 25 processors arranged in a 5 ⁇ 5 matrix, and each processor has the same shape with the same function. However, if the configuration includes three or more processors that communicate with each other and all of the processors are not directly connected to each other, the number of processors may not necessarily be 25. It is not necessary to arrange them in a 5 ⁇ 5 matrix, and it is not always necessary that the processors have the same function, and it is not always necessary that the processors have the same shape.
- each of the first OS 601 to the KOS 604 has been described as an example of a different type of OS.
- examples of the operation pattern information include those shown in FIGS. 9a to 9f and FIG. 11. However, any one of the processors to which tasks are assigned is the first.
- the second processor the operation pattern information includes the first processor and the second processor in which the number of processors to which tasks are assigned among the directly connected processors is smaller than that of the first processor. And so that the amount of tasks assigned to the first processor is equal to or greater than the amount of tasks assigned to the second processor for all combinations of the first processor and the second processor.
- the processor are not necessarily limited to those shown in FIGS.
- the hypervisor 631 assigns each OS to the processor based on the number of tasks assigned to each OS has been described. However, the amount of tasks assigned to each OS is determined. As long as it is shown, it does not necessarily have to be based on the number of tasks assigned to each OS. For example, the total number of instruction steps included in the task, the size of data handled by the task, and the like may be used.
- a processor that has a higher total number of instruction steps in an assigned task is a processor that has other tasks assigned to it than a processor that has a lower total number of instruction steps in an assigned task.
- a processor that tends to have a large amount of traffic and that has a larger data size handled by the assigned task is assigned a different task than a processor that has a smaller data size handled by the assigned task. There is a tendency that the amount of communication with the processor that is being increased.
- the example in which all the processors constituting the multiprocessor system are configured in one semiconductor integrated circuit has been described. However, if each processor can communicate with each other, one semiconductor is not necessarily used. It is not necessary that all the processors are configured in the integrated circuit.
- the processors may be configured in a plurality of semiconductor integrated circuits, and the processors may not necessarily be formed by the semiconductor integrated circuits. .
- an example of a configuration in which a plurality of processors are arranged in one plane has been described. However, if each processor can communicate with each other, it is not necessarily arranged in one plane. It doesn't matter.
- FIG. 24 is a diagram showing an example in which 18 processors (processors 2401 to 2414) are arranged in a 3 ⁇ 3 ⁇ 2 three-dimensional shape.
- a configuration may be adopted in which a plurality of processors are arranged in a three-dimensional manner.
- the example in which the processor, the local memory, and the cache memory included in each power supply block operate with the same combination of the clock signal and the power supply voltage has been described. Can be used normally, the processor, the local memory, and the cache memory do not necessarily need to operate with the same combination of clock signal and power supply voltage.
- the cache memory may be arranged in a power supply block different from the processor, and may always operate at an operation frequency of 100 MHz and a power supply voltage of 0.8 V regardless of the operation frequency and power supply voltage of the processor.
- the local memory may be arranged in a power supply block different from that of the processor, and may be configured to operate at an operation frequency and a power supply voltage controlled independently of the processor.
- the number of tasks assigned to the processor Depending on the number of tasks assigned to the processor, the operating frequency of the processor may be set, and the power supply voltage of the processor may be constant regardless of the number of tasks assigned to the processor. Regardless, the power supply voltage and operating frequency of the processor may be constant. (10) In the second embodiment, among the allocation processor group candidates, the allocation processor that minimizes the difference between the combination of the processor and the OS allocated to the processor and the combination in the processor group to which the current task is allocated The example of selecting a group and setting the selected assigned processor group as a processor group to which a task is assigned has been described, but the combination of the processor and the power supply voltage of the processor is the combination of the processor group to which the task is currently assigned.
- An allocation processor group with the smallest difference may be selected, and an allocation with the smallest difference between the combination of the processor and the operating frequency of the processor with the combination in the processor group to which the current task is assigned is selected.
- the processor group may be selected.
- the task assignment flag holding module 1436 may be configured to set the task assignment flag to “0” for a processor to which no task is assigned for a certain time (for example, 15 minutes).
- a certain time for example, 15 minutes.
- the upper limit is not necessarily limited to 80, and tasks are not limited depending on the type of task and the performance of the processor.
- the upper limit number may be 81 or more, or 79 or less.
- the example in which the second modified processor system performs the operation of reassigning the task to the processor every predetermined time has been described. However, it is not always necessary to perform the operation every predetermined time.
- the task may be reassigned to the processor when a change in the number of target tasks is detected.
- the present invention can be widely used for information processing apparatuses including a plurality of processors.
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Abstract
Description
以下、本発明に係るマルチプロセッサシステムの一実施形態として、25個のプロセッサが、5×5の行列状に配置されたマルチプロセッサLSIを用いて実現されるマルチプロセッサシステムについて説明する。
図1は、マルチプロセッサLSI100に配置されている25個のプロセッサA111~プロセッサY135の接続関係を示す図である。
ここで電源ブロックとは、電源電圧を共通とする複数の回路からなるブロックであり、各電源ブロックは互いに独立な電源電圧で動作する。
マルチプロセッサLSI100は、その上で実行されるソフトウエアに応じて、様々な機能、例えば、MPEG(Moving Picture Experts Group)のエンコード処理や、映像加工処理等の機能を実現する。
以下、上述の起動処理のうち、ステップS1010の処理とステップS1020の処理とについて、具体例を用いて説明を補足する。
<実施の形態2>
以下、本発明に係るマルチプロセッサシステムの一実施形態として、実施の形態1に係るマルチプロセッサシステムの一部を変形した実施の形態2に係る変形マルチプロセッサシステムについて説明する。
実施の形態2に係る変形マルチプロセッサLSIと実施の形態1に係るマルチプロセッサLSI100とのハードウエア上の相違点は、(1)メッシュ電源配線として、電圧が0.7Vのメッシュ構造配線である0.7V電源配線が追加されている点と、(2)電圧制御部203が変形電圧制御部に変形されている点と、(3)各電源ブロックの電源選択回路500が、電源選択回路1300に変形されている点と(4)クロック制御部202が変形クロック制御部に変形されている点である。
ここでは、本実施の形態2に係る変形マルチプロセッサシステムの行う処理のうち、変形マルチプロセッサLSIが起動されてから、各OSのスケジューラがタスクのスケジューリングを開始するまでの起動処理と、各OSのスケジューラから定期的にタスク負荷指標を取得するシステム負荷管理処理と、各プロセッサにタスクを割り当てるプロセッサ選択処理とについて説明する。
図17は、本実施の形態2に係る変形マルチプロセッサシステムの行う起動処理のフローチャートである。
図18は、本実施の形態2に係る変形マルチプロセッサシステムの行うシステム負荷管理処理のフローチャートである。
図19は、本実施の形態2に係る変形マルチプロセッサシステムの行うプロセッサ選択処理のフローチャートである。
以下、本発明に係るマルチプロセッサシステムの一実施形態として、実施の形態2に係る変形マルチプロセッサシステムの一部をさらに変形した実施の形態3に係る第2変形マルチプロセッサシステムについて説明する。
ここでは、本実施の形態3に係る第2変形マルチプロセッサシステムの行う処理のうち、各OSのスケジューラから定期的にタスク負荷指標を取得する変形システム負荷管理処理と、各プロセッサにタスクを割り当てる変形プロセッサ選択処理とについて説明する。
この変形システム負荷管理処理は、実施の形態2におけるシステム負荷管理処理の一部を変形したものであって、実施の形態2におけるシステム負荷管理処理のステップS1820の処理が終わると、ステップS1830の処理を行うことなくステップS1840以下の処理を行い、ステップS1850の処理が終わるとステップS1860の処理とステップS1870の処理とを行うことなく、再びステップS1820以下の処理を行うというものである。
この変形プロセッサ選択処理は、実施の形態2におけるプロセッサ選択処理の一部を変形したものであって、実施の形態2におけるプロセッサ選択処理のステップS1925の処理を、後述のステップS2225の処理に置き換えられたものである。
図23は、ハイパーバイザ2031によって、タスクをプロセッサに割り当て直される直前の時刻(以後、時刻t1という。)と直後の時刻(以後、時刻t2という。)とにおける、プロセッサに割り当てられているOSとタスクの数との一例を示す図である。
<補足>
以上、本発明に係るマルチプロセッサシステムの一実施形態として、実施の形態1、実施の形態2、実施の形態3として、3つのマルチプロセッサシステムの例に基づいて説明したが、以下のように変形することも可能であり、本発明は上述した実施の形態で示した通りの認証システムに限られないことはもちろんである。
(1)実施の形態1において、マルチプロセッサLSI100は、5×5の行列状に配置された25個のプロセッサによって構成され、各プロセッサは、互いに同じ機能を持った同じ形状である例について説明したが、3以上の互いに通信するプロセッサを含む構成であって、それらのプロセッサの全てが互いに直接接続されていない構成であれば、必ずしもプロセッサの数は25個でなくても良いし、必ずしもプロセッサが5×5の行列状に配置される必要もないし、必ずしも各プロセッサが同じ機能である必要もないし、必ずしも各プロセッサが同じ形状である必要もない。
(2)実施の形態1において、第1OS601~第KOS604のそれぞれは、互いに異なる種類のOSである例について説明したが、ハイパーバイザ631上で動作するものであれば、必ずしも互いに異なる種類のOSである必要はなく、それらの一部、もしくは全部が同じ種類のOSであっても構わない。
(3)実施の形態1において、動作パターン情報の例として、図9a~図9f、図11に示されるものを挙げたが、タスクの割り当てられているプロセッサのうちのいずれかのプロセッサを第1のプロセッサ、第2のプロセッサとすると、この動作パターン情報は、第1のプロセッサと、直接接続されるプロセッサのうちタスクの割り当てられているプロセッサの数が第1のプロセッサよりも少ない第2のプロセッサとが存在する場合に、第1のプロセッサと第2のプロセッサの全ての組み合わせについて、第1のプロセッサに割り当てられるタスクの量が第2のプロセッサに割り当てられるタスクの量以上となるように、OSとプロセッサとを対応付けるものであれば、必ずしも図9a~図9f、図11に示されるものに限られる必要はない。
(4)実施の形態1において、ハイパーバイザ631が、各OSに割り当てられているタスクの数に基づいて各OSをプロセッサに割り当てる例について説明したが、各OSに割り当てられているタスクの量を示すものであれば、必ずしも各OSに割り当てられているタスクの数に基づくものでなくても構わない。例えば、タスクに含まれる命令ステップの総数、タスクが取り扱うデータのサイズ等であってもよい。
(5)実施の形態1において、マルチプロセッサシステムを構成する全てのプロセッサが1つの半導体集積回路内に構成されている例について説明したが、各プロセッサが互いに通信することができれば、必ずしも1つの半導体集積回路内に全てのプロセッサが構成されている必要はなく、例えば、複数の半導体集積回路内に構成されていても構わないし、また、必ずしも半導体集積回路でプロセッサが形成されていなくても構わない。
(6)実施の形態1において、複数のプロセッサが1つの平面内に配置された構成の例について説明したが、各プロセッサが互いに通信することができれば、必ずしも1つの平面内に配置されていなくても構わない。
(7)実施の形態1において、各電源ブロックに含まれるプロセッサとローカルメモリとキャッシュメモリとが同じクロック信号と電源電圧との組み合わせで動作する例について説明したが、プロセッサがローカルメモリとキャッシュメモリとを正常に使用することができれば、必ずしも、プロセッサとローカルメモリとキャッシュメモリとが同じクロック信号と電源電圧との組み合わせで動作する必要はない。
(8)実施の形態1において、外部メモリ440はマルチプロセッサLSI100の外部に存在する例について説明したが、マルチプロセッサLSI100内に集積されていても構わない。
(9)実施の形態1において、プロセッサに割り当てられているタスクの数に応じて、そのプロセッサの電源電圧と動作周波数とが設定される例について説明したが、プロセッサに割り当てられているタスクの数に応じて、そのプロセッサの動作周波数が設定され、プロセッサの電源電圧は、そのプロセッサに割り当てられているタスクの数に関わらず一定であるとしても構わないし、プロセッサに割り当てられているタスクの数に関わらず、そのプロセッサの電源電圧と動作周波数とが一定であるとしても構わない。
(10)実施の形態2において、割当プロセッサ群候補の中から、プロセッサとそのプロセッサに割り当てられるOSとの組み合わせについて、現在タスクの割り当てられているプロセッサ群における組み合わせとの差分が最も少なくなる割当プロセッサ群を選出し、選出した割当プロセッサ群を、タスクを割り当てるプロセッサ群とする例について説明したが、プロセッサとそのプロセッサの電源電圧との組み合わせについて、現在タスクの割り当てられているプロセッサ群における組み合わせとの差分が最も少なくなる割当プロセッサ群を選出するとしても構わないし、プロセッサとそのプロセッサの動作周波数との組み合わせについて、現在タスクの割り当てられているプロセッサ群における組み合わせとの差分が最も少なくなる割当プロセッサ群を選出するとしても構わない
(11)実施の形態2において、ハイパーバイザ1431上で3つの種類のOSが動作する例について説明したが、必ずしもOSの種類は3つでなくても構わない。
(12)実施の形態2において、タスク割当フラグは、タスク割当フラグ保持モジュール1436によってハイパーバイザ1431起動時に初期値“0”で初期化される例について説明したが、必ずしも、ハイパーバイザ1431起動時にのみ“0”に設定されるという構成に限る必要はない。
(13)実施の形態2において、各プロセッサには80個を上限としてタスクを割り当てる例について説明したが、必ずしも上限が80個に限られる必要はなく、タスクの種類やプロセッサの性能に応じてタスクの上限数を81個以上、又は79個以下としても構わない。
(14)実施の形態3において、第2変形プロセッサシステムは、タスクをプロセッサに割り当て直す動作を所定の時間毎に行う例について説明したが、必ずしも所定の時間毎に行う必要はなく、例えば、処理対象であるタスクの数の変動を検出する場合にタスクをプロセッサに割り当て直すとしても構わない。
652 第2タスク
653 第3タスク
654 第4タスク
655 第Nタスク
601 第1OS
602 第2OS
603 第3OS
604 第KOS
631 ハイパーバイザ
632 OSタスク対応情報保持モジュール
633 プロセッサ選択モジュール
634 電圧周波数情報保持モジュール
635 動作パターン情報保持モジュール
Claims (10)
- 各プロセッサが互いに通信する3以上のプロセッサを含み、タスク群の処理を行うマルチプロセッサシステムであって、
プロセッサ間の接続関係を反映した接続情報を記憶する記憶手段と、
前記記憶手段に記憶されている接続情報を参照して、各プロセッサに処理させるタスクを割り当てるタスク管理手段とを備え、
前記タスク管理手段は、前記タスクの割り当てにおいて、第1のプロセッサと、直接接続されるプロセッサのうちタスクの割り当てられているプロセッサの数が前記第1のプロセッサよりも少ない第2のプロセッサとについては、前記第1のプロセッサに割り当てられるタスクの量が前記第2のプロセッサに割り当てられるタスクの量以上となるように前記タスクの割り当てを行う
ことを特徴とするマルチプロセッサシステム。 - 前記タスク管理手段によって各プロセッサに割り当てられたタスクの量に基づいて、各プロセッサの動作周波数を決定する動作周波数決定手段と、
前記動作周波数決定手段によって決定された動作周波数で各プロセッサを動作させる動作制御手段とを備え、
前記動作周波数決定手段は、前記動作周波数の決定において、前記第1のプロセッサと前記第2のプロセッサとについては、前記第1のプロセッサの動作周波数が前記第2のプロセッサの動作周波数以上となるように前記動作周波数の決定を行う
ことを特徴とする請求項1記載のマルチプロセッサシステム。 - 前記動作周波数決定手段によって決定された前記プロセッサの各々の動作周波数に基づいて、第1の動作周波数で動作するプロセッサと当該第1の動作周波数未満の動作周波数である第2の動作周波数で動作するプロセッサとが存在する場合に、前記第1の動作周波数で動作するプロセッサの動作電圧が前記第2の動作周波数で動作するプロセッサの動作電圧以上となるように、各プロセッサの動作電圧を決定する動作電圧決定手段と、
前記動作電圧決定手段で決定された動作電圧を各プロセッサに供給する電圧供給手段とを備える
ことを特徴とする請求項2記載のマルチプロセッサシステム。 - 前記タスク管理手段は、前記タスクの割り当てを、タスクが割り当てられる各プロセッサが接続するプロセッサのうちの少なくとも1つは、タスクが割り当てられるプロセッサとなるように行う
ことを特徴とする請求項3記載のマルチプロセッサシステム。 - 前記動作周波数決定手段は、前記決定する動作周波数の決定を、タスクが割り当てられていないプロセッサが存在する場合に、当該プロセッサの動作周波数が0ヘルツとなるように行う
ことを特徴とする請求項4記載のマルチプロセッサシステム。 - 前記タスクの量が、タスクの数である
ことを特徴とする請求項1記載のマルチプロセッサシステム。 - 前記タスク管理手段は、時間の経過を測定するタイマを備え、前記タスクの割り当てを、所定時間毎に、割り当てるタスクの量が最多となるプロセッサが直前に割り当てていたタスクの量が最多のプロセッサ以外となるように行う、
ことを特徴とする請求項1記載のマルチプロセッサシステム。 - 前記マルチプロセッサシステムに含まれる全てのプロセッサは1つの半導体集積回路内に行列状に配置され、
各プロセッサは、互いに同じ形状の長方形であって、隣接する他のプロセッサと直接接続する
ことを特徴とする請求項1記載のマルチプロセッサシステム。 - 各プロセッサが互いに通信する3以上のプロセッサと、プロセッサ間の接続関係を反映した接続情報を記憶する記憶手段とを含み、タスク群の処理を行うマルチプロセッサシステムを制御するマルチプロセッサ制御方法であって、
各プロセッサに処理させるタスクを割り当てる場合に、前記記憶手段に記憶されている前記接続情報を参照して、第1のプロセッサと、直接接続されるプロセッサのうちタスクの割り当てられているプロセッサの数が前記第1のプロセッサよりも少ない第2のプロセッサとについては、前記第1のプロセッサに割り当てられるタスクの量が前記第2のプロセッサに割り当てられるタスクの量以上となるように前記タスクの割り当てを行う
ことを特徴とするマルチプロセッサ制御方法。 - 各プロセッサが互いに通信する3以上のプロセッサを含み、タスク群の処理を行うマルチプロセッサ集積回路であって、
プロセッサ間の接続関係を反映した接続情報を記憶する記憶手段と、
前記記憶手段に記憶されている接続情報を参照して、各プロセッサに処理させるタスクを割り当てるタスク管理手段とを備え、
前記タスク管理手段は、前記タスクの割り当てにおいて、第1のプロセッサと、直接接続されるプロセッサのうちタスクの割り当てられているプロセッサの数が前記第1のプロセッサよりも少ない第2のプロセッサとについては、前記第1のプロセッサに割り当てられるタスクの量が前記第2のプロセッサに割り当てられるタスクの量以上となるように前記タスクの割り当てを行う
ことを特徴とするマルチプロセッサ集積回路。
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Also Published As
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US20110119677A1 (en) | 2011-05-19 |
US9032407B2 (en) | 2015-05-12 |
EP2437170A4 (en) | 2013-03-13 |
JPWO2010137262A1 (ja) | 2012-11-12 |
EP2437170A1 (en) | 2012-04-04 |
JP5406287B2 (ja) | 2014-02-05 |
CN102105866A (zh) | 2011-06-22 |
CN102105866B (zh) | 2014-02-26 |
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