WO2010125616A1 - 符号化ストリーム復号装置 - Google Patents
符号化ストリーム復号装置 Download PDFInfo
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- WO2010125616A1 WO2010125616A1 PCT/JP2009/004878 JP2009004878W WO2010125616A1 WO 2010125616 A1 WO2010125616 A1 WO 2010125616A1 JP 2009004878 W JP2009004878 W JP 2009004878W WO 2010125616 A1 WO2010125616 A1 WO 2010125616A1
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- 238000000034 method Methods 0.000 claims abstract description 112
- 238000012790 confirmation Methods 0.000 claims description 20
- 238000011084 recovery Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 15
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 15
- 238000001514 detection method Methods 0.000 description 5
- 238000012804 iterative process Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
- H04L65/60—Network streaming of media packets
- H04L65/75—Media network packet handling
- H04L65/762—Media network packet handling at the source
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/146—Data rate or code amount at the encoder output
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
- H04N19/89—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
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- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/005—Correction of errors induced by the transmission channel, if related to the coding algorithm
Definitions
- the present invention relates to a signal processing apparatus that handles stream data, and more particularly, to an encoded stream decoding apparatus that includes variable-length encoded data.
- variable-length code decoding device described in Patent Document 1 has a configuration in which an error can be easily detected when a bitstream to be decoded is incorrect.
- the variable length code decoding device includes a first storage unit 1, a decoding unit 2, a timer unit 3, and a control unit 4.
- the first storage unit 1 stores the received variable length code data.
- the decoding unit 2 decodes the Huffman code read from the first storage unit 1.
- the timer unit 3 outputs a time-up signal after a predetermined time has elapsed from the start of decoding by the decoding unit 2.
- the control unit 4 forcibly terminates the decoding by the decoding unit 2 based on the time-up signal from the timer unit 3.
- JP 2002-185332 A (page 3-11, FIG. 1 etc.)
- the present invention solves the above-described problems, and an object of the present invention is to provide an encoded stream decoding apparatus that can efficiently detect errors in a system that requires high-speed and complicated processing.
- the present invention detects a stream error based on the total consumed stream amount after the decoding process and the number of decoding processes, so that it does not wait for a long timeout period. To do.
- the encoded stream decoding apparatus of the present invention includes a buffer unit that stores a stream input from the outside, a decoding unit that performs a variable-length code decoding process on the stream stored in the buffer unit, and the decoding unit A control unit for generating a control signal for controlling the operation and outputting the control signal to the decoding unit, a threshold setting unit for storing a threshold value of a consumption stream consumed by the decoding unit, a threshold value of the threshold setting unit, And an invalidating unit that generates a decoding invalidation signal based on the consumed stream amount consumed by the decoding unit and outputs the decoding invalidation signal to the control unit.
- the encoded stream decoding apparatus further comprises a filling confirmation means for confirming that a sufficient amount of stream considering the threshold stored by the threshold setting means is stored in the buffer means. Is characterized in that the decoding means waits until the filling of the stream is confirmed by the filling confirmation means.
- the present invention provides the encoded stream decoding apparatus, wherein when the control means receives a decoding invalidation signal from the invalidation means, the control means stops the decoding operation of the decoding means by the control signal, and the decoding means When the invalidation means generates a decoding invalidation signal, the decoding process is stopped by the control signal from the control means, and the stream is not consumed.
- the present invention provides the encoded stream decoding apparatus, wherein the control means generates a control signal for continuing the decoding of the decoding means even when receiving the decoding invalidation signal from the invalidating means, and the decoding means comprises: The decoding invalidation signal generated by the invalidation means is received, and while receiving the decoding invalidation signal, the control means behaves as if it received the control signal generated by the control means and operated. It is characterized by that.
- the decoding unit does not perform a decoding process while receiving a decoding invalidation signal from the invalidating unit, and generates a special value as a decoding result.
- the decoding result of the special value is output to the control means.
- the present invention is characterized in that, in the encoded stream decoding apparatus, the decoding means reduces power consumption such as clock down while receiving a decoding invalidation signal from the invalidation means.
- control means determines whether or not a decoding invalidation signal is generated from the invalidating means after completion of a task consisting of a series of decoding processes, and the decoding invalidation When the control signal is generated, control for returning is performed.
- the invalidation unit can transmit a difference between the threshold value of the threshold setting unit and the total consumption amount of the stream consumed by the decoding unit, and the buffer unit can store the internal stream.
- a state storage unit that can transmit a state, and the state storage unit sets a new difference between the threshold and the total stream consumption when the interrupted decoding process is resumed after the decoding process in the decoding unit is interrupted.
- the threshold setting unit is notified as a threshold value, and the stream state of the buffer unit is restored.
- the state storage unit changes a difference between the threshold value and the total stream consumption amount and notifies the threshold setting unit, and the buffer to cope with the change.
- the stream state of the means is changed so that the stream can be rewound or skipped.
- the encoded stream decoding apparatus further includes another control unit that generates another control signal for controlling the operation of the decoding unit and outputs the control signal to the decoding unit. While receiving the decoding invalidation signal from the conversion means, the decoding processing based on the control signal from the other control means is executed.
- control unit controls a plurality of tasks in parallel, and the decoding unit performs the decoding process based on any one of the plurality of tasks. While receiving the decryption invalidation signal from the invalidation means, the decryption process of another task is executed.
- the encoded stream decoding apparatus of the present invention includes a buffer unit that stores a stream input from the outside, a decoding unit that performs a variable-length code decoding process on the stream stored in the buffer unit, and controls the operation of the decoding unit
- a control unit that generates a control signal for output to the decoding unit, a threshold setting unit that stores a threshold of the number of times the control signal is generated by the control unit, a threshold of the threshold setting unit, and the control unit
- an invalidating means for generating a decoding invalidation signal based on the number of generations of the control signal and notifying the control means.
- the present invention further comprises a filling confirmation means for confirming that a predetermined amount of stream has been stored in the buffer means, and the control means uses the filling confirmation means to reduce the stream to a predetermined amount.
- the decoding means is made to wait until it is confirmed that the charging is completed.
- the present invention provides the encoded stream decoding apparatus, wherein when the control means receives a decoding invalidation signal from the invalidation means, the control means stops the decoding operation in the decoding means by the control signal, and the decoding means comprises: When the invalidation means generates a decoding invalidation signal, the decoding process is stopped in response to the control signal from the control means, and the stream is not consumed.
- the consumption stream amount that has been decoded is accumulated, and when the total consumption stream amount exceeds the threshold value of the threshold setting unit, Alternatively, when the number of times the control signal is generated by the control means, that is, when the number of decoding processes exceeds the threshold value of the threshold setting means, the invalidation means immediately generates a decoding invalidation signal. It is detected immediately without generating.
- the buffer means does not enter the underflow state until the decoding invalidation signal is generated by the invalidating means.
- the decoding means stops the consumption of the stream, so that the buffer means can be used even when the external stream input is delayed after the generation of the decoding invalidating signal. Will not fall into an underflow condition.
- control means it is not necessary for the control means to check for each decoding process whether or not the decoding invalidation signal is generated and whether or not the buffer means is in an underflow state. It becomes.
- the decoding means when a decoding invalidation signal is generated, the decoding means outputs a special value, for example, 0, as a decoding result. Therefore, even if a decoding invalidation signal is generated during audio signal processing, the output is silent. Can be. Therefore, generation of noise due to stream errors is prevented without performing exception processing by the control means.
- control means does not perform error detection every time the decoding process is executed, but after completion of the continuous series of decoding processes, obtains the presence or absence of the generation of the decoding invalidation signal from the invalidating means, Since return processing is performed as necessary, it is possible to insert error detection and return processing at predetermined regular intervals while simplifying control by the control means for executing each decoding processing.
- the state storage means stores the difference between the threshold value and the total stream consumption and the stream state of the buffer means, the task consisting of a series of continuous decoding processes is temporarily interrupted. It is possible to perform decoding processing of other tasks and other streams, and then resume the interrupted task.
- the difference between the threshold value and the total stream consumption is changed from the original value, and the state of the stream of the buffer means is changed correspondingly. It becomes possible to skip.
- control means processes a plurality of tasks or when there are a plurality of control means
- decoding invalidation signal when a decoding invalidation signal is generated, another task or other control means can use the decoding means.
- a stream error can be detected without causing a long waiting time, so that a decoding system or multitask system that operates at high speed or a constant bit rate can be used. Even when a non-codec is handled, the relative waiting time until error detection can be effectively shortened.
- FIG. 1 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is a flowchart showing a processing example of the encoded stream decoding apparatus.
- FIG. 3 is a block diagram showing the configuration of the encoded stream decoding apparatus according to Embodiment 2 of the present invention.
- FIG. 4 is a flowchart showing a processing example of the encoded stream decoding apparatus.
- FIG. 5 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 3 of the present invention.
- FIG. 6 is a flowchart showing a processing example of the encoded stream decoding apparatus.
- FIG. 1 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is a flowchart showing a processing example of the encoded stream decoding apparatus.
- FIG. 3 is a block diagram showing the configuration of the encoded stream decoding apparatus
- FIG. 7 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 4 of the present invention.
- FIG. 8 is a flowchart showing a processing example of the encoded stream decoding apparatus.
- FIG. 9 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 5 of the present invention.
- FIG. 10 is a block diagram showing another configuration of the encoded stream decoding apparatus.
- FIG. 11 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 6 of the present invention.
- FIG. 12 is a diagram illustrating an example of an encoding table.
- FIG. 13 is a block diagram showing a configuration of a conventional variable length code decoding apparatus.
- FIG. 1 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 1 of the present invention.
- the encoded stream decoding apparatus shown in FIG. 1 includes a buffer circuit 11, a decoding circuit 12, a control circuit 13 made of, for example, a processor, a threshold setting circuit 14, and an invalidation circuit 15, and a stream input from the outside.
- the variable length code is decoded.
- the buffer circuit (buffer means) 11 is filled with a stream input from the outside in preparation for decoding processing.
- the decoding circuit (decoding means) 12 performs a variable length decoding process corresponding to the control signal on the stream input from the buffer circuit 11, and outputs a decoding result and a consumption amount of the stream consumed at that time.
- control circuit (control means) 13 performs various controls regarding the decoding operation of the decoding circuit 12.
- a series of operations of the control circuit 13 is hereinafter referred to as a task.
- the control circuit 13 generates a control signal for controlling the decoding circuit 12 and repeats the operation of receiving the decoding result.
- a method of generating the control signal a method of determining the next control signal depending on the stream input so far, a method of determining by decoding the header portion of the stream, and the like are conceivable.
- the threshold value setting circuit (threshold value setting means) 14 is set with a threshold value before the start of the decoding process by the outside or the control circuit 13, and outputs the threshold value to the invalidation circuit 15. Furthermore, the invalidation circuit (invalidation means) 15 calculates the sum of the stream consumptions output from the decoding circuit 12, and validates the decoding invalidation signal if it exceeds the threshold value output from the threshold setting circuit 14. To do. Specifically, “0” is output as the decryption invalidation signal when the sum of the stream consumption amounts is equal to or smaller than the threshold value, and “1” as the decryption invalidation signal when the sum of the stream consumption amounts exceeds the threshold value. Is output.
- FIG. 2 shows a decoding process flow according to this configuration.
- the threshold setting circuit 14 stores the threshold received from the outside or the control circuit 13.
- the “16” bits are set as the “threshold value” equal to the normal (no error) total consumed stream amount.
- the control circuit 13 enters an iterative process for the decoding process. It is assumed that the control circuit 13 knows that decoding is completed in six decoding processes by analyzing the header portion of the stream or the like, or knows in advance by the standard.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and “1”, which is a length of “0”, is transmitted to the invalidation circuit 15 as a stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “1” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “a” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and The length “3” of “110” is transmitted to the invalidation circuit 15 as the stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “4” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “c” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable-length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and “1”, which is a length of “0”, is transmitted to the invalidation circuit 15 as a stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “5” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “a” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable-length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and “2”, which is a length of “10”, is transmitted to the invalidation circuit 15 as a stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “7” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “b” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable-length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and “2”, which is a length of “10”, is transmitted to the invalidation circuit 15 as a stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “9” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “b” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and “7”, which is the length of “1111111”, is transmitted to the invalidation circuit 15 as a stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “16” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs a decoding process and outputs the decoding result “h” to the control circuit 13.
- the 17th bit is a stream that follows the stream that should be decoded.
- the threshold setting circuit 14 stores the threshold received from the outside or the control circuit 13. It is assumed that 16 bits as the stream length are input from the outside, and that “16” is set as a threshold value.
- the control circuit 13 enters an iterative process for the decoding process.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and “1”, which is a length of “0”, is transmitted to the invalidation circuit 15 as a stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “1” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “a” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and The length “3” of “110” is transmitted to the invalidation circuit 15 as the stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “4” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “c” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 acquires the stream “0” from the buffer circuit 11.
- the decryption circuit 12 transmits the stream consumption “1” to the invalidation circuit 15, and the invalidation circuit 15 compares the threshold value “16” with the total stream consumption “5”. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “a” to the control circuit 13.
- the control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable-length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and “2”, which is a length of “10”, is transmitted to the invalidation circuit 15 as a stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “7” of the stream consumption amounts. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “b” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable-length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and The length “1111111” “7” is transmitted to the invalidation circuit 15 as the stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the total stream consumption amount “14”. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs a decoding process and outputs the decoding result “h” to the control circuit 13. The control circuit 13 confirms that the decoding invalidation signal is “0” and continues the processing.
- the control circuit 13 After confirming that the buffer circuit 11 is not in the underflow state, the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and The length “3” of “110” is transmitted to the invalidation circuit 15 as the stream consumption amount, and the invalidation circuit 15 compares the threshold value “16” with the sum “17” of the stream consumption amounts. Since the sum of the stream consumption amounts exceeds the threshold value, the invalidation circuit 15 outputs “1” as a decoding invalidation signal. Since the decoding invalidation signal is “1”, the control circuit 13 outputs to the decoding circuit 12 a control signal for stopping the decoding repetition process. As a result, the decoding circuit 12 stops the decoding process and does not consume the stream thereafter. Further, the control circuit 13 performs a return process and ends the task.
- the stream length when there is no error is stored in the header, and the correct stream length can be acquired before decoding.
- the configuration of the present embodiment can be adopted by using the maximum value of or using the maximum length that may be an actual usage scene as a threshold value.
- FIG. 3 is a block diagram showing the configuration of the encoded stream decoding apparatus according to Embodiment 2 of the present invention. Unlike the first embodiment, this configuration has a filling confirmation circuit 16. The rest is the same as in the first embodiment.
- a filling confirmation circuit (filling confirmation means) 16 receives a filling stream amount from the buffer circuit 11 and a threshold value from a threshold setting circuit. Both are compared, and if the amount of the filled stream is equal to or greater than the threshold value, the control circuit 13 is notified of this.
- FIG. 4 shows a processing flow example of this configuration.
- the control circuit 13 After the threshold value is set, the control circuit 13 generates a first control signal after the filling confirmation circuit 16 confirms the filling amount equal to or larger than the threshold value of the stream to the buffer circuit 11, and until the confirmation, the decoding circuit 12 performs the decoding. Wait for processing. The rest is the same as in the first embodiment.
- This configuration can eliminate the possibility of underflow during decoding processing in a system with unstable stream supply. For this reason, in a system in which the decoding circuit 12 returns an invalid value when underflow with a small amount of data in the decoding process, underflow determination during decoding decoding can be omitted. Further, in a system in which the decoding circuit 12 waits until the buffer circuit 12 is filled at the time of underflow, when an underflow occurs at the time of decoding processing, the control circuit 13 waits until the buffer circuit 12 is filled. The configuration prevents underflow during the decoding process, and the control circuit 13 can be used for processing other tasks until the buffer circuit 12 is filled before the decoding process starts.
- FIG. 5 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 3 of the present invention.
- the decoding invalidation signal generated by the invalidation circuit 15 is also notified to the decoding circuit 12. Further, it is assumed that how many times the decoding process is necessary is known in advance.
- FIG. 6 shows a processing flow example of this configuration.
- the control circuit 13 does not perform branching based on the decoding invalidation signal when executing the decoding processing, and continues to generate a control signal for continuing the decoding processing regardless of the decoding invalidation signal.
- the decoding circuit 12 accepts the control signal generated by the control circuit 13 when the decoding invalidation signal is “1”, but does not actually perform the decoding process. “0” is output to the control circuit 13 as a decoding result, and it behaves as if the decoding process was received in response to the control signal.
- the decoding circuit 12 may perform clock down, power interruption, or the like in order to reduce power consumption of unnecessary circuits.
- the control circuit 13 performs control for the return process when the decoding invalidation signal has been enabled after the end of the last decoding process.
- the threshold setting circuit 14 stores the threshold received from the outside or the control circuit 13. It is assumed that 16 bits as the stream length are input from the outside, and that “16” is set as a threshold value.
- the control circuit 13 enters an iterative process for the decoding process. It is assumed that the control circuit 13 knows that decoding is completed after 6 decoding processes.
- the control circuit 13 generates a control signal for decoding the variable-length code, and the decoding circuit 12 looks at the beginning of the stream of the buffer circuit 11 and sets “1”, which is “0” in length, as the stream consumption amount.
- the invalidation circuit 15 compares the threshold value “16” with the total stream consumption “1”. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “a” to the control circuit 13. The control circuit 13 continues the process regardless of the decoding invalidation signal.
- the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and sets “3”, which is “110” in length, as the stream consumption amount.
- the invalidation circuit 15 compares the threshold value “16” with the total stream consumption “4”. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “c” to the control circuit 13. The control circuit 13 continues the process regardless of the decoding invalidation signal.
- the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 acquires the stream “0” from the buffer circuit 11.
- the decryption circuit 12 transmits the stream consumption “1” to the invalidation circuit 15, and the invalidation circuit 15 compares the threshold value “16” with the total stream consumption “5”. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “a” to the control circuit 13. The control circuit 13 continues the process regardless of the decoding invalidation signal.
- the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and sets “7”, which is the length of “1111111” as the stream consumption amount.
- the invalidation circuit 15 compares the threshold value “16” with the stream consumption sum “12”. Since the sum of the stream consumption amounts is equal to or less than the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs a decoding process and outputs the decoding result “h” to the control circuit 13. The control circuit 13 continues the process regardless of the decoding invalidation signal.
- the control circuit 13 generates a control signal for decoding the variable length code, and the decoding circuit 12 looks at the head of the stream of the buffer circuit 11 and sets “5” which is the length of “11110” as the stream consumption amount.
- the invalidation circuit 15 compares the threshold value “16” with the total stream consumption “17”. Since the sum of the stream consumption amounts exceeds the threshold value, the invalidation circuit 15 outputs “1” as a decoding invalidation signal. Since the decoding invalidation signal is “1”, the decoding circuit 12 does not perform the decoding process, but outputs “0” as the decoding result. The control circuit 13 continues the process regardless of the decoding invalidation signal.
- the control circuit 13 generates a control signal for decoding the variable length code, but since the decoding invalidation signal is “1”, the decoding circuit 12 does not perform the decoding process and outputs “0” as the decoding result. To do.
- the control circuit 13 does not need to determine whether the value of the decoding invalidation signal is “0” or “1” for each decoding process. Since the stream input from the outside usually has no error in many cases, the processing that the control circuit 13 has to perform in each decoding process on the stream without the error can be reduced. If the decoding invalidation signal is “1” at the end, the control circuit 13 may perform control such as discarding one task with an error.
- FIG. 7 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 4 of the present invention.
- the configuration of the present embodiment includes a state storage circuit 17.
- the state storage circuit (state storage means) 17 stores the difference between the threshold value input from the invalidation circuit 15 and the total stream consumption (threshold value-total stream consumption) and the state of the stream in the buffer circuit 11. Also, the difference between the stored threshold and the total stream consumption is notified to the threshold setting circuit 14 to restore the stream state of the buffer circuit 11.
- FIG. 8 shows a processing flow example of this configuration.
- the control circuit 13 can perform control for interrupting the decoding process when determining whether to continue the decoding process.
- the state storage circuit 17 receives the difference between the threshold value input from the invalidation circuit 15 and the total stream consumption and the buffer circuit acquired from the buffer circuit 11. The state of 11 streams is stored.
- decoding is resumed, the state of the stream in the buffer circuit 11 is restored, the difference between the stored threshold and the total stream consumption is notified to the threshold setting circuit 14 as a new threshold, and the interrupted process is resumed.
- the state storage circuit 17 is the difference between the threshold “16” and the total stream consumption “7”. “9” and the state held by the buffer circuit 11 such as a pointer pointing to the head of the stream are stored. Thereafter, when the decoding process is resumed, “9” is set as a new threshold value in the threshold setting circuit 14, the pointer of the buffer circuit 11 is set, and if necessary, the stream is filled. Resume processing from processing.
- control circuit 13 is realized by a processor that also executes tasks other than the decoding process, a more complicated system can be configured if it can be switched to another task in the middle of the decoding process.
- stream skipping and rewinding can be realized by changing and restoring the difference between the threshold value and the total stream consumption and the state of the stream in the buffer circuit 11.
- FIG. 9 is a block diagram showing the configuration of the encoded stream decoding apparatus according to Embodiment 5 of the present invention.
- the configuration of the present embodiment includes a control circuit 13a and another control circuit (other control means) 13b.
- the decoding circuit 12 accepts only the control signal generated by any one of the control circuits (for example, 13a), and the task of the control circuit 13a being executed is completed, or the method of the fourth embodiment Until the processing is interrupted, only the control signal from the same control circuit 13a is accepted.
- the decoding invalidation signal becomes valid to “1”
- the decoding circuit 12 does not need to perform decoding for the task thereafter, so that only the control signal generated by the other control circuit 13b is accepted. To do.
- FIG. 10 shows a configuration in which one control circuit 13 performs a plurality of tasks 18a and 18b in parallel.
- each task 18a, 18b outputs a control signal
- an identification signal for distinguishing the tasks is output at the same time, whereby processing can be performed in the same manner as when there are a plurality of control circuits.
- FIG. 11 is a block diagram showing a configuration of an encoded stream decoding apparatus according to Embodiment 6 of the present invention.
- 11 includes a buffer circuit 11, a decoding circuit 12, a control circuit 13, a threshold setting circuit 14, an invalidation circuit 15, and a filling confirmation circuit 16.
- the buffer circuit 11 is filled with a stream input from the outside in preparation for the decoding process.
- the decoding circuit 12 performs a decoding process corresponding to the control signal on the stream input from the buffer circuit 11, and outputs a decoding result.
- the control circuit 13 generates a control signal for controlling the decoding circuit 12 and receives the result.
- the threshold setting circuit (threshold setting means) 14 is set by the external or control circuit 13 the number of times that the control circuit 13 generates the control signal, that is, the threshold of the number of decoding processes, and the threshold is invalidated by the circuit 15. Output to.
- the invalidation circuit 15 compares the number of times that the control circuit 13 has generated the control signal with the threshold value from the threshold value setting circuit 14, and if the predetermined number of control signal generation times exceeds the threshold value, the invalidation circuit 15 validates the decoding invalidation signal.
- the filling confirmation circuit 16 receives the filling stream amount from the buffer circuit 11 and notifies the control circuit 13 when the filling stream amount is equal to or larger than a predetermined amount.
- the threshold setting circuit 14 stores a threshold received from the outside or the control circuit 13.
- “6” is input from the outside as the number of normal control signal generations (normal number of decoding processes), and “6” is set as a threshold value.
- the control circuit 13 enters an iterative process for the decoding process.
- the control circuit 13 generates a control signal for decoding the variable length code, and the invalidation circuit 15 compares the threshold “6” with the number of control signal generations “1”. Since the number of generations of the control signal is less than or equal to the threshold value, the invalidation circuit 15 outputs “0” as the decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “a” to the control circuit 13. Since the decoding result is not “h”, the control circuit 13 continues the processing.
- the control circuit 13 generates a control signal for decoding the variable-length code, and the invalidation circuit 15 compares the threshold “6” with the number of control signal generations “2”. Since the total number of control signal generations is less than or equal to the threshold value, the invalidation circuit 15 outputs “0” as a decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “c” to the control circuit 13. Since the decoding result is not “h”, the control circuit 13 continues the processing.
- the control circuit 13 generates a control signal for decoding the variable-length code, and the invalidation circuit 15 compares the threshold “6” with the number of control signal generations “3”. Since the total number of control signal generations is less than or equal to the threshold value, the invalidation circuit 15 outputs “0” as a decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “a” to the control circuit 13. Since the decoding result is not “h”, the control circuit 13 continues the processing.
- the control circuit 13 generates a control signal for decoding the variable-length code, and the invalidation circuit 15 compares the threshold “6” with the number of control signal generations “4”. Since the total number of control signal generations is less than or equal to the threshold value, the invalidation circuit 15 outputs “0” as a decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “b” to the control circuit 13. Since the decoding result is not “h”, the control circuit 13 continues the processing.
- the control circuit 13 generates a control signal for decoding the variable length code, and the invalidation circuit 15 compares the threshold “6” with the number of control signal generations “5”. Since the total number of control signal generations is less than or equal to the threshold value, the invalidation circuit 15 outputs “0” as a decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “b” to the control circuit 13. Since the decoding result is not “h”, the control circuit 13 continues the processing.
- the control circuit 13 generates a control signal for decoding the variable length code, and the invalidation circuit 15 compares the threshold “6” with the number of control signal generations “6”. Since the total number of control signal generations is less than or equal to the threshold value, the invalidation circuit 15 outputs “0” as a decoding invalidation signal. Since the decoding invalidation signal is “0”, the decoding circuit 12 performs the decoding process and outputs the decoding result “b” to the control circuit 13. Since the decoding result is not “h”, the control circuit 13 continues the processing.
- the control circuit 13 generates a control signal for decoding the variable-length code, and the invalidation circuit 15 compares the threshold “6” with the number of control signal generations “7”. Since the total number of control signal generation times exceeds the threshold value, the invalidation circuit 15 outputs “1” as a decoding invalidation signal. Since the decoding invalidation signal is “1”, the control circuit 13 generates a control signal for stopping the decoding process, and as a result, the decoding circuit 12 does not perform the decoding process. Thereafter, the control circuit 13 ends the process.
- the encoded stream decoding apparatus can detect stream errors without requiring a long waiting time, the apparatus for decoding audio or video using advanced encoding technology, or a variable It is useful when applied to applications such as communication devices using long codes.
- Buffer circuit (buffer means) 12 Decoding circuit (decoding means) 13 Control circuit (control means) 13b Other control circuit (other control means) 14 Threshold setting circuit (threshold setting means) 15 Invalidation circuit (invalidation means) 16 Filling confirmation circuit (filling confirmation means) 17 State storage circuit (state storage means)
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Abstract
Description
図1は、本発明の実施形態1に係る符号化ストリーム復号装置の構成を示すブロック図である。
図3は、本発明の実施形態2に係る符号化ストリーム復号装置の構成を示すブロック図である。この構成では、実施形態1と異なり、充填確認回路16を持つ。それ以外は実施形態1と同じである。
図5は、本発明の実施形態3に係る符号化ストリーム復号装置の構成を示すブロック図である。
図7は、本発明の実施形態4に係る符号化ストリーム復号装置の構成を示すブロック図である。
図9は、本発明の実施形態5に係る符号化ストリーム復号装置の構成を示すブロック図である。
図11は、本発明の実施形態6に係る符号化ストリーム復号装置の構成を示すブロック図である。
12 復号回路(復号手段)
13 制御回路(制御手段)
13b 他の制御回路(他の制御手段)
14 閾値設定回路(閾値設定手段)
15 無効化回路(無効化手段)
16 充填確認回路(充填確認手段)
17 状態保存回路(状態保存手段)
Claims (14)
- 外部から入力されるストリームを蓄えるバッファ手段と、
前記バッファ手段に蓄えられたストリームに対し可変長符号復号処理を行う復号手段と、
前記復号手段の動作を制御するための制御信号を生成して前記復号手段に出力する制御手段と、
前記復号手段で消費された消費ストリームの閾値を格納する閾値設定手段と、
前記閾値設定手段の閾値と、前記復号手段で消費された消費ストリーム量とに基づいて復号無効化信号を発生して前記制御手段に出力する無効化手段とを備えた
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項1記載の符号化ストリーム復号装置において、
前記閾値設定手段が格納する閾値を考慮した十分な量のストリーム量が前記バッファ手段に蓄えられたことを確認する充填確認手段を備え、
前記制御手段は、前記充填確認手段によりストリームの充填が確認されるまで前記復号手段を待機させる
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項1又は2記載の符号化ストリーム復号装置において、
前記制御手段は、前記無効化手段から復号無効化信号を受けたとき、制御信号により前記復号手段の復号動作を停止させ、
前記復号手段は、前記無効化手段が復号無効化信号を発生しているとき、前記制御手段からの制御信号により復号処理を停止し、ストリームを消費しない
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項1又は2記載の符号化ストリーム復号装置において、
前記制御手段は、前記無効化手段から復号無効化信号を受けても、前記復号手段の復号を継続させる制御信号を生成し、
前記復号手段は、前記無効化手段が発生する復号無効化信号を受け、この復号無効化信号を受けている間は、前記制御手段に対して、前記制御手段が生成する制御信号を受理して動作したようにふるまう
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項4記載の符号化ストリーム復号装置において、
前記復号手段は、
前記無効化手段からの復号無効化信号を受けている間は、復号処理を行わず、
復号結果として特殊な値を生成して、その特殊な値の復号結果を前記制御手段に出力する
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項4又は5記載の符号化ストリーム復号装置において、
前記復号手段は、
前記無効化手段からの復号無効化信号を受けている間は、クロックダウンなどの消費電力の低減を行う
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項5記載の符号化ストリーム復号装置において、
前記制御手段は、
一連の復号処理からなるタスクの終了後、前記無効化手段から復号無効化信号が発生しているかどうかを判断し、その復号無効化信号が発生しているとき、復帰のための制御を行う
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項3記載の符号化ストリーム復号装置において、
前記無効化手段から前記閾値設定手段の閾値と前記復号手段で消費したストリーム総消費量との差分を伝えられると共に、前記バッファ手段から内部のストリームの状態を伝えられる状態保存手段を備え、
前記状態保存手段は、前記復号手段での復号処理が中断した後、その中断した復号処理の再開時には、前記閾値とストリーム総消費量との差分を新たな閾値として前記閾値設定手段に通知すると共に、前記バッファ手段のストリームの状態を復元させる
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項8記載の符号化ストリーム復号装置において、
前記状態保存手段は、
前記閾値とストリーム総消費量との差分を変更して前記閾値設定手段に通知すると共に、この変更に対応するように前記バッファ手段のストリームの状態を変更して、
ストリームの巻き戻し又はスキップを可能とした
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項3記載の符号化ストリーム復号装置において、
前記復号手段の動作を制御するための他の制御信号を生成して前記復号手段に出力する他の制御手段を備え、
前記復号手段は、前記無効化手段から復号無効化信号を受けている間は、前記他の制御手段からの制御信号に基づく復号処理を実行する
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項3記載の符号化ストリーム復号装置において、
前記制御手段は、複数のタスクを並列に制御し、
前記復号手段は、前記複数のタスクのうち何れか1つのタスクに基づく復号処理の実行時において前記無効化手段から復号無効化信号を受けている間は、他タスクの復号処理を実行する
ことを特徴とする符号化ストリーム復号装置。 - 外部から入力されるストリームを蓄えるバッファ手段と、
前記バッファ手段に蓄えられたストリームに対し可変長符号復号処理を行う復号手段と、
前記復号手段の動作を制御するための制御信号を生成して前記復号手段に出力する制御手段と、
前記制御手段での制御信号の生成回数の閾値を格納する閾値設定手段と、
前記閾値設定手段の閾値と前記制御手段での制御信号の生成回数とに基づいて復号無効化信号を発生して前記制御手段に通知する無効化手段とを備えた
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項12記載の符号化ストリーム復号装置において、
所定量のストリーム量が前記バッファ手段に蓄えられたことを確認する充填確認手段を備え、
前記制御手段は、前記充填確認手段によりストリームの所定量への充填が確認されるまで前記復号手段を待機させる
ことを特徴とする符号化ストリーム復号装置。 - 前記請求項12又は13記載の符号化ストリーム復号装置において、
前記制御手段は、前記無効化手段から復号無効化信号を受けたとき、制御信号により前記復号手段での復号動作を停止させ、
前記復号手段は、前記無効化手段が復号無効化信号を発生しているとき、前記制御手段からの制御信号を受けて、復号処理を停止し、ストリームを消費しない
ことを特徴とする符号化ストリーム復号装置。
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