WO2010123765A2 - Thin bond line semiconductor packages - Google Patents
Thin bond line semiconductor packages Download PDFInfo
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- WO2010123765A2 WO2010123765A2 PCT/US2010/031344 US2010031344W WO2010123765A2 WO 2010123765 A2 WO2010123765 A2 WO 2010123765A2 US 2010031344 W US2010031344 W US 2010031344W WO 2010123765 A2 WO2010123765 A2 WO 2010123765A2
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- adhesive
- substrate
- semiconductor
- adhesive system
- die
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
- C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
- C09J5/04—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving separate application of adhesive ingredients to the different surfaces to be joined
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
- C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
- C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01016—Sulfur [S]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
A semiconductor assembly comprises a plurality of semiconductor dies that are stacked one on top of the other and bonded to each other using a two-part adhesive system, in which one part of the adhesive system is applied to the top side of one die and the second part of the adhesive system is applied to the back side of another die, in which the two parts of the adhesive system are reactive with each other, and in which the two parts of the adhesive system when contacted together initiate a reaction and partial curing between the two parts of the adhesive system.
Description
THIN BOND LINE SEMICONDUCTOR PACKAGES
CROSS-REFERENCE TO RELATED APPLICATION
[0001) This application claims the benefit of United States Provisional Patent Application No. 61/170803 filed April 20, 2009, the contents of which is incorporated herein by reference.
BACKGROUND
[0002] This invention is directed to thin bond line semiconductor packages and methods for making such packages.
[0003] Miniaturization and slimming of electrical and electronic equipment leads to a need for smaller semiconductor packages and thinner semiconductor chips or dies. Smaller packages are obtained through the stacking of semiconductor dies, and particularly through the stacking of ever yet thinner semiconductor dies. Thinner dies, however, are more fragile than their thicker counterparts, and exhibit a greater number of fractures and cracks during thermal excursions or mechanical handling. Moreover, as the size of integrated circuits shrinks and the density of inputs/outputs increases, cross-talk between interconnections occurs and causes malfunction in the circuit. This can be corrected by the use of low dielectric constant ("low-K") materials to insulate the interconnects from their surroundings. Low-K interlayer dielectrics (particularly those below about 2.5) are generally weaker and more brittle than conventional dielectric materials and this fragility can also lead to fractures and cracks during thermal excursions or mechanical handling. To date there is a limit to techniques for achieving thinner electrical and electronic devices, which creates a need within the semiconductor industry to seek other avenues to reach miniaturization.
[0004] One such way is the reduction of the adhesive bond line between dies in a die stacking arrangement, which allows for the stacking of an increased number of dies in a given amount of vertical height. (At present, the die attach adhesive bond line is about 25 micron.)
[0005] Stacked die packaging has caused a shift to film adhesives and away from liquid die attach paste adhesives for die attach. The advantages of a film adhesive over a paste adhesive, when building a stack of multiple dies, are the elimination of separate attach cure steps for each of the individually placed dies, and sufficient mechanical strength and tack to hold six, eight or
more dies together in a stack prior to die attach cure, and, in some cases, sufficient strength to allow completion of wire bonding on the entire stack before die attach cure.
[0006] Processes for pyramid and shingle or staircase stacks use this advantage with the film adhesives by stacking all the dies first, then wire bonding all at one time at the same station. Attempting this process with a dispensable liquid or paste adhesive is not practical because of the potential for die shifting and misalignment of the die stack when the adhesive is not cured independently for each die as it is stacked.
[0007] Despite these advantages, film die attach adhesives are more expensive than liquid paste counterparts, they are difficult to obtain in a thickness of less than 0.005 microns, and they can cause placement voids if not handled properly.
[0008] It would be desirable to have a process by which a die attach adhesive bond line of less than 0.005 microns may be created without the expense and voiding issues of die attach adhesive films, but with sufficient strength to allow multiple die stacking and wire bonding on the entire stack before die attach cure.
SUMMARY OF THE INVENTION
[0009] This invention relates to a fast-setting two-part adhesive system that uses a minimal amount of adhesive to adhere semiconductors and their substrates. There is a reduction in bond line thickness when the minimal amount of adhesive is used, which then contributes to miniaturization. A semiconductor can be either a chip or a package; a package comprises at least one chip and one substrate. A substrate can be another chip or any rigid or flexible frame or carrier for a chip or for a package, such as, an interposer or a circuit board.
[00010] In one embodiment, the adhesive system comprises a first part, A, which is a low viscosity, self-leveling liquid that activates a cure mechanism on contact with the second part, B, with little or no heating; and a second part B, which is capable of being B-staged. Capable of being B-staged means that the adhesive can be heated or irradiated to a partial cure or to evaporate any solvent present, typically to the point that the adhesive after B-staging has no or low tack.
[00011] In other embodiments, the invention is a method for preparing an assembly of a semiconductor and a substrate, and in particular a semiconductor die stack prepared from a plurality of semiconductor dies.
[00012] In a further embodiment, the method comprises the steps of (1) providing (a) an adhesive system comprising a first part, A, which is a low viscosity, self-leveling liquid that activates a cure mechanism on contact with the second part, B, with little or no heating; and a second part B, which is capable of being B-staged, and (b) at least one semiconductor and one substrate; (2) dispensing part A on the top side of a substrate; (3) coating part B on the back side of a semiconductor and B-staging part B; (4) contacting the back side of the semiconductor with the B-staged part B to the part A adhesive on the top side of the substrate and spreading the part A adhesive to a combined adhesive layer with a thickness of < 50 microns (preferably < 5 microns); (5) allowing the part A and part B adhesives to react at room temperature, thereby partially curing; (6) repeating steps 2 through 5 as many times as needed to compose the assembly; and (7) subsequently, completing the curing of the part A and part B adhesives with heat.
[00013] In another embodiment, the method comprises (1 ) providing (a) an adhesive system comprising a first part, A, which is a low viscosity, self-leveling liquid that activates a cure mechanism on contact with the second part, B, with little or no heating; and a second part B, which is capable of being B-staged, and (b) at least one substrate and one semiconductor; (2) dispensing part A onto the top side of the substrate; (3) dispensing part B onto the part A adhesive on the top side of the substrate; (4) contacting the back side of the semiconductor with the top side of the substrate and spreading the part A and part B adhesives to a layer with a thickness of < 50 microns (preferably < 5 microns); (5) allowing the part A and part B adhesives to react at room temperature, thereby partially curing; (6) repeating steps 2 through 5 as many times as needed to compose the assembly; and (7) subsequently, completing the curing of the part A and part B adhesives with heat.
DETAILED DESCRIPTION OF THE INVENTION
[00014] The liquid part A is dispensed on the top of the substrate that is to come into contact with the back side of a semiconductor. Part A is typically dispensed in a pattern, such as, a dot, cross, X, snowflake, and the like). Part A has a thixotropic index in the range of 1 to 6 so that,
when later subjected to shear imposed by contact with a semiconductor having part B dispensed on it, it will flow and level over any topography on the substrate surface.
[00015] In one embodiment, part B is dispensed onto the back side of a semiconductor wafer using spraying, printing, spin coating or any other known method of coating. After coating, part B is B-staged by a method appropriate to the chemistry. The dispense is done to accomplish a level of approximately < 50 microns, preferably < 5 microns, thickness after B-staging. After B- staging, the wafer is diced into individual semiconductor dies. The B-staged part B on the back side of each of the semiconductor dies is then contacted to the part A adhesive on the substrate with sufficient pressure to cause capillary flow of the part A and ensure full coverage of part A over that part of the substrate desired. Because part A levels out on the substrate, void formations are prevented when the flat semiconductor die is placed on it using standard die attachment conditions of temperature (120 - 1500C), force (0.5 to 4.0 N), and time (1 to 1000 msecs).
[00016] In a further embodiment, part A is dispensed onto a substrate and part B is dispensed onto part A. In this embodiment, part B is not B-staged. The dispense volumes of A and B are calculated to achieve a cured thickness < 50 microns (preferably < 5 microns) . The back side of the semiconductor is then contacted to the combination of the part A and part B adhesive. Under standard placement conditions (120 - 1500C, 0.5 to 4.0 N, and 1 to 1000 msecs), there is sufficient pressure and time for parts A and B to mix.
[00017] In both embodiments, parts A and B after coming into contact begin curing and develop sufficient strength to withstand additional processing, such as, die stacking and subsequent wire bonding. Full cure is achieved during other heating steps, such as, at wire bond or molding.
[00018] The dispensing of the adhesive parts A and B can be effected by spraying, atomizing, blade coating, syringe dispensing, printing, jet printing, spin-coating, and laminating. In any of these application techniques, a thin, substantially uniform layer is applied to the semiconductor and/or substrate.
[00019] In another embodiment, this invention is a semiconductor assembly comprising a plurality of semiconductor dies that are stacked one on top of the other and bonded to each other using a two-part adhesive system, in which one part of the adhesive system was applied to the
top side of one die and the second part of the adhesive system was applied to the back side of another die, in which the two parts of the adhesive system are reactive with each other, and in which the two parts of the adhesive system were contacted together, thereby initiating a reaction and partial curing between the two parts of the adhesive system.
[00020] The two part adhesive is designed so that neither part will cure without contact with the other part, but will begin to cure immediately upon contact. Suitable chemistry pairs for two part systems are those that react with each other, for example, a curable compound with an activator or initiator for the curing. Examples are acrylate and peroxide; epoxy and amine; bismaleimide and peroxides or amines; cyanoacrylates and water (or primers/accelerators made of organic or inorganic bases).
[00021] The adhesive parts A and B are applied in thickness to yield a bond that after cure has a thickness in the range of 0.001 to 0.050 mm. In one embodiment, the cured bond thickness will be in the range of 0.001 to 0.005 mm.
[00022] The relative sizes of the semiconductor and substrate can be the same or different, and the alignment of the semiconductor chip and substrate can be similar or offset provided it allows bonding. The surface area of the semiconductor chip and substrate will be in the range of 1 mm2 to 625 mm2, and in one embodiment will be in the range of 30 mm2 to 80 mm2.
[00023] The adhesive system may be based on one or more of the following chemistries and a curing initiator for that chemistry. The chemistries include epoxy, episulfide, (meth)acrylate, cyanoacrylate, maleimide, nadimide, itaconimide, and isocyanate.
[00024] Suitable maleimide, nadimide or itaconimide compounds include, respectively, structures I, II, and III:
II III
in which m is 1-15; p is 0-15; each R2 independently is hydrogen or lower alkyl; J is a monovalent or a polyvalent organic moiety having sufficient length and branching to render the maleimide, nadimide and/or itaconimide compound a liquid. In one embodiment J is an organosiloxane or a hydrocarbyl, optionally containing heteroatoms (such as, oxygen, nitrogen, and sulfur). In some embodiments, p is zero (organic radical enclosed in parentheses is not present) and m is 1 to 6; in another embodiment, p is zero and m is 1 to 3. In those cases in which the J moiety contains heteroatoms or groups containing heteroatoms, the heteroatoms or groups are selected from the group consisting of -O-, -S-, -NR-, -O-C(O)-, -0-C(O)-O-, -0-C(O)-NR-, -NR-C(O)-, -NR-C(O)-O-, -NR-C(O)-NR-, -S-C(O)-, -S-C(O)-O-, -S-C(O)-NR-, -S(O)-, -S(O)2-, -0-S(O)2-, -0-S(O)2-O-, -0-S(O)2-NR-, -O-S(O)-, -0-S(O)-O-, -0-S(O)-NR-, -O-NR-C(O)-, -0-NR-C(O)-O-, -0-NR-C(O)-NR-, -NR-O-C(O)-, -NR-O-C(O)-O-, -NR-O-C(O)-NR-, -0-NR-C(S)-, -0-NR-C(S)-O-, -0-NR-C(S)-NR-, -NR-O-C(S)-, -NR-O-C(S)-O-, -NR-O-C(S)-NR-, -O-C(S)-, -0-C(S)-O-, -0-C(S)-NR-, -NR-C(S)-, -NR-C(S)-O-, -NR-C(S)-NR-, -S-S(O)2-, -S-S(O)2-O-, -S-S(O)2-NR-, -NR-O-S(O)-, -NR-O-S(O)-O-, -NR-O-S(O)-NR-, -NR-O-S(O)2-, -NR-O-S(O)2-O-, -NR-O-S(O)2-NR-, -0-NR-S(O)-, -0-NR-S(O)-O-, -0-NR-S(O)-NR-, -0-NR-S(O)2-O-, -0-NR-S(O)2-NR-, -0-NR-S(O)2-, -0-P(O)R2-, -S-P(O)R2-, -NR-P(O)R2-, where each R is independently hydrogen, alkyl or substituted alkyl.
[00025] A semiconductor package so formed includes a semiconductor chip bonded to a substrate by a two-step adhesive system as described in this specification.
Claims
1. An adhesive system comprising: a first part, A, that is a low viscosity, self-leveling liquid that activates a cure mechanism on contact with the second part, B, with little or no heating; and a second part B, that is capable of being B-staged.
2. The adhesive system of claim 1 in which part A adhesive is selected from the group consisting of peroxide; amine; water; and primers/accelerators made of organic or inorganic bases; and part B adhesive is selected from the group consisting of epoxy, episulfide, (meth)acrylate, cyanoacrylate, maleimide, nadimide, itaconimide, and isocyanate, provided that part A part B can react together.
3. A method for preparing an assembly of a semiconductor and a substrate comprising the steps of:
(1) providing (a) an adhesive system comprising a first part, A, that is a low viscosity, self-leveling liquid that activates a cure mechanism on contact with the second part, B, with little or no heating; and a second part B, that is capable of being B-staged, and (b) at least one semiconductor and one substrate;
(2) dispensing part A on the top side of a substrate;
(3) coating part B on the back side of a semiconductor die and B-staging part B;
(4) contacting the back side of the die with the B-staged part B to the part A adhesive on the top side of the substrate and spreading the part A adhesive resulting in a total adhesive layer with a thickness of < 50 microns (preferably < 5 microns);
(5) allowing the part A and part B adhesives to react at room temperature, thereby partially curing;
(6) repeating steps 2 through 5 as many times as needed to compose the assembly; and
(7) subsequently, completing the curing of the part A and part B adhesives with heat and/or irradiation.
4. A method for preparing an assembly of a semiconductor and a substrate comprising the steps of:
(1) providing (a) an adhesive system comprising a first part, A5 that is a low viscosity, self-leveling liquid that activates a cure mechanism on contact with the second part, B, with little or no heating; and a second part B5 that is capable of being B-staged, and (b) at least one substrate and one semiconductor die;
(2) dispensing part A onto the top side of the substrate;
(3) dispensing part B onto the part A adhesive on the top side of the substrate;
(4) contacting the back side of the semiconductor die with the top side of the substrate and spreading the part A and part B adhesives resulting in a total adhesive layer with a thickness of < 50 microns (preferably < 5 microns);
(5) allowing the part A and part B adhesives to react at room temperature, thereby partially curing;
(6) repeating steps 2 through 5 as many times as needed to compose the assembly; and
(7) subsequently, completing the curing of the part A and part B adhesives with heat and/or irradiation.
5. A semiconductor assembly comprising a plurality of semiconductor dies that are stacked one on top of the other and bonded to each other using a two-part adhesive system, in which one part of the adhesive system was applied to the top side of one die and the second part of the adhesive system was applied to the back side of another die, in which the two parts of the adhesive system are reactive with each other, and in which the two parts of the adhesive system were contacted together, thereby initiating a reaction and partial curing between the two parts of the adhesive system.
6. The semiconductor assembly according to claim 6 in which the stack of semiconductor dies is adhered to a substrate using the two-part adhesive system.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17080309P | 2009-04-20 | 2009-04-20 | |
| US61/170,803 | 2009-04-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2010123765A2 true WO2010123765A2 (en) | 2010-10-28 |
| WO2010123765A3 WO2010123765A3 (en) | 2011-01-20 |
Family
ID=43011695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2010/031344 WO2010123765A2 (en) | 2009-04-20 | 2010-04-16 | Thin bond line semiconductor packages |
Country Status (2)
| Country | Link |
|---|---|
| TW (1) | TW201100515A (en) |
| WO (1) | WO2010123765A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9549934B2 (en) | 2011-11-11 | 2017-01-24 | Almirall, S.A. | Cyclohexylamine derivatives having β2 adrenergic agonist and M3 muscarinic antagonist activities |
| US9582287B2 (en) | 2012-09-27 | 2017-02-28 | Intel Corporation | Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4581427A (en) * | 1982-05-26 | 1986-04-08 | Loctite Corporation | Two part self-indicating adhesive composition |
| US5973052A (en) * | 1996-12-16 | 1999-10-26 | Shell Oil Company | Die attach adhesive compositions |
| KR20030059805A (en) * | 2000-10-11 | 2003-07-10 | 스미토모 베이클리트 컴퍼니 리미티드 | Die-attaching paste and semiconductor device |
| KR20090032680A (en) * | 2007-09-28 | 2009-04-01 | 엘에스엠트론 주식회사 | Composition of semiconductor attaching paste |
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2010
- 2010-04-16 WO PCT/US2010/031344 patent/WO2010123765A2/en active Application Filing
- 2010-04-20 TW TW099112367A patent/TW201100515A/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4581427A (en) * | 1982-05-26 | 1986-04-08 | Loctite Corporation | Two part self-indicating adhesive composition |
| US5973052A (en) * | 1996-12-16 | 1999-10-26 | Shell Oil Company | Die attach adhesive compositions |
| KR20030059805A (en) * | 2000-10-11 | 2003-07-10 | 스미토모 베이클리트 컴퍼니 리미티드 | Die-attaching paste and semiconductor device |
| KR20090032680A (en) * | 2007-09-28 | 2009-04-01 | 엘에스엠트론 주식회사 | Composition of semiconductor attaching paste |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9549934B2 (en) | 2011-11-11 | 2017-01-24 | Almirall, S.A. | Cyclohexylamine derivatives having β2 adrenergic agonist and M3 muscarinic antagonist activities |
| US9582287B2 (en) | 2012-09-27 | 2017-02-28 | Intel Corporation | Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010123765A3 (en) | 2011-01-20 |
| TW201100515A (en) | 2011-01-01 |
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