TW201100515A - Thin bond line semiconductor packages - Google Patents

Thin bond line semiconductor packages Download PDF

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Publication number
TW201100515A
TW201100515A TW099112367A TW99112367A TW201100515A TW 201100515 A TW201100515 A TW 201100515A TW 099112367 A TW099112367 A TW 099112367A TW 99112367 A TW99112367 A TW 99112367A TW 201100515 A TW201100515 A TW 201100515A
Authority
TW
Taiwan
Prior art keywords
component
substrate
semiconductor
adhesive system
adhesive
Prior art date
Application number
TW099112367A
Other languages
Chinese (zh)
Inventor
James T Huneke
Original Assignee
Henkel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Henkel Corp filed Critical Henkel Corp
Publication of TW201100515A publication Critical patent/TW201100515A/en

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
    • C09J5/04—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving separate application of adhesive ingredients to the different surfaces to be joined
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01016—Sulfur [S]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

A semiconductor assembly comprises a plurality of semiconductor dies that are stacked one on top of the other and bonded to each other using a two-part adhesive system, in which one part of the adhesive system is applied to the top side of one die and the second part of the adhesive system is applied to the back side of another die, in which the two parts of the adhesive system are reactive with each other, and in which the two parts of the adhesive system when contacted together initiate a reaction and partial curing between the two parts of the adhesive system.

Description

201100515 六、發明說明： 【發明所屬之技術領域】 導體封裳及用力製造諸等封裝 本發明係關於細膠合線半 之方法。 【先前技術】 電學及電子設備之微型化及小型化導致對於較小半導體 封裝及較薄半導體晶片或晶粒產 今格„ |生而求。經由半導體晶粒 之堆豐’且尤其經由仍更薄半導體晶粒之堆疊，可獲得較 小封裝。然而’較薄晶粒較其等較厚相對物更易碎，且於 熱歷程或機械處理期間出現較大量裂痕與裂縫。此外，隨 著積體電路尺寸縮小且輸人/輸出密度增加，互連間會發 生串擾並導致電路故障。此可藉由使用低介電常數（「低 κ」）材料以使該等互連與其周圍環境絕緣而得以修正。低 κ夾層電介質(尤其彼等低於約2 5者卜般較習知介電材料 脆弱及易碎且此脆性於熱歷程或機械處理期間亦可導致裂 痕與裂縫。至目前為止，由於用於獲得較薄電學及電子設 備之技術受到限制，故在半導體工業中產生探求達成微型 化的其他途徑之需求。 其中-個此類方法係縮小晶粒堆疊佈局中介於晶粒間的 黏結劑膠合線，其容許在指定量垂直高度中堆疊增量之晶 粒。（目前’晶粒黏附黏結劑膠合線係約25微米。） 經堆疊之晶粒封裝已導致向薄膜黏結劑位移並遠離用於 晶粒黏附之液體晶粒黏附糊狀黏結劑。當組成多晶粒堆疊 時，薄膜黏結劑優於糊狀黏結劑之處係免去每一各自安置 147614.doc 201100515 晶粒之分別黏附固化步驟，及在晶粒黏附固化之前，於一 疊t將六個、A個或更多個晶粒固持在—起之充足機械 強度及黏性，及於某些情況下，容許在晶粒黏附固化之前 - 於整個堆疊上完成引線接合的充足強度。 “ 用於角錐及覆瓦狀或階梯狀堆疊之方法㈣薄膜黏結劑 之此項優點’藉由首先堆疊所有晶粒，然後在同一位置一 f性將全部晶粒引線接合而達成。由於當晶粒未於堆疊狀 態下獨立固化時，晶粒堆疊具有晶粒位移及失準之可能 性，故嘗試此種可分配液體或糊狀黏結劑之方法係不切實 際。 雖…;'有此等優點’但薄膜晶粒黏附黏結劑仍較液體糊狀 對等物昂貴’其等難得到小於〇 〇〇5微米之厚度，且若處 理不當，則其等可導致安置空隙。 期望有-種不具有黏附黏結劑薄膜之成本及空隙問題下 產生小於0.005微米之晶粒黏附黏結劑膠合線，但具有在 〇日日日粒黏附固化前允許㈣個堆#上進行多個晶粒堆疊及引 線接合之充分強度的方法。 【發明内容】 本發明係關於一種使用以氏量黏結劑以黏附半㈣及其 等基板之快速固化雙組份型黏著系統（t勝邮邊以-system)。當使用最低量黏結劑時’膠合線厚度會減低，此 然後促成小型化。半導體可係晶片或封裝；封裝包括至少 一晶片及-基板。基板可係另一晶片或任何剛性或可捷性 框或用於晶片或用於封裝之載體，諸如内插器或電路板。 147614.doc 201100515 於實施例中’该黏著系統包括第一組份（part)A，其係 在稍許加熱或不加熱下，與第二組份B接觸時激活固化機 制的低黏性、自動調平液體；及第二組份B，其可匕階 化。可B-階化意指黏結劑可經加熱至或加以輻射而部分固 化或以蒸發存在之任何溶劑，一般係達到經B階化之黏結 劑不具有黏性或具有低黏性之程度。 於其他實施例中，本發明係一種用於製備半導體及基板 總成之方法，且特定言之係由複數個半導體晶粒製備半導 體晶粒堆疊之方法。 於又一實施例中’該方法包括以下步驟：（丨）提供（a)包 含第一組份A之黏著系統，此組份a係在稍許加熱或不加 熱下’與第二組份B接觸時激活固化機制的低黏性、自動 調平液體；及第二組份B，其可B-階化，及（b)至少一半導 體及一基板；（2)將A組份分配於該基板之頂側面上；（3)將 B組份塗覆於該半導體之背側面上且將B組份B-階化；（句 使具有該B-階化B組份之該半導體背侧面與該基板頂侧面 上之A組份黏結劑接觸並將a組份黏結劑散佈成具有£5〇微 米（較佳$5微米）厚度之組合黏著層；（5)允許A組份與b組 份黏結劑於室溫下反應，從而部分固化；（6)重複步驟2至5 視需要之次數而構成總成；及（7)隨後，藉由加熱完成A組 份及B組份黏結劑之固化。 於另一實施例中’該方法包括（1)提供（a)包含第一組份 A(其係在稍許加熱或不加熱下，與第二組份B接觸時激活 固化機制的低黏性、自動調平液體）及第二組份B(其可B_ 147614.doc 201100515 階化）之黏著系統’及（b)至少一基板及一半導體；（2)將a 組份分配於該基板之頂側面上；（3)將B組份分配於該基板 頂側面上之A組份黏結劑上；（4)使該半導體背側面與該基 - 板之頂側面接觸並將該等A與B組份黏結劑散佈成具有<50 w 微米（較佳微米）厚度之層；（5)允許該等A與B組份黏結 劑在室溫下反應，從而部分固化；（6)重複步驟2-5視需要 之次數而構成總成；及（7)隨後，藉由加熱完成該等a組份 與B組份黏結劑之固化。 〇 【實施方式】 將液體A組份分配於基板欲與半導體背側面接觸之頂 部。A組份一般係以一圖案（諸如點、十字、χ、雪花等）之 形式分配。A組份具有在1至6範圍内之觸變指數，以便隨 後當受到因與其上分配有B組份的半導體接觸而施加之剪 切時’其將流動並於基板表面上調平任何表面形態。 於一實施例中，使用喷灑、印刷、旋轉塗覆或任何其他 已知塗覆方法將B組份分配於半導體晶圓之背側面上。塗 覆後，B組份係藉由對化學試劑適宜之方法加以B_階化。 分配係為於B-階化後達到約£5〇微米，較佳微米之厚 度。B-階化後，將晶圓切割成個別半導體晶粒。然後，以 足以導致A組份之毛細管流動及確保A組份完全覆蓋所需 基板部勿上之壓力，將每一半導體晶粒背側面上之Β·階化 Β組份與基板上之a組份黏結劑接觸。由於a組份在基板上 變平，故在使用標準晶粒附著條件-溫度（丨2〇_丨5〇。〇）、力 (0.5至4.0N)及時間（丨至丨⑽❶毫秒）下，將扁平半導體晶 147614.doc 201100515 粒置於其上時，可避免空隙形成。 於又一實施例中，將A組份分配於基板上並將b組份分 配於A組份上。於此實施例中，b組份未經B_階化。計算a 與B之分配體積以達成固化厚度$50微米（較佳g微米）。然 後’使半導體背側面與A組份與B組份黏結劑組合接觸。 在標準安置條件（120-150 °C，0.5至4.0 N，及1至1〇〇〇百萬 秒）下，有供A組份與B混合之充足壓力及時間。 兩實施例中，A組份與B組份在接觸後，開始固化及發 展足以承受額外處理諸如晶粒堆疊及隨後引線接合之強 度。在其他加熱步驟（諸如在引線接合或成形）期間，達成 完全固化。 黏結劑A組份與B組份之分配可藉由喷灑、霧化、到 塗、注射器分配、印刷、喷射印刷、旋轉塗覆、及層壓而 Λ現。於任一此等施加技術中，將基本上均勻之薄層施加 於半導體及/或基板。 於另一實施例中，本發明係一種半導體總成，其包括彼 此上下堆疊且使用雙組份型黏著系統彼此黏合之複數個半 導體晶粒，其中將該黏著系統之一組份施加於一晶粒之頂 側面且將該黏著系統之第二組份係施加於另一晶粒之背側 面，其中該黏著系統之該兩個組份可彼此反應，且其中該 黏，系統之該兩個組份接觸在一起，從而引發反應並於該 黏著系統之兩個組份間部分固化。 該種雙組份型黏結劑經設計以使在不與另一組份接觸時 兩、’且f刀自不固化，但一旦接觸就立即開始固化。該等雙組 147614.doc 201100515 份型系統之適宜化學試劑對係彼等彼此可反應者，例如 於固化之具有活化劑或引發劑之可固化化合物。實例係 烯酸酯與過氧化物；環氧樹脂與胺；雙馬來醯亞胺與過氧 化物或胺；氰基丙稀酸酯與水（或由有機或無機鹼製成之 底漆/加速劑）。 以得到固化後具有0.001至0.050 mm範圍内厚度的黏合 劑之厚度施加黏結劑A組份與B組份。於一實施例中，、妙 固化之黏合劑厚度在0.001至0.005201100515 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of thinning a half of a thin glue. [Prior Art] The miniaturization and miniaturization of electrical and electronic equipment has led to the creation of smaller semiconductor packages and thinner semiconductor wafers or crystals, which are produced by semiconductor wafers, and especially through still more Small semiconductor dies can be stacked to obtain a smaller package. However, 'thinner grains are more brittle than their thicker counterparts, and larger amounts of cracks and cracks occur during thermal history or mechanical processing. The circuit size is reduced and the input/output density is increased, crosstalk between interconnects can occur and circuit failure can occur. This can be achieved by using low dielectric constant ("low κ") materials to insulate the interconnects from their surroundings. Corrected. Low-k interlayer dielectrics (especially those less than about 25 are more fragile and brittle than conventional dielectric materials and can also cause cracks and cracks during thermal history or mechanical processing. Up to now, due to The technology to obtain thinner electrical and electronic devices is limited, so there is a need in the semiconductor industry to explore other ways to achieve miniaturization. One such method is to reduce the interfacial bond glue line in the die stack layout. It allows stacking of incremental grains in a specified amount of vertical height. (Currently, the 'die adhesion adhesive gluing line is about 25 microns.) The stacked die package has caused displacement to the film binder and away from the crystal. The granule-adhered liquid crystal grain adheres to the paste-like binder. When the multi-grain stack is formed, the film binder is superior to the paste-like binder, and the separate adhesion curing steps of each of the 147614.doc 201100515 grains are eliminated. And preserving the sufficient mechanical strength and viscosity of the six, A or more grains in a stack of t, and in some cases, permitting the grains in the stack. Adhesion before curing - sufficient strength to complete wire bonding on the entire stack. "Methods for pyramid and shingle or stepped stacking (4) This advantage of film bonding agents' by stacking all the grains first, then in the same position This is achieved by wire bonding all of the grains. Since the die stack has the possibility of grain displacement and misalignment when the grains are not cured independently in the stacked state, try to dispense such a liquid or paste bond. The method of the agent is impractical. Although...[there are such advantages], the film-grain adhesion adhesive is still more expensive than the liquid paste-like equivalent, which is difficult to obtain a thickness less than 〇〇〇5 μm, and if processed Improper, it may lead to the placement of voids. It is expected that there will be a grain adhesion adhesive bonding line of less than 0.005 micron without the cost of adhesion of the adhesive film and voids, but before the day of particle adhesion curing A method for allowing sufficient strength of a plurality of die stacking and wire bonding on (four) stacks. [Invention] The present invention relates to the use of a binder to adhere to a half (four) and The fast-curing two-component adhesive system of its substrate (t-mail edge-system). When the minimum amount of binder is used, the thickness of the glue line is reduced, which then contributes to miniaturization. The semiconductor can be wafer or package; At least one wafer and substrate are included. The substrate may be another wafer or any rigid or flexible frame or carrier for the wafer or for packaging, such as an interposer or circuit board. 147614.doc 201100515 In an embodiment The adhesive system includes a first component A which is a low viscosity, self-leveling liquid that activates the curing mechanism when in contact with the second component B with little or no heating; and a second component B B-stage can mean any solvent in which the binder can be partially cured or evaporated by heating or being irradiated. Generally, the B-staged binder does not have viscosity or has The degree of low viscosity. In other embodiments, the invention is a method for fabricating semiconductor and substrate assemblies, and in particular a method of fabricating a stack of semiconductor grains from a plurality of semiconductor grains. In yet another embodiment, the method comprises the steps of: (a) providing (a) an adhesive system comprising a first component A, the component a being in contact with the second component B with little or no heating a low viscosity, self-leveling liquid that activates the curing mechanism; and a second component B, which can be B-staged, and (b) at least one semiconductor and a substrate; (2) a component A is dispensed onto the substrate (3) applying component B to the back side of the semiconductor and B-stage the component B; (sentence the semiconductor back side having the B-staged component B with the The component A adhesive on the top side of the substrate is contacted and the component a binder is dispersed into a combination adhesive layer having a thickness of £5 μm (preferably $5 μm); (5) the component A and the b component are allowed to be bonded. Reacting at room temperature to partially cure; (6) repeating steps 2 to 5 to form the assembly as needed; and (7) subsequently curing the component A and component B by heating. In another embodiment, the method comprises (1) providing (a) comprising a first component A (which is in contact with the second component B with little or no heating) When the curing mechanism is activated, the low viscosity, self-leveling liquid) and the second component B (which can be B_147614.doc 201100515 graded) the adhesion system 'and (b) at least one substrate and a semiconductor; (2) a component is dispensed on the top side of the substrate; (3) component B is dispensed onto the component A on the top side of the substrate; (4) the back side of the semiconductor and the top side of the substrate are Contacting and dispersing the A and B component binders into a layer having a thickness of <50 w microns (preferably microns); (5) allowing the A and B component binders to react at room temperature, thereby partially Curing; (6) repeating steps 2-5 to form the assembly as needed; and (7) subsequently, curing of the component A and component B by heating is completed. 〇 [Embodiment] Component A is distributed on top of the substrate to be in contact with the back side of the semiconductor. Component A is typically distributed in the form of a pattern (such as dots, crosses, enamel, snowflakes, etc.) Component A has a touch in the range of 1 to 6. Varying index so that when subsequently subjected to shear applied by contact with a semiconductor to which component B is dispensed Any surface morphology will be flowed and leveled on the surface of the substrate. In one embodiment, component B is dispensed onto the back side of the semiconductor wafer using spray, printing, spin coating or any other known coating method. After the coating, the B component is B_staged by a method suitable for the chemical reagent. The distribution system is about 5 μm, preferably a micron thickness after the B-stage. After the B-stage, The wafer is diced into individual semiconductor dies, and then the back side of each semiconductor die is graded with a pressure sufficient to cause capillary flow of component A and to ensure that component A is completely covered by the required substrate portion. The ruthenium component is in contact with the component a binder on the substrate. Since the component a is flattened on the substrate, standard grain adhesion conditions - temperature (丨2〇_丨5〇) are used. 〇), force (0.5 to 4.0 N) and time (丨 to 丨 (10) ❶ milliseconds), when the flat semiconductor crystal 147614.doc 201100515 is placed thereon, void formation can be avoided. In yet another embodiment, component A is dispensed onto the substrate and component b is dispensed onto component A. In this embodiment, component b is not B_staged. The dispensed volume of a and B is calculated to achieve a cure thickness of $50 microns (preferably g microns). Then, the semiconductor back side is brought into contact with the component A and the component B binder. Under standard conditions (120-150 ° C, 0.5 to 4.0 N, and 1 to 1 million sec), there is sufficient pressure and time for mixing component A with B. In both embodiments, component A and component B begin to cure and develop after contact to withstand the strength of additional processing such as die stacking and subsequent wire bonding. Complete curing is achieved during other heating steps, such as during wire bonding or forming. The dispensing of component A and component B of the binder can be achieved by spraying, atomizing, coating, syringe dispensing, printing, jet printing, spin coating, and lamination. In any such application technique, a substantially uniform thin layer is applied to the semiconductor and/or substrate. In another embodiment, the present invention is a semiconductor assembly comprising a plurality of semiconductor dies stacked one on another and bonded to each other using a two-component type adhesion system, wherein one component of the adhesion system is applied to a crystal The top side of the granule and the second component of the adhesive system is applied to the back side of the other granule, wherein the two components of the adhesive system are reactive with each other, and wherein the viscous, the two groups of the system The parts are brought together to initiate a reaction and partially cure between the two components of the adhesive system. The two-component type adhesive is designed such that it does not cure when it is not in contact with another component, but begins to cure as soon as it is contacted. The suitable chemical reagent pairs of the two sets of 147614.doc 201100515 parting systems are those which are reactive with each other, for example, a curable compound having an activator or an initiator which is cured. Examples of olefin esters and peroxides; epoxy resins and amines; bismaleimide with peroxides or amines; cyanoacrylates with water (or primers made of organic or inorganic bases / Accelerator). The binder A component and the B component are applied to obtain a thickness of the adhesive having a thickness in the range of 0.001 to 0.050 mm after curing. In one embodiment, the thickness of the adhesive is 0.001 to 0.005.

mm範圍内。 半導體與基板之相對大小可相同或不同，且半導體晶片 與基板之對準可對齊或偏移’其條件為其允許黏合。半導 體晶片與基板之表面積可在1 mm2至625 mm2範圍内，且於 一實施例中，在30 mm2至80 mm2範圍内。 針對彼化學物質，黏著系統可基於下列化學物質中之一 或多者及用於該化學物質之固化引發劑。化學物質包括環 氧樹脂、環硫化物、（甲基）丙稀酸酯、氰基丙稀酸酯、馬 來醯亞胺、橋亞甲基四氫化鄰苯二甲醯亞胺、衣康醯亞胺 及異氰酸S旨。 適宜馬來醯亞胺、橋亞曱基四氫化鄰苯二甲醯亞胺或衣 康醯亞胺化合物分別包括結構I、II及III :Within the range of mm. The relative sizes of the semiconductor and the substrate may be the same or different, and the alignment of the semiconductor wafer with the substrate may be aligned or offset' with the condition that it allows adhesion. The surface area of the semiconductor wafer to the substrate can range from 1 mm2 to 625 mm2, and in one embodiment, from 30 mm2 to 80 mm2. For the chemical substance, the adhesion system can be based on one or more of the following chemicals and a curing initiator for the chemical. Chemicals include epoxy resins, episulfides, (meth) acrylates, cyanoacrylates, maleimine, benzylidene tetrahydro phthalimide, clothing Imine and isocyanate S. Suitable for maleimide, sulfhydryl tetrahydrophthalic imide or itaconide compounds include structures I, II and III, respectively:

147614.doc 201100515 其中m係1-15 ; p係0-15 ;各R2獨立為氫或較低碳烷基；J 係具有足夠長度及分支以使馬來醯亞胺、橋亞甲基四氫化 鄰苯二甲醢亞胺及/或衣康醯亞胺化合物為液體之單價或 多價有機基團。於一實施例中，J係視需要含有雜原子（諸 如氧、氮及硫）之有機矽氧烷或烴基。於一些實施例中，P 係零（包含於括弧内之有機基不存在）且m係1至6 ;於另一 實施例中，p係零且m係1至3。於彼等情況下，其中J基團 含有雜原子或含有雜原子之基團，雜原子或基團係選自 *-〇-、_S-、-NR-、-0-C(0)-、-0-C(0)-0-、-0-C(0)-NR-、-NR-C(O)-、-NR-C(0)-0-、-NR-C(0)-NR-、-S-C(O)-、 -s-c(o)-o-、-s-c(o)-nr-、-s(o)-、-s(o)2-、-o-s(o)2-、-o-s(o)2-o-、-o-s(o)2-nr-、-o-s(o)-、-o-s(o)-o-、 -0-S(0)-NR-、-O-NR-C(O)-、-0-NR-C(0)-0-、-0-NR-C(0)-NR- 、-NR-O-C(O)---NR-0-C(0)-0---NR-0-C(0)-NR---O-NR-C(S)- 、-0-NR-C(S)-0-、-0-NR-C(S)-NR-、-NR-O-C(S)-、 -NR-0-C(S)-0-、-NR-0-C(S)-NR-、-0-C(S)-、-0-C(S)-0-、-0-C(S)-NR-、-NR-C(S)-、-NR-C(S)-0-、-NR-C(S)-NR- 、-s-s(o)2-、-s-s(o)2-o-、-s-s(o)2-nr-、-nr-o-s(o)-、-NR-0-S(0)-0-、-NR-0-S(0)-NR-、-NR-0-S(0)2-、 -NR-0-S(0)2-0-、-NR-0-S(0)2-NR-、-O-NR-S(O)-、 -0-NR-S(0)-0-、-0-NR-S(0)-NR-、-0-NR-S(0)2-〇-、 -0-NR-S(0)2-NR-、-0-NR-S(0)2-、-0-P(0)R2-、-S-P(〇)R2-、-NR-P(0)R2-組成之群，其中各R係獨立為氫、烷基或經 取代之烧基。 147614.doc •10· 201100515 如此形成之半導體封裝包括藉由如本專利說明書所定義 之兩階段黏著系統而黏合於基板之半導體晶片。 〇147614.doc 201100515 wherein m is 1-15; p is 0-15; each R2 is independently hydrogen or lower alkyl; J is of sufficient length and branch to make maleimine, bridge methylene tetrahydrogenation The phthalimide and/or itaconimine compound is a liquid monovalent or polyvalent organic group. In one embodiment, J is optionally an organooxane or a hydrocarbyl group containing a hetero atom such as oxygen, nitrogen and sulfur. In some embodiments, P is zero (the organic group contained in parentheses is absent) and m is 1 to 6; in another embodiment, p is zero and m is 1 to 3. In such cases, wherein the J group contains a hetero atom or a group containing a hetero atom, the hetero atom or group is selected from the group consisting of *-〇-, _S-, -NR-,-0-C(0)-, -0-C(0)-0-,-0-C(0)-NR-, -NR-C(O)-, -NR-C(0)-0-, -NR-C(0)- NR-, -SC(O)-, -sc(o)-o-, -sc(o)-nr-, -s(o)-, -s(o)2-, -os(o)2- , -os(o)2-o-, -os(o)2-nr-, -os(o)-, -os(o)-o-, -0-S(0)-NR-, -O -NR-C(O)-, -0-NR-C(0)-0-, -0-NR-C(0)-NR-, -NR-OC(O)---NR-0-C (0)-0---NR-0-C(0)-NR---O-NR-C(S)-,-0-NR-C(S)-0-,-0-NR-C (S)-NR-, -NR-OC(S)-, -NR-0-C(S)-0-, -NR-0-C(S)-NR-,-0-C(S)- ,-0-C(S)-0-,-0-C(S)-NR-, -NR-C(S)-, -NR-C(S)-0-, -NR-C(S) -NR-, -ss(o)2-, -ss(o)2-o-, -ss(o)2-nr-, -nr-os(o)-, -NR-0-S(0) -0-, -NR-0-S(0)-NR-, -NR-0-S(0)2-, -NR-0-S(0)2-0-, -NR-0-S( 0) 2-NR-, -O-NR-S(O)-, -0-NR-S(0)-0-, -0-NR-S(0)-NR-,-0-NR-S (0)2-〇-, -0-NR-S(0)2-NR-,-0-NR-S(0)2-,-0-P(0)R2-, -SP(〇)R2 a group of -NR-P(0)R2-, wherein each R is independently hydrogen, alkyl or substituted alkyl. 147614.doc •10· 201100515 The semiconductor package thus formed includes a semiconductor wafer bonded to a substrate by a two-stage adhesive system as defined in this patent specification. 〇

147614.doc -11 -147614.doc -11 -

Claims (1)

201100515 七、申請專利範圍： 1 · 一種黏著系統，其包含： 第-組份A ’其係在務許或不加熱下，與第二組份轉 觸時激活固化機制之低黏性、自動調平液體；及 第二組份B，其可B-階化。 2. 如請求項1之黏著系統，其中 A組份黏結劑係選自由過氧化物、胺、水、及由有機 或無機鹼製成之底漆/加速劑組成之群；及 B組份黏結劑係選自由環氧樹脂、環硫化物、（甲基）丙 稀酸酯、氰基丙稀酸酯、馬來酿亞胺、橋亞甲基四氯化 鄰苯二甲醢亞胺、衣康醯亞胺、及異氰酸酯組成之群， 其條件為A組份、B組份可一起反應。 3. 一種用於製備半導體及基板的總成之方法，其包括以下 步驟： (1) 提供（a)—種黏著系統，其包含第一組份A，其係在 稍許或不加熱下，與第二組份B接觸時激活固化機制之 低黏性、自動調平液體；及第二組份B，其係可B_階 化’及（b)至少一半導體及一基板； (2) 將A組份分配於該基板之頂側面； (3) 將B組份塗覆於該半導體晶粒之背側面並使b組份 階化； (4) 使具有經B-階化之B組份的該晶粒背側面與該基板 頂側面之A組份黏結劑接觸並散佈A組份黏結劑，導致具 有竺50微米（較佳0微米）厚度之總黏結劑層； 147614.doc 201100515 (5) 允許A組份與B組份黏結劑於室溫下反應，從而部 分固化； (6) 重複步驟2至5視需要之次數，以構成總成；及 (7) 隨後’藉由加熱及/或施加輻射完成a組份及B組份 黏結劑之固化。 4. 一種用於製備半導體及基板之總成的方法，其包括以下 步驟： (1) 提供（a) —黏著系統，其包含第—組份a，該組份A 係在稍許或不加熱下與第二組份B接觸時激活固化機制 之低黏性、自動調平液體；及第二組份B，其係可B—階 化’及（b)至少一基板及一半導體晶粒； (2) 將A組份分配於該基板之頂側面；201100515 VII. Patent application scope: 1 · An adhesive system, which comprises: the first component A' is under the condition of no or no heating, and the low viscosity and automatic adjustment of the curing mechanism are activated when the second component is touched. a flat liquid; and a second component B, which can be B-staged. 2. The adhesive system of claim 1, wherein the component A adhesive is selected from the group consisting of peroxides, amines, water, and primers/accelerators made of organic or inorganic bases; and component B bonding The agent is selected from the group consisting of epoxy resins, episulfides, (meth) acrylates, cyanoacrylates, maleimine, benzylidene tetramethylene phthalate, and clothing. A group consisting of quinone and isocyanate, wherein the components A and B can be reacted together. 3. A method for preparing an assembly of a semiconductor and a substrate, comprising the steps of: (1) providing (a) an adhesive system comprising a first component A, which is attached with little or no heating, The second component B contacts a low viscosity, self-leveling liquid that activates the curing mechanism; and a second component B, which can be B_staged and (b) at least one semiconductor and a substrate; (2) The component A is distributed on the top side of the substrate; (3) the component B is coated on the back side of the semiconductor crystal grain and the b component is graded; (4) the B component having the B-stage is made The back side of the die is in contact with the component A binder on the top side of the substrate and interspersed with the component A binder, resulting in a total binder layer having a thickness of 50 microns (preferably 0 microns); 147614.doc 201100515 (5 Allowing component A and component B to react at room temperature to partially cure; (6) repeat steps 2 through 5 as needed to form the assembly; and (7) then 'by heating and / Or radiation is applied to complete the curing of component a and component B binder. 4. A method for preparing an assembly of a semiconductor and a substrate, comprising the steps of: (1) providing (a) an adhesion system comprising a component a, the component A being slightly or not heated a low viscosity, self-leveling liquid that activates a curing mechanism when in contact with the second component B; and a second component B that is B-staged and (b) at least one substrate and a semiconductor die; 2) dispensing component A on the top side of the substrate; (3 )將B組份分配於該基板頂侧面上之a組份黏結劑 (4) 使該半導體晶粒之背側面與該基板之頂側面接觸並 散佈A組份與B組份黏結劑，導致具有$5〇微米（較佳y微 米）厚度之總黏結劑層； (5) 允許A組份與B組份黏結劑於室溫下反應，從而部 分固化； (6) 重複步驟2至5視需要之次數’以構成總成；及 (7) 隨後，藉由加熱及/或輻射完成A組份及B組份黏結 劑之固化。 5. —種半導體總成，其包含彼此上下堆疊且使用雙組份型 黏著系統彼此黏合之複數個半導體晶粒，其中該黏著系 147614.doc 201100515 統之一組份係施加於一晶粒之 _ <頂側面且該黏著系統之第 一組份係施加於另一晶粒之昔相丨丨品 <牙側面’其中該黏著系統之 該兩組份彼此可反應，且其中該黏著系統之該兩組份可 一起接觸，從而引發反應並於該黏著系統之該兩組份之 間部分固化。 6·如請求項5之半導體總成，其中半導體晶粒之該堆疊係 使用該雙組份型黏著系統黏附於一基板。 〇(3) the component A is distributed on the top side of the substrate to the component a (4), the back side of the semiconductor die is brought into contact with the top side of the substrate, and the component A and the component B are dispersed. Resulting in a total binder layer having a thickness of $5 〇 micron (preferably y micron); (5) allowing component A and component B to react at room temperature to partially cure; (6) repeat steps 2 to 5 The number of times required 'to constitute the assembly; and (7) Subsequently, the curing of the A component and the B component adhesive is completed by heating and/or irradiation. 5. A semiconductor assembly comprising a plurality of semiconductor dies stacked one on another and bonded to each other using a two-component adhesive system, wherein one component of the adhesive system 147614.doc 201100515 is applied to a die _ < top side and the first component of the adhesive system is applied to the other side of the granules < flank 'where the two components of the adhesive system are reactive with each other, and wherein the adhesive system The two components can be contacted together to initiate a reaction and partially cure between the two components of the adhesive system. 6. The semiconductor assembly of claim 5, wherein the stack of semiconductor dies is adhered to a substrate using the two-component adhesive system. 〇 147614.doc 201100515 四、指定代表圖： (一) 本案指定代表圖為：（無） (二) 本代表圖之元件符號簡單說明： 五、本案若有化學式時，請揭示最能顯示發明特徵的化學式： (無）147614.doc 201100515 IV. Designation of the representative representative: (1) The representative representative of the case is: (none) (2) The symbol of the symbol of the representative figure is simple: 5. If there is a chemical formula in this case, please reveal the best indication of the characteristics of the invention. Chemical formula: (none) 147614.doc147614.doc
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