WO2010103987A1 - データ伝送システムおよびそのデータ読出し方法 - Google Patents
データ伝送システムおよびそのデータ読出し方法 Download PDFInfo
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- WO2010103987A1 WO2010103987A1 PCT/JP2010/053515 JP2010053515W WO2010103987A1 WO 2010103987 A1 WO2010103987 A1 WO 2010103987A1 JP 2010053515 W JP2010053515 W JP 2010053515W WO 2010103987 A1 WO2010103987 A1 WO 2010103987A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
Definitions
- the present invention relates to a data transmission system and a data reading method thereof, and more particularly to a data transmission system in which a plurality of devices are connected via a serial bus to a switch that performs priority control according to the type of packet, and a data reading method thereof.
- Serial RapidIO (registered trademark) is a standard for connecting various devices in such a board to a switch via a serial line and enabling high-speed communication of up to 10 Gbps between the devices (for example, RapidIO TM).
- Wireless base station devices that are compatible with the Serial RapidIO (registered trademark) standard are being put into practical use.
- a packet for performing communication is defined.
- a packet whose type is NREAD is a read packet that requests reading of data from the counterpart device.
- a packet whose type is NWRITE is a write packet for writing data to the counterpart device.
- RapidIOTM Interconnect Specification Part1 Input / Output Logical Specification Rev1.3, June 2005, Internet (URL: http://www.rapidio.org/zdata/specs/IO_logical.pdf)
- the write packet of Serial RapidIO (registered trademark) is set to have a higher priority than the read packet for the same transfer source and transfer destination devices.
- FIG. 9 is a diagram for explaining a conventional packet transmission example.
- Write packets NWRITE (4) are sequentially output from device A, input to multiport switch 1, and stored in a buffer in multiport switch 1.
- the multiport switch 1 extracts the write packets NWRITE (3) and NWRITE (4) from the buffer before the read packet NREAD (1) and outputs them to the device B.
- the read packet NREAD (1) is output from the buffer only when there is no write packet in which the transfer source device is the device A and the transfer destination device is the device B in the buffer of the multiport switch 1.
- the present invention provides a data transmission system and a method for reading the data transmission system that can deliver a read request to a counterpart device without delay even when the read packet transmission priority is lower than that of a write packet. That is.
- a data transmission system includes a multiport switch, and a first device and a second device connected to a port of the multiport switch via one or more serial buses.
- the multiport switch includes a buffer and a priority control unit that preferentially outputs a write packet when there are a write packet and a read packet having the same transfer destination and transfer source in the buffer,
- the first device and the second device include a memory, an output unit that outputs the generated packet to the multiport switch, a reception unit that receives the packet from the multiport switch, and a write address included in the received write packet.
- the first device includes a predetermined address of the memory of the second device as a write address, and a read request including the read address of the memory of the second device in the payload
- a read request unit for generating a write packet is provided, and the second device detects that a read request has been received when data is written to a predetermined address of the memory, and is written to the predetermined address
- a read response unit that reads data from a read address of the memory and generates a read response write packet including the read data in a payload is provided.
- the read request unit in the first device, the read request unit generates a read request write packet including a read size in the payload, and in the second device, the read response unit writes to a predetermined address in the memory. Data is read from the memory for the read size that has been read, and a read response write packet including the read data for the read size in the payload is generated.
- the read request unit generates a read request write packet including, in the payload, an address of the memory of the first device to which the read data is written, and in the second device
- the read response unit generates a read response write packet including the address of the memory of the first device written at a predetermined address of the memory as a write address.
- the read response unit generates an interrupt packet notifying that the response to the detected read request is completed after generating the read response write packet.
- the read request unit when the read request unit receives the interrupt packet, the read request unit detects that the response to the read request is completed.
- an interrupt line is further connected between the first device and the second device, and in the second device, the read response unit transmits the read response write packet through the interrupt line. And that the response to the detected read request is completed.
- the read request unit detects the completion of the response to the read request when receiving a notification that the response to the detected read request is completed through the interrupt wiring. .
- a data transmission method includes a multiport switch, and a first device and a second device connected to a port of the multiport switch via one or more serial buses.
- a data read method in a system wherein a multiport switch includes a buffer and a priority control unit that preferentially outputs a write packet when there are a write packet and a read packet having the same transfer destination and transfer source in the buffer
- the read request can be delivered to the counterpart device without delay.
- FIG. 1 is a diagram showing a data transmission system according to an embodiment of the present invention.
- a plurality of devices A to D and a multiport switch 1 are mounted on a substrate 90.
- Device A is connected to port A of multiport switch 1 through serial bus 51.
- Device B is connected to port B of multiport switch 1 through serial bus 52.
- Device C is connected to port C of multiport switch 1 through serial bus 53.
- the device D is connected to the port D of the multiport switch 1 through the serial bus 54.
- FIG. 2 is a diagram for explaining an example of packet transmission according to the embodiment of this invention.
- the write packet NWRITE (4) is sequentially output from the device A, input to the multiport switch 1, and stored in a buffer in the multiport switch 1.
- the read request write packet NWRITE (R) has a write packet configuration, but is a packet that requests the transfer destination device B to read data. Details of this packet will be described later.
- the multiport switch 1 takes out the read request write packet NWRITE (R) from the buffer next to the write packet NWRITE (2) and outputs it to the device B.
- FIG. 3 is a diagram illustrating a configuration of a request source device that issues a request, a multiport switch, and a request destination device that receives the request.
- the request source device is, for example, device A in FIG. 1
- the request destination device is, for example, device B in FIG.
- the request source device 10 and the multiport switch 1 are connected by a serial bus 41.
- the multiport switch 1 and the requested device 20 are connected by a serial bus 42.
- the request source device 10 includes a memory 11, a write request unit 12, a normal read request unit 14, a special read request unit 13, a write processing unit 15, a packet output unit 16, a packet reception unit 17, A packet interpretation unit 18.
- the packet output unit 16 outputs the generated packet to the multiport switch 1 via the serial bus.
- the packet receiver 17 receives a packet output from the multiport switch 1 via the serial bus.
- the packet interpretation unit 18 refers to the transaction type of the received packet and interprets whether the received packet is a write packet (NWRITE), a response packet (RESPONSE), or an interrupt packet (DOORBELL).
- NWRITE write packet
- RESPONSE response packet
- DOORBELL interrupt packet
- the packet interpretation unit 18 outputs the received packet to the write processing unit 15.
- the packet interpretation unit 18 outputs the received packet to the normal read request unit 14.
- the packet interpretation unit 18 outputs the received packet to the special read request unit 13.
- write data included in the payload of the received write packet is written.
- the write request unit 12 specifies the address of the memory 27 of the request destination device 20 in the write address portion, specifies the size of the write data in the write size portion, and generates a write packet including the write data in the payload.
- the normal read request unit 14 designates the address of the memory 27 of the request destination device 20 in the read address portion, and generates a read packet in which the size of the read data is designated in the read size portion.
- the normal read request unit 14 extracts the read data from the payload of the response packet transmitted from the request destination device 20 in response to the read packet.
- the special read request unit 13 designates a predetermined address (fixed address) of the memory 27 of the request destination device 20 in the write address portion, and includes the address of the memory 27 of the request destination device 20 in the payload as a read address.
- the read request write packet is generated so as to include the size of the read data read from the read address as the read size and the address of the memory 11 of the request source device 10 as the read data write address. Further, the special read request unit 13 detects that the response of the special read request is completed when an interrupt packet is received from the request destination device 20.
- the write processing unit 15 writes the data included in the payload of the received write packet to the address of the memory 11 specified by the write address portion of the received write packet.
- the multiport switch 1 includes a communication unit 4, a buffer 2, and a priority control unit 3.
- the communication unit 4 receives the packet output from the device 10 or 20 and outputs it to the buffer 2. Further, the communication unit 4 transmits the packet stored in the buffer 2 to the device 10 or 20.
- Buffer 2 stores packets output from one device, and outputs when the other device is ready to receive.
- the priority control unit 3 preferentially outputs a write packet when there are a write packet and a read packet having the same transfer destination and transfer source in the buffer 2.
- the priority control unit 3 identifies whether it is a write packet (NWRITE) or a read packet (NREAD) according to the transaction type included in the packet.
- the request destination device 20 includes a memory 27, a packet receiving unit 21, a packet interpretation unit 22, a packet output unit 23, a write processing unit 24, a read processing unit 25, and a special read request response unit 26. .
- the packet output unit 23 outputs the generated packet to the multiport switch 1 via the serial bus.
- the packet receiving unit 21 receives a packet output from the multiport switch 1 via the serial bus.
- the packet interpretation unit 22 refers to the transaction type of the received packet and interprets whether the received packet is a write packet (NWRITE) or a read packet (NREAD). When the received packet is a write packet, the packet interpretation unit 22 outputs the received packet to the write processing unit 24. When the received packet is a read packet, the packet interpretation unit 22 outputs the received packet to the read processing unit 25.
- NWRITE write packet
- NREAD read packet
- the write data included in the payload of the write packet output from the request source device 10 is written in the memory 27.
- the read data read from the memory 27 is embedded in the payload of the response packet or read response write packet output to the request source device 10.
- the write processing unit 24 writes the write data included in the payload to the address of the memory 27 specified by the write address portion of the received write packet by the size specified by the write size portion.
- the read processing unit 25 reads data from the memory 27 by the size specified in the read size portion starting from the address of the memory 27 specified in the read address portion of the received packet.
- the read processing unit 25 generates a response packet including the read data read in the payload.
- the special read request response unit 26 detects that a read request has been received when data is written to a predetermined address of the memory 27, and the read address of the memory 27 written to the predetermined address of the memory 27. (A), read size (b), and write address (c) of memory 11 are read.
- the special read request response unit 26 reads data from the read address (a) of the memory 27 by the read size (b).
- the special read request response unit 26 generates a read response write packet including the read address (c) of the memory 11 read in the write address portion and the read data read out in the payload.
- the special read request response unit 26 further generates an interrupt packet after generating the read response write packet.
- FIG. 4 is a diagram illustrating a packet configuration according to the embodiment of this invention. These packets conform to the Serial RapidIO (registered trademark) standard.
- FIG. 4A shows the structure of the read packet. This read packet is transmitted when a normal read request is issued.
- the read packet includes a request source device ID, a request destination device ID, a transaction type, a transaction ID, R_ADD, and R_SIZE.
- the request source device ID describes an ID for identifying the device that has issued the normal read request.
- an ID for identifying a device that receives a normal read request is described.
- NREAD is described in the transaction type.
- the transaction ID describes an ID for identifying this packet.
- R_ADD read address portion
- R_SIZE read size portion
- FIG. 4B is a diagram showing the configuration of a normal write packet. This normal write packet is transmitted when a write request is issued.
- the normal write packet includes a request source device ID, a request destination device ID, a transaction type, a transaction ID, W_ADD, W_SIZE, and write data.
- the request source device ID describes an ID for identifying the device that has issued the write request.
- an ID for identifying a device that receives a write request is described.
- NWRITE is described in the transaction type.
- the transaction ID describes an ID for identifying this packet.
- W_ADD write address portion
- W_SIZE write size portion
- the payload includes write data.
- FIG. 4C shows the structure of the response packet. This response packet is transmitted when a response (response) is made to a normal read request.
- the response packet includes a request source device ID, a request destination device ID, a transaction type, a status, and read data.
- the request source device ID describes an ID for identifying a device that has issued a response, that is, a device that has received a normal read request.
- the request destination device ID describes an ID for identifying a device that receives a response, that is, a device that has issued a normal read request.
- RESPONSE is described in the transaction type.
- the transaction ID describes an ID for identifying this packet.
- the status describes whether or not the process according to the normal read request, that is, the read process has been executed normally.
- the payload includes read data obtained by the reading process.
- FIG. 4D shows the structure of the read request write packet. This read request write packet is transmitted when a special read request is issued.
- the read request write packet includes a request source device ID, a request destination device ID, a transaction type, a transaction ID, W_ADD, and W_SIZE.
- the request source device ID an ID for identifying the device that has issued the special read request is described.
- the request destination device ID describes an ID for identifying a device that receives a special read request.
- NWRITE is described in the transaction type.
- the transaction ID describes an ID for identifying this packet.
- W_ADD write address portion
- W_ADD is a memory address of a request destination device into which payload data is written.
- W_ADD is a predetermined value “10000”.
- W_SIZE write size portion
- W_SIZE write size portion
- the read request write packet includes R_ADD, R_SIZE, and RT_ADD in the payload.
- R_ADD a memory address of a request destination device which is a data read target is described.
- R_SIZE describes how many bytes of data are to be read starting from the memory address specified by R_ADD.
- RT_ADD describes the memory address of the request source device to which the read data is written.
- FIG. 4 (e) is a diagram showing the configuration of a read response write packet. This read response write packet is transmitted when a response is made to a special read request.
- the read response write packet includes a request source device ID, a request destination device ID, a transaction type, a transaction ID, W_ADD, W_SIZE, and read data.
- the request source device ID describes an ID for identifying a device that has issued a response to the special read request.
- the request destination device ID describes an ID for identifying a device that receives a response to the special read request.
- NWRITE is described in the transaction type.
- the transaction ID describes an ID for identifying this packet.
- W_ADD write address portion
- W_ADD write address portion
- W_SIZE write size portion
- W_ADD write size portion
- R_SIZE included in the read request write packet is described.
- the payload includes read data obtained by the reading process.
- FIG. 4 (f) is a diagram showing the configuration of the interrupt packet. This interrupt packet is transmitted when notifying that the response to the special read request has been completed.
- the interrupt packet includes a request source device ID, a request destination device ID, a transaction type, and a transaction ID.
- the request source device ID describes an ID for identifying the device that issued the interrupt notification.
- the request destination device ID describes an ID for identifying a device that receives an interrupt notification.
- the transaction type describes DOORBELL.
- the transaction ID describes an ID for identifying this packet.
- FIG. 5 is a flowchart showing the write operation procedure.
- the write request unit 12 of the request source device 10 generates a normal write packet as shown in FIG. 4B (step S101).
- the packet output unit 16 of the request source device 10 outputs the normal write packet to the multiport switch 1 (step S102).
- the communication unit 4 of the multiport switch 1 receives the normal write packet and stores the write packet in the buffer 2.
- the priority control unit 3 takes out the write packet and outputs it to the communication unit 4 when there is no longer any packet accumulated in the buffer 2.
- the priority control unit 3 extracts the write packet before the read packet, 4 is output.
- the communication unit 4 outputs the write packet to the request destination device 20 (step S103).
- the packet receiver 21 of the request destination device 20 receives a packet from the multiport switch 1 (step S104).
- the packet interpretation unit 22 of the request destination device 20 interprets the received packet as a write packet because the transaction type of the received packet is NWRITE (step S105).
- the write processing unit 24 of the request destination device 20 writes the write data included in the payload to the memory 27 by the size specified by W_SIZE, starting from the memory address specified by W_ADD of the received write packet ( Step S106).
- FIG. 6 is a flowchart showing a normal read operation procedure.
- the normal read request unit 14 of the request source device 10 generates a read packet as shown in FIG. 4A (step S201).
- the packet output unit 16 of the request source device 10 outputs the read packet to the multiport switch 1 (step S202).
- the communication unit 4 of the multiport switch 1 receives the read packet and stores the read packet in the buffer 2.
- the priority control unit 3 extracts the stored read packet when there is no write packet having the same request source and request destination device in the buffer 2 and there is no preceding read packet, and the communication unit Output to 4.
- the communication unit 4 outputs the read packet to the request destination device 20 (step S203).
- the packet receiver 21 of the request destination device 20 receives a packet from the multiport switch 1 (step S204).
- the packet interpretation unit 22 of the request destination device 20 interprets the received packet as a read packet because the transaction type of the received packet is NREAD (step S205).
- the read processing unit 25 of the requested device 20 reads data from the memory 27 by the size specified by R_SIZE, starting from the memory address specified by R_ADD of the received packet (step S206).
- the read processing unit 25 of the request destination device 20 generates a response packet as shown in FIG. 4C (step S207).
- the packet output unit 23 of the request destination device 20 outputs a response packet to the multiport switch 1 (step S208).
- the communication unit 4 of the multiport switch 1 receives the response packet and stores the response packet in the buffer 2.
- the priority control unit 3 takes out the stored response packet and outputs it to the communication unit 4 when there is no preceding packet in the buffer 2.
- the communication unit 4 outputs a response packet to the request destination device 20 (step S209).
- the packet receiver 7 of the request source device 10 receives a packet from the multiport switch 1 (step S210).
- the packet interpretation unit 18 of the request source device 10 interprets the received packet as a response packet because the transaction type of the received packet is RESPONSE (step S211).
- the normal read request unit 14 of the request source device 10 extracts the read data from the payload of the received response packet (step S212).
- FIG. 7 is a flowchart showing the operation procedure of the special read.
- the special read request unit 13 of the request source device 10 generates a read request write packet as shown in FIG. 4D (step S301).
- the packet output unit 16 of the request source device 10 outputs the read request write packet to the multiport switch 1 (step S302).
- the communication unit 4 of the multi-port switch 1 receives the read request write packet and stores the read request write packet in the buffer 2.
- the priority control unit 3 takes out the read request write packet and outputs it to the communication unit 4 when there is no longer any packet accumulated in the buffer 2. However, even when the request source device and the request destination device are the same in the buffer 2 and there is a preceding read bucket, the priority control unit 3 takes out the read request write packet before the read packet.
- the communication unit 4 outputs the read request write packet to the request destination device 20 (step S303).
- the packet receiver 21 of the request destination device 20 receives the packet from the multiport switch 1 (step S304).
- the packet interpretation unit 22 of the request destination device 20 interprets it as a write packet because the transaction type of the received packet is NWRITE (step S305).
- the write processing unit 24 of the requested device 20 writes the data included in the payload to the memory 27 by the size specified by W_SIZE, starting from the memory address specified by W_ADD of the received write packet (step S40). S306).
- the special read request response unit 26 of the request destination device 20 detects that a special read request has been received since the data is stored at the address “10000” in the memory 27 (step S307).
- the special read request response unit 26 of the request destination device 20 reads R_ADD, R_SIZE, and RT_ADD, which are data written to the address “10000”.
- the special read request response unit 26 reads data from the memory 27 by the size specified by R_SIZE, starting from the memory address specified by the read R_ADD (step S308).
- the special read request response unit 26 of the request destination device 20 generates a read response write packet as shown in FIG.
- the special read request response unit 26 uses the RT_ADD and R_SIZE data read in step S308 as the W_ADD and W_SIZE data of the read response write packet, and uses the read data read in step S308 as payload data (step S309). ).
- the packet output unit 23 of the request destination device 20 outputs the read response write packet to the multiport switch 1 (step S310).
- the communication unit 4 of the multi-port switch 1 receives the read response write packet and stores the read response write packet in the buffer 2.
- the priority control unit 3 takes out the read response write packet and outputs it to the communication unit 4 when there is no longer any packet accumulated in the buffer 2. However, even if the request source device and the request destination device are the same in the buffer 2 and there is a preceding read bucket, the priority control unit 3 takes out the read response write packet before the read packet.
- the communication unit 4 outputs the read response write packet to the request destination device 20 (step S311).
- the packet receiver 7 of the request source device 10 receives a packet from the multiport switch 1 (step S312).
- the packet interpretation unit 18 of the request source device 10 interprets the received packet as a write packet because the transaction type of the received packet is NWRITE (step S313).
- the write processing unit 15 of the request source device 10 writes the write data included in the payload by the size specified by W_SIZE from the memory address specified by W_ADD of the received write packet to the memory 27 ( Step S314).
- the special read request response unit 26 of the request destination device 20 generates an interrupt packet as shown in FIG. 4F (step S315).
- the packet output unit 23 of the request destination device 20 outputs the interrupt packet to the multiport switch 1 (step S316).
- the communication unit 4 of the multiport switch 1 receives the interrupt packet and stores the interrupt packet in the buffer 2.
- the priority control unit 3 takes out the stored interrupt packet and outputs it to the communication unit 4 when there is no preceding packet in the buffer 2 (step S317).
- the packet receiver 7 of the request source device 10 receives a packet from the multiport switch 1 (step S318).
- the packet interpretation unit 18 of the request source device 10 interprets it as an interrupt packet because the transaction type of the received packet is DOORBELL, and outputs this interrupt packet to the special read request unit 13. (Step 319).
- step S320 when the special read request unit 13 of the request source device 10 receives the interrupt packet, it detects that the response of the special read request has been completed.
- FIG. 8 is a diagram showing a configuration of a modified example.
- FIG. 8 the modification of FIG. 8 differs from the configuration of the embodiment of FIG. 3 in the following points.
- the request source device 10 and the request destination device 20 are directly connected by the interrupt wiring 61.
- the special read request response unit 126 After generating the read response write packet, the special read request response unit 126 notifies the special read request unit 113 that the response process for the special read request is completed through the interrupt wiring 61.
- the device is described as being connected to the port of the multiport switch via one serial bus.
- the present invention is not limited to this.
- a device may be connected to a port of a multiport switch via a plurality of serial buses.
- 1 multi-port switch 2 buffer, 3 priority control unit, 4 communication unit, 10 request source device, 11, 27 memory, 13,113 special read request unit, 14 normal read request unit, 15, 24 write processing unit, 16 , 23 packet output unit, 17, 21 packet receiving unit, 18, 22 packet interpretation unit, 25 read processing unit, 26, 126 special read request response unit, 61 interrupt wiring, 41, 42, 51, 52, 53, 54 serial bus, 90 board.
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Abstract
Description
図9を参照して、デバイスAを転送元デバイス、デバイスBを転送先デバイスとしたライトパケットNWRITE(1)、ライトパケットNWRITE(2)、リードパケットNREAD(1)、ライトパケットNWRITE(3)、ライトパケットNWRITE(4)が順次デバイスAから出力されて、マルチポートスイッチ1へ入力されて、マルチポートスイッチ1内のバッファ内に蓄積される。
(データ伝送システム構成)
図1は、本発明の実施形態のデータ伝送システムを表わす図である。
図2は、本発明の実施形態のパケットの伝送例を説明するための図である。
図3は、要求を発する要求元デバイスと、マルチポートスイッチと、要求を受ける要求先デバイスの構成を表わす図である。要求元デバイスは、たとえば図1のデバイスAとし、要求先デバイスは、たとえば図1のデバイスBとする。
通信部4は、デバイス10または20から出力されたパケットを受信し、バッファ2に出力する。また、通信部4は、バッファ2に蓄積されているパケットをデバイス10または20へ送信する。
図4は、本発明の実施形態のパケットの構成を表わす図である。これらのパケットは、Serial RapidIO(登録商標)規格に準拠する。
図5は、ライトの動作手順を表わすフローチャートである。
図6は、通常リードの動作手順を表わすフローチャートである。
図7は、特殊リードの動作手順を表わすフローチャートである。
(1) 割込み
図8は、変形例の構成を表わす図である。
本発明の実施形態では、デバイス10が読出要求、特殊読出および書込要求を発し、デバイス20がこれらの要求を受けるものとして説明したが、これに限定するものではない。デバイスAが、ある時点でこれらの要求をデバイスBに発するとともに、別の時点でデバイスBまたはデバイスCからこれらの要求を受けるものとしてもよい。この場合には、デバイスAには、本発明の実施形態で説明した要求元デバイスの構成要素と、要求先デバイスの構成要素の両方を備えることとなる。
本発明の実施形態では、デバイスがマルチポートスイッチのポートに1つのシリアルバスを介して接続されるものとして説明したが、これに限定するものではない。たとえば、デバイスがマルチポートスイッチのポートに複数本のシリアルバスを介して接続されるものとしてもよい。
Claims (8)
- マルチポートスイッチ(1)と、
前記マルチポートスイッチ(1)のポートに1または複数のシリアルバス(41,42)を介して接続される第1のデバイス(10)および第2のデバイス(20)とを備えたデータ伝送システムであって、
前記マルチポートスイッチ(1)は、
バッファ(2)と、
前記バッファ(2)内に転送先と転送元が同一のライトパケットとリードパケットがある場合に、ライトパケットを優先して出力する優先制御部(3)とを備え、
前記第1のデバイス(10)および前記第2のデバイス(20)は、
メモリ(11,27)と、
生成したパケットを前記マルチポートスイッチへ出力する出力部(16,23)と、
前記マルチポートスイッチからパケットを受信する受信部(17,21)と、
受信したライトパケットに含まれる書込アドレスで指定されるメモリのアドレスに、前記受信したライトパケットのペイロードに含まれるデータを書込む書込処理部(15,24)とを備え、
前記第1のデバイス(10)は、
前記第2のデバイス(20)のメモリ(27)の所定のアドレスを書込アドレスとして含み、かつペイロードに前記第2のデバイス(20)のメモリ(27)の読出アドレスを含む読出要求用ライトパケットを生成する読出要求部(13,113)を備え、
前記第2のデバイス(20)は、
前記メモリ(27)の所定のアドレスにデータが書込まれた場合に、読出要求を受けたことを検知し、前記所定のアドレスに書込まれたメモリ(27)の読出アドレスからデータを読出し、前記読出したデータをペイロードに含む読出応答用ライトパケットを生成する読出応答部(26,126)を備えたデータ伝送システム。 - 前記第1のデバイス(10)において、
前記読出要求部(13,113)は、前記ペイロードに、さらに読出サイズを含む前記読出要求用ライトパケットを生成し、
前記第2のデバイス(20)において、
前記読出応答部(26,126)は、前記メモリ(27)の所定のアドレスに書込まれた読出サイズだけ、前記メモリ(27)からデータを読出し、前記読出サイズ分の読出したデータをぺイロードに含む前記読出応答用ライトパケットを生成する、請求の範囲1記載のデータ伝送システム。 - 前記第1のデバイス(10)において、
前記読出要求部(13,113)は、前記ペイロードに、さらに読出したデータの書込先の前記第1のデバイス(10)のメモリ(11)のアドレスを含む前記読出要求用ライトパケットを生成し、
前記第2のデバイス(20)において、
前記読出応答部(26,126)は、前記メモリ(27)の所定のアドレスに書込まれた前記第1のデバイス(10)のメモリ(11)のアドレスを書込アドレスとして含む前記読出応答用ライトパケットを生成する、請求の範囲1記載のデータ伝送システム。 - 前記第2のデバイス(20)において、
前記読出応答部(26)は、前記読出応答用ライトパケットの生成後に、前記検知した読出要求への応答が終了したことを通知する割込パケットを生成する、請求の範囲1記載のデータ伝送システム。 - 前記第1のデバイス(10)において、
前記読出要求部(13)は、前記割込パケットを受信した場合に、前記読出要求に対する応答が終了したことを検知する、請求の範囲4記載のデータ伝送システム。 - 前記第1のデバイス(10)と前記第2のデバイス(20)の間に、さらに割込用配線(61)が接続され、
前記第2のデバイス(20)において、
前記読出応答部(126)は、前記読出応答用ライトパケットの生成後に、前記割込用配線(61)を通じて、前記検知した読出要求への応答が終了したことを通知する、請求の範囲1記載のデータ伝送システム。 - 前記第1のデバイス(10)において、
前記読出要求部(113)は、前記前記割込用配線(61)を通じて、前記検知した読出要求への応答が終了したことの通知を受信した場合に、前記読出要求に対する応答が終了したことを検知する、請求の範囲6記載のデータ伝送システム。 - マルチポートスイッチ(1)と、前記マルチポートスイッチ(1)のポートに1または複数のシリアルバス(41,42)を介して接続される第1のデバイス(10)および第2のデバイス(20)とを備えたデータ伝送システムにおけるデータ読出し方法であって、
前記マルチポートスイッチ(1)は、バッファ(2)と、前記バッファ(2)内に転送先と転送元が同一のライトパケットとリードパケットがある場合に、ライトパケットを優先して出力する優先制御部(3)とを備え、
前記データ読出し方法は、
第1のデバイス(10)が、第2のデバイス(20)のメモリ(27)の所定のアドレスを書込アドレスとして含み、かつペイロードに前記第2のデバイス(20)のメモリ(27)の読出アドレスを含む読出要求用ライトパケットを生成するステップと、
前記第1のデバイス(10)が、前記生成された読出要求用ライトパケットを前記マルチポートスイッチ(1)を介して前記第2のデバイス(20)に送信するステップと、
前記第2のデバイス(20)が、前記読出要求用ライトパケットを受信するステップと、
前記第2のデバイス(20)が、前記受信した読出要求用ライトパケットに含まれる書込アドレスで指定されるメモリ(27)のアドレスに、前記受信した読出要求用ライトパケットのペイロードに含まれるデータを書込むステップと、
前記第2のデバイス(20)が、前記メモリ(27)の所定のアドレスにデータが書込まれた場合に、読出要求を受けたことを検知し、前記所定のアドレスに書込まれたメモリ(27)の読出アドレスからデータを読出し、前記読出したデータをペイロードに含む読出応答用ライトパケットを生成するステップと、
前記第2のデバイス(20)が、前記生成された読出応答用ライトパケットを前記マルチポートスイッチ(1)を介して前記第1のデバイス(10)に送信するステップと、
前記第1のデバイス(10)が、前記読出応答用ライトパケットを受信するステップとを備えた、データ読出し方法。
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