WO2010103780A1 - Dispositif de gestion de mémoire, enregistreur de données, et procédé de détermination de zone de mémoire - Google Patents

Dispositif de gestion de mémoire, enregistreur de données, et procédé de détermination de zone de mémoire Download PDF

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Publication number
WO2010103780A1
WO2010103780A1 PCT/JP2010/001593 JP2010001593W WO2010103780A1 WO 2010103780 A1 WO2010103780 A1 WO 2010103780A1 JP 2010001593 W JP2010001593 W JP 2010001593W WO 2010103780 A1 WO2010103780 A1 WO 2010103780A1
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Prior art keywords
data
area
memory
program data
program
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PCT/JP2010/001593
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English (en)
Japanese (ja)
Inventor
友田政明
田中基一
濱邉勝志
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パナソニック株式会社
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Priority to JP2011503699A priority Critical patent/JP5395163B2/ja
Publication of WO2010103780A1 publication Critical patent/WO2010103780A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7204—Capacity control, e.g. partitioning, end-of-life degradation

Definitions

  • the present invention relates to a memory management device that manages a nonvolatile memory, a data recording device including the memory management device, and a memory area setting method that sets a memory area of the nonvolatile memory.
  • flash memories which are nonvolatile memories, are frequently used in digital devices such as digital audio players, IC recorders, and digital cameras, and memory cards such as SD cards and MMC cards. Flash memory has become larger in capacity due to process evolution. In particular, as a data storage medium, a NAND flash memory suitable for increasing the capacity is frequently used.
  • the NAND flash memory is divided into, for example, 4096 physical blocks, although the size and the like vary depending on the type. This block is the minimum unit of erasure.
  • the block is composed of 128 pages.
  • a page is a basic unit of writing and reading.
  • the page includes a 2048-byte user data area and a 64-byte redundant area.
  • an application program that reads and writes data in a microcomputer or personal computer incorporated in a device often manages data in a storage medium in units of sectors (512 bytes) as a common unit.
  • the sector may be different from the page which is the basic unit of writing and reading that has been performed.
  • flash memory there is a limit to the number of times flash memory can be written (hereinafter, including erasure).
  • the limit of the number of times of writing is about 100,000 times. Therefore, if the number of times of writing exceeding the limit is performed on a certain area, the area is not guaranteed. In other words, there is a possibility that it is destroyed and cannot be read and written.
  • memory fatigue progresses not only by writing but also by reading. Therefore, when realizing a device equipped with a flash memory, in order to ensure the reliability of the device, usually, a device such as wear leveling is applied so that writing does not concentrate on a specific physical area.
  • the present invention relates to a memory management device, a data recording device, and a memory that reduce the risk of destruction of extremely important data such as program data in memory management using a flash memory or the like that has a limit on the number of times of writing and reading.
  • An object is to provide a region setting method.
  • an object of the present invention is to provide a memory management device, a data recording device, and a memory area setting method that prevent program data from being rewritten as user data is rewritten.
  • a memory management device is a memory management device including a memory control unit that controls a memory, wherein a data area of the memory is managed in units of first and second management areas, and the first management area is It is a unit for reading and writing data, the second management area is a unit for erasing data, the second management area includes a plurality of first management areas, and the data area of the memory only reads data.
  • the memory control unit includes a read-only data area and a read-write data area for writing and erasing data, and the memory control unit matches a boundary between the read-only data area and the read-write data area with a boundary between the second management areas Thus, the data area of the memory is managed.
  • the read-only data area may be provided in a continuous second management area in the memory.
  • the first management area may be a page, and the second management area may be a block.
  • the data recording device of the present invention includes the memory management device and a data recording unit that records data in a memory having an area set by the memory management device.
  • Program data for controlling the operation of the data recording apparatus may be recorded in the read-only data area, and user data may be recorded in the read / write data area.
  • the memory area setting method of the present invention is a method for setting an area of a memory, wherein the data area of the memory is managed in units of first and second management areas, and the first management area reads and writes data.
  • the second management area is a data erasing unit, the second management area includes a plurality of first management areas, and a read-only data area that only reads data in the data area of the memory; Set the read / write data area where data is written and erased, and set the memory data area so that the boundary between the read-only data area and the read / write data area matches the boundary between the second management areas To do.
  • the data area of the memory is set so that the boundary between the read-only data area and the read / write data area matches the boundary that is the least common multiple between the multiple sizes of the second management area. It may be set.
  • the read-only data area may be composed of a plurality of continuous second management areas.
  • the second management area may be a page, and the second management area may be a block.
  • program data and user data are stored in a device in which extremely important data such as program data that is read only and user data that is written and read are stored in the same flash memory.
  • FIG. 1 shows a logical block arrangement
  • FIG. 2A and 2B are diagrams showing a memory area of a flash memory, in which FIG. 1A shows a logical block arrangement
  • FIG. 4 is a diagram illustrating data rewriting, where (a) is a diagram illustrating physical block arrangement, (b) is a detailed diagram of a physical block before rewriting, and (c) is a detailed diagram of a physical block after rewriting.
  • FIG. 7 is a flowchart showing a program data writing method including a memory area setting method according to the first embodiment of the present invention
  • 2A and 2B are diagrams illustrating an example of a NAND flash memory, in which FIG. 1A is a diagram illustrating a logical block arrangement, and FIG. 2A and 2B are diagrams showing an example of a NAND flash memory, where FIG. 1A is a diagram showing a logical block arrangement, and FIG. The figure which shows the program writing apparatus of Embodiment 2 of this invention.
  • FIG. 7 It is a figure which shows block arrangement after program data and system data are written, (a) is a figure which shows logical block arrangement, (b) is a figure which shows physical block arrangement, (c) is after rearrangement Diagram showing physical block layout 7 is a flowchart showing a memory area setting method including data rearrangement according to the second embodiment of the present invention.
  • the data recording apparatus is an IC recorder that records / reproduces sound data.
  • the data recording device reads out and executes the program data stored in the program data area of the flash memory, thereby performing an operation as an IC recorder (recording / reproducing / USB connection, etc.).
  • the data recording apparatus of this embodiment includes a function as a memory management apparatus that manages the memory area of the flash memory.
  • a program data area for only reading is provided in a block different from a user data area for rewriting. That is, the memory area is managed so that the boundary between the program data area and the user data area coincides with the boundary between blocks. As a result, it is possible to prevent the program data from being rewritten with the rewriting of the user data, and to reduce the risk of the program data being destroyed.
  • FIG. 1 shows an IC recorder which is an example of the data recording apparatus of the first embodiment.
  • the data recording apparatus 100 includes a memory management unit 110 that manages a memory in the data recording apparatus 100, a display unit 104, an operation unit 105, an audio processing unit 106, a microphone 107, a speaker 108, and a communication unit 109.
  • the audio processing unit 106 includes an encoder 106e and a decoder 106d.
  • the memory management unit 110 includes a flash memory 102 that is a nonvolatile memory and a memory control unit 120 that controls the flash memory 102.
  • the memory management unit 110 has a function as a memory management device that sets an area of the flash memory 102 and a data recording unit that writes data in the set area.
  • the memory control unit 120 includes a control unit 101 (microcomputer) and a RAM 103.
  • the flash memory 102 is a NAND flash memory in this embodiment.
  • the memory area (data area) 102m of the flash memory 102 includes a program data area 102p for storing program data, a system data area 102s for storing system data, and a user data area 102y for storing user data.
  • the program data is an important program or data that, if destroyed, causes a fatal injury in the operation of the device.
  • the system data includes parameters such as resume data used for the operation of the device.
  • User data is recorded data, music files, and the like.
  • Program data is data that is not rewritten, whereas system data and user data are data that is rewritten. Therefore, the program data area 102p is managed as a read-only data area for only reading data, and the system data area 102s and the user data area 102y are managed as read / write data areas for writing and erasing data.
  • the data recording device 100 is a device for recording / reproducing sound data.
  • the data recording apparatus 100 reads part or all of the program data stored in the program data area 102p of the flash memory 102, develops it in the RAM 103, and executes the program.
  • the program manages the flash memory 102 for example, reads / writes data
  • the data recording apparatus 100 operates as an IC recorder.
  • basic operations of recording / playback / USB connection as an IC recorder will be described.
  • the microphone 107 picks up sound data.
  • the encoder 106e of the audio processing unit 106 encodes sound data picked up by the microphone 107 (for example, MP3 encoding).
  • the control unit 101 records the encoded data in the user data area 102y of the flash memory 102.
  • the encoder 106e of the audio processing unit 106 stops the MP3 encoding.
  • the control unit 101 stops recording encoded data in the flash memory 102.
  • the display unit 104 can display a list of sound data recorded in the user data area 102 y of the flash memory 102.
  • the user can select desired sound data from the list displayed on the display unit 104.
  • the control unit 101 reads desired sound data from the flash memory 102.
  • the decoder 106 d of the audio processing unit 106 decodes the read sound data (in this embodiment, MP3 decoding), and outputs sound from the speaker 108. The same applies to the case where sound is output from the inner phone instead of the speaker 108.
  • the control unit 101 transmits MP3 data or the like from a PC or the like to the user data area 102y of the flash memory 102 via a communication unit 109 in accordance with a communication interface such as USB (Universal Serial Bus) or SATA (Serial Advanced Technology Attachment). It is possible to write. At this time, the written MP3 data or the like can be reproduced.
  • a communication interface such as USB (Universal Serial Bus) or SATA (Serial Advanced Technology Attachment).
  • the control unit 101 is a microcomputer that does not have a built-in RAM and does not have a built-in NOR flash memory for storing program data.
  • the control unit 101 of this embodiment is connected to an external RAM 103 and a flash memory 102 that stores program data in a program data area 102p.
  • the control unit 101 performs part or all of the program data stored in the program data area 102p of the flash memory 102. Is loaded into the RAM 103 and the program is executed.
  • the executed program performs memory management of the flash memory 102 (specifically, data read / write), whereby the data recording apparatus 100 operates as an IC recorder.
  • FIG. 2A shows an example of the memory management unit 110 in the present embodiment.
  • FIG. 2B shows another example (memory management unit 110 ′) of the memory management unit 110.
  • 2A and 2B are diagrams illustrating the memory control unit 120 of the memory management unit 110 of FIG. 1 in another format. Specifically, it is a diagram in which the RAM 103 is incorporated in the control unit 101 and simplified in another format.
  • the memory management unit 110 can be expressed in various forms, and is not limited to FIGS. 2 (a) and 2 (b).
  • the memory management unit 110 includes a memory control unit 120 and a flash memory 102.
  • the memory control unit 120 includes an application program unit 802 and a memory controller 803.
  • the flash memory 102 includes a memory area 102m.
  • the memory management unit 110 in FIG. 2A shows an example in which the memory controller 803 is mounted on the memory control unit 120 side.
  • the memory area 102m of the flash memory 102 includes the program data area 102p shown in FIG. 1, and an application program is stored in the program data area 102p.
  • the memory control unit 120 reads an application program from the memory area 102m, and the application program unit 802 executes the application program.
  • the memory management unit 110 ′ includes a memory control unit 120 and a flash memory 102.
  • the memory control unit 120 includes an application program unit 802.
  • the flash memory 102 includes a memory controller 853 and a memory area 102m.
  • the memory management unit 110 ′ in FIG. 2B shows an example in which the memory controller 853 is mounted on the flash memory 102 side.
  • the memory area 102m of the flash memory 102 includes the program data area 102p shown in FIG. 1, and an application program is stored in the program data area 102p.
  • the memory control unit 120 reads an application program from the memory area 102m, and the application program unit 802 executes the application program.
  • FIG. 2A a case where the memory management unit 110 has a memory controller 803 mounted on the memory control unit 120 side will be described.
  • FIGS. 3A and 3B show an example of correspondence between the logical block arrangement and the physical block arrangement in the memory area 102m.
  • PBA indicates a physical block address (Physical Block Address)
  • LBA indicates a logical block address (Logical Block Address).
  • FIG. 4 shows an example of the logical-physical conversion table.
  • the logical-physical conversion table 700 of FIG. 4 is an example of a table that associates the physical address and logical address of the memory area 102m.
  • the logical block 910 (LBA0), logical block 911 (LBA1), logical block 912 (LBA2), logical block 913 (LBA3), logical block 914 (LBA4), and logical block 916 in the logical block arrangement of FIG. (LBA6) is the physical block 961 (PBA1), physical block 966 (PBA6), physical block 963 (PBA3), physical block 969 (PBA9), and physical block 971 (physical block arrangement) in the physical block arrangement of FIG. PBA11) and physical block 962 (PBA2).
  • the memory controller 803 in FIG. 2A includes the logical-physical conversion table 700 in FIG. 4 and associates physical block addresses with logical block addresses.
  • the logical-physical conversion table 700 is normally generated and managed in the memory controller 803 in many cases, but the generation and management method is not limited here.
  • the application program unit 802 in FIG. 2A performs data read / write access to a logical address instead of a physical address.
  • the memory controller 803 performs correspondence conversion between a logical address and a physical address, and controls so that writing (including erasure) to a specific physical block address is not concentrated.
  • the memory controller 803 makes full use of a wear leveling technique.
  • the wear leveling technique is a technique for appropriately changing the correspondence between logical addresses and physical addresses (here, detailed description thereof is omitted).
  • the application program unit 802 does not need to create a complicated program that does not write (including erasure) biased to a specific physical block address, and does not need to create a logical address (logical block, logical page,
  • the program can be realized by a logical sector or the like. For example, even if the system parameters stored in the flash memory are frequently rewritten and updated, an excessive number of writing (including erasing) is not performed on a specific physical block address. Therefore, the risk of memory destruction due to the memory life is reduced.
  • FIG. 5A shows an example of the physical block arrangement in the memory area 102m in FIG.
  • FIG. 5B shows a physical block at physical block address 2 (PBA2) before data rewriting.
  • FIG. 5C shows the physical block of the physical block address 4094 (PBA4094) after data rewriting.
  • PBA2 physical block address 2
  • FIGS. 5B and 5C each physical block is composed of 128 pages.
  • a page is a basic unit of writing / reading, and includes a payload part (2 Kbytes) and a redundant part (64 bytes).
  • program data A, program data B, and program data C are all pages of physical block address 0 (PBA0), all pages of physical block address 4 (PBA4), and physical block address 2, respectively. It is stored in page 0 of (PBA2). Further, system data D is stored in page 64 of physical block address 2 (PBA2). Also, the physical block address 2 (PBA2) is associated with LBA6 in the logical-physical conversion table 700 of FIG.
  • the application program unit 802 rewrites (updates) the system data stored in the page 64 of the LBA6.
  • the memory controller 803 rewrites (updates) the system data D stored in the page 64 of the PBA 2 corresponding to the LBA 6 using the logical-physical conversion table 700 shown in FIG.
  • the memory controller 803 copies the program data C stored in page 0 of PBA2 to page 0 of PBA4094 as program data E, reads the system data D stored in page 64 of PBA2, and reads the necessary part. Is updated and written as system data F in page 64 of PBA4094. If data exists in other pages, a copy operation like page 0 is performed.
  • the PBA 4094 becomes a new LBA 6 storage area.
  • PBA2 By erasing PBA2, it becomes an unused block. That is, in the logical-physical conversion table 700, the physical address corresponding to LBA6 is rewritten from PBA2 to PBA4094.
  • the entire physical block is copied (reading PBA2, writing to PBA4094, and erasing PBA2).
  • the program data area 102p for program data to be read only, the system data area 102s and the user data area 102y to be read / written are not conscious of physical block boundaries.
  • program data and system data or user data are mixedly stored in the same block.
  • the physical block address of the logical block in which all or a part of the program data is stored also moves frequently. That is, copying (reading and writing) of blocks storing program data is frequently performed. In the case of an IC recorder, recorded data is often rewritten frequently.
  • control unit 101 does not write system data and user data in the same block as program data. That is, the memory area 102m is managed so that the program data area 102p is a separate block from the system data area 102s and the user data area 102y. Thereby, the said risk is reduced.
  • Memory area setting and program writing method> A memory area setting and program data writing method (transfer method) will be described with reference to FIGS.
  • the program data is written at the time of manufacture or shipment of the IC recorder that is the data recording apparatus 100.
  • old program data is stored in the program data area 102p and new program data is written, that is, in the case of an update operation, the following description can be similarly applied.
  • the control unit 101 sets the program data area 102p based on the size of the program data stored in the temporary user data area.
  • the control unit 101 transfers the program data once placed in the temporary user data area to the program data area 102p, and erases the program data remaining in the temporary user data area. At this point, the transfer of the program data to the program data area 102p is completed, and the data recording apparatus 100 becomes operable.
  • FIG. 6 shows an example of a flowchart of a method for writing program data in the present embodiment.
  • FIG. 7 is an example of data arrangement in the memory area 102m, and shows a state after the program data is written.
  • FIG. 7A shows a logical block arrangement of the memory area 102 of the flash memory 102.
  • the memory area 102m includes a program data area, a system data area, a user data area, and a spare data area.
  • Program data A, program data B, and program data C are stored in the program data area.
  • System data D is stored in the system data area.
  • FIG. 7B shows block data of LBA 2 (logical block address 2) of the flash memory 102.
  • LBA 2 logical block address 2
  • the size of a sector which is a common minimum unit that can be handled by the control unit 101, is 512 bytes (in consideration of the affinity with the PC, it is set to 512 bytes).
  • the total size of the program data A, B, and C to be written is 525824 bytes.
  • the control unit 101 manages the sector numbers (sector 0 to sector 2097151) in all blocks with serial numbers.
  • control unit 101 first sets the memory area 102m of the flash memory 102 into a program data area 102p, a system data area 102p, and a user data area 102y (S401 to S408), and then Program data and system data are written to each set area (S409 and S410).
  • the control unit 101 determines a start sector and an end sector of the program data area 102p (S404). In the logical block arrangement of FIG. 7A, the control unit 101 sets the start sector of the program data area 102p as “the first sector of page 0 of LBA0 (ie, sector 0)” and the end sector as “the last sector of LBA2. It is determined as “the last sector of the page 127 (that is, the sector 1535)”. In the present embodiment, the control unit 101 secures the end sector of the program data area 102p not to the limit of the program data size but to the end of the block boundary.
  • the page 0 of LBA0 to page 0 of LBA2 is reserved as the program data area 102p. This prevents data to be rewritten such as user data from being written to page 1 to page 127 of LBA2.
  • the control unit 101 determines the start sector and end sector of the system data area 102s (S406). In the case of the logical block arrangement of FIG. 7A, the control unit 101 sets the start sector of the system data area 102s as “the first sector of page 0 of LBA3 (ie, sector 1536)” and the end sector as “the last sector of LBA3”. It is determined as the last sector of the page 127 (that is, the sector 2047).
  • control unit 101 secures the end sector of the system data area 102s not to the limit of the system data size but to the end of the block boundary.
  • system data is included, but it is not always necessary.
  • the user data size is a size that is secured as an area for recording sound data as an IC recorder or capturing data from a PC via USB.
  • the control unit 101 determines the start sector and end sector of the user data area 102y (S408). In the case of the logical block arrangement of FIG. 7A, the control unit 101 sets the start sector of the user data area 102y as “the first sector of LBA4 (ie, sector 2048)” and the end sector as “the last page of LBA 3999”.
  • the minimum required user data area size has been described as a multiple of the block size. However, even if the user data area size is not a multiple of the block size, the end sector is secured up to the end of the block boundary as with system data To do.
  • control unit 101 moves to a system data writing operation (S410).
  • the control unit 101 writes 512 bytes of system data in the system data area 102s. Specifically, the data is written to LBA3. Little is written after page 1 of LBA3.
  • the data recording apparatus 100 can perform the above-described recording operation, reproduction operation, and the like.
  • the program data area 102p does not coexist in the same physical block as the system data area 102s and the user data area 102y to be read / written.
  • the boundary between the program data area 102p for only reading data and the system data area 102s and user data area 102y for writing and erasing data coincide with the boundary of the physical block. Therefore, for example, in FIG. 7, when system data is frequently updated (rewritten), only the physical block copy operation corresponding to LBA3 occurs frequently, corresponding to LBA0 to LBA2 in which program data is stored. No physical block copy occurs.
  • each area may be set by the method described above.
  • each area is common at the sector number level in the plurality of flash memories. It is good to set so that. This makes it possible to share a program when realizing IC recorders having different storage capacities.
  • FIG. 8 shows an arrangement of the memory area 102m different from that in FIG.
  • the size of a sector which is a common minimum unit that can be handled by the control unit 101, is 512 bytes (in consideration of the affinity with the PC, 512 bytes), and the size of a page with 4 sectors as one page is 2 Kbytes, 64 bytes.
  • the size of a block with one page is 128 Kbytes, and the number of blocks is 8192.
  • the size of the program data is 525824 bytes.
  • the control unit 101 manages the sector numbers (sector 0 to sector 2097151) in all blocks with serial numbers.
  • FIG. 8 shows an example of data arrangement in the memory area 102m different from that in FIG. 7, and shows a state after each area is set and program data and system data are written according to the flow shown in FIG.
  • FIG. 8A shows a logical block arrangement of the memory area 102 of the flash memory 102.
  • the memory area 102m includes a program data area, a system data area, a user data area, and a spare data area.
  • Program data A, program data B, program data C, program data D, and program data E are written in the program data area.
  • System data F is written in the system data area.
  • FIG. 8B shows block data of LBA 4 (logical block address 4) of the flash memory 102.
  • the control unit 101 determines a start sector and an end sector of the program data area 102p (S404). In the logical block arrangement shown in FIG. 8A, the control unit 101 sets the start sector of the program data area 102p as “the first sector of page 0 of LBA0 (ie, sector 0)” and the end sector as “LBA5. The final sector of the page 63 that is the final page (that is, the sector 1535) is determined.
  • the control unit 101 secures the end sector of the program data area 102p not to the limit of the program data size but to the boundary end of the common block instead of the block boundary end.
  • the control unit 101 determines the start sector and end sector of the system data area 102s (S406).
  • the control unit 101 sets the start sector of the system data area 102s as “the first sector of page 0 of LBA6 (that is, sector 1536)” and the end sector as “the last sector of LBA7”. It is determined as “the last sector of the page 127 (that is, the sector 2047)” (S406).
  • the control unit 101 secures the end sector of the system data area 102s not to the limit of the system data size but to the boundary end of the common block instead of the block boundary end. Specifically, not the last sector of the page 127 that is the last page of the LBA6 (that is, the sector 1791) but the common sector is considered and the last sector of the page 127 that is the last page of the LBA7 (that is, the sector 2047) is secured. To do.
  • the control unit 101 determines the start sector and end sector of the user data area 102y (S408). In the case of the logical block arrangement of FIG. 8, the control unit 101 sets the start sector of the user data area 202y as “the first sector of LBA8 (ie, sector 2048)” and the end sector of “page 127, which is the last page of LBA7999”. The final sector (ie, sector 2047999) ”is determined.
  • the minimum required user data area size has been described as a multiple of the common block size. Secure to the end.
  • control unit 101 moves to a program data write operation (S409).
  • the control unit 101 writes 525824 bytes of program data in the program data area 102p.
  • program data is converted into program data A (131072 bytes), program data B (131072 bytes), program data C (131072 bytes), program data D (131072 bytes), and program data E (1536 bytes). Therefore, the data is written in LBA0, LBA1, LBA2, LBA3, and LBA4, respectively. None is written in page 1 and subsequent pages of LBA4 and LBA5.
  • control unit 101 moves to a system data writing operation (S410).
  • the control unit 101 writes 512 bytes of system data in the system data area 102s. Specifically, the data is written in LBA6. Little is written in page 1 and subsequent pages of LBA6 and LBA7.
  • the data recording apparatus 100 can perform the recording operation and the reproduction operation described above.
  • the physical storage locations of program data and user data are distinguished and managed in units of common blocks. It is possible to reduce the risk of program data destruction and to share application programs (increase development efficiency).
  • the sector address that divides each area can be shared, and data reading and writing are shared. Can be managed by sector address. Therefore, the program can be shared and the development efficiency can be improved.
  • the program data area 102p, the system data area 102s to be read / written, and the user data area 102y do not coexist in the same physical block.
  • the boundary between the program data area 102p for only reading data, the system data area 102s for writing and erasing data, and the user data area 102y coincides with the boundary between physical blocks. Therefore, for example, in FIG. 8, even if system data is frequently updated (rewritten), only a physical block copy operation corresponding to LBA 6 occurs. Also, for example, even if user data is frequently updated (rewritten), only physical block copy operations corresponding to LBA8 to LBA7999 occur frequently. Therefore, no physical block copy corresponding to LBA0, LBA1, LBA2, LBA3, and LBA4 in which program data is stored occurs. As a result, the risk of memory destruction can be reduced.
  • program data and user data can be stored in one memory.
  • a conventional data recording device such as an IC recorder has a memory for storing program data (for example, a NOR flash memory) and user data such as recording data in order to prevent destruction of the program data.
  • a memory for example, a NAND flash memory.
  • the program data and the user data can be prevented from being destroyed, so that one memory can be used. For example, it is not necessary to provide a dedicated memory for programs. Therefore, the cost of the data recording apparatus 100 can be reduced.
  • the data recording apparatus 100 has been described using an IC recorder that reads and writes audio data from and to the flash memory 102 that is a non-volatile storage medium.
  • the type of the data recording apparatus 100 is not limited to this embodiment.
  • the form is not limited.
  • the data recording device 100 may be any device that reads / writes user data from / to a nonvolatile storage medium.
  • the data recording device 100 may be a digital camera or a portable terminal.
  • the memory management unit 110 is a memory management apparatus. It may not be provided in the data recording apparatus 100 as part of the function.
  • the memory management device may be provided inside a device different from the data recording device 100, or the memory management device itself may function as one device.
  • the memory management device may be a part or all of the functions of a device for setting a program data area and a program writing device for producing a flash memory in which program data is written.
  • the flash memory 102 is a NAND flash memory
  • the type of the flash memory 102 is not limited to the present embodiment.
  • any other nonvolatile storage medium such as a NOR flash memory and an EEPROM may be used.
  • control unit 101 is used as a microcomputer and the RAM 103 is provided as an external RAM has been described as an example.
  • the RAM 103 may be built in the control unit 101.
  • the program data, the system data, and the user data are stored in the flash memory 102.
  • the type of data stored in the flash memory 102 is not limited to the present embodiment.
  • the present embodiment can be applied when program data and other data to be read and written (for example, user data) are stored in the same flash memory.
  • the area is set immediately before the program data is written (S409).
  • the area may be set at a timing different from the program data write (transfer process).
  • the pre-processing of S409 (including S401, S402, S403, S405, and S407) is not necessarily performed during the transfer process, and may be calculated in advance.
  • the memory management device of this embodiment is a device (program writing device) that is provided in a factory or the like and produces a large amount of flash memory in which program data is written.
  • the program writing apparatus according to the present embodiment rearranges the physical block to which program data is written, and copies the flash memory using the rearranged flash memory as a master, thereby copying a large amount of data in a short time (that is, , Production of pre-written flash memory).
  • FIG. 9 shows a program writing device which is an example of a memory management device in the present embodiment.
  • the program writing device 1000 includes a ROM writer 1001 and a personal computer (PC) 1002.
  • the ROM writer 1001 is connected to the PC 1002.
  • the ROM writer 1001 can write data stored in the PC 1002 to the blank flash memories 1004, 1005, and the like.
  • the ROM writer 1001 can read data recorded in the written flash memory 1003 from the written flash memory 1003 and save it in the PC 1002.
  • the PC 1002 can read data from the ROM writer 1001, process the read data, and write the processed data to the blank flash memories 1004 and 1005.
  • the written flash memory 1003 and the blank flash memories 1004 and 1005 are NAND flash memories.
  • FIGS. 10A and 10B show a state where program data and system data are written in the written flash memory 1003.
  • FIG. 10A shows the arrangement in the logical block
  • FIG. 10B shows the arrangement in the physical block.
  • program data A, program data B, program data C, program data D, and program data E are written in the program data area.
  • System data F is written in the system data area.
  • the physical block arrangement in FIG. 10B is obtained by rearranging the blocks in the logical block arrangement in FIG. 10A into the physical arrangement, and includes program data and system data included in the logical block arrangement.
  • FIG. 10C shows the physical block arrangement after the program data and system data included in the physical block arrangement of FIG. 10B are rearranged on the PC 1002 in this embodiment.
  • the flash memory 1003 is in a state. Specifically, program data A is stored in LBA 0, program data B is LBA 1, program data C is stored in LBA 2, program data D is stored in LBA 3, and program data E is stored in LBA 4, as shown in the logical block arrangement of FIG. As a result, the system data F is stored in the LBA 6.
  • the ROM writer 1001 writes data for 14 blocks in the physical block arrangement into the blank flash memory 1004.
  • the time required for writing at this time is a time for writing data for 14 blocks (and including verification and the like).
  • the blank flash memory 1004 is in a state in which program data and the like are written.
  • another blank flash memory 1005 is mounted on the ROM writer 1001.
  • the ROM writer 1001 writes data for 14 blocks in the physical block arrangement to the blank flash memory 1005.
  • the application program can recognize only the logical address, even if the program data is written in a continuous area in the logical block arrangement by the data recording apparatus 100 or the like of the first embodiment, it is actually shown in the physical block arrangement of FIG. Thus, it will be written at a distant position.
  • the ROM writer 1001 can access the flash memory only with a physical address. Since the ROM writer 1001 does not know where the program data is arranged in the physical block, for example, only the PBAs 1, 3, 6, 9, and 11 shown in FIG. Therefore, for example, all the physical blocks in which the program can be stored are read out from all areas of the flash memory, that is, from the first block (PBA0) of the physical block to the last block of the physical block.
  • Physical blocks (including empty blocks) are written to the blank flash memory. Therefore, the conventional memory management device cannot produce a large amount of written flash memory in a short time. Therefore, in the present embodiment, as shown below, the physical blocks of the written flash memory that is the master are rearranged.
  • FIG. 11 shows a flowchart of a program storage method including memory area setting (specifically, relocation of program data) in the second embodiment.
  • Program data is stored in the continuous areas LBA0 to LBA4 of the written flash memory 1003 as in the logical block arrangement of FIG. However, in actuality, they are arranged apart like the physical block arrangement of FIG. 10B (see the logical-physical conversion table 700 of FIG. 4). Since the ROM writer 1001 accesses the flash memory with a physical address, it cannot read only the PBAs 1, 3, 6, 9, and 11. When reading all program data and system data, if the physical block address where the data is stored is known in advance, the ROM writer 1001 reads the block data up to the final physical block (PBA). Good.
  • the ROM writer 1001 reads data for 14 blocks from PBA0 to PBA13.
  • program data A is arranged in PBA1, program data B in PBA6, program data C in PBA3, program data D in PBA9, and program data E in PBA11.
  • the system data F is arranged in PBA2.
  • the ROM writer 1001 transmits the read 14 blocks of data to the PC 1002. As a result, the read data is taken into the PC 1002.
  • the program writing apparatus 1000 rearranges physical blocks in which program data and system data are written on the PC 1002 (S1102). That is, the physical block arrangement in FIG. 10B is rearranged to the physical block arrangement in FIG. Specifically, the PC 1002 virtually creates a physical block arrangement. Next, the physical block arrangement is searched from PBA0, and the physical block PBA1 including the program data A first found is arranged in PBA0 of the physical block arrangement.
  • the physical block in which the data is stored includes a mechanism that makes it possible to identify an empty block.
  • the PC 1002 arranges the physical block PBA2 including the system data F found next in the physical block arrangement PBA1.
  • the physical block PBA3 including the program data C is allocated to the PBA2 having the physical block arrangement
  • the physical block PBA6 including the program data B is allocated to the PBA3 having the physical block arrangement
  • the physical block including the program data D is included.
  • PBA9 is arranged in PBA4 of physical block arrangement
  • physical block PBA11 including program data E is arranged in PBA5 of physical block arrangement.
  • the PC 1002 writes the completed physical block arrangement for six blocks to another blank flash memory mounted on the ROM writer 1001.
  • the physical address after rearrangement is made to correspond to the logical address by the logical physical conversion table 700.
  • the program data area 102p and the system data area 102s are set to PBA0 to PBA5. If the order of the divided program data is known in advance, rearrangement may be performed in that order.
  • This flash memory becomes the master flash ROM.
  • a flash memory in which program data is written by the program writing apparatus 1000 of the present embodiment (that is, a flash memory in which the program data area and the system data area are set to PBA0 to PBA5) is a data recording apparatus such as an IC recorder, for example. Incorporated into.
  • the system data F is arranged between the program data A and the program data C, but it is more preferable to arrange the program data and the system data separately.
  • the system data F is preferably arranged in the next block of the program data E.
  • the program data area is composed of continuous physical blocks.
  • the program data arranged in the physically distributed physical blocks is rearranged in the physically continuous physical blocks and stored in the flash memory, so that the memory described in the first embodiment While maintaining the effect of reducing the risk of destruction, it is possible to reduce the writing time in the ROM writer when the flash memory storing the program data is mass-produced with the ROM writer or the like. That is, the program data area to be read in the physical block arrangement can be reduced by rearranging the program data write destination. Therefore, the size of data to be written by a ROM writer can be reduced, and the writing time can be shortened.
  • system data and the system data are described as an example in which the ROM writer 1001 writes the written flash memory to the blank flash memory.
  • the system data does not necessarily need to be written to the blank flash memory.
  • At least the program data may be written.
  • the program data area is set to a continuous physical block by relocation of the program data.
  • the program writing apparatus 1000 including the ROM writer 1001 and the PC 1002 is described as an example of the memory management apparatus.
  • the configuration of the memory management apparatus is not limited to this embodiment. Any device capable of reading / rearranging / writing data with respect to a physical block of the flash memory 1003 (same as a physical address such as a physical sector or a physical page) can be regarded as having the same configuration as in the present embodiment. Do not exclude them because they can.
  • the flash memories 1003, 1004, and 1005 are NAND flash memories
  • the types of the flash memories 1003, 1004, and 1005 are not limited to the present embodiment.
  • any other nonvolatile storage medium such as a NOR flash memory and an EEPROM may be used.
  • program data, system data, and user data are stored in the flash memory
  • type of data stored in the flash memory is not limited to this embodiment.
  • the present embodiment can be applied when program data and other data to be read and written (for example, user data) are stored in the same flash memory.
  • the program data and the system data are written.
  • the type and number of data to be written are not limited to these. Even various combinations can be regarded as the same configuration as in the present embodiment, and thus are not excluded.
  • the present invention has the effect of reducing the risk of destruction of extremely important data such as program data that is read only, and is useful for IC recorders and semiconductor music players equipped with flash memory.
  • SYMBOLS Data recording device 101 Control part 102 Flash memory 102p Program data area 102s System data area 102y User data area 102m Memory area 103 RAM DESCRIPTION OF SYMBOLS 104 Display part 105 Operation part 106 Audio processing part 106e Encoder 106d Decoder 107 Microphone 108 Speaker 109 Communication part 110 Memory management part 120 Memory control part 700 Logical physical conversion table 802 Application program part 803 Memory controller 853 Memory controller 1000 Program writing device 1001 ROM Writer 1002 PC 1003 Pre-programmed flash memory 1004 Blank flash memory 1005 Blank flash memory

Abstract

L'invention concerne un dispositif de gestion de mémoire qui réduit le risque de destruction des données importantes, telles que des données de programme qui sont seulement lues et, également, un enregistreur de données et un procédé de détermination de zone de mémoire. Un dispositif de gestion de mémoire est équipé d'une unité de commande de mémoire (120) qui commande une mémoire (102). La zone de données de la mémoire est gérée par unités de première et seconde zones de gestion. La première zone de gestion est l'unité de lecture/écriture de données, la seconde zone de gestion est l'unité d'effacement de données et la seconde zone de gestion comprend une pluralité de premières zones de gestion. La zone de données de la mémoire comprend une zone de données à lecture seule (102p) dans laquelle les données sont seulement lues et des zones de lecture/écriture de données (102s, 102y) dans lesquelles les données sont écrites et effacées. L'unité de commande de mémoire gère la zone de données de la mémoire de sorte que la frontière entre la zone de données à lecture seule et la zone de lecture/écriture de données corresponde à la frontière entre les secondes zones de gestion.
PCT/JP2010/001593 2009-03-12 2010-03-08 Dispositif de gestion de mémoire, enregistreur de données, et procédé de détermination de zone de mémoire WO2010103780A1 (fr)

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KR102491624B1 (ko) 2015-07-27 2023-01-25 삼성전자주식회사 데이터 저장 장치의 작동 방법과 상기 데이터 저장 장치를 포함하는 시스템의 작동 방법
WO2021005777A1 (fr) 2019-07-11 2021-01-14 Ｐｒｉｍｅｔａｌｓ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｊａｐａｎ株式会社 Procédé de fonctionnement d'un dispositif de laminage, dispositif de commande pour dispositif de laminage et équipement de laminage

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