WO2010071306A2 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2010071306A2
WO2010071306A2 PCT/KR2009/007017 KR2009007017W WO2010071306A2 WO 2010071306 A2 WO2010071306 A2 WO 2010071306A2 KR 2009007017 W KR2009007017 W KR 2009007017W WO 2010071306 A2 WO2010071306 A2 WO 2010071306A2
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WO
WIPO (PCT)
Prior art keywords
common
electrodes
voltage
pixel electrodes
pixel
Prior art date
Application number
PCT/KR2009/007017
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English (en)
Korean (ko)
Other versions
WO2010071306A3 (fr
Inventor
최상철
홍광표
Original Assignee
엘지이노텍주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 엘지이노텍주식회사 filed Critical 엘지이노텍주식회사
Publication of WO2010071306A2 publication Critical patent/WO2010071306A2/fr
Publication of WO2010071306A3 publication Critical patent/WO2010071306A3/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures

Definitions

  • An embodiment relates to a display device.
  • display devices such as LCD, PDP and AMOLED are widely used.
  • the LCD may include common electrodes and pixel electrodes facing each other, and a liquid crystal layer interposed between the two electrodes.
  • the common electrodes and the pixel electrodes may be driven in various ways such as frame inversion, line inversion, and dot inversion.
  • the embodiment provides a display device having improved image quality and low power consumption.
  • a display device includes: a plurality of gate lines extending in a first direction; A plurality of data lines crossing the gate lines and extending in a second direction; A plurality of pixel electrodes disposed in pixel regions defined by the gate lines and the data lines, respectively; A plurality of first common electrodes corresponding to some of the pixel electrodes and extending in the second direction; And a plurality of second common electrodes disposed between the first common electrodes, respectively.
  • a display device includes a substrate on which a plurality of pixel areas are defined; A plurality of first pixel electrodes and a plurality of second pixel electrodes disposed in the pixel regions, respectively; First common electrodes corresponding to the first pixel electrodes and electrically connected to each other; Second common electrodes corresponding to the second pixel electrodes and electrically connected to each other; And a driver configured to apply a first common voltage signal to the first common electrodes and to apply a second common voltage signal to the second common electrodes.
  • a display device in one embodiment, includes a substrate; First pixel electrodes arranged in a first column on the substrate; Second pixel electrodes arranged in a second column on the substrate; A first common electrode disposed to correspond to the first pixel electrodes; And a second common electrode corresponding to the second pixel electrodes and receiving a signal different from the first common electrode.
  • the display device may drive the first common electrodes and the second common electrodes in different ways. That is, the first common voltage signal may be applied to the first common electrodes, and the second common voltage signal may be applied to the second common electrodes.
  • a negative voltage may be applied to the first pixel electrodes facing the first common electrodes
  • a positive voltage may be applied to the second pixel electrodes facing the second common electrodes.
  • voltages applied to the first common electrodes, the second common electrodes, the first pixel electrodes, and the second pixel electrodes may be inverted or alternated.
  • the display device may be driven by a dot inversion method.
  • the display device divides the common electrode into two types, and applies two types of signals to each of them, thereby implementing a dot inversion method.
  • the display device according to the embodiment can implement a dot inversion scheme without consuming much power. That is, the display device according to the embodiment can implement the improved image quality with little power.
  • FIG. 1 is a circuit diagram illustrating a liquid crystal display according to an embodiment.
  • FIG. 2 is a block diagram illustrating a liquid crystal display according to an embodiment.
  • FIG. 3 is a plan view illustrating a liquid crystal display according to an embodiment.
  • FIG. 4 is a cross-sectional view illustrating a cross section taken along line AA ′ in FIG. 3.
  • FIG. 5 is a cross-sectional view illustrating a cross section taken along line BB ′ in FIG. 3.
  • FIG. 6 is a waveform diagram illustrating common voltage signals, data signals, and gate signals.
  • FIG. 7 is a diagram illustrating an inversion method of the liquid crystal display according to the embodiment.
  • each panel, layer, electrode, wiring or substrate, etc. is formed on or under the "on” of each panel, layer, electrode, wiring or substrate, etc.
  • “on” and “under” include both being formed “directly” or “indirectly” through other components.
  • the criteria for the top or bottom of each component will be described with reference to the drawings. The size of each component in the drawings may be exaggerated for description, and does not mean a size that is actually applied.
  • FIG. 1 is a circuit diagram illustrating a liquid crystal display according to an embodiment.
  • 2 is a block diagram illustrating a liquid crystal display according to an embodiment.
  • 3 is a plan view illustrating a liquid crystal display according to an embodiment.
  • FIG. 4 is a cross-sectional view illustrating a cross section taken along line AA ′ in FIG. 3.
  • FIG. 5 is a cross-sectional view illustrating a cross section taken along line BB ′ in FIG. 3.
  • 6 is a waveform diagram illustrating common voltage signals, data signals, and gate signals.
  • 7 is a diagram illustrating an inversion method of the liquid crystal display according to the embodiment.
  • the liquid crystal display device includes a liquid crystal panel 10 and a driver IC 20.
  • the liquid crystal panel 10 includes a plurality of gate lines GL1, GL2..., A plurality of data lines DL1, DL2,..., A plurality of thin film transistors TFT, and a plurality of pixel electrodes. PE1 and PE2 and a plurality of common electrodes CE1 and CE2.
  • the gate lines GL1, GL2... Extend in a first direction and are arranged in parallel with each other.
  • the gate lines GL1, GL2... Are disposed on the first transparent substrate 100.
  • Examples of the material used for the gate lines GL1, GL2... include aluminum, copper, tungsten, molybdenum, titanium, alloys thereof, and the like.
  • the data lines DL1, DL2,... are arranged to cross the gate lines GL1, GL2.
  • the data lines DL1, DL2,... Extend in a second direction and are arranged in parallel with each other.
  • a plurality of pixel regions P is formed by the gate lines GL1, GL2... And the data lines DL1, DL2,.
  • the pixel areas P have a rectangular shape.
  • a gate insulating film 101 covering the gate lines GL1, GL2... Is disposed between the gate lines GL1, GL2... And the data lines DL1, DL2... Can be arranged.
  • the thin film transistors TFT are disposed in an area where the gate lines GL1, GL2... And the data lines DL1, DL2,...
  • the thin film transistors TFT are turned on or turned off in accordance with gate signals GS1, GS2,..., Applied through the gate lines GL1, GL2.
  • the thin film transistors TFT selectively apply the data signals DS1 and DS2 applied through the data lines DL1, DL2,... To the pixel electrodes PE1 and PE2. do.
  • the pixel electrodes PE1 and PE2 are disposed in the pixel regions P. As illustrated in FIG. In more detail, the pixel electrodes PE1 and PE2 are disposed in the pixel regions P, respectively. That is, the pixel electrodes PE1 and PE2 are arranged in a matrix form.
  • the liquid crystal panel 10 has a passivation layer 102 covering the data line, and the pixel electrodes PE1 and PE2 are disposed on the passivation layer 102.
  • the first common electrodes CE1 extend in the second direction.
  • the first common electrodes CE1 are disposed parallel to each other.
  • the first common electrodes CE1 are disposed to face the pixel electrodes PE1.
  • the first common electrodes CE1 are disposed under the second transparent substrate 200.
  • the first common electrodes CE1 may be disposed in parallel with the data lines DL1, DL2,... And correspond to the data lines DL1, DL2,...
  • the first common electrodes CE1 are electrically connected to each other.
  • the first common electrodes CE1 may be integrally formed to receive the same signals from the driver IC 20.
  • the second common electrodes CE2 extend in the second direction.
  • the second common electrodes CE2 are disposed parallel to each other.
  • the second common electrodes CE2 are disposed to face the pixel electrodes PE2.
  • the second common electrodes CE2 are disposed under the second transparent substrate 200.
  • the second common electrodes CE2 are alternately disposed with the first common electrodes CE1.
  • one second common electrode CE2 is disposed between the first common electrodes CE1.
  • the second common electrodes CE2 are disposed in parallel with the data lines DL1, DL2,... And the first common electrodes CE1.
  • the second common electrodes CE2 are electrically connected to each other.
  • the second common electrodes CE2 are integrally formed to receive the same signals from the driver IC 20.
  • the pixel electrodes PE1 and PE2 are opposed to the first pixel electrodes PE1 facing the first common electrodes CE1 and the second pixel electrodes facing the second common electrodes CE2.
  • Divided by (PE2) For example, the first common electrodes CE1 correspond to pixel areas of the odd-numbered columns CL1, CL3,..., And the first pixel electrodes PE1 correspond to odd-numbered columns ( And the pixel areas of CL1, CL3, ).
  • the second common electrodes CE2 correspond to pixel regions of even-numbered columns CL2, CL4,...
  • the second pixel electrodes PE2 correspond to even-numbered columns CL2,. Are arranged in the pixel areas of CL4, ).
  • the liquid crystal panel 10 includes a liquid crystal layer 300 interposed between the first transparent substrate 100 and the second transparent substrate 200, and the common electrodes CE1 and CE2 and the liquid crystal layer 300.
  • the color filter layer 201 is interposed between the second transparent substrate 200.
  • the driver IC 20 generates a signal for driving the liquid crystal panel 10 and supplies it to the liquid crystal panel 10.
  • the driver IC 20 may be mounted on the liquid crystal panel 10.
  • the driver IC 20 may be a chip in which a plurality of circuits for driving the liquid crystal panel 10 are integrated.
  • the driver IC 20 includes a latch unit 21, a display RAM 22, a source driver 23a, a gate driver 23b, a first common driver 24a and a second common driver 24b, and a register 27. ), An address counter 25, a timing controller 26, and a power supply circuit 28.
  • the latch unit 21 receives and latches data for displaying an image such as RGB data from an interface. In addition, the latch unit 21 transfers the latched data to the display RAM 22.
  • the display RAM 22 stores the latched data, loads the stored data, and transmits the stored data to the source driver 23a.
  • the source driver 23a receives the data from the display RAM 22. In addition, the source driver 23a receives the timing signal from the timing controller 26, generates the data signals DS1 and DS2, and supplies the data signals DS1 and DS2 to the liquid crystal panel 10. In more detail, the source driver supplies the data signals DS1 and DS2 to the data lines DL1, DL2,...
  • the gate driver 23b receives the timing signal from the timing controller 26, generates the gate signals GS1, GS2,..., And supplies the gate signals to the liquid crystal panel 10. In more detail, the gate driver 23b supplies the gate signals GS1, GS2,... To the gate lines GL1, GL2.
  • the first common driver 24a receives the timing signal from the timing controller 26, generates the first common voltage signal CS1, and supplies the first common voltage signal CS1 to the liquid crystal panel 10. In more detail, the first common driver applies the first common voltage signal CS1 to the first common electrodes CE1.
  • the second common driver 24b receives the timing signal from the timing controller, generates the second common voltage signal CS2, and supplies the second common voltage signal CS2 to the liquid crystal panel 10. In more detail, the second common driver 24b supplies the second common voltage signal CS2 to the second common electrodes CE2.
  • the register 27 receives command signals DE, HSYNC, and VSYNC from the interface to control the timing controller 26 and the address counter 25.
  • the register 27 may include a data register capable of storing and loading the command signals DE, HSYNC, and VSYNC, and a control register controlling the timing controller 26 and the address counter 25. have.
  • the timing controller 26 converts a clock signal generated as an internal reference to generate timing signals. In addition, the timing controller 26 transmits the timing signals to the display RAM 22 and the drivers 23a, 23b, 24a, and 24b.
  • the display RAM 22 stores and loads the data by the timing signal.
  • the power supply circuit 28 receives an external voltage Vcc from the outside, and generates an internal voltage used in the driver IC 20.
  • the power supply circuit 28 includes the latch unit 21, the display RAM 22, the drivers 23a, 23b, 24a, 24b, the register 27, the address counter 25, and the like. A voltage for driving the timing controller 26 is generated.
  • the power supply circuit 28 also receives a ground voltage GND from the outside.
  • the first common voltage signal CS1 and the second common voltage signal CS2 have reverse phases.
  • the first common driver 24a applies the high voltage VH to the first common electrodes CE1
  • the second common driver 24b is the second common electrodes CE2.
  • VL low voltage
  • the first common driver 24a applies the low voltage VL to the first common electrodes CE1
  • the second common driver 24b is applied to the second common electrodes CE2.
  • the high voltage VH is applied.
  • the first common voltage signal CS1 and the second common voltage signal CS2 are signals in which the high voltage VH and the low voltage VL are alternated with each other.
  • the first common driver 24a and the second common driver 24b may be configured such that the first common electrodes CE1 and the second common electrodes CE2 have different voltage levels. The voltages applied to the first common electrodes CE1 and the second common electrodes CE2 are continuously alternated.
  • the first common driver 24a may have a low voltage VL and a high voltage VH (for example, VL, VH, VL, VH, ...) in order to the first common electrodes CE1. Are applied alternately.
  • the second common driver 24b may have a high voltage VH and a low voltage VL (for example, VH, VL, VH, VL, ...) in order to the second common electrodes CE2. Are applied alternately.
  • the driver IC 20 first applies a low voltage VL to the first common electrodes CE1 and applies a high voltage VH to the second common electrodes CE2. . Thereafter, the driver IC 20 applies a high voltage VH to the first common electrodes CE1 and a low voltage VL to the second common electrodes CE2.
  • the data driver 23a applies first data signals DS1 to the first pixel electrodes PE1 through the odd-numbered data lines DL1, DL3,... Similarly, the data driver 23a applies the second data signals DS2 to the second pixel electrodes PE2 through the even-numbered data lines DL2, DL4,...
  • the gate driver 23b applies gate signals GS1, GS2,... To the gate lines GL1, GL2..., Respectively to turn on the thin film transistors TFT that are turned on. Decide That is, the gate driver 23b determines a line on which an image is displayed.
  • a turn-on signal is applied to the thin film transistors TFT of the first line LN1 through the first gate line GL1.
  • the first data signals DS1 are applied to the odd data lines DL1, DL3,..., And the second data on even-numbered data lines DL2, DL4,... Signals DS2 are applied.
  • a positive polarity voltage is applied to the first pixel electrodes PE1 of the first line LN1 and a low voltage VL is applied to the first common electrodes CE1.
  • a negative voltage is applied to the second pixel electrodes PE2 of the first line LN1 and a high voltage VH is applied to the second common electrodes CE2.
  • a turn-on signal is applied to the thin film transistors TFT of the second line LN2 through the second gate line GL2.
  • the first data signals DS1 are applied to the odd data lines DL1, DL3,...
  • the second data signals are applied to even-numbered data lines DL2, DL4,... DS2 is applied.
  • a negative voltage is applied to the first pixel electrodes PE1 of the second line LN2, and a high voltage VH is applied to the first common electrodes CE1.
  • a positive polarity voltage is applied to the second pixel electrodes PE2 of the second line LN2, and a low voltage VL is applied to the second common electrodes CE2.
  • voltages of different polarities are applied to the pixel electrodes PE1 and PE2 included in the pixel areas adjacent to each other based on one frame. That is, a voltage whose polarity is inverted in a dot unit is applied to the pixel electrodes PE1 and PE2.
  • the liquid crystal display according to the embodiment may be driven by a dot inversion method, and an improved screen may be realized.
  • liquid crystal display according to the exemplary embodiment may implement dot inversion by applying only two types of signals to the common electrodes CE1 and CE2, and thus may realize an improved image quality without much power consumption.
  • liquid crystal display device in which the pixel electrodes and the common electrodes are disposed on different substrates, for example, a TN mode liquid crystal display device, has been described, but the present invention is not limited thereto.
  • the structure and driving method according to the present embodiment may be applied.
  • the common electrodes and the pixel electrodes may be disposed in respective pixel regions of the first transparent substrate, and the common electrodes of the same column may be electrically connected to each other.
  • the common electrodes of the odd-numbered column and the common electrodes of the even-numbered column may be driven separately as in the driving method described above.
  • the embodiment applies to the field of display.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un dispositif d'affichage comprenant: une pluralité de conducteurs de grille qui s'étendent dans une première direction; une pluralité de conducteurs de données qui croisent les conducteurs de grille et s'étendent dans une seconde direction; une pluralité d'électrodes de pixels disposées dans les régions de pixels respectives délimitées par les conducteurs de grille et les conducteurs de données; une pluralité de premières électrodes communes qui correspondent à la partie électrodes de pixels et s'étendent dans la seconde direction; et une pluralité de secondes électrodes communes disposées parmi les premières électrodes communes. Le dispositif d'affichage excite séparément les premières électrodes communes et les secondes électrodes communes, et cela, dans un système d'inversion de points.
PCT/KR2009/007017 2008-12-17 2009-11-26 Dispositif d'affichage WO2010071306A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2008-0128289 2008-12-17
KR1020080128289A KR20100069770A (ko) 2008-12-17 2008-12-17 액정표시장치

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WO2010071306A2 true WO2010071306A2 (fr) 2010-06-24
WO2010071306A3 WO2010071306A3 (fr) 2010-08-26

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN107577074A (zh) * 2017-10-30 2018-01-12 武汉华星光电技术有限公司 薄膜晶体管液晶显示面板

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JP2005300948A (ja) * 2004-04-13 2005-10-27 Hitachi Displays Ltd 表示装置及びその駆動方法
JP2006011405A (ja) * 2004-05-21 2006-01-12 Sanyo Electric Co Ltd 表示装置

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JPH11282431A (ja) * 1998-03-31 1999-10-15 Toshiba Electronic Engineering Corp 平面表示装置

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Publication number Priority date Publication date Assignee Title
JP2001350451A (ja) * 2000-06-06 2001-12-21 Seiko Epson Corp 液晶装置、その駆動装置及びその駆動方法、並びに電子機器
JP2005300948A (ja) * 2004-04-13 2005-10-27 Hitachi Displays Ltd 表示装置及びその駆動方法
JP2006011405A (ja) * 2004-05-21 2006-01-12 Sanyo Electric Co Ltd 表示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107577074A (zh) * 2017-10-30 2018-01-12 武汉华星光电技术有限公司 薄膜晶体管液晶显示面板

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