WO2010071306A2

WO2010071306A2 - Display device

Info

Publication number: WO2010071306A2
Application number: PCT/KR2009/007017
Authority: WO
Inventors: 최상철; 홍광표
Original assignee: 엘지이노텍주식회사
Priority date: 2008-12-17
Filing date: 2009-11-26
Publication date: 2010-06-24
Also published as: KR20100069770A; WO2010071306A3

Abstract

A display device is disclosed. The display device comprises: a plurality of gate wires extending in a first direction; a plurality of data wires which intersect the gate wires, and which extend in a second direction; a plurality of pixel electrodes disposed in the respective pixel regions defined by the gate wires and the data wires; a plurality of first common electrodes which correspond to the pixel electrode portion, and which extend in the second direction; and a plurality of second common electrodes disposed among the first common electrodes. The display device separately drives the first common electrodes and the second common electrodes, thus driving the electrodes in a dot inversion system.

Description

Display

An embodiment relates to a display device.

As information processing technology develops, display devices such as LCD, PDP and AMOLED are widely used.

Among such display devices, the LCD may include common electrodes and pixel electrodes facing each other, and a liquid crystal layer interposed between the two electrodes. In this case, the common electrodes and the pixel electrodes may be driven in various ways such as frame inversion, line inversion, and dot inversion.

The embodiment provides a display device having improved image quality and low power consumption.

In an exemplary embodiment, a display device includes: a plurality of gate lines extending in a first direction; A plurality of data lines crossing the gate lines and extending in a second direction; A plurality of pixel electrodes disposed in pixel regions defined by the gate lines and the data lines, respectively; A plurality of first common electrodes corresponding to some of the pixel electrodes and extending in the second direction; And a plurality of second common electrodes disposed between the first common electrodes, respectively.

According to an exemplary embodiment, a display device includes a substrate on which a plurality of pixel areas are defined; A plurality of first pixel electrodes and a plurality of second pixel electrodes disposed in the pixel regions, respectively; First common electrodes corresponding to the first pixel electrodes and electrically connected to each other; Second common electrodes corresponding to the second pixel electrodes and electrically connected to each other; And a driver configured to apply a first common voltage signal to the first common electrodes and to apply a second common voltage signal to the second common electrodes.

In one embodiment, a display device includes a substrate; First pixel electrodes arranged in a first column on the substrate; Second pixel electrodes arranged in a second column on the substrate; A first common electrode disposed to correspond to the first pixel electrodes; And a second common electrode corresponding to the second pixel electrodes and receiving a signal different from the first common electrode.

The display device according to the exemplary embodiment may drive the first common electrodes and the second common electrodes in different ways. That is, the first common voltage signal may be applied to the first common electrodes, and the second common voltage signal may be applied to the second common electrodes.

In addition, a negative voltage may be applied to the first pixel electrodes facing the first common electrodes, and a positive voltage may be applied to the second pixel electrodes facing the second common electrodes.

Thereafter, voltages applied to the first common electrodes, the second common electrodes, the first pixel electrodes, and the second pixel electrodes may be inverted or alternated.

In this manner, the display device according to the exemplary embodiment may be driven by a dot inversion method.

In addition, the display device according to the embodiment divides the common electrode into two types, and applies two types of signals to each of them, thereby implementing a dot inversion method.

Accordingly, the display device according to the embodiment can implement a dot inversion scheme without consuming much power. That is, the display device according to the embodiment can implement the improved image quality with little power.

1 is a circuit diagram illustrating a liquid crystal display according to an embodiment.

2 is a block diagram illustrating a liquid crystal display according to an embodiment.

3 is a plan view illustrating a liquid crystal display according to an embodiment.

FIG. 4 is a cross-sectional view illustrating a cross section taken along line AA ′ in FIG. 3.

FIG. 5 is a cross-sectional view illustrating a cross section taken along line BB ′ in FIG. 3.

6 is a waveform diagram illustrating common voltage signals, data signals, and gate signals.

7 is a diagram illustrating an inversion method of the liquid crystal display according to the embodiment.

In the description of the embodiments, it is described that each panel, layer, electrode, wiring or substrate, etc., is formed on or under the "on" of each panel, layer, electrode, wiring or substrate, etc. In the case, “on” and “under” include both being formed “directly” or “indirectly” through other components. In addition, the criteria for the top or bottom of each component will be described with reference to the drawings. The size of each component in the drawings may be exaggerated for description, and does not mean a size that is actually applied.

1 is a circuit diagram illustrating a liquid crystal display according to an embodiment. 2 is a block diagram illustrating a liquid crystal display according to an embodiment. 3 is a plan view illustrating a liquid crystal display according to an embodiment. FIG. 4 is a cross-sectional view illustrating a cross section taken along line AA ′ in FIG. 3. FIG. 5 is a cross-sectional view illustrating a cross section taken along line BB ′ in FIG. 3. 6 is a waveform diagram illustrating common voltage signals, data signals, and gate signals. 7 is a diagram illustrating an inversion method of the liquid crystal display according to the embodiment.

1 to 5, the liquid crystal display device includes a liquid crystal panel 10 and a driver IC 20.

The liquid crystal panel 10 includes a plurality of gate lines GL1, GL2..., A plurality of data lines DL1, DL2,..., A plurality of thin film transistors TFT, and a plurality of pixel electrodes. PE1 and PE2 and a plurality of common electrodes CE1 and CE2.

The gate lines GL1, GL2... Extend in a first direction and are arranged in parallel with each other. The gate lines GL1, GL2... Are disposed on the first transparent substrate 100. Examples of the material used for the gate lines GL1, GL2... Include aluminum, copper, tungsten, molybdenum, titanium, alloys thereof, and the like.

The data lines DL1, DL2,... Are arranged to cross the gate lines GL1, GL2. The data lines DL1, DL2,... Extend in a second direction and are arranged in parallel with each other.

A plurality of pixel regions P is formed by the gate lines GL1, GL2... And the data lines DL1, DL2,. The pixel areas P have a rectangular shape.

In addition, a gate insulating film 101 covering the gate lines GL1, GL2... Is disposed between the gate lines GL1, GL2... And the data lines DL1, DL2... Can be arranged.

The thin film transistors TFT are disposed in an area where the gate lines GL1, GL2... And the data lines DL1, DL2,... The thin film transistors TFT are turned on or turned off in accordance with gate signals GS1, GS2,..., Applied through the gate lines GL1, GL2.

Accordingly, the thin film transistors TFT selectively apply the data signals DS1 and DS2 applied through the data lines DL1, DL2,... To the pixel electrodes PE1 and PE2. do.

The pixel electrodes PE1 and PE2 are disposed in the pixel regions P. As illustrated in FIG. In more detail, the pixel electrodes PE1 and PE2 are disposed in the pixel regions P, respectively. That is, the pixel electrodes PE1 and PE2 are arranged in a matrix form.

In addition, the liquid crystal panel 10 has a passivation layer 102 covering the data line, and the pixel electrodes PE1 and PE2 are disposed on the passivation layer 102.

The first common electrodes CE1 extend in the second direction. The first common electrodes CE1 are disposed parallel to each other. The first common electrodes CE1 are disposed to face the pixel electrodes PE1. The first common electrodes CE1 are disposed under the second transparent substrate 200. In addition, the first common electrodes CE1 may be disposed in parallel with the data lines DL1, DL2,... And correspond to the data lines DL1, DL2,...

The first common electrodes CE1 are electrically connected to each other. For example, the first common electrodes CE1 may be integrally formed to receive the same signals from the driver IC 20.

The second common electrodes CE2 extend in the second direction. The second common electrodes CE2 are disposed parallel to each other. The second common electrodes CE2 are disposed to face the pixel electrodes PE2. The second common electrodes CE2 are disposed under the second transparent substrate 200.

In addition, the second common electrodes CE2 are alternately disposed with the first common electrodes CE1. For example, one second common electrode CE2 is disposed between the first common electrodes CE1.

In addition, the second common electrodes CE2 are disposed in parallel with the data lines DL1, DL2,... And the first common electrodes CE1.

The second common electrodes CE2 are electrically connected to each other. For example, the second common electrodes CE2 are integrally formed to receive the same signals from the driver IC 20.

Accordingly, the pixel electrodes PE1 and PE2 are opposed to the first pixel electrodes PE1 facing the first common electrodes CE1 and the second pixel electrodes facing the second common electrodes CE2. Divided by (PE2). For example, the first common electrodes CE1 correspond to pixel areas of the odd-numbered columns CL1, CL3,..., And the first pixel electrodes PE1 correspond to odd-numbered columns ( And the pixel areas of CL1, CL3, ...).

Similarly, the second common electrodes CE2 correspond to pixel regions of even-numbered columns CL2, CL4,..., And the second pixel electrodes PE2 correspond to even-numbered columns CL2,. Are arranged in the pixel areas of CL4, ...).

In addition, the liquid crystal panel 10 includes a liquid crystal layer 300 interposed between the first transparent substrate 100 and the second transparent substrate 200, and the common electrodes CE1 and CE2 and the liquid crystal layer 300. The color filter layer 201 is interposed between the second transparent substrate 200.

The driver IC 20 generates a signal for driving the liquid crystal panel 10 and supplies it to the liquid crystal panel 10. The driver IC 20 may be mounted on the liquid crystal panel 10. The driver IC 20 may be a chip in which a plurality of circuits for driving the liquid crystal panel 10 are integrated.

The driver IC 20 includes a latch unit 21, a display RAM 22, a source driver 23a, a gate driver 23b, a first common driver 24a and a second common driver 24b, and a register 27. ), An address counter 25, a timing controller 26, and a power supply circuit 28.

The latch unit 21 receives and latches data for displaying an image such as RGB data from an interface. In addition, the latch unit 21 transfers the latched data to the display RAM 22.

The display RAM 22 stores the latched data, loads the stored data, and transmits the stored data to the source driver 23a.

The source driver 23a receives the data from the display RAM 22. In addition, the source driver 23a receives the timing signal from the timing controller 26, generates the data signals DS1 and DS2, and supplies the data signals DS1 and DS2 to the liquid crystal panel 10. In more detail, the source driver supplies the data signals DS1 and DS2 to the data lines DL1, DL2,...

The gate driver 23b receives the timing signal from the timing controller 26, generates the gate signals GS1, GS2,..., And supplies the gate signals to the liquid crystal panel 10. In more detail, the gate driver 23b supplies the gate signals GS1, GS2,... To the gate lines GL1, GL2.

The first common driver 24a receives the timing signal from the timing controller 26, generates the first common voltage signal CS1, and supplies the first common voltage signal CS1 to the liquid crystal panel 10. In more detail, the first common driver applies the first common voltage signal CS1 to the first common electrodes CE1.

The second common driver 24b receives the timing signal from the timing controller, generates the second common voltage signal CS2, and supplies the second common voltage signal CS2 to the liquid crystal panel 10. In more detail, the second common driver 24b supplies the second common voltage signal CS2 to the second common electrodes CE2.

The register 27 receives command signals DE, HSYNC, and VSYNC from the interface to control the timing controller 26 and the address counter 25.

The register 27 may include a data register capable of storing and loading the command signals DE, HSYNC, and VSYNC, and a control register controlling the timing controller 26 and the address counter 25. have.

The timing controller 26 converts a clock signal generated as an internal reference to generate timing signals. In addition, the timing controller 26 transmits the timing signals to the display RAM 22 and the

drivers

23a, 23b, 24a, and 24b.

In this case, the display RAM 22 stores and loads the data by the timing signal.

The power supply circuit 28 receives an external voltage Vcc from the outside, and generates an internal voltage used in the driver IC 20. In more detail, the power supply circuit 28 includes the latch unit 21, the display RAM 22, the

drivers

23a, 23b, 24a, 24b, the register 27, the address counter 25, and the like. A voltage for driving the timing controller 26 is generated.

The power supply circuit 28 also receives a ground voltage GND from the outside.

As shown in FIG. 6, the first common voltage signal CS1 and the second common voltage signal CS2 have reverse phases. For example, when the first common driver 24a applies the high voltage VH to the first common electrodes CE1, the second common driver 24b is the second common electrodes CE2. ) Applies a low voltage (VL). In addition, when the first common driver 24a applies the low voltage VL to the first common electrodes CE1, the second common driver 24b is applied to the second common electrodes CE2. The high voltage VH is applied.

That is, the first common voltage signal CS1 and the second common voltage signal CS2 are signals in which the high voltage VH and the low voltage VL are alternated with each other.

The first common driver 24a and the second common driver 24b may be configured such that the first common electrodes CE1 and the second common electrodes CE2 have different voltage levels. The voltages applied to the first common electrodes CE1 and the second common electrodes CE2 are continuously alternated.

That is, the first common driver 24a may have a low voltage VL and a high voltage VH (for example, VL, VH, VL, VH, ...) in order to the first common electrodes CE1. Are applied alternately.

In addition, the second common driver 24b may have a high voltage VH and a low voltage VL (for example, VH, VL, VH, VL, ...) in order to the second common electrodes CE2. Are applied alternately.

For example, the driver IC 20 first applies a low voltage VL to the first common electrodes CE1 and applies a high voltage VH to the second common electrodes CE2. . Thereafter, the driver IC 20 applies a high voltage VH to the first common electrodes CE1 and a low voltage VL to the second common electrodes CE2.

The data driver 23a applies first data signals DS1 to the first pixel electrodes PE1 through the odd-numbered data lines DL1, DL3,... Similarly, the data driver 23a applies the second data signals DS2 to the second pixel electrodes PE2 through the even-numbered data lines DL2, DL4,...

In this case, the gate driver 23b applies gate signals GS1, GS2,... To the gate lines GL1, GL2..., Respectively to turn on the thin film transistors TFT that are turned on. Decide That is, the gate driver 23b determines a line on which an image is displayed.

6 and 7, a turn-on signal is applied to the thin film transistors TFT of the first line LN1 through the first gate line GL1. At the same time, the first data signals DS1 are applied to the odd data lines DL1, DL3,..., And the second data on even-numbered data lines DL2, DL4,... Signals DS2 are applied.

Accordingly, a positive polarity voltage is applied to the first pixel electrodes PE1 of the first line LN1 and a low voltage VL is applied to the first common electrodes CE1. In addition, a negative voltage is applied to the second pixel electrodes PE2 of the first line LN1 and a high voltage VH is applied to the second common electrodes CE2.

Accordingly, an image is displayed in the pixel areas of the first line LN1.

Thereafter, a turn-on signal is applied to the thin film transistors TFT of the second line LN2 through the second gate line GL2. At the same time, the first data signals DS1 are applied to the odd data lines DL1, DL3,..., And the second data signals are applied to even-numbered data lines DL2, DL4,... DS2 is applied.

Accordingly, a negative voltage is applied to the first pixel electrodes PE1 of the second line LN2, and a high voltage VH is applied to the first common electrodes CE1. In addition, a positive polarity voltage is applied to the second pixel electrodes PE2 of the second line LN2, and a low voltage VL is applied to the second common electrodes CE2.

Accordingly, an image is displayed in the pixel areas of the second line LN2.

In this manner, an image is displayed in the pixel areas of each line LN1, LN2,...

In addition, as illustrated in FIG. 7, voltages of different polarities are applied to the pixel electrodes PE1 and PE2 included in the pixel areas adjacent to each other based on one frame. That is, a voltage whose polarity is inverted in a dot unit is applied to the pixel electrodes PE1 and PE2.

As described above, the liquid crystal display according to the embodiment may be driven by a dot inversion method, and an improved screen may be realized.

In addition, the liquid crystal display according to the exemplary embodiment may implement dot inversion by applying only two types of signals to the common electrodes CE1 and CE2, and thus may realize an improved image quality without much power consumption.

Also, in the present exemplary embodiment, the liquid crystal display device in which the pixel electrodes and the common electrodes are disposed on different substrates, for example, a TN mode liquid crystal display device, has been described, but the present invention is not limited thereto.

That is, even in a structure in which all of the common electrodes are disposed on the first transparent substrate, the structure and driving method according to the present embodiment may be applied.

For example, the common electrodes and the pixel electrodes may be disposed in respective pixel regions of the first transparent substrate, and the common electrodes of the same column may be electrically connected to each other. In this case, the common electrodes of the odd-numbered column and the common electrodes of the even-numbered column may be driven separately as in the driving method described above.

Although the above description has been made based on the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains may not have been exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

The embodiment applies to the field of display.

Claims

A plurality of gate lines extending in a first direction;

A plurality of data lines crossing the gate lines and extending in a second direction;

A plurality of pixel electrodes disposed in pixel regions defined by the gate lines and the data lines, respectively;

A plurality of first common electrodes corresponding to some of the pixel electrodes and extending in the second direction; And

And a plurality of second common electrodes disposed between the first common electrodes, respectively.
The method of claim 1, wherein the first common electrodes and the second common electrodes are alternately arranged side by side,

The first common electrodes are electrically connected to each other,

The second common electrode is electrically connected to each other.
2. The driving unit of claim 1, wherein a first common voltage signal is applied to the first common electrodes and a second common voltage signal having a reverse phase with respect to the first common voltage signal is applied to the second common electrodes. Display device comprising a.
The method of claim 3, wherein the first common voltage signal is a signal that is alternately applied to a first voltage and a second voltage to the first common electrodes, and

And the second common voltage signal is a signal in which the second voltage and the first voltage are alternately applied to the second common electrodes.
The method of claim 3, wherein the driving unit

A first common driver generating the first common voltage signal; And

And a second common driver to generate the second common voltage signal.
The semiconductor device of claim 1, further comprising: a first substrate on which the gate lines, the data lines and the pixel electrodes are disposed; And

And a second substrate on which the first common electrodes and the second common electrodes are disposed.
A substrate in which a plurality of pixel regions are defined;

A plurality of first pixel electrodes and a plurality of second pixel electrodes disposed in the pixel regions, respectively;

First common electrodes corresponding to the first pixel electrodes and electrically connected to each other;

Second common electrodes corresponding to the second pixel electrodes and electrically connected to each other; And

And a driving unit configured to apply a first common voltage signal to the first common electrodes and to apply a second common voltage signal to the second common electrodes.
The display device of claim 7, wherein the first common voltage signal has a phase different from that of the second common voltage signal.
The display device of claim 7, wherein the driver applies a voltage having a first polarity to the first pixel electrodes and a voltage having a second polarity different from the first polarity to the second pixel electrodes.
The display device of claim 9, wherein the driver inverts the voltage of the first polarity and the voltage of the second polarity in units of dots.
The method of claim 7, wherein the driving unit

A first common driver generating the first common voltage signal; And

And a second common driver to generate the second common voltage signal.
The display device of claim 7, wherein the first common electrodes and the second common electrodes are disposed on the substrate.
Board;

First pixel electrodes arranged in a first column on the substrate;

Second pixel electrodes arranged in a second column on the substrate;

A first common electrode disposed to correspond to the first pixel electrodes; And

And a second common electrode corresponding to the second pixel electrodes and receiving a signal different from the first common electrode.
The method of claim 13, wherein after applying a low voltage to the first common electrode and applying a high voltage to the second common electrode, the high voltage is applied to the first common electrode and the second common electrode. And a driving unit to apply the low voltage.
The method of claim 14, wherein the driving unit applies the low voltage to the first common electrode and the high voltage to the second common electrode.

Applying a positive data signal to one of the first pixel electrodes, applying a negative data signal to one of the second pixel electrodes,

When the high voltage is applied to the first common electrode and the low voltage is applied to the second common electrode,

And a negative data signal applied to the other one of the first pixel electrodes, and a positive data signal applied to the other one of the second pixel electrodes.