WO2010070866A1

WO2010070866A1 - Display panel driving apparatus and display apparatus

Info

Publication number: WO2010070866A1
Application number: PCT/JP2009/006847
Authority: WO
Inventors: 永野哲; 有澤大治郎
Original assignee: パナソニック株式会社
Priority date: 2008-12-19
Filing date: 2009-12-14
Publication date: 2010-06-24
Also published as: JP2010145803A

Abstract

The number of output signals can be increased at a low cost. A display panel driving apparatus, which is configured to generate a plurality of output signals, comprises: a shift register that has a plurality of cells each adapted to store a one-bit value and that causes the value of an input signal to be stored into one of the cells and then shifts the stored value among the cells one by one; and a plurality of selectors that are associated with at least some respective ones of the cells of the shift register. The number of the cells of the shift register is smaller than the number of the output signals. The shift register shifts the value of the input signal in a first direction and thereafter shifts the value of the input signal in a second direction different from the first direction. In response to a change of shift direction of the shift register, each selector outputs a signal representative of the value of the respective associated cell as an output signal different from the corresponding one outputted before the change of shift direction.

Description

Display panel driving device and display device

The present disclosure relates to a display panel driving device that drives a display panel represented by a plasma display panel or a liquid crystal display panel.

A display panel in which a plurality of scanning lines and a plurality of signal lines are arranged so as to cross each other is known. Such display panels include flat panel displays (FPD: Flat Panel Display) such as plasma display panels (PDP: Plasma Display Panel), liquid crystal display (LCD: Liquid Crystal Display) panels, and electroluminescent (EL) panels. It has been known.

With an increase in the number of pixels of a display panel, a device that drives the display panel is required to increase the number of output signals that drive the display panel. However, as the number of output signals increases, the size of the shift register used and the number of control circuits for each output signal increase. For this reason, it is difficult to increase the number of output signals per se, or the scale of the driving device increases, resulting in an increase in cost. Patent Document 1 describes an example of a panel driving circuit in which the number of flip-flops constituting a shift register is reduced.

JP 2002-132203 A

However, according to Patent Document 1, it is difficult to make the number of flip-flops less than half the number of output signals. Further, when a circuit for preventing a through current of the output circuit is provided, a circuit for preventing such a through current is required for each output signal.

The display panel driving device according to the present invention makes it possible to increase the number of output signals for driving the display panel at a low cost.

A display panel driving apparatus according to an exemplary embodiment of the present invention is a display panel driving apparatus that generates a plurality of output signals for driving a display panel, each including a plurality of cells each storing a 1-bit value. A shift register that stores the value of the input signal in one of the plurality of cells and sequentially shifts the stored value between the plurality of cells; and at least a part of the plurality of cells of the shift register And a plurality of selectors respectively corresponding to. The number of the plurality of cells of the shift register is less than the number of the plurality of output signals, and the shift register shifts the value of the input signal in a first direction, and then the first direction Shift in a different second direction. The plurality of selectors correspond to two or more output signals of the plurality of output signals so that they do not overlap each other, and signals indicating the values of the corresponding cells are included in the corresponding plurality of output signals. And outputting a signal indicating the value of the corresponding cell different from that before the change of the shift direction among the plurality of corresponding output signals in accordance with the change of the shift direction of the shift register. Output as a signal.

According to this, the number of shift register cells can be significantly smaller than the number of output signals. For this reason, cost reduction of a display panel drive device can be achieved.

A display device according to an exemplary embodiment of the present invention includes a display panel and a display panel driving device that generates a plurality of output signals for driving the display panel. The display panel driving device includes a plurality of cells each storing a 1-bit value, stores an input signal value in one of the plurality of cells, and stores the stored value between the plurality of cells. And a plurality of selectors respectively corresponding to at least some of the plurality of cells of the shift register. The number of the plurality of cells of the shift register is less than the number of the plurality of output signals, and the shift register shifts the value of the input signal in a first direction, and then the first direction Shift in a different second direction. The plurality of selectors correspond to two or more output signals of the plurality of output signals so that they do not overlap each other, and signals indicating the values of the corresponding cells are included in the corresponding plurality of output signals. And outputting a signal indicating the value of the corresponding cell different from that before the change of the shift direction among the plurality of corresponding output signals in accordance with the change of the shift direction of the shift register. Output as a signal.

According to the embodiment of the present invention, it is possible to reduce the scale of the shift register in the display panel driving device. Therefore, the display panel driving device can be realized at low cost.

FIG. 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of the scan driver of FIG. FIG. 3 is a block diagram illustrating a configuration example of the shift register of FIG. FIG. 4 is a timing chart showing signals in the scan driver of FIG. FIG. 5 is a conceptual diagram showing the relationship between pulse movement and generated output signals in the shift register of FIG. FIG. 6 is a block diagram showing a configuration of a modification of the shift register of FIG. FIG. 7 is a timing chart showing signals in the scan driver when the shift register of FIG. 6 is provided. FIG. 8 is a conceptual diagram showing the relationship between pulse movement and generated output signals in the shift register of FIG. FIG. 9 is a block diagram showing a configuration of a modified example of the scan driver of FIG. FIG. 10 is a block diagram showing a configuration of another modified example of the scan driver of FIG. FIG. 11 is a block diagram illustrating a configuration example of the shift register of FIG. FIG. 12 is a timing chart showing signals in the scan driver of FIG. FIG. 13 is a conceptual diagram showing the relationship between pulse movement and generated output signals in the shift register of FIG. FIG. 14 is a block diagram showing a configuration of a modification of the shift register of FIG. FIG. 15 is a timing chart showing signals in the scan driver when the shift register of FIG. 14 is provided. FIG. 16 is a conceptual diagram showing the relationship between the pulse movement and the generated output signal in the shift register of FIG. FIG. 17 is a block diagram showing a configuration of a modified example of the scan driver of FIG. FIG. 18 is a block diagram showing a configuration of another modification of the shift register of FIG. FIG. 19 is a timing chart showing signals in the scan driver when the shift register of FIG. 18 is provided. FIG. 20 is a conceptual diagram showing the relationship between pulse movement and generated output signals in the shift register of FIG. FIG. 21 is a block diagram showing a configuration of a modification of the shift register of FIG. FIG. 22 is a timing chart showing signals in the scan driver when the shift register of FIG. 21 is provided. FIG. 23 is a conceptual diagram showing the relationship between the pulse movement and the generated output signal in the shift register of FIG. FIG. 24 is a circuit diagram showing an example of one of the output circuits of FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the components indicated by the same reference numerals in the last two digits correspond to each other and are the same or similar components. Solid lines between functional blocks in the drawing indicate electrical connections.

FIG. 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention. The display device of FIG. 1 includes a plurality of scan drivers 100 as a display panel driving device, a plurality of data line drivers 192, and a display panel 194 driven by them. The display panel 194 is typically a plasma display panel, but may be another type of flat panel display such as a liquid crystal display panel or an electroluminescence panel.

Each scan driver 100 generates output signals OUT1,..., OUT2n for driving the display panel 194, and drives a plurality of scanning lines running in the horizontal direction in FIG. 1 by the output signals OUT1 to OUT2n (n is 3 or more) Integer). Each scanning line is connected to a pixel in a corresponding row of the display panel 194 (a column of pixels arranged side by side). Each data line driver 192 drives a plurality of data lines running in the vertical direction in FIG. 1 by a plurality of output signals. The scan driver 100 outputs the pulses as the output signals OUT1,..., OUT2n one by one in order, and notifies the next-stage scan driver 100 by the signal OUT that the pulse of the output signal OUT2n has been output. The scan driver 100 also performs the same operation, and further notifies the next-stage scan driver 100.

FIG. 2 is a block diagram illustrating a configuration example of the scan driver 100 of FIG. The scan driver 100 includes a shift register 210, output control units 222_1, 222_2, ..., 222_n-1, 222_n, 222_n + 1, selectors 224_1, 224_2, ..., 224_n-1, output circuits 226_1, 226_2, ..., 226_n-. 1, 226 — n, 226 — n + 1, 226 — n + 2,... 226 — 2n−1, 226 — 2n, and a shift control unit 228. The shift register 210 has

registers

212, 214, and 216. The register 214 includes n-2 cells 242_2,... 242_n-1.

The shift register 210 stores a value of n + 1 bits less than 2n that is the number of the output signals OUT1 to OUT2n according to the clock CLK, and shifts it to the right or left. The direction of the shift is controlled by a shift control signal SL output from the shift control unit 228.

FIG. 3 is a block diagram illustrating a configuration example of the shift register 210 in FIG. Register 212 includes cell 232 and register 216 includes

cells

252 and 254. The cell 232 is a composite cell including a selector 337 and a D flip-flop 338.

The selector 337 selects one of the terminals A and B in accordance with the shift control signal SL output from the shift control unit 228, and outputs an input signal to the selected terminal from the terminal Y. In the following, as an example, the selector 337 selects the terminal A when the shift control signal SL is “L”, and selects the terminal B when the shift control signal SL is “H”. D flip-flop 338 in accordance with the rising edge of the clock CLK, and outputs a signal input to the terminal D from the terminal _{Q 1.} Other cells in this specification are configured in the same manner as the cell 232.

The n + 1 cells 232, 242_2 to 242_n-1, 252 and 254 of the shift register 210 each store a 1-bit value. Although not shown in FIG. 3, signals output from the terminals Q ₁ , Q ₂ ,..., Q _n−1 , Q _n , Q _{n + 1} of the cells of the shift register 210 are output control units 222_1, 222_2,..., 222_n−1, 222_n, and 222_n + 1, respectively.

FIG. 4 is a timing chart showing signals in the scan driver 100 of FIG. The operation of the scan driver 100 will be described with reference to FIGS. The shift control unit 228 outputs “H” as the shift control signal SL when causing the shift register 210 to perform a right shift (right shift), and when causing the shift register 210 to perform a left shift (left shift). “L” is output as the shift control signal SL.

In FIG. 4, first, the shift control unit 228 sets the shift control signal SL to “H”. Each cell in FIG. 3 selects a signal input to its terminal B. Cell 232 in accordance with the rising edge of the clock CLK, select and store the value of the input signal IN, and outputs a signal indicating the stored value from the terminal _{Q 1} to the cell 242_2. When a pulse (active signal) is input as the input signal IN as shown in FIG. 4, the cell 232 outputs a pulse whose width is equal to the period of the clock CLK.

Cell 242_2 in accordance with the rising edge of the clock CLK, and stores the value of the signal from the cell 232, and outputs a signal indicating the stored value from the terminal Q ₂ to the next cell to the right. Signal output from the terminal Q ₂ is a signal obtained by delaying the signal outputted from the terminal Q ₁ by the period of the clock CLK. Similarly, every time the clock CLK rises, the value indicated by the input signal IN is sequentially shifted rightward and reaches the cell 242_n−1 as shown in FIG.

The cell 252 stores the value of the signal output from the cell 242_n−1 in accordance with the rising edge of the clock CLK, and outputs a signal indicating the stored value from the terminal Q _n to the cell 254. The cell 254 stores the value of the signal output from the cell 252 in accordance with the rising edge of the clock CLK, and outputs a signal indicating the stored value from the terminal Q _{n + 1} to the cell 242_n−1 and the shift control unit 228.

When the signal output from the terminal Q _{n + 1} becomes “H”, the shift control unit 228 sets the shift control signal SL to “L”. Then, each cell in FIG. 3 selects a signal input to each terminal A. The cell 242_n−1 stores the value of the signal output from the cell 254 in accordance with the rising edge of the clock CLK, and outputs a signal indicating the stored value from the terminal Q _n−1 to the next cell on the left side. Similarly, every time the clock CLK rises, the value indicated by the signal output from the cell 254 is sequentially shifted leftward and reaches the cell 242_2 as shown in FIG.

Cell 232 in accordance with the rising edge of the clock CLK, and stores the value of the signal outputted from the cell 242_2, and outputs a signal indicating the stored value from the terminal Q ₁ to the shift control unit 228. When the signal output from the terminal Q ₁ is becomes "H", the shift control unit 228 outputs a signal OUT pulse (active signal) to the next-stage scan driver, to a shift control signal SL "H".

In this manner, when the shift control signal SL is “H”, the shift register 210 performs a right shift of n bits from the cell 232 having the terminal Q ₁ to the cell 254 having the terminal Q _{n + 1} , and the shift control signal SL When SL is “L”, a left shift of n−1 bits from the cell 254 to the cell 232 is performed. Further, the selectors 224_1 to 224_n−1 output the outputs of the corresponding output control units as different output signals each time the shift direction is changed.

Although the case where the shift direction is changed when the pulse reaches the cell 254 having the terminal Q _{n + 1} and the cell 232 having the terminal Q ₁ has been described, the shift direction when the pulse reaches another cell is described. May be changed.

2 correspond to the cells 232, 242_2,..., 242_n−1, 252 and 254 of the shift register 210, respectively. Each of the output control units 222_1 to 222_n + 1 generates two signals having a predetermined time difference based on a signal indicating the value of the corresponding cell (one of signals output from the terminals Q ₁ to Q _{n + 1} ). Output. For example, the output control section 222_1 based on the signal output from the terminal Q _1, and outputs the this signal, a signal which the rising edge of the signal delayed a predetermined time.

The selectors 224_1, 224_2, ..., 224_n-1 correspond to the cells 232, 242_2, ..., 242_n-1 of the shift register 210, respectively. The selectors 224_1, 224_2,..., 224_n−1 correspond to the output signals OUT1, OUT2,..., OUTn−1, respectively, and correspond to the output signals OUT2n, OUT2n−1,. Generally speaking, the selectors 224_1 to 224_n−1 correspond to two output signals of the output signals OUT1 to OUTn−1 and OUTn + 2 to OUT2n so as not to overlap each other. The number of cells in the shift register 210 is less than the number of output signals. The output circuits 226_1, 226_2, ..., 226_n-1, 226_n, 226_n + 1, 226_n + 2, ..., 226_2n-1, 226_2n output signals OUT1, OUT2, ..., OUTn-1, OUTn, OUTn + 1, OUTn + 2,. Output.

When the shift register 210 performs a right shift, each of the selectors 224_1 to 224_n-1 uses two signals generated by the corresponding output control unit in FIG. 2 as two output signals corresponding to the selector. As one of these, it outputs via the output circuit corresponding to the output signal. When the shift register 210 performs a left shift, each of the selectors 224_1 to 224_n−1 uses two signals generated by the corresponding output control unit in FIG. 2 as two output signals corresponding to the selector. As an output signal different from that in the right shift, the output signal is output via an output circuit corresponding to the output signal. That is, according to the change in the shift direction of the shift register 210, the selectors 224_1 to 224_n-1 output different output signals from those before the change in the shift direction. The shift direction is notified from the shift control unit 228 to each selector. The same applies to other examples below.

FIG. 24 is a circuit diagram showing an example of one of the output circuits of FIG. The output circuit 226_1 in FIG. 24 includes a PMOS transistor 2402 and an NMOS transistor 2404. The source of the PMOS transistor 2402 is supplied with the power supply voltage VDDH for driving the display panel higher than the power supply voltage VDD for the circuit, and the source of the NMOS transistor 2404 is supplied with the floating ground voltage FGND. Depending on the type of the display panel to be driven, the power supply voltage VDD may be applied instead of the power supply voltage VDDH, or the ground voltage GND may be applied instead of the floating ground voltage FGND.

The drain of the PMOS transistor 2402 is connected to the drain of the NMOS transistor 2404, and an output signal OUT1 is output from this node. Of the two signals generated by the output control unit 222_1, the signal having the earlier rising edge timing is input to the gate of the PMOS transistor 2402. The gate of the NMOS transistor 2404 is generated by the output control unit 222_1. Of the two signals, the signal having the later rising edge timing is input.

When the signal at the terminal _{Q 1} is becomes "H", PMOS transistor 2402 First is turned off, then, NMOS transistor 2404 is turned on. Accordingly, since the two transistors are not turned on at the same time, the generation of a through current can be prevented. As shown in FIG. 4, the signal at the terminal _{Q 1} is corresponding to become "H", the output signal OUT1 becomes "L".

Although the case where the output circuit 226_1 in FIG. 24 includes the PMOS transistor 2402 and the NMOS transistor 2404 has been described, the output circuit 226_1 may include an NMOS transistor instead of the PMOS transistor 2402. The output circuit 226_1 may have another configuration as long as the output circuit 226_1 generates and outputs a signal having a voltage necessary for driving the scan line of the display panel.

As described above, the output circuit 226_1 generates and outputs a signal of a voltage necessary for driving the display panel 194 in accordance with the output signal of the corresponding selector 224_1. Since the other output circuits are configured in the same manner, description thereof will be omitted. The scan driver 100 generates output signals OUT1 to OUT2n as shown in FIG. 4, and drives the scanning lines of the display panel 194.

FIG. 5 is a conceptual diagram showing the relationship between pulse movement and generated output signals in the shift register 210 of FIG. The pulse of the input signal IN input to the cell 232 is right-shifted and sequentially output from the terminals Q ₁ , Q ₂ ,..., Q _{n + 1} , and as a result, the pulses are sequentially output as output signals OUT 1, OUT 2,. Is done. Thereafter, the pulse at the terminal Q _{n + 1} is shifted to the left and output in order from the terminals Q _n−1 ,..., Q ₂ , Q ₁ , and as a result, the pulses are output in order as output signals OUTn + 2,. The Further, a pulse is output to the next-stage scan driver as the output signal OUT.

FIG. 6 is a block diagram showing a configuration of a modification of the shift register 210 of FIG. The scan driver 100 may include the shift register 610 in FIG. 6 instead of the shift register 210 in FIG. The shift register 610 in FIG. 6 is different from the shift register 210 in FIG. 3 in that a register 614 is provided instead of the register 214. A shift control unit 628 is used for controlling the shift register 610. The register 614 includes a cell 242_2. The shift register 610 in FIG. 6 corresponds to the case of n = 3 in FIG.

FIG. 7 is a timing chart showing signals in the scan driver 100 when the shift register 610 of FIG. 6 is provided. The shift register 610 performs a right shift from the cell 232 having the terminal Q ₁ to the cell 254 having the terminal Q ₄ in accordance with the shift control signal SL from the shift control unit 628, similarly to the shift register 210 of FIG. The left shift from the cell 254 to the cell 232 is performed.

Thereafter, the shift register 610 performs a right shift from the cell 232 having the terminal Q ₁ to the cell 254 having the terminal Q ₄ in accordance with the shift control signal SL from the shift control unit 628, and then from the cell 254 to the cell 232. Shift left. Then, the scan driver 100 generates the output signals OUT1 to OUT11 as shown in FIG. The selector 224_2 outputs the output of the corresponding output control unit as a different output signal each time the shift direction is changed. The selector 224_1 outputs the output of the corresponding output control unit as a different output signal every time the shift direction becomes a predetermined direction. When the signal for the output signal OUT11 is generated by the shift register 610, the shift control unit 628 outputs a pulse as the signal OUT to the next-stage scan driver.

FIG. 8 is a conceptual diagram showing the relationship between the movement of pulses and the generated output signal in the shift register 610 of FIG. The pulse of the input signal IN input to the cell 232 is right-shifted and sequentially output from the terminals Q ₁ , Q ₂ ,..., Q ₄ , and as a result, the pulses are sequentially output as the output signals OUT 1, OUT 2,. Is done. Thereafter, a pulse of the terminal _{Q 4} are output sequentially from the terminal _Q 2, _{Q 1} is left-shifted, as a result, pulses are sequentially outputted as an output signal OUT5, OUT6.

Further, the pulse is further shifted to the right and sequentially output from the terminals Q ₂ to Q _4. As a result, the pulses are sequentially output as the output signals OUT 7 to OUT 9. Thereafter, a pulse of the terminal _{Q 4} are output sequentially from the terminal _Q 2, _{Q 1} is left-shifted, as a result, pulses are sequentially outputted as an output signal OUT10, OUT11. Further, a pulse is output to the next-stage scan driver as the output signal OUT.

Thus, since the shift register 610 further reciprocates after reciprocating the pulse, a large number of output signals can be generated while suppressing the circuit scale of the shift register 610. Although the case where the pulse is reciprocated twice has been described here, the pulse may be reciprocated many more times. Then, a very large number of output signals can be generated while suppressing the circuit scale of the shift register 610.

FIG. 9 is a block diagram showing a configuration of a modified example of the scan driver 100 of FIG. The scan driver 900 of FIG. 9 is substantially the same as the scan driver 100 of FIG. 2 except that the output control units 222_1 to 222_n + 1 are not included. The selectors 224_1 to 224_n−1 output a signal indicating the value of the corresponding cell as a corresponding output signal via an output circuit corresponding to the output signal. According to the scan driver 900, the circuit can be simplified.

FIG. 10 is a block diagram showing a configuration of another modified example of the scan driver 100 of FIG. The scan driver 1000 of FIG. 10 includes a shift register 1010, output control units 1022_1, 1022_2,..., 1022_n-1, 1022_n, 1022_n + 1, 1022_2n, selectors 1024_1, 1024_2,. There are 2x (x is an integer of 3 or more) output circuits 1026 and a shift control unit 1028. The shift register 1010 includes

registers

1012, 214, and 216.

The shift register 1010 stores a value of n + 2 bits smaller than 2x that is the number of output signals OUT1 to OUT2x according to the clock CLK, and shifts it to the right or left. The direction of the shift is controlled by a shift control signal SL output from the shift control unit 1028.

FIG. 11 is a block diagram illustrating a configuration example of the shift register 1010 in FIG. The register 1012 includes

cells

1132 and 1134. The

cells

1132 and 1134 are configured in the same manner as the cell 232.

The n + 2

cells

1132, 1134, 242_2 to 242_n-1, 252 and 254 of the shift register 1010 each store a 1-bit value. Although not shown in FIG. 11, the signals output from the terminals Q ₁ , Q ₂ ,..., Q _n−1 , Q _n , Q _{n + 1} , Q _2n of the cells of the shift register 1010 are output control of FIG. , 1022 — n−1, 1022 — n, 1022 — n + 1, 1022 — 2n, respectively.

FIG. 12 is a timing chart showing signals in the scan driver 1000 of FIG. The operation of the scan driver 1000 will be described with reference to FIGS. The shift control unit 1028 outputs a shift control signal SL similarly to the shift control unit 228.

In FIG. 12, first, the shift control unit 1028 sets the shift control signal SL to “H”. Each cell in FIG. 11 selects a signal input to its terminal B. Cell 1132, according to the rising edge of the clock CLK, select and store the value of the input signal IN, and outputs a signal indicating the stored value from the terminal _{Q 1} to the cell 242_2. Thereafter, as in the case of FIGS. 3 and 4, the pulse reaches the terminal Q _{n + 1} of the cell 254.

When the signal output from the terminal Q _{n + 1} becomes “H”, the shift control unit 1028 sets the shift control signal SL to “L”. Then, each cell in FIG. 11 selects a signal input to each terminal A. Thereafter, 3, as in the case of FIG. 4, a pulse reaches the terminal _{Q 2} of the cell 242_2.

Cell 1134, according to the rising edge of the clock CLK, and stores the value of the signal outputted from the cell 242_2, and outputs a signal indicating the stored value from the terminal _{Q 2n} in cell 1132. Cell 1132, according to the rising edge of the clock CLK, and stores the value of the signal output from the cell 1134, and outputs a signal indicating the stored value from the terminal _{Q 1} to the cell 242_2 and the shift control unit 1028.

After that, the shift register 1010 performs a right shift of n bits from the cell 1132 to the cell 254 in accordance with the shift control signal SL from the shift control unit 1028, and then from the cell 254 to the cell 1132 via the cell 1134. Shift left by n bits. Thereafter, if necessary, a right shift for n bits and a left shift for n bits are repeated alternately. Then, the scan driver 1000 generates the output signals OUT1 to OUT2x as shown in FIG. That is, each of the selectors 1024_1 to 1024_n + 1, 1024_2n sequentially selects one of the corresponding output signals every time the shift direction is changed, and outputs the corresponding output control unit as the selected output signal. Output. When the signal for the output signal OUT2x is generated by the shift register 1010, the shift control unit 1028 outputs a pulse as the signal OUT to the next-stage scan driver.

FIG. 13 is a conceptual diagram showing the relationship between pulse movement and generated output signals in the shift register 1010 of FIG. The pulse of the input signal IN input to the cell 1132 is shifted to the right and sequentially output from the terminals Q ₁ , Q ₂ ,..., Q _{n + 1} , and as a result, the pulses are output in order as output signals OUT 1, OUT 2,. Is done. Thereafter, the pulse at the terminal Q _{n + 1} is shifted to the left and sequentially output from the terminals Q _n−1 ,..., Q ₂ , Q _2n , Q ₁ , and as a result, as output signals OUTn−1,. Pulses are output in order. Thereafter, the right shift and the left shift are repeated in the same manner. Finally, a pulse is output to the next-stage scan driver as the output signal OUT.

FIG. 14 is a block diagram showing a configuration of a modification of the shift register 1010 of FIG. The scan driver 1000 may include the shift register 1410 in FIG. 14 instead of the shift register 1010 in FIG. A shift register 1410 in FIG. 14 is different from the shift register 1010 in FIG. 11 in that a register 614 is provided instead of the register 214. A shift control unit 1428 is used to control the shift register 1410. The shift register 1410 in FIG. 14 corresponds to the case where n = 3 in FIG.

FIG. 15 is a timing chart showing signals in the scan driver 1000 when the shift register 1410 of FIG. 14 is provided. Similarly to the shift register 1010 of FIG. 11, the shift register 1410 performs a right shift from the cell 1132 having the terminal Q ₁ to the cell 254 having the terminal Q ₄ in accordance with the shift control signal SL from the shift control unit 1428. , Shift left from cell 254 to cell 1132.

Thereafter, the shift register 1410 performs a right shift from the cell 1132 having the terminal Q ₁ to the cell 254 having the terminal Q ₄ in accordance with the shift control signal SL from the shift control unit 1428, and then from the cell 254 to the cell 1134. Shift left. Then, the scan driver 1000 generates the output signals OUT1 to OUT12 as shown in FIG. The selector 1024_2 outputs the output of the corresponding output control unit as a different output signal each time the shift direction is changed. The selectors 1024_1, 1024_3, 1024_4, and 1024_6 output the outputs of the corresponding output control units as different output signals each time the shift direction becomes a predetermined direction. When the signal for the output signal OUT12 is generated by the shift register 1410, the shift control unit 1428 outputs a pulse as the signal OUT to the next-stage scan driver.

FIG. 16 is a conceptual diagram showing the relationship between pulse movement and generated output signals in the shift register 1410 of FIG. The pulse of the input signal IN input to the cell 1132 is right-shifted and sequentially output from the terminals Q ₁ , Q ₂ ,..., Q ₄ , and as a result, the pulses are output in order as output signals OUT 1, OUT 2,. Is done. Thereafter, a pulse of the terminal _{Q 4} are outputted from the order terminal _{_Q} _2, _Q _6, _Q ₁ is left-shifted, as a result, pulses are sequentially outputted as an output signal OUT5 ~ OUT7.

Further, the pulse is further shifted to the right and sequentially output from the terminals Q ₂ to Q _4. As a result, the pulses are sequentially output as output signals OUT 8 to OUT 10. Thereafter, a pulse of the terminal _{Q 4} are outputted from the order terminal _Q 2, _{Q 6} is left-shifted, as a result, pulses are sequentially outputted as an output signal OUT11, OUT12. Further, a pulse is output to the next-stage scan driver as the output signal OUT.

Thus, since the shift register 1410 further reciprocates after reciprocating the pulse, many output signals can be generated while suppressing the circuit scale of the shift register 1410. Although the case where the pulse is reciprocated twice has been described here, the pulse may be reciprocated many more times.

FIG. 17 is a block diagram showing a configuration of a modified example of the scan driver 1000 of FIG. The scan driver 1700 in FIG. 17 is substantially the same as the scan driver 1000 in FIG. 10 except that the output control units 1022_1 to 1022_n + 1 and 1022_2n are not included. The selectors 1024_1 to 1024_n + 1, 1022_2n output a signal indicating the value of the corresponding cell as a corresponding output signal via an output circuit corresponding to the output signal. According to the scan driver 1700, the circuit can be simplified.

FIG. 18 is a block diagram showing a configuration of another modification of the shift register 1010 of FIG. The scan driver 1000 may include the shift register 1810 in FIG. 18 instead of the shift register 1010 in FIG. The shift register 1810 in FIG. 18 is different from the shift register 1010 in FIG. 11 in that a register 212 is provided instead of the register 1012, and a register 1816 is provided instead of the register 216. The register 1816 has a cell 252. A shift control unit 1828 is used to control the shift register 1810. The output control unit, the selector, and the output circuit that process signals from the terminal Q _{n + 1} and the terminal Q _2n in FIG. 10 are unnecessary.

FIG. 19 is a timing chart showing signals in the scan driver 1000 when the shift register 1810 of FIG. 18 is provided. Shift register 1810, like the shift register 1010 of FIG. 11, in accordance with a shift control signal SL from the shift control unit 1828, performs a right shift of the cell 232 having terminals _{Q 1} to the cell 252 having terminals _{Q n,} then The left shift from the cell 252 to the cell 232 is performed.

Then, the scan driver 1000 generates output signals OUT1 to OUT2n-1 as shown in FIG. The selectors 1024_2 to 1024_n-1 output the outputs of the corresponding output control units as different output signals each time the shift direction is changed. The selectors 1024_1 and 1024_n output the outputs of the corresponding output control units as different output signals each time the shift direction becomes a predetermined direction. When the signal for the output signal OUT2n-1 is generated by the shift register 1810, the shift control unit 1828 outputs a pulse as the signal OUT to the next-stage scan driver.

FIG. 20 is a conceptual diagram showing the relationship between the pulse movement and the generated output signal in the shift register 1810 of FIG. The pulse of the input signal IN input to the cell 232 is right-shifted and sequentially output from the terminals Q ₁ , Q ₂ ,..., Q _n , and as a result, the pulses are sequentially output as the output signals OUT 1, OUT 2,. Is done. Thereafter, the terminal _{Q n} of the pulses in order terminal _{Q n-1} is left-shifted, ..., outputted from _{Q 1,} as a result, the output signal OUTn + 1, ..., pulses are outputted sequentially as OUT2N-1. Further, a pulse is output to the next-stage scan driver as the output signal OUT.

The circuit scale of the shift register 1810 can be smaller than that of the shift register 210 in FIG. 3 and the shift register 1010 in FIG.

FIG. 21 is a block diagram showing a configuration of a modification of the shift register 1810 of FIG. The scan driver 1000 may include the shift register 2110 in FIG. 21 instead of the shift register 1010 in FIG. The shift register 2110 in FIG. 21 is different from the shift register 1810 in FIG. 18 in that a register 614 is provided instead of the register 214. A shift control unit 2128 is used to control the shift register 2110. The shift register 2110 in FIG. 21 corresponds to the case where n = 3 in FIG.

FIG. 22 is a timing chart showing signals in the scan driver 1000 when the shift register 2110 of FIG. 21 is provided. The shift register 2110 performs a right shift from the cell 232 having the terminal Q ₁ to the cell 252 having the terminal Q ₃ in accordance with the shift control signal SL from the shift control unit 2128, as in the shift register 1810 of FIG. The left shift from the cell 252 to the cell 232 is performed.

Thereafter, the shift register 2110 performs a right shift from the cell 252 having the terminal Q ₁ to the cell 252 having the terminal Q ₃ in accordance with the shift control signal SL from the shift control unit 2128, and then from the cell 252 to the cell 232. Shift left. Then, the scan driver 1000 generates output signals OUT1 to OUT9 as shown in FIG. The selector 1024_2 outputs the output of the corresponding output control unit as a different output signal each time the shift direction is changed. The selectors 1024_1 and 1024_3 output the outputs of the corresponding output control units as different output signals each time the shift direction becomes a predetermined direction. When the signal for the output signal OUT9 is generated by the shift register 2110, the shift control unit 2128 outputs a pulse as the signal OUT to the next-stage scan driver.

FIG. 23 is a conceptual diagram showing the relationship between pulse movement and generated output signals in the shift register 2110 of FIG. The pulse of the input signal IN input to the cell 232 is right-shifted and sequentially output from the terminals Q ₁ , Q ₂ , and Q ₃ , and as a result, the pulses are sequentially output as the output signals OUT 1, OUT 2, and OUT 3. Then, pulses of terminals _{Q 3} are output sequentially from the terminal _Q 2, _{Q 1} is left-shifted, as a result, pulses are sequentially outputted as an output signal OUT4, OUT5.

Further, the pulse is further shifted to the right and sequentially output from the terminals Q ₂ and Q ₃ , and as a result, the pulse is sequentially output as the output signals OUT 6 and OUT 7. Then, pulses of terminals _{Q 3} are output sequentially from the terminal _Q 2, _{Q 1} is left-shifted, as a result, pulses are sequentially outputted as an output signal OUT8, OUT9. Further, a pulse is output to the next-stage scan driver as the output signal OUT.

Thus, since the shift register 2110 further reciprocates after reciprocating the pulse, a large number of output signals can be generated while suppressing the circuit scale of the shift register 2110. Although the case where the pulse is reciprocated twice has been described here, the pulse may be reciprocated many more times.

In the above embodiment, the case where the shift control unit 228 and the like change the shift control signal SL according to the output of the cell has been described. However, the number of shifts is counted using the clock CLK, and the shift control signal according to the count value SL may be changed.

In the above embodiment, the scan driver 100 has been described. However, the data line driver 192 may include a circuit having substantially the same configuration.

Many features and advantages of the present invention will be apparent from the written description, and thus, it is intended by the appended claims to cover all such features and advantages of the present invention. Further, since many changes and modifications will readily occur to those skilled in the art, the present invention should not be limited to the exact construction and operation as illustrated and described. Accordingly, all suitable modifications and equivalents are intended to be within the scope of the present invention.

As described above, according to various embodiments of the present invention, the circuit scale can be suppressed, so that the present invention is useful for a display panel driving device and the like.

100, 900, 1000, 1700

Scan drivers

210, 610, 1010, 1410, 1810, 2110 Shift registers 222_1 to 222_n + 1, 1021_1 to 1022_n + 1, 1022_2n Output control units 224_1 to 224_n-1, 1024_1 to 1024_n + 1, 1024_2n selectors 226_1 to 226_2n, 1026_1 to 1026_2x

Output circuits

228, 628, 1028, 1428, 1828, 2128 Shift control unit

Claims

A display panel driving device that generates a plurality of output signals for driving a display panel,
A shift register having a plurality of cells each storing a 1-bit value, storing a value of an input signal in one of the plurality of cells, and sequentially shifting the stored value among the plurality of cells; ,
A plurality of selectors respectively corresponding to at least some of the plurality of cells of the shift register;
The number of the plurality of cells of the shift register is less than the number of the plurality of output signals,
The shift register shifts the value of the input signal in a first direction, and then shifts in a second direction different from the first direction;
The plurality of selectors correspond to two or more output signals of the plurality of output signals so that they do not overlap each other, and signals indicating the values of the corresponding cells are included in the corresponding plurality of output signals. And outputting a signal indicating the value of the corresponding cell different from that before the change of the shift direction among the plurality of corresponding output signals in accordance with the change of the shift direction of the shift register. A display panel driving device that outputs signals.
The display panel driving device according to claim 1,
A display panel drive further comprising a plurality of output circuits that respectively correspond to a plurality of output signals of the plurality of selectors and generate and output a signal of a voltage necessary for driving the display panel according to the output signals of the corresponding selectors apparatus.
The display panel driving device according to claim 1,
A plurality of output control units each corresponding to a plurality of cells of the shift register, each generating and outputting two signals having a time difference based on a signal indicating a value of a corresponding cell of the shift register; Prepared,
Each of the plurality of selectors is a display panel driving device that outputs two signals generated by the corresponding output control unit as the output signals.
The display panel driving device according to claim 1,
The shift register is
Alternately repeating a shift of a plurality of bits in the first direction of the input signal and a shift of a plurality of bits in the second direction;
Each of the plurality of selectors sequentially selects one of the corresponding plurality of output signals each time the shift direction of the shift register changes, and the signal indicating the value of the corresponding cell is selected. A display panel driving device that outputs as an output signal.
The display panel driving device according to claim 1,
The shift register is
First, second and third registers each having at least one cell storing one bit;
When the shift register shifts in the first direction, the first register shifts the input signal or the signal output from the second register to the second register according to a clock, The second register shifts the signal output from the first register to the third register according to the clock,
When the shift register shifts in the second direction, the third register shifts the signal output from the second register to the second register according to the clock, and the second register The register is a display panel driving device that shifts the signal output from the third register to the first register according to the clock.
The display panel driving device according to claim 5,
The second register has a plurality of cells each storing one bit;
The plurality of cells are:
When the shift register shifts in the first direction, the signal output from the first register is shifted in the first direction according to the clock;
When the shift register shifts in the second direction, the display panel driving device shifts the signal output from the third register in the second direction according to the clock.
The display panel driving device according to claim 5,
The third register is
A first cell for storing and outputting the output of the second register;
A display panel driving device comprising: a second cell that stores an output of the first cell and outputs the output to the second register.
The display panel driving device according to claim 7,
The first register is:
A first cell for storing and outputting the output of the second register;
A display panel driving device comprising: a second cell that stores the input signal or the output of the first cell and outputs the second signal to the second register.
A display panel;
A display panel driving device that generates a plurality of output signals for driving the display panel;
The display panel driving device includes:
A shift register having a plurality of cells each storing a 1-bit value, storing a value of an input signal in one of the plurality of cells, and sequentially shifting the stored value among the plurality of cells; ,
A plurality of selectors respectively corresponding to at least some of the plurality of cells of the shift register;
The number of the plurality of cells of the shift register is less than the number of the plurality of output signals,
The shift register shifts the value of the input signal in a first direction, and then shifts in a second direction different from the first direction;
The plurality of selectors correspond to two or more output signals of the plurality of output signals so that they do not overlap each other, and signals indicating the values of the corresponding cells are included in the corresponding plurality of output signals. And outputting a signal indicating the value of the corresponding cell different from that before the change of the shift direction among the plurality of corresponding output signals in accordance with the change of the shift direction of the shift register. A display device that outputs signals.