JP2013041641A - Shift pulse generating circuit and integrated circuit for display device drive - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a shift pulse generating circuit capable of achieving both circuit area reduction and circuit simplification, and an integrated circuit for display device drive using the circuit.SOLUTION: A shift pulse generating circuit comprises: a pulse generating circuit CR1 including a latch circuit 13 which generates a shift pulse signal Q11 from a signal IN1 and outputs the shift pulse signal Q11 to a pulse generating circuit CR2, and a latch circuit 14 which generates a shift pulse signal Q21 from a shift pulse signal Q2; a pulse generating circuit CRi (i=2 to n-1) including a bidirectional latch circuit which generates a shift pulse signal Qi from a shift pulse signal Q(i-1) to output the shift pulse signal Qi to a pulse generating circuit Q(i+1) and generates a shift pulse Qi from a shift pulse signal Q(i+1) to output the shift pulse signal Qi to a pulse generating circuit CR(i-1); and a pulse generating circuit CRn including a latch circuit 33 which generates a shift pulse signal Q1n from a shift pulse signal Q(n-1), and a latch circuit 34 which generates a shift pulse signal Q2n from a shift pulse signal Q1n.

Description

  The present invention relates to a shift pulse generation circuit and an integrated circuit for driving a display device using the shift pulse generation circuit.

  Conventionally, a display device such as a liquid crystal display has a display device driving integrated circuit (hereinafter referred to as a “drive circuit” as appropriate) for driving a picture element array composed of a plurality of picture elements and a signal line connected to the picture element array. For example).

  Here, FIG. 6 shows an example of a conventional semiconductor device. The semiconductor device shown in FIG. 6 is a drive circuit 100 that drives a data signal line (video signal line), and is mounted on a tape 200. The tape 200 includes output terminals OUT11 to OUT5e connected to video signal lines of the display device, input terminals I1 to If, a driving circuit 100, a wiring 201 connecting the output circuit CO of the driving circuit 100 and the output terminals OUT11 to OUT5e, and A wiring 202 connecting the input circuit of the drive circuit 100 and the input terminals I1 to If is configured. Note that the configuration of the drive circuit for driving the scanning signal lines is basically the same as that of the drive circuit 100.

  As shown in FIG. 6, the drive circuit 100 includes an output circuit group COB1 including a (a is an integer of 3 or more) output circuits CO11 to CO1a, an output circuit group COB2 including a number of output circuits CO21 to CO2a, Output circuit group COB3 having b output circuits CO31 to CO3b (b is an integer of 3 or more), output circuit group COB4 having c output circuits CO41 to CO4c (c is an integer of 3 or more), c outputs Output circuits CO11 to CO1a, CO21 to CO2a, CO31 to CO3b, CO41 provided corresponding to each of the output circuit group COB5 and the output circuit groups COB1 to COB5 having the circuits CO51 to CO5c and constituting the output circuit groups COB1 to COB5. Shift pulse generation circuits CSR101 to CSR10 that output pulse signals to CO4c and CO51 to CO5c, respectively. An input circuit for receiving an input signal from the input terminal I1～If, and an output circuit group COB1～COB5, and a control circuit for controlling the shift pulse generating circuit CSR101~CSR105 and the input circuit.

  Here, FIG. 7 shows a case where the number of video signal lines is 256 and 256 output circuits are provided as one configuration example of the drive circuit 100. In the case of FIG. 7, the output circuit group COB1 is configured to include output circuits CO11 to 160, the output circuit group COB2 is configured to include 60 output circuits CO21 to 260, and 16 output circuit groups COB3. Output circuit CO31 to 316, the output circuit group COB4 includes 60 output circuits CO41 to 460, and the output circuit group COB5 includes 60 output circuits CO51 to 560. Has been.

  The drive circuit 100 is a rectangular integrated circuit, and output circuit groups COB2 to COB4 are formed in this order from the left side of the drawing along the long side of the tape 200 where the output terminals OUT11 to OUT5n are formed. An output circuit group COB1, an input circuit, and an output circuit group COB5 are formed in this order from the left side of the drawing along the long side. The shift pulse generation circuits CSR101 to CSR105 are formed so as to be in contact with the corresponding output circuit groups COB1 to COB5, respectively, and are arranged in the center of the drive circuit 100. As shown in FIG. 6, the area occupied by the output circuit CO in the drive circuit 100 is large.

  Here, FIG. 8 shows a configuration example of the output circuit group COB, and FIG. 9 shows a configuration example of the shift pulse generation circuit CSR.

  As shown in FIG. 8, the output circuit group COBk (k = 1 to 5) includes output circuits COk1 to COkn. The output circuits COkj (n = 1a when j = 1 to n, k = 1, 2, n = b when k = 3, n = c when k = 4, 5) are data latch and hold latch, respectively. , A level shifter, a DA conversion circuit, and a comparator. Since all video signal lines connected to the picture element array of the display device need to be driven, the number of output circuits COk1 to kn in the entire drive device is the same as the number of video signal lines.

  More specifically, in the output circuit COkj, the data latch is input to the data bus D [7: 0] in time series by the control circuit at the timing of the pulse signal SENBkj output from the shift pulse generation CSR 100 described later. Display data SD is stored. The display data SD stored in the data latch is transferred to the hold latch and subjected to level conversion by the level shifter. The DAC selects a gradation voltage corresponding to the display data SD that has been level-converted by the level shifter, and outputs it to the operational amplifier. The operational amplifier performs impedance conversion on the gradation voltage selected by the DAC and outputs it to the output terminal OUTkj.

  Each of the shift pulse generation circuits CSR101 to 105 includes the same number of pulse generation circuits CR100 as the output circuits CO of the corresponding output circuit groups COB1 to COB5, and displays data for the output circuits COkj connected to each pulse generation circuit CR100. A pulse signal SENBkj for sampling the SD is output.

  In addition, when the signal L / R is at the H level, the shift pulse generation circuits 101 to 105 shown in FIG. 8 receive the signal output from the control circuit and generate a new shift pulse signal. The shift pulse generation circuits CSR102 to CSR105 are configured to receive the shift pulse signals output from the shift pulse generation circuits 101 to 104, respectively, in this order. Yes. Further, when the signal L / R is at the L level, the shift pulse generation circuit CSR 105 is configured to accept a signal output from the control circuit, generate a new shift pulse signal, and output it to the shift pulse generation circuit 104. The shift pulse generation circuits CSR104 to CSR101 are configured to receive the shift pulse signals output from the shift pulse generation circuits 105 to 102, respectively, in this order.

  Here, FIG. 9 shows a schematic configuration example of the shift pulse generation circuit 101 and the shift pulse generation circuit 102. Here, the signal IN1 is an input signal output from the control circuit, IN2 is an input signal (shift pulse signal) output from the shift pulse generation circuit 103, and the signal L / R is a shift of the shift pulse signal. A shift direction control signal indicating a direction, and a signal CK is a clock signal. Note that the configurations of the shift pulse generation circuit 105 and the shift pulse generation circuit 104 correspond to the shift pulse generation circuit 101 and the shift pulse generation circuit 102, respectively.

  Specifically, as shown in FIG. 9, the shift pulse generation circuit 101 generates n stages of pulses to generate a pulse signal that defines the sampling timing of the display data SD input in time series by the output circuit CO described above. Circuits CR111 to CR11n are provided.

  The pulse generation circuit CR111 receives the input signal IN1 and the shift pulse signal Q12 output from the D flip-flop circuit of the pulse generation circuit CR112. When the signal L / R is at the H level, the pulse generation circuit CR111 receives the input signal IN1 as the signal L / R. Is provided with a selector circuit that selects and outputs the shift pulse signal Q12 when L is at the L level, and a D flip-flop circuit that receives a signal output from the selector circuit and generates a new shift pulse signal Q11. .

  The pulse generation circuit CR121 receives the input signal IN2 and the shift pulse signal Q22 output from the D flip-flop circuit of the pulse generation circuit CR122. When the signal L / R is at the H level, the pulse generation circuit CR121 receives the shift pulse signal Q22 as the signal L / A selector circuit that selects and outputs an input signal IN2 when R is at an L level, and a D flip-flop circuit that receives a signal output from the selector circuit and generates a new shift pulse signal Q21 are provided. .

  The pulse generation circuit CR11i (k = 2 to n-1) has a shift pulse signal Q1 (i-1) output from the pulse generation circuit 11 (i-1) and a shift output from the pulse generation circuit CR11 (i + 1). When pulse signal Q1 (i + 1) is input and signal L / R is at H level, shift pulse signal Q1 (i-1) is selected, and when signal L / R is at L level, shift pulse signal Q1 (i + 1) is selected. And a D flip-flop circuit that receives a signal output from the selector circuit and generates a new shift pulse signal Q1i.

  The pulse generation circuit CR12i (i = 2 to n) includes a shift pulse signal Q2 (i-1) output from the pulse generation circuit 12 (i-1) and a shift pulse signal output from the pulse generation circuit CR12 (i + 1). When Q2 (i + 1) is input and the signal L / R is at the H level, the shift pulse signal Q2 (i + 1) is selected, and when the signal L / R is at the L level, the shift pulse signal Q2 (i-1) is selected. A selector circuit for output and a D flip-flop circuit for receiving a signal output from the selector circuit and generating a new shift pulse signal Q2i are provided.

  The pulse generation circuit CR11n receives the shift pulse signal Q1 (n-1) output from the pulse generation circuit 11 (n-1) and the shift pulse signal Q2n output from the pulse generation circuit CR121, and the signal L / R is A selector circuit that selects and outputs the shift pulse signal Q1 (n-1) when it is at the H level, and a shift pulse signal Q2n when the signal L / R is at the L level, and a signal that is output from the selector circuit. A D flip-flop circuit for generating a new shift pulse signal Q1n is provided.

  The pulse generation circuit CR12n receives the shift pulse signal Q1n output from the pulse generation circuit CR11n and the shift pulse signal Q2 (n-1) output from the pulse generation circuit CR12 (n-1), and the signal L / R is A selector circuit that selects and outputs the shift pulse signal Q1n when it is at the H level and a shift pulse signal Q2 (n-1) when the signal L / R is at the L level, and a signal that is output from the selector circuit. A D flip-flop circuit for generating a new shift pulse signal Q2n is provided.

  In FIG. 8, when the signal L / R is at the H level, the pulse generation circuits 111 to 11n and 12n to 121 generate shift pulse signals in this order, and the output circuit CO corresponding to the shift pulse signal as the pulse signal. Respectively.

  By the way, with the increase in data capacity of video data in recent years, the number of video signal lines tends to increase, and an increase in circuit area becomes a problem.

  On the other hand, as a shift pulse generation circuit capable of reducing the circuit area, n output circuits are equally divided into L groups by x (x × L = n), and x pulse generation circuits are provided. There is a shift pulse generation circuit that sequentially switches the reception destination of the pulse signal output from the generation circuit in the order of the 1st to Lth groups (for example, see Patent Document 1).

  In this shift pulse generation circuit, it is necessary to add a group switching circuit. However, since only x pulse generation circuits need be provided, the circuit area of the entire drive circuit can be increased.

JP 2002-215119 A

  However, in the shift pulse generation circuit described in Patent Document 1, since the output circuits are grouped, a group switching circuit for performing group selection control, shift pulse signal output destination switching control, and the like is necessary. Additional circuitry is required.

  Further, in the case of the shift pulse generation circuit described in Patent Document 1, since grouping is performed, the shift pulse signal output timing to the next-stage shift pulse generation circuit at the time of group switching, control of group switching timing, shift pulse It becomes necessary to control the switching timing of the signal generation order, and the control becomes complicated, and the configuration of the control circuit for the control becomes complicated.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a shift pulse generation circuit capable of satisfying both area reduction and circuit simplification. In addition, an integrated circuit for driving a display device using the shift pulse generation circuit is provided.

  In order to achieve the above object, a shift pulse generation circuit according to the present invention is a shift pulse generation circuit including n pulse generation circuits (where n is an integer of 3 or more), and the first pulse generation circuit. Receives a first input signal, generates a shift pulse signal and outputs it to the second-stage pulse generation circuit, and receives the shift-pulse signal output from the second-stage pulse generation circuit. A second latch circuit for generating a new shift pulse signal, and an i-th (i = 2 to n−1) -th pulse generation circuit is output from the (i−1) -th pulse generation circuit. A shift pulse signal is received, a new shift pulse signal is generated and output to the (i + 1) th stage pulse generation circuit, and a shift pulse signal output from the (i + 1) th stage pulse generation circuit is received. A bidirectional latch circuit that generates a new shift pulse signal and outputs it to the (i-1) -th stage pulse generation circuit, and the n-th stage pulse generation circuit comprises the (n-1) -th stage A third latch circuit that receives the shift pulse signal output from the pulse generation circuit and generates a new shift pulse signal; and a new latch pulse signal that receives a shift pulse signal output from the third latch circuit. A fourth latch circuit is provided that generates and outputs to the (n-1) -th stage pulse generation circuit.

  More preferably, in the shift pulse generation circuit having the above characteristics, the i-th (i = 2 to n−1) -th pulse generation circuit is output from the (i−1) -th pulse generation circuit. Any one of the signal and the shift pulse signal output from the (i + 1) -th stage pulse generation circuit, the shift pulse signal output from the third latch circuit and the fourth latch circuit, or the third latch circuit, An input-side selector circuit that selects based on at least one of the shift pulse signals input to the fourth latch circuit is provided, and the bidirectional latch circuit receives the shift pulse signal selected by the input-side selector circuit. To generate a new shift pulse signal.

  More preferably, in the shift pulse generation circuit having the above characteristics, the i-th (i = 2 to n−1) pulse generation circuit generates a new shift pulse signal generated by the bidirectional latch circuit (i− 1) The shift pulse signal output from the third latch circuit and the fourth latch circuit or the third latch circuit is provided to one of the pulse generation circuit at the first stage and the pulse generation circuit at the (i + 1) th stage. And an output-side selector circuit for selectively outputting based on at least one of the shift pulse signals input to the fourth latch circuit.

  More preferably, the shift pulse generation circuit having any one of the above characteristics is configured such that the first pulse generation circuit can further receive a second input signal, and the second latch circuit includes the second input. A new shift pulse signal is generated by receiving a signal and output to the pulse generation circuit at the second stage, and the first latch circuit receives a shift pulse signal output from the pulse generation circuit at the second stage and newly generates a new shift pulse signal. And the fourth latch circuit when the second input signal is input to the first-stage pulse generation circuit. Receives a shift pulse signal output from the (n−1) -th stage pulse generation circuit, generates a new shift pulse signal, and outputs the shift pulse signal to the third latch circuit. And is configured to output a fourth accepts the shift pulse signal outputted from the latch circuit to generate a new shift pulse signal (n-1) th stage of the pulse generating circuit.

  More preferably, in the shift pulse generation circuit having any one of the above characteristics, the new shift pulse signal generated by the latch circuit included in the pulse generation circuit of the pulse generation circuit of the j-th stage (j = 1 to n) is provided. Or in synchronism with the jth output circuit of the first output circuit group having n output circuits and the jth output circuit group of the second output circuit group having n output circuits. Each of the output circuits is configured to output a pulse signal separately, and the first-stage pulse generation circuit includes the first latch circuit and the first output circuit of the first output circuit group. , The second latch circuit outputs the pulse signal to the first output circuit of the second output circuit group, and the i-th stage (i = 2 to n−1). ) Of the pulse generation circuit of (i-1) stage When the shift pulse signal output from the raw circuit is received, the pulse signal is output to the i-th output circuit of the first output circuit group, and output from the pulse generation circuit at the (i + 1) -th stage. When the received shift pulse signal is received, the pulse signal is output to the i-th output circuit of the second output circuit group, and the n-th pulse generation circuit is connected to the third latch circuit. The pulse signal is output to the first output circuit of the first output circuit group, and the fourth latch circuit outputs the pulse signal to the first output circuit of the second output circuit group. Is output.

  More preferably, in the shift pulse generation circuit having any one of the above characteristics, the new shift pulse signal generated by the latch circuit included in the pulse generation circuit of the pulse generation circuit of the j-th stage (j = 1 to n) is provided. Or in synchronism with the jth output circuit of the first output circuit group having n output circuits and the jth output circuit group of the second output circuit group having n output circuits. Each of the output circuits is configured to output a pulse signal separately, and the first-stage pulse generation circuit includes the first latch circuit and the first output circuit of the first output circuit group. And the second latch circuit outputs the pulse signal to the first output circuit of the second output circuit group, and the i-th stage (i = 1 to n). The pulse generation circuit is connected to the first pulse generation circuit. When the first input signal is input and the shift pulse signal output from the pulse generation circuit at the (i-1) stage is received, the i-th output circuit of the first output circuit group is When the pulse signal is output and a shift pulse signal output from the pulse generation circuit at the (i + 1) th stage is received, the pulse signal is output to the i-th output circuit of the second output circuit group When the second input signal is input to the pulse generation circuit at the first stage, the second pulse is output when the shift pulse signal output from the pulse generation circuit at the (i-1) stage is received. When the pulse signal is output to the i-th output circuit of the output circuit group and the shift pulse signal output from the pulse generation circuit at the (i + 1) -th stage is received, i of the first output circuit group Th The pulse signal is output to the output circuit based on the shift pulse signal, and the third latch circuit is connected to the first output circuit group of the first output circuit group. The fourth latch circuit outputs the pulse signal to the first output circuit of the second output circuit group.

  In order to achieve the above object, an integrated circuit for driving a display device according to the present invention performs the time series processing based on the shift pulse generation circuit having the above characteristics and the pulse signal output from the shift pulse generation circuit. A first output circuit group composed of a plurality of output circuits and a second output circuit group composed of n output circuits, wherein the n pulse generation circuits of the shift pulse generation circuit are formed of a rectangular semiconductor device. The j-th (j = 1 to n) output circuit of the first output circuit group and the j-th output circuit of the second output circuit group are aligned in the long side direction, It is characterized by being arranged at positions facing each other across the pulse generation circuit.

  According to the shift pulse generating circuit having the above characteristics, the first output circuit group and the second output circuit group including n output circuits and the second output circuit group including n output circuits are The latch circuits of the pulse generation circuits in the 2nd to (n-1) th stages corresponding to the second output circuit group can be made common to one.

  Therefore, conventionally, there are 2n latch circuits for two circuit groups, a first output circuit group composed of n output circuits and a second output circuit group composed of n output circuits. However, the shift pulse generation circuit according to the present invention includes n + 2 latch circuits, and the circuit area of n-2 latch circuits can be reduced. For example, in the case of FIG. 7, the shift pulse generation circuit having the above characteristics can be applied to the shift pulse generation circuits COB1 and COB2, and each of the shift pulse generation circuits COB1 and COB2 includes 60 stages of pulse generation circuits. The circuit area of the latch circuit can be reduced. Similarly, the shift pulse generation circuit having the above characteristics can be applied to the shift pulse generation circuits COB4 and COB5, and each of the shift pulse generation circuits COB4 and COB5 includes 60 stages of pulse generation circuits. The circuit area can be reduced. Therefore, the entire semiconductor device conventionally requires 256 latch circuits, whereas the shift pulse generation circuit according to the present invention can reduce the number of latch circuits of 58 × 2 = 116, and 140 This can be realized with a latch circuit.

  According to the shift pulse generation circuit having the above characteristics, the latch circuits of the pulse generation circuits in the 2nd to (n-1) th stages corresponding to the first output circuit group and the second output circuit group are shared. Since the latch circuit is provided for each output circuit at the nth stage, group selection control and switching control of three or more complicated output destinations as in the shift pulse generation circuit described in Patent Document 1. Is not necessary, and the circuit configuration is not complicated.

  Moreover, in the shift pulse generation circuit described in Patent Document 1, the output circuit of the output circuit group is divided into a plurality of groups, so that the wiring path from the shift pulse generation circuit to the output circuit may be complicated. On the other hand, in the integrated circuit for driving the display device having the above characteristics, the first output circuit group and the second output circuit group are arranged at positions facing each other with the shift pulse generating circuit interposed therebetween. Since the latch circuit of the eye pulse generation circuit is shared, the circuit area can be reduced without complicating the wiring path.

It is a schematic block diagram which shows the schematic structural example of the integrated circuit for a display apparatus drive which concerns on this invention. 1 is a schematic circuit diagram showing a schematic configuration example of a shift pulse generating circuit according to the present invention. 6 is a timing chart showing an example of the operation of the shift pulse generation circuit according to the present invention. It is a schematic circuit diagram which shows the schematic structural example in another embodiment of the shift pulse generation circuit which concerns on this invention. It is a schematic circuit diagram which shows the schematic structural example in another embodiment of the shift pulse generation circuit which concerns on this invention. It is a schematic block diagram which shows the schematic structural example of the semiconductor device with which the integrated circuit for a display apparatus drive which concerns on a prior art is mounted. It is a schematic block diagram which shows the schematic structural example of the integrated circuit for a display apparatus drive which concerns on a prior art. It is a schematic circuit diagram which shows the schematic structural example of the output circuit group in the integrated circuit for a display apparatus drive which concerns on a prior art. It is a schematic circuit diagram which shows the schematic structural example of the shift pulse generation circuit in the display apparatus drive integrated circuit which concerns on a prior art.

  Hereinafter, embodiments of a shift pulse generating circuit (hereinafter, appropriately referred to as “present circuit”) and a display device driving integrated circuit (hereinafter, appropriately referred to as “driving circuit”) according to the present invention will be described with reference to the drawings. explain.

<Device configuration of drive circuit and circuit of the present invention>
First, the configuration of the drive circuit and the circuit of the present invention will be described with reference to FIGS. Here, FIG. 1 shows a schematic configuration example of the drive circuit 1, and FIG. 2 shows a schematic configuration example of the circuit CSR of the present invention.

  The drive circuit 1 is a rectangular circuit, and is mounted on the semiconductor device so that the long side direction of the semiconductor device and the long side of the drive circuit 1 are parallel to each other. The semiconductor device on which the drive circuit 1 according to the present invention is mounted is the same as the semiconductor device shown in FIG. 6 although the configuration of the drive circuit 1 is different. In this embodiment, the case of a circuit for driving the data signal line is described, but the present invention may be applied to a circuit for driving the scanning signal line.

  As shown in FIG. 1, the drive circuit 1 is a first circuit comprising a present invention circuit CSR, which will be described later, and n output circuits CO11 to CO1n that perform time-series processing based on a pulse signal output from the present circuit CSR. An output circuit group COB1 and a second output circuit group COB2 including n output circuits CO21 to CO2n are provided. The present invention circuit CSR includes n-stage pulse generation circuits CR1 to CRn. The n-stage pulse generation circuits CR1 to CRn are arranged in the long side direction of the rectangular semiconductor device, and the first output The j-th (j = 1 to n) output circuit CO1j of the circuit group CB1 and the j-th output circuit CO2j of the second output circuit group COB2 are arranged at positions facing each other across the j-th shift pulse generation circuit CRj. Has been.

  The configuration of the first output circuit group COB1 and the second output circuit group COB2 is the same as that of the conventional output circuit group COB shown in FIG.

  The present invention circuit CSR includes n stages (where n is an integer of 3 or more) of pulse generation circuits CR1 to CRn for outputting a pulse signal to the output circuit CO, a control signal SC1 for controlling the pulse generation circuits CR1 to CRn, and A control signal generation circuit CSC for generating SC2 is provided. Here, the input signal IN1 and the input signal IN2 are shift pulse signals input by the control circuit, and either the input signal IN1 or the input signal IN2 is input according to the selection order of the data side signal lines. The external control signal L / R is a signal indicating which of the input signals IN1 and IN2 is input. The input signal IN1 is input when it is at the H level, and the input signal IN2 is input when it is at the L level. It means that.

  The control signal generation circuit CSC includes the first control signal generation circuit CSC1 that generates the control signal SC1 indicating the propagation direction of the shift pulse signal, and the pulse signal generated by the shift pulse generation circuit CRi (i = 2 to n−1). A second control signal generation circuit CSC2 for generating a control signal SC2 for switching the output destination (output circuit group COB) is provided.

  The first control signal generation circuit CSC1 includes an OR circuit 41 that obtains a logical sum of the input signal IN1 and the input signal IN2, and a shift pulse signal Q1n and a DFF circuit that are output from a DFF circuit 33 of an n-th pulse generation circuit described later. The OR circuit 42 for calculating the logical sum of the shift pulse signal Q2n output from 34 and the signal IN3 output from the OR circuit 41 as a set input, the signal output from the OR circuit 42 as a reset input, and a control signal SC1 as An RS latch circuit 43 to be generated is provided.

  The second control signal generation circuit CSC2 includes an EXNOR circuit 44 that calculates a negative exclusive OR of the external control signal L / R and the control signal SC1 and generates the control signal SC2.

  The first-stage pulse generation circuit CR1 includes selector circuits 11 and 15, an input switching circuit 12, and DFF circuits 13 and 14.

  More specifically, the selector circuit 11 receives the signal IN3 output from the first control signal generation circuit CSC1 and the shift pulse signal Q2 output from the second-stage pulse generation circuit CR2, and the control signal SC1 is at the H level. In this case, the signal IN3 is output, and in the case of L level, the shift pulse signal Q2 is output. When the control signal SC2 is at H level, the input switching circuit 12 outputs a signal output from the selector circuit 11 to the DFF circuit 13, outputs an L level signal to the DFF circuit 14, and the control signal SC2 is at L level. In this case, a signal output from the selector circuit 11 is output to the DFF circuit 14 and an L level signal is output to the DFF circuit 13.

  The DFF circuit 13 (corresponding to the first latch circuit) receives the signal output from the input switching circuit 12, generates a new shift pulse signal Q11 at the falling timing of the clock signal CK, and selects a selector circuit 15 described later. And output to the first output circuit CO11 of the first output circuit group COB1. Here, the shift pulse signal Q11 becomes the pulse signal Q11 as it is. The DFF circuit 14 (corresponding to the second latch circuit) receives the signal output from the input switching circuit 12, generates a new shift pulse signal Q21 at the falling timing of the clock signal CK, and selects a selector circuit 15 described later. And output to the first output circuit CO21 of the second output circuit group COB2. Here, the shift pulse signal Q21 is directly used as the pulse signal Q21.

  The selector circuit 15 (corresponding to the input side selector circuit) receives the shift pulse signal Q11 output from the DFF circuit 13 and the shift pulse signal Q21 output from the DFF circuit 14, and shifts when the signal L / R is at the H level. When the pulse signal Q11 is at L level, the shift pulse signal Q21 is output.

  The i-th pulse generation circuit CRi (i = 2 to n−1) includes a selector circuit 21 (21 ′) (input-side selector circuit), a DFF latch circuit 22 (22 ′), and an output switching circuit 23, respectively. (23 ′).

  More specifically, the selector circuit 21 includes the shift pulse signal Q (i−1) output from the pulse generation circuit CR (i−1) and the shift pulse signal Q (i + 1) output from the pulse generation circuit (i + 1). ) And outputs the shift pulse signal Q (i−1) when the control signal SC1 is at the H level and the shift pulse signal Q (i + 1) when the control signal SC1 is at the L level. The DFF circuit 22 (bidirectional latch circuit) receives a signal output from the selector circuit 21, generates a new shift pulse signal Q2 at the falling timing of the clock signal CK, and outputs an output switching circuit 23, a pulse generation circuit. (I-1) and the pulse generation circuit (i + 1). The output switching circuit 23 receives the shift pulse signal Q2 output from the DFF circuit 22. When the control signal SC2 is at the H level, the output switching circuit 23 sends the shift pulse signal Q2 to the i-th output circuit CO1i of the first output circuit group COB1. The pulse signal Q12 is output, and the L-level pulse signal Q22 is output to the i-th output circuit CO2i of the second output circuit group COB2. When the control signal SC2 is at the L level, the output circuit CO1i has the L-level pulse signal. The signal Q12 is output, and the shift pulse signal Q2 is output as the pulse signal Q22 to the output circuit CO2i.

  The n-th pulse generation circuit CRn includes selector circuits 31, 35, and 36, an input switching circuit 32, and DFF circuits 33 and 34.

  More specifically, the selector circuit 31 receives the shift pulse signal Q (n−1) output from the pulse generation circuit CR (n−1) and the signal output from the selector circuit 36, and the control signal SC1 is H. The shift pulse signal Q (n-1) is output when the level is set, and the signal output from the selector circuit 36 is output when the level is the L level. The input switching circuit 32 receives the signal output from the selector circuit 31, and outputs the signal output from the selector circuit 31 to the DFF circuit 33 and the LFF to the DFF circuit 34 when the control signal SC2 is at the H level. When the control signal SC2 is at L level, the signal output from the selector circuit 31 is output to the DFF circuit 34, and the L level signal is output to the DFF circuit 33.

  The DFF circuit 33 (corresponding to the third latch circuit) receives the signal output from the input switching circuit 32, generates a new shift pulse signal Q1n at the falling timing of the clock signal CK, and selects the selector circuits 35 and 36. And output to the first control signal generation circuit CSC1. Here, the shift pulse signal Q1n becomes the pulse signal Q1n as it is. The DFF circuit 34 (fourth latch circuit) receives the signal output from the input switching circuit 32, generates a new shift pulse signal Q2n at the falling timing of the clock signal CK, and selects the selector circuits 35 and 36, 1 is output to the control signal generation circuit CSC1. Here, the shift pulse signal Q2n becomes the pulse signal Q2n as it is.

  The selector circuit 35 receives the shift pulse signal Q1n output from the DFF circuit 33 and the shift pulse signal Q2n output from the DFF circuit 34, and is output from the DFF circuit 34 when the external control signal L / R is at the H level. When the shift pulse signal Q2n is at L level, the shift pulse signal Q1n output from the DFF circuit 33 is output to the pulse generation circuit CR (n−1). The selector circuit 36 receives the shift pulse signal Q1n output from the DFF circuit 33 and the shift pulse signal Q2n output from the DFF circuit 34, and is output from the DFF circuit 33 when the external control signal L / R is at the H level. When the shift pulse signal Q1n is at L level, the shift pulse signal Q2n output from the DFF circuit 34 is output to the selector circuit 31.

  In the circuit CSR of the present invention, as described above, the functions of the two shift pulse generation circuits CSR101 and CSR102 in the prior art shown in FIG. 6 can be realized by one shift pulse generation circuit CSR1. In the prior art, 2n latch circuits are required for two shift pulse generation circuits, whereas the circuit CSR of the present invention can be composed of n + 2 latch circuits, so that the area of the latch circuit is reduced to about half. Can do. For this reason, as shown in FIG. 1, the n-stage pulse generation circuits CO constituting the inventive circuit CSR are aligned in the long side direction of the rectangular semiconductor device, and the j-th ( In the case where the output circuit CO1j of j = 1 to n) and the j-th output circuit CO2j of the second output circuit group COB2 are arranged at positions facing each other across the j-th shift pulse generating circuit CRj, the semiconductor It is possible to reduce the width of the circuit CSR of the present invention in the edge direction of the device.

<Operation of the circuit of the present invention>
Subsequently, the operation of the circuit CSR of the present invention will be described with reference to FIG.

  Here, FIG. 3A shows a case where the external control signal L / R is at the H level, and FIG. 3B shows a case where the external control signal L / R is at the L level. Also, time t indicates the falling timing of the clock signal CK.

  First, the case where the external control signal L / R is at the H level will be described with reference to FIG.

  When the external control signal L / R is at the H level, the selector circuit 35 of the pulse generation circuit CRn always selects the shift pulse signal Q1n output from the DFF circuit 33, and the selector circuit 36 always operates the DFF circuit. The shift pulse signal Q2n output from 34 is selected. When the external control signal L / R is at the H level, a pulse signal is input to the input signal IN1, and the input signal IN2 is maintained at the L level. The signal IN3 that is the logical sum of the input signal IN1 and the input signal IN2 is always at the same level as the signal IN1 because the input signal IN2 is maintained at the L level.

  When the input signal IN1 becomes H level at time t0, the signal IN3 output from the OR circuit 41 becomes H level, the RS latch circuit 43 is set, and the control signal SC1 becomes H level. In the second control signal generation circuit CSC2, the external control signal L / R and the control signal SC1 are both at the H level, so that the control signal SC2 output from the EXNOR circuit 44 is at the H level.

  At this time, in the pulse generation circuit CR1, since the control signal SC1 is at the H level, the selector circuit 11 selects the input signal IN3 generated from the input signal IN1 and outputs it to the input switching circuit 12, and the control signal SC2 Therefore, the input switching circuit 12 outputs the input signal IN3 to the DFF circuit 13. That is, the propagation signal of the input signal IN1 is input to the D terminal of the DFF circuit 13.

  In the pulse generation circuit CRi (i = 2 to n−1), since the control signal SC1 is at the H level, the selector circuit 21 (21 ′) shifts output from the pulse generation circuit CR (i−1). The pulse signal Q (i−1) is selected and output to the DFF circuit 22 (22 ′).

  In the pulse generation circuit CRn, since the control signal SC1 is at the H level, the selector circuit 31 selects the shift pulse signal Q (n-1) output from the pulse generation circuit CR (n-1) and selects the input switching circuit. Since the control signal SC2 is at H level, the input switching circuit 32 outputs the shift pulse signal Q (n−1) to the DFF circuit 33.

  At time t1, since the propagation signal of the signal IN1 input to the DFF circuit 13 is H level, the shift pulse signal Q11 output from the DFF circuit 13 transitions from L level to H level. At this time, the input switching circuit 12 inputs an L level signal to the DFF circuit 14, and the shift pulse signal Q21 is maintained at the L level.

  At time t2, since the shift pulse signal Q11 input to the DFF circuit 22 of the shift pulse generation circuit CR2 is at H level, the shift pulse signal Q2 output from the DFF circuit 22 of the shift pulse generation circuit CR2 transitions to H level. At this time, the shift pulse signal Q12 transitions to the H level by the output switching circuit 23, and the shift pulse signal Q22 is maintained at the L level. Further, since the propagation signal of the signal IN1 input to the DFF circuit 13 transits from H level to L level, the shift pulse signal Q11 transits from H level to L level.

  Similarly, at time th (h = 3 to n−1), the shift pulse signal Q (h−1) input to the DFF circuit 21 (21 ′) of the shift pulse generation circuit CRh is at the H level. The shift pulse signal Qh output from the DFF circuit 21 (21 ′) of the generation circuit CRh transitions to the H level. At this time, the pulse signal Q1h is changed from the L level to the H level by the output switching circuit 23, and the pulse signal Q2h is maintained at the L level. Further, since the shift pulse signal Q (h-2) input to the DFF circuit 21 (21 ') of the shift pulse generation circuit CR (h-1) is at the L level, the DFF of the shift pulse generation circuit CR (h-1). The shift pulse signal Q (h−1) output from the circuit 21 (21 ′) also changes to the L level. At this time, the output switching circuit 23 (23 ') causes the pulse signal Q1 (h-1) to transition from the H level to the L level.

  At time tn, since the shift pulse signal Q (n−1) input to the DFF circuit 33 of the shift pulse generation circuit CRn is at the H level, the shift pulse signal Q1n output from the DFF circuit 33 transitions to the H level. Further, since the shift pulse signal Q (h-2) input to the DFF circuit 21 'of the shift pulse generation circuit CR (n-1) is at the L level, the DFF circuit 21' of the shift pulse generation circuit CR (n-1). The shift pulse signal Q (n−1) output from is also shifted to the L level.

  When the shift pulse signal Q1n transitions to H level, the output signal of the OR circuit 42 of the first control signal generation circuit CSC1 becomes H level, the RS latch circuit 43 is reset, and the control signal SC1 transitions from H level to L level. To do. Further, when the control signal SC1 becomes L level, the control signal SC2 becomes L level because the external control signal L / R which is the input of the EXNOR circuit 44 is H level and the control signal SC1 is L level.

  At this time, in the pulse generation circuit CRn, since the control signal SC1 transits from the H level to the L level, the selector circuit 31 switches the input destination to the selector circuit 36 (shift pulse signal Q1n) and outputs it to the input switching circuit 32. To do. Further, since the control signal SC2 transits from the H level to the L level, the input switching circuit 32 switches the output destination to the DFF circuit 34 and outputs the shift pulse signal Q1n.

  In the pulse generation circuit CRi (i = 2 to n−1), since the control signal SC1 transits from the H level to the L level, the selector circuit 21 (21 ′) is output from the pulse generation circuit CR (i + 1). The shift pulse signal Q (i + 1) is selected and output to the DFF circuit 22 (22 ′).

  Further, in the pulse generation circuit CR1, since the control signal SC1 transits from the H level to the L level, the selector circuit 11 switches the input destination to the shift pulse signal Q2 of the pulse generation circuit CR2 and outputs it to the input switching circuit 12. Further, since the control signal SC2 transitions from the H level to the L level, the input switching circuit 12 switches the output destination to the DFF circuit 14 and outputs the shift pulse signal Q2.

  At time t (n + 1), since the shift pulse signal Q1n input to the DFF circuit 34 of the shift pulse generation circuit CRn is at the H level, the shift pulse signal Q2n output from the DFF circuit 34 transitions to the H level. Further, since the control signal SC2 is at L level, the output of the input switching circuit 32 input to the DFF circuit 33 becomes L level, and the shift pulse signal Q1n transits from H level to L level. The shift pulse signal Q2n is input to the reset terminal of the RS latch circuit 43 of the first control signal generation circuit CSC1 via the OR circuit 42. However, since the RS circuit 43 is already in the reset state, the control signal SC1 is maintained at the L level.

  At time t (n + 2), since the shift pulse signal Q2n input to the DFF circuit 22 ′ of the shift pulse generation circuit CR (n−1) is at the H level, the DFF circuit 22 ′ of the shift pulse generation circuit CR (n−1). Shift pulse signal Q (n-1) output from H goes to H level. At this time, the output switching circuit 23 'causes the pulse signal Q2 (n-1) to transition to the H level, and the pulse signal Q1 (n-1) is maintained at the L level. Further, since the shift pulse signal Q1n input to the DFF circuit 34 changes from the H level to the L level, the shift pulse signal Q2n changes from the H level to the L level.

  Similarly, at time t (n + h) (h = 3 to n−1), the shift pulse signal Q (2n−h + 1) input to the DFF circuit 21 (21 ′) of the shift pulse generation circuit CR (2n−h). ) Is at the H level, the shift pulse signal Q (2n−h) output from the DFF circuit 21 (21 ′) of the shift pulse generating circuit CR (2n−h) transitions to the H level. At this time, the output switching circuit 23 (23 ') causes the pulse signal Q2 (2n-h) to transition to the H level, and the pulse signal Q1 (2n-h) is maintained at the L level. Further, since the shift pulse signal Q (2n−h + 2) input to the DFF circuit 21 (21 ′) of the shift pulse generation circuit CR (2n−h + 1) is at the L level, the DFF of the shift pulse generation circuit CR (2n−h + 1). The shift pulse signal Q (2n−h + 1) output from the circuit 21 (21 ′) also changes to the L level. At this time, the output switching circuit 23 (23 ′) of the shift pulse generating circuit CR (2n−h + 1) causes the pulse signal Q2 (2n−h + 1) to transition from the H level to the L level, and the pulse signal Q1 (2n−h + 1). Is maintained at the L level.

  At time t2n, since the shift pulse signal Q2 input to the DFF circuit 14 of the shift pulse generating circuit CR1 is at the H level, the shift pulse signal Q21 output from the DFF circuit 14 transitions to the H level. At this time, the input switching circuit 12 inputs an L level signal to the DFF circuit 13, and the shift pulse signal Q11 is maintained at the L level.

  As described above, the input signal IN1 propagates in the order of the pulse generation circuits CR1 to CRn and CRn to CR1. Further, pulse signals Q11 to Q1n and Q2n to Q21 are output in this order.

  Next, the case where the external control signal L / R is at the L level will be briefly described with reference to FIG.

  When the external control signal L / R is at the L level, the selector circuit 35 of the pulse generation circuit CRn always selects the shift pulse signal Q2n output from the DFF circuit 34, and the selector circuit 36 always operates the DFF circuit. The shift pulse signal Q1n output from 33 is selected. When the external control signal L / R is at L level, a pulse signal is input to the input signal IN2, and the input signal IN1 is maintained at L level. The signal IN3 that is the logical sum of the input signal IN1 and the input signal IN2 is always at the same level as the signal IN2 because the input signal IN1 is maintained at the L level.

  When the input signal IN2 becomes H level at time t0, the signal IN3 becomes H level, the RS latch circuit 43 is set, and the control signal SC1 becomes H level. Further, the control signal SC2 becomes L level.

  At this time, since the control signal SC1 is at the H level and the control signal SC2 is at the L level, the pulse generation circuit CR1 transmits the propagation signal of the input signal IN2 through the selector circuit 11 and the input switching circuit 12 to the DFF circuit 14. Input to the D terminal. In the pulse generation circuit CRi (i = 2 to n−1), the selector circuit 21 (21 ′) outputs the shift pulse signal Q (i−1) output from the pulse generation circuit CR (i−1) to the DFF circuit 22. (22 '). In the pulse generation circuit CRn, the selector circuit 31 and the input switching circuit 32 input the shift pulse signal Q (n−1) output from the pulse generation circuit CR (n−1) to the DFF circuit 33.

  At time t1, since the propagation signal of the signal IN2 input to the DFF circuit 14 is H level, the shift pulse signal Q21 output from the DFF circuit 14 transits from L level to H level. At this time, the input switching circuit 12 inputs an L level signal to the DFF circuit 13, and the shift pulse signal Q11 is maintained at the L level.

  At time t2, since the shift pulse signal Q21 input to the DFF circuit 22 of the shift pulse generation circuit CR2 is at H level, the shift pulse signal Q2 output from the DFF circuit 22 of the shift pulse generation circuit CR2 transitions to H level. At this time, the shift pulse signal Q22 transitions to the H level by the output switching circuit 23, and the shift pulse signal Q12 is maintained at the L level. Further, since the propagation signal of the signal IN2 input to the DFF circuit 14 transits from H level to L level, the shift pulse signal Q21 transits from H level to L level.

  Similarly, at time th (h = 3 to n−1), the shift pulse signal Q (h−1) input to the DFF circuit 21 (21 ′) of the shift pulse generation circuit CRh is at the H level. The shift pulse signal Qh output from the DFF circuit 21 (21 ′) of the generation circuit CRh transitions to the H level. At this time, the pulse signal Q2h is changed from the L level to the H level by the output switching circuit 23, and the pulse signal Q1h is maintained at the L level. Further, since the shift pulse signal Q (h-2) input to the DFF circuit 21 (21 ') of the shift pulse generation circuit CR (h-1) is at the L level, the DFF of the shift pulse generation circuit CR (h-1). The shift pulse signal Q (h−1) output from the circuit 21 (21 ′) also changes to the L level. At this time, the output switching circuit 23 (23 ') causes the pulse signal Q2 (h-1) to transition from the H level to the L level.

  At time tn, since the shift pulse signal Q (n−1) input to the DFF circuit 34 of the shift pulse generating circuit CRn is at the H level, the shift pulse signal Q2n output from the DFF circuit 34 transitions to the H level. Further, since the shift pulse signal Q (h-2) input to the DFF circuit 21 'of the shift pulse generation circuit CR (n-1) is at the L level, the DFF circuit 21' of the shift pulse generation circuit CR (n-1). The shift pulse signal Q (n−1) output from is also shifted to the L level.

  When the shift pulse signal Q2n transits to H level, the output signal of the OR circuit 42 of the first control signal generation circuit CSC1 becomes H level, the RS latch circuit 43 is reset, and the control signal SC1 transits from H level to L level. To do. Further, when the control signal SC1 becomes L level, the control signal SC2 becomes H level because the external control signal L / R which is the input of the EXNOR circuit 44 is L level and the control signal SC1 is L level.

  At this time, in the pulse generation circuit CRn, since the control signal SC1 transits from the H level to the L level, the selector circuit 31 switches the input destination to the selector circuit 36 (shift pulse signal Q2n) and outputs the input signal to the input switching circuit 32. To do. Further, since the control signal SC2 transits from the H level to the L level, the input switching circuit 32 switches the output destination to the DFF circuit 33 and outputs the shift pulse signal Q2n.

  In the pulse generation circuit CRi (i = 2 to n−1), since the control signal SC1 transits from the H level to the L level, the selector circuit 21 (21 ′) is output from the pulse generation circuit CR (i + 1). The shift pulse signal Q (i + 1) is selected and output to the DFF circuit 22 (22 ′).

  Further, in the pulse generation circuit CR1, since the control signal SC1 transits from the H level to the L level, the selector circuit 11 switches the input destination to the shift pulse signal Q2 of the pulse generation circuit CR2 and outputs it to the input switching circuit 12. Further, since the control signal SC2 transits from the H level to the L level, the input switching circuit 12 switches the output destination to the DFF circuit 13 and outputs the shift pulse signal Q2.

  At time t (n + 1), since the shift pulse signal Q2n input to the DFF circuit 33 of the shift pulse generation circuit CRn is at the H level, the shift pulse signal Q1n output from the DFF circuit 33 transitions to the H level. Further, since the control signal SC2 is at L level, the output of the input switching circuit 32 input to the DFF circuit 34 becomes L level, and the shift pulse signal Q2n transits from H level to L level.

  At time t (n + 2), since the shift pulse signal Q1n input to the DFF circuit 22 ′ of the shift pulse generation circuit CR (n−1) is at the H level, the DFF circuit 22 ′ of the shift pulse generation circuit CR (n−1). Shift pulse signal Q (n-1) output from H goes to H level. At this time, the output switching circuit 23 'causes the pulse signal Q1 (n-1) to transition to the H level, and the shift pulse signal Q2 (n-1) is maintained at the L level. Further, since the shift pulse signal Q2n input to the DFF circuit 33 transits from the H level to the L level, the shift pulse signal Q1n transits from the H level to the L level.

  Similarly, at time t (n + h) (h = 3 to n−1), the shift pulse signal Q (2n−h + 1) input to the DFF circuit 21 (21 ′) of the shift pulse generation circuit CR (2n−h). ) Is at the H level, the shift pulse signal Q (2n−h) output from the DFF circuit 21 (21 ′) of the shift pulse generating circuit CR (2n−h) transitions to the H level. At this time, the output switching circuit 23 (23 ') causes the pulse signal Q1 (2n-h) to transition to the H level, and the pulse signal Q2 (2n-h) is maintained at the L level. Further, since the shift pulse signal Q (2n−h + 2) input to the DFF circuit 21 (21 ′) of the shift pulse generation circuit CR (2n−h + 1) is at the L level, the DFF of the shift pulse generation circuit CR (2n−h + 1). The shift pulse signal Q (2n−h + 1) output from the circuit 21 (21 ′) also changes to the L level. At this time, the output switching circuit 23 (23 ′) of the shift pulse generating circuit CR (2n−h + 1) causes the pulse signal Q1 (2n−h + 1) to transition from the H level to the L level, and the pulse signal Q2 (2n−h + 1). Is maintained at the L level.

  At time t2n, since the shift pulse signal Q2 input to the DFF circuit 13 of the shift pulse generation circuit CR1 is at the H level, the shift pulse signal Q11 output from the DFF circuit 13 transitions to the H level. At this time, the input switching circuit 12 inputs an L level signal to the DFF circuit 14, and the shift pulse signal Q21 is maintained at the L level.

  As described above, the input signal IN2 propagates in the order of the pulse generation circuits CR1 to CRn and CRn to CR1. Further, pulse signals Q21 to Q2n, Q1n to Q11 are output in this order.

<Another embodiment>
<1> In the above embodiment, the input signal IN1 and the input signal IN2 can be input, the direction from the first output circuit group COB1 to the second output circuit group COB2, and the second output circuit group COB2 to the first output circuit. The case where the shift pulse signal can be propagated in both directions of the group COB1 has been described. However, as shown in FIG. 4, only the input signal IN1 can be input, and the second output circuit group COB2 can be input from the first output circuit group COB1 side. You may comprise so that a shift pulse signal can be propagated only to the direction.

<2> In the above embodiment, the shift pulse signal received by the input-side selector circuit 21 (21 ′) for the i-th (i = 2 to n−1) pulse generation circuit CRi is the shift pulse signal Q (i− Although the shift direction is controlled by switching between 1) and the shift pulse signal Q (i + 1), the present invention is not limited to this.

  For example, as shown in FIG. 5, for the i-th pulse generation circuit CRi, a new shift pulse signal Qi generated by the bidirectional latch circuit 22 (22 ′) is (i−1) based on the control signal SC1. ) The output side selector circuit 24 (24 ′) for outputting to either one of the pulse generator circuit CR (i−1) in the stage and the pulse generator circuit CR (i + 1) in the (i + 1) stage is configured. Also good.

<3> In the above embodiment, in the j-th (j = 1 to n) pulse generation circuit CRj, the output from the Q terminal of the latch circuit is used as it is as a pulse signal. However, the present invention is not limited to this. For example, another circuit such as a buffer circuit may be provided between the output circuit CO and a pulse signal may be generated using an output signal from the NQ terminal of the latch circuit.

  Further, a shift pulse signal may be generated using an output signal from the NQ terminal of the latch circuit.

1. Display Device Integrated Circuit (Driver Circuit) According to the Present Invention
11 selector circuit 12 input switching circuit 13 latch circuit 14 latch circuit 15 selector circuit 21 selector circuit 21 'selector circuit 22 latch circuit 22' latch circuit 23 output switching circuit 23 'output switching circuit 31 selector circuit 32 input switching circuit 33 latch circuit 34 Latch circuit 35 Selector circuit 36 Selector circuit 41 OR circuit 42 OR circuit 43 RS latch circuit 44 EXNOR circuit 100 Drive circuit 200 according to prior art Tape 201 Wiring 202 Wiring COB Output circuit group CO Output circuit CSR Shift pulse generating circuit according to the present invention CSR1 Shift pulse generating circuit CSR2 according to the present invention Shift pulse generating circuit CSR3 Shift pulse generating circuit CSR100 according to the present invention Shift pulse generating circuit CSC1 according to the prior art First control signal generating circuit CSC2 second control signal generating circuit CR pulse generating circuit I input terminal OUT output terminal

Claims (7)

A shift pulse generating circuit comprising n stages of pulse generating circuits (where n is an integer of 3 or more),
The first-stage pulse generation circuit receives a first input signal, generates a shift pulse signal, and outputs it to the second-stage pulse generation circuit, and the second-stage pulse generation circuit outputs it. A second latch circuit that receives the shift pulse signal and generates a new shift pulse signal,
The i-th (i = 2 to n−1) -th pulse generation circuit receives the shift pulse signal output from the (i−1) -th pulse generation circuit and generates a new shift pulse signal (i + 1). ) Output to the pulse generation circuit at the stage, and receive a shift pulse signal output from the pulse generation circuit at the (i + 1) stage to generate a new shift pulse signal (i-1) the pulse at the stage One bidirectional latch circuit for outputting to the generator circuit;
a third latch circuit that receives the shift pulse signal output from the (n-1) th stage pulse generation circuit and generates a new shift pulse signal; and A shift pulse generation circuit comprising: a fourth latch circuit that receives a shift pulse signal output from the circuit, generates a new shift pulse signal, and outputs the shift pulse signal to the pulse generation circuit at the (n-1) th stage. The i-th pulse generation circuit (i = 2 to n−1) includes the shift pulse signal output from the (i−1) -th pulse generation circuit and the (i + 1) -th pulse generation circuit. One of the output shift pulse signals is the shift pulse signal output from the third latch circuit and the fourth latch circuit or the shift pulse signal input to the third latch circuit and the fourth latch circuit. Comprising an input side selector circuit for selecting based on at least one of the following:
2. The shift pulse generation circuit according to claim 1, wherein the bidirectional latch circuit receives a shift pulse signal selected by the input side selector circuit and generates a new shift pulse signal.   The i-th (i = 2 to n-1) pulse generation circuit sends a new shift pulse signal generated by the bidirectional latch circuit to the (i-1) -th pulse generation circuit and (i + 1). A shift pulse signal output from the third latch circuit and the fourth latch circuit or a shift pulse signal input to the third latch circuit and the fourth latch circuit is provided to any one of the pulse generation circuits in the stage. The shift pulse generation circuit according to claim 1, further comprising an output-side selector circuit that selectively outputs a signal based on at least one of the above. The first-stage pulse generation circuit is further configured to receive a second input signal, and the second latch circuit receives the second input signal and generates a new shift pulse signal, Output to the pulse generation circuit, the first latch circuit is configured to receive a shift pulse signal output from the pulse generation circuit of the second stage and generate a new shift pulse signal,
When the second input signal is input to the pulse generation circuit at the n-th stage and the pulse generation circuit at the first stage, the fourth latch circuit performs the pulse at the (n−1) -th stage. A shift pulse signal output from the generation circuit is received and a new shift pulse signal is generated and output to the third latch circuit. The third latch circuit receives the shift pulse signal output from the fourth latch circuit. The shift pulse according to any one of claims 1 to 3, wherein a new shift pulse signal is generated and output to the (n-1) -th stage pulse generation circuit. Generation circuit. The pulse generation circuit at the j-th stage (j = 1 to n) includes n output circuits based on or in synchronization with the new shift pulse signal generated by the latch circuit included in the pulse generation circuit. A pulse signal is separately output to each of the j-th output circuit of the first output circuit group and the j-th output circuit of the second output circuit group including the n output circuits. Configured,
In the first-stage pulse generation circuit, the first latch circuit outputs the pulse signal to the first output circuit in the first output circuit group, and the second latch circuit includes the second latch circuit. Outputting the pulse signal to the first output circuit of the output circuit group;
When the i-th (i = 2 to n-1) pulse generation circuit receives a shift pulse signal output from the (i-1) -th pulse generation circuit, the first output circuit group When the pulse signal is output to the i-th output circuit and the shift pulse signal output from the (i + 1) -th stage pulse generation circuit is received, the i-th output circuit of the second output circuit group Output the pulse signal to the output circuit,
In the n-th pulse generation circuit, the third latch circuit outputs the pulse signal to the first output circuit of the first output circuit group, and the fourth latch circuit includes the second latch circuit. 4. The shift pulse generation circuit according to claim 1, wherein the pulse signal is output to the first output circuit of the output circuit group. 5. The pulse generation circuit at the j-th stage (j = 1 to n) includes n output circuits based on or in synchronization with the new shift pulse signal generated by the latch circuit included in the pulse generation circuit. A pulse signal is separately output to each of the j-th output circuit of the first output circuit group and the j-th output circuit of the second output circuit group including the n output circuits. Configured,
In the first-stage pulse generation circuit, the first latch circuit outputs the pulse signal to the first output circuit in the first output circuit group, and the second latch circuit includes the second latch circuit. Outputting the pulse signal to the first output circuit of the output circuit group;
The pulse generation circuit of the i-th stage (i = 1 to n)
When the first input signal is input to the pulse generation circuit at the first stage, and the shift pulse signal output from the pulse generation circuit at the (i-1) stage is received, the first output circuit When the pulse signal is output to the i-th output circuit of the group and the shift pulse signal output from the pulse generation circuit at the (i + 1) stage is received, the i-th output circuit of the second output circuit group Outputting the pulse signal to the output circuit;
When the second input signal is input to the pulse generation circuit at the first stage, and when the shift pulse signal output from the pulse generation circuit at the (i-1) stage is received, the second output circuit When the pulse signal is output to the i-th output circuit of the group and the shift pulse signal output from the (i + 1) -th pulse generation circuit is received, the i-th output circuit group of the first output circuit group Output the pulse signal based on the shift pulse signal to the output circuit,
In the n-th pulse generation circuit, the third latch circuit outputs the pulse signal to the first output circuit of the first output circuit group, and the fourth latch circuit includes the second latch circuit. 5. The shift pulse generation circuit according to claim 4, wherein the pulse signal is output to the first output circuit of the output circuit group. A first output comprising the shift pulse generation circuit according to any one of claims 5 and 6, and n output circuits that perform time-series processing based on the pulse signal output from the shift pulse generation circuit. A second output circuit group comprising a circuit group and n output circuits,
The n-stage pulse generation circuits of the shift pulse generation circuit are aligned in the long side direction of the rectangular semiconductor device, and the jth (j = 1 to n) output circuits of the first output circuit group An integrated circuit for driving a display device, wherein the jth output circuit of the second output circuit group is disposed at a position facing the jth stage of the shift pulse generation circuit.

Images